JP2013182998A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a leak current running between power lines as well as power consumption involved in charge and discharge into/from the power lines.SOLUTION: In a buffer which inputs and outputs a signal into/from a signal processing circuit and a latch which controls a switch for switching power supply to the signal processing circuit, a transistor with an off current per channel width of not more than 1×10A/μm is provided between wirings for supplying power supply to suppress a leak current and power consumption.

Description

The present invention relates to a semiconductor device.

In recent years, technological development for reducing power consumption of semiconductor devices such as microcomputers has been promoted.

Examples of the semiconductor device include a microcomputer that can stop supply of power supply voltage to an MPU (Micro Processing Unit), a memory, and the like in a period in which power supply is not required (for example, Patent Document 1).

JP 2009-116851 A

However, the conventional microcomputer has been insufficient in reducing power consumption.

For example, a conventional microcomputer is a latch for switching power supply to signal processing circuits such as an MPU and a memory, and wastes electric power due to a leak current flowing between power supply lines.

In addition, since the conventional microcomputer is configured to repeatedly stop and restart the power supply to the peripheral circuits of the signal processing circuit such as a latch and a buffer, charge and discharge of the charge on the power supply line connected to each circuit is performed. Was wasting power.

An object of one embodiment of the present invention is to reduce leakage current flowing between power supply lines to reduce power consumption.

Another object of one embodiment of the present invention is to reduce power consumption associated with charging and discharging of power to and from a power supply line when switching power supply to a signal processing circuit between stop and restart.

According to one embodiment of the present invention, in a latch that controls a buffer that inputs / outputs a signal to / from a signal processing circuit and a switch that switches power supply to the signal processing circuit, an off-per-channel width is provided between wirings that supply power. A transistor with a current of 1 × 10 ⁻¹⁹ A / μm or less is provided to reduce leakage current and reduce power consumption.

In one embodiment of the present invention, in the buffer and the latch, the transistor is turned off without stopping power supply, so that power consumption due to charge / discharge of electric charge is reduced.

One embodiment of the present invention includes a signal processing circuit, a buffer that inputs and outputs a signal processed by the signal processing circuit, a switch that controls power supply to the signal processing circuit, and switching of the switch according to the operation state of the signal processing circuit The buffer and the latch are semiconductor devices provided with a transistor having an off current per channel width of 1 × 10 ⁻¹⁹ A / μm or less between wirings for supplying power.

In one embodiment of the present invention, the transistor is preferably a semiconductor device that is an n-channel transistor in which an oxide semiconductor is used for a channel region.

In one embodiment of the present invention, the buffer and the latch are preferably semiconductor devices that are unipolar circuits.

In one embodiment of the present invention, the inverter included in the buffer and the latch is preferably a semiconductor device which is a complementary circuit in which an n-channel transistor and a p-channel transistor are combined.

In one embodiment of the present invention, the latch is preferably a semiconductor device that is a set / reset type flip-flop.

In one embodiment of the present invention, the latch is preferably a semiconductor device that controls switching of a switch in accordance with a set signal input from the outside of the semiconductor device and a reset signal input from a signal processing circuit.

According to one embodiment of the present invention, leakage current between power supply lines and power consumption associated with charge / discharge can be reduced.

4A and 4B illustrate a structure of a semiconductor device. The figure which shows the structural example of a circuit. FIG. 6 illustrates a configuration example of a circuit in a semiconductor device. 4A and 4B illustrate a structure of a semiconductor device. The figure which shows the structural example of a circuit. The flowchart figure of the signal generation at the time of circuit operation. FIG. 10 is a schematic cross-sectional view for illustrating the structure of a semiconductor device. FIG. 10 illustrates an example of an electronic device. Arrhenius plot for explaining the off-current.

An example of an embodiment of the present invention will be described. Note that it is easy for those skilled in the art to change the contents of the embodiments without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the description of the following embodiments.

Note that the size and thickness of each component illustrated in the drawings and the like in the embodiments are exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale.

In addition, the functions of the “source” and “drain” of the transistor may be switched when a transistor with a different polarity is used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

(Embodiment 1)
In this embodiment, an example of a semiconductor device that controls stop and restart of power supply to a signal processing circuit will be described.

First, a structure example of a semiconductor device is described with reference to FIG.

A semiconductor device 100 illustrated in FIG. 1A includes a signal processing circuit 101, a buffer 102, a latch 103, and a switch 104 for power supply control. As a peripheral circuit of the semiconductor device 100, a power supply circuit 105 and an external circuit 106 are illustrated in FIG.

The signal processing circuit 101, the buffer 102, and the latch 103 are each supplied with the potential VDD from the power supply line connected to the power supply circuit 105, and are supplied with power from the ground line GND.

The signal processing circuit 101 is a circuit that performs processing such as calculation on data input from the external circuit 106 via the buffer 102 and holds the processed data or outputs the processed data to the external circuit 106 via the buffer 102. . The signal processing circuit 101 is a circuit that outputs a reset signal to the latch 103 in accordance with the progress of processing of input data.

Note that the signal processing circuit 101 includes a volatile memory circuit and a nonvolatile memory circuit. The signal processing circuit 101 saves data in the nonvolatile memory circuit immediately before the power supply is stopped, and the nonvolatile memory circuit immediately after the power supply is restarted. A configuration in which the stored data is input to the volatile storage circuit is preferable. Thereby, the state recovery of the signal processing circuit 101 when the power supply is resumed can be accelerated.

The buffer 102 is a circuit for performing input / output of data processed by the signal processing circuit 101 with the external circuit 106. Specifically, data to be processed by the signal processing circuit 101 is input from the external circuit 106 via the buffer 102. Data processed by the signal processing circuit 101 is output to the external circuit 106 via the buffer 102. The buffer 102 may be configured by a circuit having multiple stages of flip-flops and inverters.

The latch 103 is a circuit that outputs a control signal for the switch 104 in accordance with a set signal and a reset signal. Specifically, the control signal output to the switch 104 is held at the H level by the set signal from the external circuit 106, and the control signal output to the switch 104 is held at the L level by the reset signal from the signal processing circuit 101. It is a circuit to do. The latch 103 may be composed of a set / reset type flip-flop.

The switch 104 is provided between the signal processing circuit 101 and the ground line GND, and stops the supply of power to the signal processing circuit 101 by controlling the conduction state of the switch 104 with a control signal output from the latch 103. And a circuit for switching the restart. The switch 104 may be formed using a transistor. Specifically, when an n-channel transistor is used as the switch 104, the supply of power to the signal processing circuit 101 is stopped when the control signal from the latch 103 is an L level signal, and signal processing is performed using an H level signal. The power supply to the circuit 101 is resumed.

Note that the switch 104 may be provided between the power supply circuit 105 and the signal processing circuit 101.

The power supply circuit 105 is a circuit for supplying power to the signal processing circuit 101, the buffer 102, and the latch 103. 1A illustrates a configuration in which the power supply circuit 105 is provided outside the semiconductor device 100, a configuration in which the power supply circuit 105 is provided in the semiconductor device 100 may be employed.

The external circuit 106 is a circuit for inputting / outputting data to / from the buffer 102 in accordance with the processing of the signal processing circuit 101. The external circuit 106 is a circuit that outputs a set signal to the latch 103 in accordance with a signal from another circuit.

An example of the external circuit 106 is a mass storage device that can store data. The external circuit 106 that outputs the set signal may be an input device such as a keyboard or operation keys. Therefore, the external circuit 106 has a function of generating data in accordance with a state of input to the semiconductor device 100 or an external input device, in addition to a function of storing data and inputting / outputting data to / from the buffer 102.

Next, FIG. 1B illustrates a circuit configuration of a transistor provided between power supply lines of the buffer 102 and the latch 103 which is one embodiment of the present invention.

FIG. 1B illustrates a structure in which the transistor 111 and the transistor 112 are provided between the wiring to which the potential VDD is supplied and the ground line GND.

In the transistor 111, one of a source and a drain is connected to a wiring to which the potential VDD is supplied. The gate of the transistor 111 is connected to the input terminal. In the transistor 111, the other of the source and the drain is connected to the output terminal.

One of the source and the drain of the transistor 112 is connected to the output terminal. The gate of the transistor 112 is connected to the inverting input terminal. In the transistor 112, the other of the source and the drain is connected to the ground line GND.

A transistor provided between the power supply lines connected to the buffer 102 and the latch 103 is formed using a transistor with a small off-state current whose off-current per channel width is 1 × 10 ⁻¹⁹ A / μm or less. At this time, the transistor having an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less has a function of reducing leakage current between power supply lines by turning off the transistor.

The transistor having an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less includes, for example, a channel formation region containing an oxide semiconductor material having a wider band gap than silicon, and the channel formation region is substantially An i-type field effect transistor can be used. The field-effect transistor including the oxide semiconductor can be manufactured by removing impurities such as hydrogen or water as much as possible and supplying oxygen to reduce oxygen vacancies as much as possible.

Note that in the drawings, an OS symbol is assigned to the transistor 111 and the transistor 112 in order to indicate that the transistor 111 and the transistor 112 include an oxide semiconductor film in a channel region.

By using a transistor having an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less between the power supply lines connected to the buffer 102 and the latch 103, the transistor can be simply turned off. Leakage current between power supply lines can be reduced. Therefore, power consumption of the semiconductor device 100 can be reduced.

For example, consider a case where the buffer 102 and the latch 103 are configured without using a transistor having an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less. At this time, in order to reduce the power consumption of the semiconductor device 100, the input / output of data from the latch 103 that controls the switch 104 and the signal processing circuit 101 is performed even if the supply of power to the signal processing circuit 101 is stopped. In the buffer 102, power consumption due to leakage current between the power supply lines increases.

In the buffer 102, the supply of power may be stopped in order to suppress an increase in power consumption due to a leakage current between power supply lines. However, if the configuration in which the supply and stop of the power supply to the buffer 102 is repeated is repeated, the power consumption increases with the charge and discharge of the power to the power supply line.

On the other hand, in the structure described in this embodiment, a transistor provided between the power supply lines of the buffer 102 and the latch 103 is a transistor having an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less. Therefore, power consumption due to a leakage current in a state where power supply to the signal processing circuit 101 is stopped can be reduced.

In addition, since the structure described in this embodiment can reduce the leakage current itself, power consumption can be reduced without stopping the supply of power to the buffer 102 and the latch 103. Therefore, the buffer 102 and the latch 103 having the structure described in this embodiment can reduce power consumption due to charge and discharge due to repeated stop and restart of power supply.

As described above, in one embodiment of the present invention, the transistor provided between the power supply lines of the buffer 102 and the latch 103 is a transistor having an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less. It is possible to reduce the leakage current flowing between the two and achieve an excellent effect of reducing power consumption. Further, according to one embodiment of the present invention, when power supply to the signal processing circuit 101 is switched, an excellent effect is achieved in that power consumption associated with charge and discharge of electric charges to and from a power supply line can be reduced.

Note that although the transistor 111 and the transistor 112 are illustrated as transistors provided between power supply lines in the structure illustrated in FIG. 1B, only one of them may be provided. Note that by providing a transistor with an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less on both the wiring side to which the potential VDD is supplied and the ground line GND side, leakage current between the power supply lines can be more reliably ensured. Can be reduced.

Note that in the case where one of the transistor 111 and the transistor 112 is provided between the power supply lines, if an L-level signal is output from the output terminal, the transistor 111 has an off-current of at least 1 × 10 ⁻¹⁹ A per channel width. / Μm or less may be used. With this structure, leakage current flowing from the wiring to which the potential VDD is supplied to the output terminal side through the transistor 111 can be reduced. On the other hand, when an H level signal is output from the output terminal, the transistor 112 may be a transistor having an off current of at least 1 × 10 ⁻¹⁹ A / μm or less per channel width. With this structure, leakage current flowing from at least the output terminal to the ground line GND side through the transistor 112 can be reduced.

In addition, a transistor with an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less provided between the power supply lines of the buffer 102 and the latch 103 is configured to form a bootstrap as shown in FIG. It may be provided. In FIG. 2A, the transistor 121, the transistor 122, the transistor 123, and the capacitor 124 are illustrated. With this structure, a signal output from the wiring to which the potential VDD is supplied to the output terminal can be output without lowering the potential.

2A illustrates a two-input circuit configuration including an input terminal and an inverting input terminal, a one-input circuit configuration including only an input terminal may be used. 2B illustrates a transistor 125 and a transistor 126 in addition to the transistor 121, the transistor 122, the transistor 123, and the capacitor 124. In this case, as shown in FIG. 2B, a transistor 125 and a transistor 126 that constitute an inverter are provided at the gate of the transistor that becomes the inverting input terminal, thereby realizing a one-input circuit configuration with only the input terminal. it can.

Note that the transistor 125 and the transistor 126 included in the inverter in FIG. 2B are complementary circuits in which a p-channel transistor and an n-channel transistor are combined. In the inverter as well, in order to reduce the leakage current between the power supply lines, it is preferable that the n-channel transistor be a transistor having an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less.

Next, a circuit configuration example of the buffer 102 and the latch 103 will be described with reference to FIG.

A circuit block 129 illustrated in FIG. 3A has the circuit configuration illustrated in FIG. In the circuit block 129 illustrated in FIG. 3A, an input terminal and an inverted input terminal to which an inverted signal is input are input, and a signal having the same logic as that of the input terminal is output as an output signal. Functions as a buffer.

FIG. 3B illustrates a set / reset type flip-flop using the circuit block 129 illustrated in FIG. 3A as an example of a circuit configuration of the latch 103.

A set / reset flip-flop 130 illustrated in FIG. 3B includes a transistor 131, a transistor 132, a transistor 133, a transistor 134, and buffers 135 to 139.

In the set / reset flip-flop 130 illustrated in FIG. 3B, the set signal and the reset signal described in FIG. 1A are input to the set terminal S and the reset terminal R which are input terminals, and the output terminal A signal corresponding to the input signal is output from Q.

In the set / reset flip-flop 130 illustrated in FIG. 3B, a transistor provided between power supply lines has an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less. Therefore, leakage current flowing between the power supply lines can be reduced, and power consumption can be reduced. In addition, since there is no charge / discharge of charge to / from the power line, power consumption associated with charge / discharge of charge to / from the power line can be reduced.

As another structure of the semiconductor device illustrated in FIG. 1A, FIG. 4 illustrates a structure in the case where the semiconductor device includes a plurality of signal processing circuits. Note that in FIG. 4, components different from those in FIG. 1A are newly assigned reference numerals, and the same components are assigned the same reference numerals for description.

A semiconductor device 100 illustrated in FIG. 4 includes a signal processing circuit 101P, a signal processing circuit 101_1 to a signal processing circuit 101_N (N is a natural number of 2 or more), a switch 104P, and a switch 104_1 to a switch 104_N as a plurality of signal processing circuits. ing.

In the semiconductor device 100 illustrated in FIG. 4, the signal processing circuit 101P can output a reset signal, and the latch 103 can switch the switch 104P and the switches 104_1 to 104_N all at once. That is, the signal processing circuit 101P can be configured to perform processing for determining whether to stop the power supply. The other signal processing circuits 101_1 to 101_N can process different data.

With the configuration shown in FIG. 4, the switches can be controlled all at once, and the number of latches for controlling each switch can be reduced. Therefore, it is possible to reduce the size of the semiconductor device.

Next, a configuration example of the switch 104 will be described with reference to FIG.

The switch 104 illustrated in FIG. 5A includes a transistor 141. Note that the transistor 141 is an n-channel transistor and is provided on the ground line GND side of the signal processing circuit 101. Note that the transistor 141 used as the n-channel transistor is preferably a transistor with an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less.

The transistor 141 is a circuit for switching power supply to the signal processing circuit 101. This switching is performed by the output signal of the latch 103 as described above.

As another structure different from that shown in FIG. 5A, FIG. 5B shows another structure that the switch 104 can take.

The switch 104 illustrated in FIG. 5B includes a transistor 142 and a transistor 143. Note that the transistor 142 and the transistor 143 are n-channel transistors and are provided on the potential VDD side of a wiring that supplies power to the signal processing circuit 101. Note that the transistor 142 and the transistor 143 used as n-channel transistors are preferably transistors with an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less.

The transistors 142 and 143 are circuits for switching between connection to the power supply circuit 105 for applying a power supply voltage to the signal processing circuit 101 and connection to a ground line for not applying the power supply voltage. This switching is performed by the output signal of the latch 103 described above and a signal obtained by inverting the output signal of the latch 103.

Further, a flowchart for generating the set signal and the reset signal in FIG. 1A described above will be described with reference to FIGS. 6A and 6B. FIG. 6A is a flowchart for outputting a reset signal, and FIG. 6B is a flowchart for outputting a set signal.

In the flowchart shown in FIG. 6A, input / output signals are first processed by a signal processing circuit (step 151).

Next, it is determined whether the input / output signal processing in the signal processing circuit is completed (step 152). If the process is not completed in step 152, the process returns to step 151.

If the processing in step 152 is completed, the signal processing circuit outputs a reset signal to the latch in order to stop the power supplied to the signal processing circuit (step 153).

The above is the flowchart for outputting the reset signal.

In the flowchart shown in FIG. 6B, the semiconductor device first monitors input / output signals to / from an external circuit (step 161).

Next, it is determined whether or not there is an input / output signal to be processed by the signal processing circuit in the external circuit (step 162). If there is no input / output signal to be processed in step 162, the process returns to step 161.

If the processing in step 162 is completed, the signal processing circuit outputs a set signal for resuming the supply of power to the signal processing circuit whose supply is stopped to the latch (step 163).

The above is a flowchart for outputting the set signal.

As described with reference to FIGS. 1 to 6, the transistor provided between the power supply lines of the buffer 102 and the latch 103 is a transistor having an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less. The leakage current flowing between the power lines can be reduced, and the power consumption can be reduced. Further, according to one embodiment of the present invention, when power supply to the signal processing circuit 101 is switched, power consumption associated with charge / discharge of electric charge on the power supply line can be reduced.

(Embodiment 2)
In this embodiment, a transistor included in the semiconductor device that is one embodiment of the present invention will be described. In this embodiment, in particular, an n-channel transistor using an oxide semiconductor in a channel region, which is a transistor having an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less described in Embodiment 1 An example of the configuration will be described with reference to a schematic cross-sectional view of FIG. In addition, each component shown in FIG. 7 may differ from an actual dimension.

A transistor illustrated in FIG. 7A includes a semiconductor layer 711, an insulating layer 714, a conductive layer 715, insulating layers 716a and 716b, an insulating layer 717, conductive layers 718a and 718b, and an insulating layer 719. Including.

The semiconductor layer 711 is provided over the element formation layer 700 with the insulating layer 701 provided therebetween. Note that the semiconductor layer 711 may be provided directly over the element formation layer 700.

The semiconductor layer 711 includes regions 712a and 712b which are separated from each other and to which a dopant is added. In addition, the semiconductor layer 711 includes a channel formation region 713 between the regions 712a and 712b.

The insulating layer 714 is provided over part of the semiconductor layer 711.

The conductive layer 715 is provided so as to overlap with the semiconductor layer 711 with the insulating layer 714 interposed therebetween.

The insulating layer 716a is provided in contact with one of the pair of side surfaces of the conductive layer 715. The insulating layer 716b is provided in contact with the other of the pair of side surfaces.

The insulating layer 717 is provided over the conductive layer 715.

The conductive layer 718a is provided in contact with the region 712a. The conductive layer 718b is provided in contact with the region 712b. The conductive layer 718a is in contact with the side surface of the insulating layer 716a. The conductive layer 718b is in contact with the side surface of the insulating layer 716b.

The insulating layer 719 is provided over the conductive layers 718a and 718b.

The conductive layers 718a and 718b and the insulating layer 719 are formed by performing planarization treatment (for example, CMP treatment) on a stack of the conductive film and the insulating layer, for example.

In addition, the transistor illustrated in FIG. 7B includes a conductive layer 751, an insulating layer 752, an insulating layer 753, a semiconductor layer 754, conductive layers 755a and 755b, conductive layers 756a and 756b, and an insulating layer 757. Have.

The conductive layer 751 is provided over the element formation layer 750.

The insulating layer 752 is provided over the element formation layer 750. The surfaces of the insulating layer 752 and the conductive layer 751 are preferably flat.

The conductive layer 751 and the insulating layer 752 are formed, for example, by performing planarization treatment (eg, CMP treatment) on a stack of the conductive film and the insulating layer.

The insulating layer 753 is provided over the conductive layer 751 and the insulating layer 752.

The semiconductor layer 754 overlaps with the conductive layer 751 with the insulating layer 753 interposed therebetween.

The conductive layers 755a and 755b are provided apart from each other and in contact with the semiconductor layer 754. At this time, the distance between the conductive layers 755a and 755b corresponds to the channel length of the transistor, and is preferably less than 50 nm, for example. For example, by etching part of the conductive film using a resist mask formed by exposure with an electron beam, the distance between the conductive layers 755a and 755b can be less than 50 nm. For example, the distance between the conductive layers 755a and 755b is preferably shorter than the distance between the conductive layers 756a and 756b.

The conductive layer 756a is provided in contact with part of the conductive layer 755a, and the conductive layer 756b is provided in contact with part of the conductive layer 755b. For example, the resistance values of the conductive layers 756a and 756b are preferably lower than the resistance values of the conductive layers 755a and 755b.

The insulating layer 757 is provided so as to cover the semiconductor layer 754.

Further, each component will be described below. Each component is not necessarily limited to a single layer, and may be a stack of applicable materials.

The insulating layer 701 functions as a base layer. As the insulating layer 701, a layer containing a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or hafnium oxide can be used, for example.

As the insulating layer 752, for example, a layer containing a material that can be used as the insulating layer 701 can be used.

The semiconductor layers 711 and 754 have a function as a layer in which a channel of the transistor is formed (also referred to as a channel formation layer).

As the semiconductor layers 711 and 754, for example, oxide semiconductor layers can be used.

The oxide semiconductor layer is in a single crystal state, a polycrystalline (also referred to as polycrystal) state, an amorphous state, or the like. Alternatively, the oxide semiconductor layer may be a stack of an amorphous layer and a layer containing crystals.

As an oxide semiconductor, for example, a metal oxide containing one or both of indium and gallium and zinc, or a metal oxide containing another metal element instead of part or all of gallium contained in the metal oxide is used. Such as things.

As the metal oxide, for example, an In-based metal oxide, a Zn-based metal oxide, an In—Zn-based metal oxide, an In—Ga—Zn-based metal oxide, or the like can be used. Alternatively, a metal oxide containing another metal element instead of part or all of Ga (gallium) contained in the In—Ga—Zn-based metal oxide may be used.

As the other metal element, for example, a metal element that can be bonded to oxygen atoms more than gallium can be used. For example, one or more of titanium, zirconium, hafnium, germanium, and tin can be used. . As the other metal element, one or more of lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium can be used. The other metal element has a function as a stabilizer. Note that the amount of the other metal element added is an amount by which the metal oxide can function as a semiconductor. Oxygen defects in the metal oxide can be reduced by using a metal element capable of bonding with oxygen atoms more than gallium and supplying oxygen into the metal oxide.

For example, when tin is used instead of all of Ga (gallium) contained in the In—Ga—Zn-based metal oxide, an In—Sn—Zn-based metal oxide is obtained, and the In—Ga—Zn-based metal oxide When titanium is used instead of a part of contained Ga (gallium), an In—Ti—Ga—Zn-based metal oxide is obtained.

Alternatively, the oxide semiconductor layer may be an oxide semiconductor layer including a CAAC-OS (C Axis Crystalline Oxide Semiconductor).

The CAAC-OS refers to an oxide semiconductor with a crystal-amorphous mixed phase structure where a crystal part is included in an amorphous phase and is not completely single crystal nor completely amorphous. Further, the crystal part included in the CAAC-OS is viewed from a direction perpendicular to the ab plane and the c-axis is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface. It has a triangular or hexagonal atomic arrangement, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers as seen from the direction perpendicular to the c-axis. Note that in this specification, the term “perpendicular” includes a range of 85 ° to 95 °. In addition, a simple term “parallel” includes a range from −5 ° to 5 °.

A field-effect transistor using the oxide semiconductor layer including the CAAC-OS as a channel formation layer has high reliability because variation in electrical characteristics due to irradiation with visible light or ultraviolet light is low.

In the case where an oxide semiconductor layer is used as the semiconductor layers 711 and 754, for example, dehydration and dehydrogenation are performed, and impurities such as hydrogen, water, a hydroxyl group, or hydride (also referred to as a hydrogen compound) in the oxide semiconductor layer are used. And by supplying oxygen to the oxide semiconductor layer, the oxide semiconductor layer can be highly purified. For example, the oxide semiconductor layer can be highly purified by using a layer containing oxygen as the layer in contact with the oxide semiconductor layer and performing heat treatment.

The oxide semiconductor layer immediately after film formation is preferably in a supersaturated state with more oxygen than in the stoichiometric composition. For example, in the case where an oxide semiconductor layer is formed by a sputtering method, the film formation is preferably performed under a condition where the proportion of oxygen in the film formation gas is large, and the film formation is performed particularly in an oxygen atmosphere (oxygen gas 100%). It is preferable. In addition, since sufficient oxygen is supplied to the oxide semiconductor layer so that oxygen is in a supersaturated state, the insulating layer in contact with the oxide semiconductor layer (the insulating layers 701, 714, 753, 757, and the like) includes an excess oxygen. (Such as SiOx) may be formed.

As the insulating layer containing excess oxygen, a SiOx film or a silicon oxynitride film in which a large amount of oxygen is contained in the film by appropriately setting film forming conditions in the PCVD method, plasma sputtering method, or other sputtering method is used. In addition, when a large amount of excess oxygen is to be included in the insulating layer, oxygen is added by an ion implantation method, an ion doping method, or plasma treatment. Further, oxygen may be added to the oxide semiconductor layer.

In the sputtering apparatus, it is preferable that the residual moisture in the deposition chamber is small. In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, the exhaust means may be a turbo molecular pump to which a cold trap is added.

For example, heat treatment is performed at a temperature of 350 ° C. or higher and lower than the strain point of the substrate, preferably 350 ° C. or higher and 450 ° C. or lower. Furthermore, you may heat-process in a subsequent process. At this time, as a heat treatment apparatus that performs the heat treatment, for example, an electric furnace or an apparatus that heats an object by heat conduction or heat radiation from a heating element such as a resistance heating element can be used. An RTA (Rapid Thermal Annealing) apparatus such as a Gas Rapid Thermal Annealing (LRAS) apparatus or an LRTA (Lamp Rapid Thermal Annealing) apparatus can be used. You may perform the said heat processing in multiple times.

In addition, after performing the above heat treatment, a high purity oxygen gas or a high purity N ₂ O gas is supplied to the same furnace as that in which the heat treatment is performed while maintaining the heating temperature or in the process of lowering the temperature from the heating temperature. Alternatively, ultra-dry air (an atmosphere having a dew point of −40 ° C. or lower, preferably −40 ° C. or lower) may be introduced. At this time, the oxygen gas or the N _{2 O} gas, water, preferably contains no hydrogen, and the like. Further, the purity of the oxygen gas or N ₂ O gas introduced into the heat treatment apparatus is 6 N or more, preferably 7 N or more, that is, the impurity concentration in the oxygen gas or N ₂ O gas is 1 ppm or less, preferably 0.1 ppm or less. It is preferable that Oxygen is supplied to the oxide semiconductor layer by the action of oxygen gas or N ₂ O gas, and defects due to oxygen deficiency in the oxide semiconductor layer can be reduced. Note that the introduction of the high-purity oxygen gas, the high-purity N ₂ O gas, or the ultra-dry air may be performed during the heat treatment.

The hydrogen concentration of the highly purified oxide semiconductor layer is 5 × 10 ¹⁹ atoms / cm ³ or less, desirably 5 × 10 ¹⁸ atoms / cm ³ or less, and more desirably 5 × 10 ¹⁷ atoms / cm ³ or less. It is preferable. For example, the hydrogen concentration in the oxide semiconductor layer can be measured using secondary ion mass spectrometry (SIMS).

By using the highly purified oxide semiconductor layer for a field effect transistor, the carrier density of the oxide semiconductor layer is less than 1 × 10 ¹⁴ / cm ³ , preferably less than 1 × 10 ¹² / cm ³ , more preferably 1 It can be made less than × 10 ¹¹ / cm ³ . The off-state current of the field effect transistor per channel length of 1 μm and channel width of 1 μm is 1 × 10 ⁻¹⁹ A (100 zA) or less, further 1 × 10 ⁻²⁰ A (10 zA) or less, and further 1 × 10 ^−21. A (1zA) or less, and further 1 × 10 ⁻²² A (100 yA) or less. The lower the off-state current of the field-effect transistor, the better. However, the lower limit value of the off-state current of the field-effect transistor is estimated to be about 1 × 10 ⁻³⁰ A / μm.

Note that in order to detect an off-state current that is minimized by purifying an oxide semiconductor, an off-state current that actually flows can be estimated by manufacturing a relatively large transistor and measuring the off-state current. FIG. 9 shows the channel width when the channel width W is 1 m (100,000 μm) and the channel length L is 3 μm, and the temperature is changed to 150 ° C., 125 ° C., 85 ° C., and 27 ° C. The figure which carried out the Arrhenius plot of the off-current per W1micrometer is shown. As can be seen from FIG. 9, it can be seen that the off-state current is as extremely small as 3 × 10 ⁻²⁶ A / μm. The reason why the off-state current was measured by raising the temperature was that measurement was difficult because the current measurement was very small at room temperature.

Examples of the dopant included in the regions 712a and 712b include a group 13 element (for example, boron) in the periodic table, a group 15 element (for example, one or more of nitrogen, phosphorus, and arsenic) in the periodic table, and One or more of noble gas elements (eg, one or more of helium, argon, and xenon) can be used.

The insulating layers 714 and 753 function as gate insulating layers of the transistors. As the insulating layers 714 and 753, for example, a layer containing a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or hafnium oxide is used. it can.

The conductive layers 715 and 751 function as gates of the transistors. As the conductive layers 715 and 751, a layer containing a metal material such as molybdenum, titanium, chromium, tantalum, magnesium, silver, tungsten, aluminum, copper, neodymium, or scandium can be used, for example.

As the insulating layers 716a, 716b, and 717, for example, a layer containing a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or hafnium oxide is used. be able to.

The conductive layers 718a and 718b, the conductive layers 755a and 755b, and the conductive layers 756a and 756b function as a source or a drain of the transistor. As the conductive layers 718a and 718b, the conductive layers 755a and 755b, and the conductive layers 756a and 756b, for example, a metal material such as molybdenum, titanium, chromium, tantalum, magnesium, silver, tungsten, aluminum, copper, neodymium, scandium, or ruthenium is used. A containing layer can be used.

The insulating layers 719 and 757 have a function as a protective layer. As the insulating layers 719 and 757, for example, a layer containing a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or hafnium oxide is used. it can.

The above is the description of the structure example of the transistor illustrated in FIGS.

As described with reference to FIGS. 7A and 7B, the transistor of this embodiment can be a transistor with an off-current per channel width of 1 × 10 ⁻¹⁹ A / μm or less. Therefore, power consumption can be reduced by applying to the transistor provided between the power supply lines of the buffer and the latch described in Embodiment 1 and reducing the leakage current flowing between the power supply lines.

(Embodiment 3)
In this embodiment, an example of an electronic device using the semiconductor device which is one embodiment of the present invention will be described with reference to FIGS.

The electronic device illustrated in FIG. 8A is an example of a video recording / reproducing device.

An electronic device illustrated in FIG. 8A includes a housing 201 and a signal processing circuit 202 provided in the housing 201.

A signal processing circuit 202 illustrated in FIG. 8A includes functions of an MPU, a memory, an image processing circuit, a controller, and the like. When the signal processing circuit 202 has the structure described in Embodiment Mode 1, the leakage current between the power supply lines and the power consumption associated with charge / discharge of charges can be reduced.

Therefore, the video recording / reproducing device shown in FIG. 8A can reduce power consumption.

The electronic device illustrated in FIG. 8B is an example of a microwave oven.

An electronic device illustrated in FIG. 8B includes a housing 211 and a signal processing circuit 212 provided in the housing 211.

A signal processing circuit 212 illustrated in FIG. 8B has functions of an MPU, a memory, and the like. When the signal processing circuit 202 has the structure described in Embodiment Mode 1, the leakage current between the power supply lines and the power consumption associated with charge / discharge of charges can be reduced.

The electronic device illustrated in FIG. 8C is an example of a portable information terminal.

A portable information terminal illustrated in FIG. 8C includes a housing 221 and a signal processing circuit 222 provided in the housing 221.

A signal processing circuit 222 illustrated in FIG. 8C includes functions of an MPU, a memory, an image processing circuit, a controller, and the like. When the signal processing circuit 222 has the structure described in Embodiment Mode 1, power consumption associated with leakage current between power supply lines and charge / discharge of electric charge can be reduced.

The electronic device illustrated in FIG. 8D is an example of a laptop computer.

A notebook computer illustrated in FIG. 8D includes a housing 231 and a signal processing circuit 232 provided in the housing 231.

A signal processing circuit 232 illustrated in FIG. 8D includes functions of an MPU, a memory, an image processing circuit, a controller, and the like. When the signal processing circuit 232 has the structure described in Embodiment Mode 1, the leakage current between power supply lines and the power consumption associated with charge / discharge of charges can be reduced.

As described above, an example of an electronic device is illustrated in FIGS. 8A to 8D, but the structure of Embodiment 1 can be applied to other electronic devices as long as the electronic device includes a signal processing circuit. It is.

100 Semiconductor Device 101 Signal Processing Circuit 101_N Signal Processing Circuit 101_1 Signal Processing Circuit 101P Signal Processing Circuit 102 Buffer 103 Latch 104 Switch 104_N Switch 104_1 Switch 104P Switch 105 Power Supply Circuit 106 External Circuit 111 Transistor 112 Transistor 121 Transistor 122 Transistor 123 Transistor 124 Capacitance Element 125 Transistor 126 Transistor 129 Circuit block 130 Flip-flop 131 Transistor 132 Transistor 133 Transistor 134 Transistor 135 Buffer 139 Buffer 141 Transistor 142 Transistor 143 Transistor 151 Step 152 Step 153 Step 161 Step 162 Step 163 Step 20 Housing 202 Signal processing circuit 211 Housing 212 Signal processing circuit 221 Housing 222 Signal processing circuit 231 Housing 232 Signal processing circuit 700 Element formation layer 701 Insulating layer 711 Semiconductor layer 712a Region 712b Region 713 Channel forming region 714 Insulating layer 715 Conductive layer 716a insulating layer 716b insulating layer 717 insulating layer 718a conductive layer 718b conductive layer 719 insulating layer 750 element formation layer 751 conductive layer 752 insulating layer 753 insulating layer 754 semiconductor layer 755a conductive layer 755b conductive layer 756a conductive layer 756b conductive layer 757 Insulation layer

Claims (6)

A signal processing circuit;
A buffer for inputting and outputting signals processed by the signal processing circuit;
A switch for controlling supply of power to the signal processing circuit;
A latch for switching the switch according to the operating state of the signal processing circuit,
The buffer and the latch are semiconductor devices in which an off-current per channel width is 1 × 10 ⁻¹⁹ A / μm or less between wirings for supplying power. 2. The semiconductor device according to claim 1, wherein the transistor is an n-channel transistor in which an oxide semiconductor is used for a channel region. 3. The semiconductor device according to claim 2, wherein the buffer and the latch are unipolar circuits. 3. The semiconductor device according to claim 2, wherein the inverter included in the buffer and the latch is a complementary circuit in which the n-channel transistor and the p-channel transistor are combined. 5. The semiconductor device according to claim 1, wherein the latch is a set / reset type flip-flop. 6. The semiconductor device according to claim 5, wherein the latch controls switching of the switch in accordance with a set signal input from the outside of the semiconductor device and a reset signal input from the signal processing circuit.

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