JP2013182629A - Test system and semiconductor device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test system capable of reducing a test time, and a semiconductor device therefor.SOLUTION: A first pad 41 receives first and second test commands CMD1 and CMD2 supplied from a test device 100. A second pad 42 receives first and second monitor voltages VMONx supplied from the test device. A voltage generation circuit 13 generates a voltage to be tested based on the first and second test commands supplied from the first pad. A comparator 61 compares the voltage to be tested from the voltage generation circuit with the first monitor voltage from the second pad and outputs a first status signal, and compares the voltage to be tested from the voltage generation circuit with the second monitor voltage from the second pad and outputs a second status signal.

Description

  FIELD Embodiments described herein relate generally to a semiconductor device test system and a semiconductor device incorporating a test circuit.

  For example, a NAND flash memory uses various internal voltages for writing and reading data. In the manufacture of the NAND flash memory, the wafer tester monitors whether or not the voltage generated by the internal voltage of the NAND flash memory on the wafer is within a specified value range.

  However, monitoring the internal voltages of a plurality of NAND flash memories on the wafer took time and took a long time for testing.

JP 2002-318265 A

  The present embodiment is intended to provide a test system capable of shortening the test time and a semiconductor device thereof.

  The semiconductor device according to the embodiment includes a first pad that receives first and second test commands supplied from a test apparatus, and a second pad that receives first and second monitor voltages supplied from the test apparatus. A voltage generation circuit for generating a voltage to be tested based on the first and second test commands supplied to the first pad, and a voltage to be tested supplied from the voltage generation circuit; The first monitor voltage supplied from the second pad is compared to output one output signal of the first or second logic level as the first status signal, and the second voltage generation The voltage to be tested supplied from the circuit is compared with the second monitor voltage supplied from the second pad, and one of the output signals of the first and second logic levels is compared with the second output voltage. Status signal and A comparator for outputting Te characterized by including the.

1 is a configuration diagram showing an example of a semiconductor device according to an embodiment. The flowchart shown in order to demonstrate the test operation | movement which concerns on this embodiment. The block diagram which shows the test process which concerns on this embodiment.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a semiconductor device according to the embodiment, and shows a case where the present embodiment is applied to a NAND flash memory.

  In FIG. 1, the semiconductor device 1 includes a NAND flash memory 2, a controller 3, an ECC (Error Checking and Correcting) unit 4, an interface unit 5, and a test circuit unit 6.

<NAND flash memory 2>
The NAND flash memory 2 includes a memory cell array 10, a row decoder (RDC) 11, a page buffer 12, a voltage generation circuit 13, a NAND sequencer 14, oscillators (OSC) 15 and 16, a data transfer unit 17, and a trimming circuit 18. Yes.

  The memory cell array 10 includes a plurality of NAND strings constituted by a plurality of memory cells (not shown). The memory cells constituting these NAND strings can be selected using a plurality of word lines, selection gate lines, and bit lines (not shown).

  The row decoder 11 selects a word line and a selection gate line (not shown) when writing, reading, and erasing data, and applies a predetermined voltage to the word line and the selection gate line.

  The page buffer 12 is configured to hold data having the same size as one page of the memory cell array 10. That is, the page buffer 12 temporarily stores data for one page read from the memory cell array 10 at the time of reading, and temporarily stores data for one page to be written to the memory cell array 10 at the time of writing. . The page buffer 12 is configured to send, for example, 64-bit data designated by an address of the page data to the data transfer unit 17 and receive 64-bit data from the data transfer unit 17. Further, the page buffer 12 includes a sense amplifier (not shown) that writes write data to the memory cell array 10 and reads data from the memory cell array 10.

  The voltage generation circuit 13 generates voltages (VREF, VPASS, VREAD, VPGM, VERA, etc.) necessary for data writing, reading, and erasing, and supplies the voltages to the row decoder 11 and the like.

  The NAND sequencer 14 controls the operation of the entire NAND flash memory 2. That is, when receiving various commands from the controller 3, the NAND sequencer 14 executes sequences such as data writing, reading, and erasing in response to the commands. Furthermore, the NAND sequencer 14 controls operations of the voltage generation circuit 13 and the page buffer 12 according to various sequences.

  The oscillator 15 generates an internal clock ICLK and supplies the internal clock ICLK to the NAND sequencer 14. The NAND sequencer 14 operates in synchronization with the internal clock ICLK. The NAND sequencer 14 generates several clock signals from the internal clock ICLK and supplies the clocks to the data transfer unit 17.

  The oscillator 16 generates an internal clock ACLK and supplies the internal clock ACLK to the controller 3. The internal clock ACLK is a reference clock for the controller 3 to operate.

  The data transfer unit 17 controls data transfer between the page buffer 12 and the ECC unit 4 and data transfer between the page buffer 12 and the interface unit 5. For this control, the data transfer unit 17 includes a plurality of buses and a plurality of latch circuits (not shown).

  The trimming circuit 18 controls the voltage generated by the voltage generation circuit 13, and has a register (not shown) that holds a plurality of numerical data as parameters set in advance corresponding to the voltage to be generated. ing. When the command is supplied from the address / command generation circuit 54, the trimming circuit 18 selects numerical data corresponding to the command and supplies it to the voltage generation circuit 13. The voltage generation circuit 13 generates a voltage based on the supplied numerical data.

<ECC part 4>
When reading data from the NAND flash memory 2, the ECC unit 4 detects and corrects errors in the read data. Further, parity data is generated for data to be programmed at the time of programming to write data to the NAND flash memory 2. The ECC unit 4 includes an ECC buffer 21 and an ECC engine 22.

  The ECC buffer 21 is connected to the data transfer unit 17 by a NAND data bus. The ECC buffer 21 temporarily stores data for ECC processing (error correction at the time of data reading and generation of parity data at the time of programming). The ECC buffer 21 is connected to the data transfer unit 17 by, for example, a 32-bit data bus.

  The ECC engine 22 performs ECC processing using the data held in the ECC buffer 21. Specifically, the ECC engine 22 corrects the error of the data input to the ECC buffer 21 and outputs the corrected data to the ECC buffer 21 again.

  That is, the ECC unit 4 generates parity data for the data transferred from the interface unit 5 to the page buffer 12 when data is written. Further, when reading data, an error in the data read from the memory cell array 10 and transferred to the page buffer 12 is detected and the error is corrected.

<Interface unit 5>
The interface unit 5 includes an interface (I / F) 31, for example.

  The interface 31 exchanges various signals such as data, control signals, commands, and addresses with a host device outside the semiconductor device 1 and a test device described later via the pad 41. Examples of the control signals include a chip enable signal / CE that enables the entire semiconductor device 1, an address valid signal / AVD for latching an address, a clock CLK for burst reading, and a write enable signal for enabling a write operation / WE and an output enable signal / OE for enabling output of data to the outside. Further, the interface 31 sends a control signal related to a write request and a read request from the host device to the controller 3.

  Further, the interface 31 receives a command supplied from the test device via the pad 41 and sends it to the controller 3 at the time of a test described later, and sends a status signal output from the test circuit 6 to the test device via the pad 41. send.

<Controller 3>
The controller 3 controls the operation of the entire semiconductor device 1. The controller 3 includes a register 51, a command user interface (CUI) 52, a state machine 53, an address / command generation circuit 54, and an address / timing generation circuit (Add / Timing) 55.

  The register 51 holds, for example, a read command, a write command, and a test command supplied from the interface 31.

  The command user interface 52 recognizes that a function execution command is given to the semiconductor device 1 by holding a predetermined command in the register 51, and sends an internal command signal to the state machine 53.

  The state machine 53 controls the sequence operation in the semiconductor device 1 based on the internal command signal supplied from the command user interface 52. The state machine 53 supports many functions including writing, reading, and erasing. The state machine 53 controls the operation of the NAND flash memory 2 so as to execute these functions.

  The address / command generation circuit 54 controls the operation of the NAND flash memory 2 based on the control of the state machine 53. Specifically, the address / command generation circuit 63 generates an address, a command (Write / Read / Load) and the like for controlling the operation of the NAND flash memory 2 in synchronization with the internal clock ACLK supplied from the oscillator 16. These are sent to the NAND sequencer 14.

  Further, the address / command generation circuit 63 generates commands CMD_UVMON and CMD_OVMON and supplies them to the trimming circuit 18 and the data inversion circuit 62 when the voltage generation circuit 13 generates a voltage. The trimming circuit 18 increases the voltage generated by the voltage generation circuit 13 when the command CMD_OVMON is the signal “0”, and generates the voltage generation circuit 13 when the command CMD_UVMON is the signal “0”. Reduce voltage.

  In the test of the voltage generation circuit 13 described later, both the command CMD_UVMON and the command CMD_OVMON are set to “1”. For this reason, the operation of the trimming circuit 18 is stopped, and the voltage generation circuit 13 generates the voltage selected by the command at the time of the test without trimming.

  The address / timing generation circuit 55 controls the operation of the ECC engine 22 based on the control of the state machine 53. Specifically, the ECC engine 22 issues necessary addresses and commands and supplies them to the ECC engine 22.

<Test circuit 6>
The test circuit 6 tests whether or not the voltage generated by the voltage generation circuit 13 is within a specified range in the manufacturing process of the semiconductor device, and outputs a test result. During the test, the wafer on which the semiconductor device 1 is formed is mounted on the test device 100, and a probe (not shown) of the test device 100 is brought into contact with the pads 41 and 42 of the semiconductor device 1. In this state, a command indicating the test content is supplied from the test apparatus 100 to the pad 41, and a reference voltage corresponding to the command is supplied to the pad 42.

  As will be described later, the test circuit 6 compares the voltage to be tested generated by the voltage generation circuit 13 according to the command with the monitor voltage supplied from the test apparatus 100, and outputs the comparison result to the test apparatus 100 as a status signal. To do.

  Specifically, the test circuit 6 includes a comparator 61, a data inversion circuit 62, and a status holding circuit 63.

  The comparator 61 compares the monitor voltage VMONx as the reference voltage supplied to the test pad 42 with the voltage to be tested (for example, VREF) generated by the voltage generation circuit 13. The monitor voltage VMONx is changed by the test apparatus 100 according to the voltage to be tested generated by the voltage generation circuit 13.

  Further, the monitor voltage VMONx is composed of two voltages, that is, an upper limit value and a lower limit value of the voltage generated by the voltage generation circuit 13 in response to the command. When the voltage (for example, VREF) generated by the voltage generation circuit 13 is, for example, 12V, the upper limit monitor voltage VMONx is set to, for example, 13V, and the lower limit monitor voltage VMONx is set to, for example, 11V.

  For example, the comparator 61 first compares the lower limit monitor voltage VMONx with the voltage VREF generated by the voltage generation circuit 13, and then compares the upper limit monitor voltage VMONx with the voltage VREF generated by the voltage generation circuit 13. Compare That is, the comparator 61 outputs a low level (“0”) as the output signal FLTRIML when the voltage VREF generated by the voltage generation circuit 13 is larger than the lower limit monitor voltage VMONx (11 V). When the voltage VREF generated by the above is smaller than the upper limit monitor voltage VMONx (13 V), a high level (“1”) is output as the output signal FLTRIML.

VMONx (11V) <VREF = “0”
VMONx (13V)> VREF = “1”
The output signal FLTRIML of the comparator 61 is supplied to the trimming circuit 18 and the data inverting circuit 62. As will be described later, the trimming circuit 18 is stopped when the internal command CMD_UVMON supplied from the address / command generation circuit 54 is at a high level and when CMD_OVMON is at a high level.

  The internal command CMD_UVMON is a command for comparing the upper limit monitor voltage VMONx with the voltage VREF generated by the voltage generation circuit 13. The internal command CMD_OVMON is generated by the lower limit monitor voltage VMONx and the voltage generation circuit 13. This is a command for comparing the applied voltage VREF.

  The data inverting circuit 62 outputs the output signal FLTRIML of the comparator 61 as it is when the internal command CMD_UVMON is at a high level, and inverts and outputs the output signal FLTRIML of the comparator 61 when the internal command CMD_OVMON is at a high level. To do. That is, the comparator 61 compares the lower limit monitor voltage VMONx with the voltage VREF generated by the voltage generation circuit 13, VMONx (11V) <VREF, and the output signal FLTRIML of the comparator 61 is the signal “0”. At this time, this signal “0” is inverted and output as a signal “1”. The output signal of the data inverting circuit 62 is temporarily held in the status holding circuit 63 and supplied to the test apparatus via the interface 31 and the pad 41.

(Test operation)
FIG. 2 shows the operation of the test apparatus 100. The operation of the test circuit 6 shown in FIG. 1 will be described with reference to FIG.

  As described above, when testing the voltage generated by the voltage generation circuit 13 of the semiconductor device in the manufacturing process of the semiconductor device, the wafer on which the semiconductor device is formed is mounted on the test apparatus 100 and the test apparatus 100 is shown in FIG. A probe (not shown) is brought into contact with the pads 41 and 42 of the semiconductor device 1.

  In this state, the test apparatus 100 selects a voltage to be tested (S11). This voltage is the voltage VERF, VPASS, VREAD, etc., as described above. Here, VERF is a reference voltage, VPASS is a voltage for turning on a non-selected memory cell when writing to the NAND flash memory, and VREAD is a voltage for turning on a non-selected memory cell during reading. Here, it is assumed that the reference voltage VREF is selected.

  Next, the test apparatus 100 issues a command CMD1 for testing the lower limit value of the selected voltage VREF (S12). Here, the command CMD1 is a command for executing a test operation, and includes a portion indicating a voltage to be tested and a portion indicating an upper limit test or a lower limit test.

  The command CMD1 is supplied to the pad 41, the interface 31, the register 51, the CUI 52, the state machine 53, and the address / command generation circuit 54 of the semiconductor device 1 in FIG. The address / command generation circuit 54 generates an internal command CMD_OVMON (“1”) based on the command CMD1. This internal command CMD_OVMON is supplied to the trimming circuit 18. The trimming circuit 18 does not perform the trimming operation when the internal command CMD_OVMON is “1”. Therefore, the voltage generation circuit 13 generates a voltage VREF of 11V according to a parameter set in advance based on the signal Param_IN. The generated voltage VREF is supplied to one input terminal of the comparator 61.

  Next, the test apparatus 100 generates a lower limit value of the monitor voltage VMONx of the voltage to be tested and supplies it to the pad 42 of the semiconductor device 1 (S13). That is, in this example, the test apparatus 100 supplies the pad 42 with the lower limit value (11V) of VREF (12V) as the lower limit value of the monitor voltage VMONx. The lower limit value of the monitor voltage VMONx is supplied from the pad 42 to the other input terminal of the comparator 61.

  The comparator 61 compares the lower limit value of the monitor voltage VMONx with the voltage VREF generated by the voltage generation circuit 13. As a result, when the relationship of VMONx (11V) <VREF (12V) is satisfied, the comparator 61 outputs the signal “0” as the output signal FLGTRIML. This signal FLGTRIML is supplied to the data inversion circuit 62. When the internal command CMD_OVMON is “1”, the data inversion circuit 62 inverts the input data and outputs it. For this reason, the signal FLGTRIML = "0" is inverted, and the data inverting circuit 62 outputs a status signal A = "1" indicating that the test result is a pass. This signal A = “1” is temporarily held in the status holding circuit 63.

  On the other hand, if the comparison does not satisfy the relationship of VMONx (11V) <VREF (12V), the comparator 61 outputs a signal “1” as the output signal FLGTRIML. This signal FLGTRIML is inverted by the data inversion circuit 62 and output. For this reason, the signal FLGTRIML = "1" is inverted, and the data inverting circuit 62 outputs a status signal A = "0" indicating that the test result is "fail". This signal A = “0” is temporarily held in the status holding circuit 63.

  A status signal A indicating a pass or a failure held in the status holding circuit 63 is read when a status read command is issued from the test apparatus 100 and is supplied to the test apparatus 100 via the interface 31 and the pad 41.

  The test apparatus 100 determines whether the status signal A is a pass (S14). As a result, when the status signal A indicates a failure, the semiconductor device 1 is rejected and the test operation is terminated (S19).

  On the other hand, when the status signal A indicates a path, the test apparatus 100 issues a command CMD2 for testing the upper limit value of the selected voltage (S15).

  The command CMD2 is supplied to the address / command generation circuit 54 via the pad 41, the interface 31, the register 51, the command user interface 52, and the state machine 53 of the semiconductor device 1 in FIG. The address / command generation circuit 54 generates a command CMD_UVMON (“1”) for testing the upper limit value in accordance with the supplied command. This internal command CMD_UVMON is supplied to the trimming circuit 18. The trimming circuit 18 does not perform trimming when the internal command CMD_UVMON is “1”. For this reason, the voltage generation circuit 13 generates a voltage VREF of 13V according to a parameter set in advance based on the signal Param_IN. The generated voltage VREF is supplied to one input terminal of the comparator 61.

  Next, the test apparatus 100 generates an upper limit value of the monitor voltage VMONx of the voltage to be tested and supplies it to the pad 42 of the semiconductor device 1 (S16). That is, in this example, the test apparatus 100 supplies the pad 42 with the upper limit value (13V) of VREF (12V) as the upper limit value of the monitor voltage VMONx. The upper limit value of the monitor voltage VMONx is supplied from the pad 42 to the other input terminal of the comparator 61.

  The comparator 61 compares the upper limit value of the monitor voltage VMONx with the voltage VREF generated by the voltage generation circuit 13. As a result, when the relationship of VMONx (13V)> VREF (12V) is satisfied, the comparator 61 outputs a signal “1” as the output signal FLGTRIML. This signal FLGTRIML is supplied to the data inversion circuit 62. When the internal command CMD_UVMON is “1”, the data inverting circuit 62 outputs the input data as it is without inverting it. Therefore, the data inverting circuit 62 outputs a status signal A = “1” indicating that the test result is a pass. This signal A = “1” is temporarily held in the status holding circuit 63.

  On the other hand, if the comparison does not satisfy the relationship of VMONx (13V)> VREF (12V), the comparator 61 outputs a signal “0” as the output signal FLGTRIML. This signal FLGTRIML is also output as it is without being inverted by the data inversion circuit 62. Therefore, the data inverting circuit 62 outputs a status signal A = “0” indicating that the test result is “fail”. The status signal A = “0” is temporarily held in the status holding circuit 63.

  A status signal A indicating a pass or a failure held in the status holding circuit 63 is read when a status read command is issued from the test apparatus 100 and is supplied to the test apparatus 100 via the interface 31 and the pad 41.

  Next, the test apparatus 100 determines whether the status signal A is a pass (S17). As a result, when the status signal A indicates a failure, the semiconductor device 1 is rejected and the test operation is terminated (S19).

  On the other hand, if the status signal A indicates a pass, it is determined whether or not all the voltage tests have been completed (S18). As a result, if it is not completed, the control proceeds to step S11, the voltage to be tested next is selected, and the same operation as described above is repeated.

  If it is determined in step S19 that all voltage tests have been completed, it is determined that the voltage test of the semiconductor device 1 has passed (S20).

(Test equipment)
FIG. 3 shows the relationship between the test apparatus 100 and a plurality of semiconductor devices (semiconductor chips) as a DUT (Device Under Test).

  As shown in FIG. 3, the test apparatus 100 includes a voltage generation circuit 101 and a control unit 102. The control unit 102 simultaneously supplies the above-described command CMD1 or CMD2 to the plurality of semiconductor devices 1 provided on the wafer 110, and monitors the lower limit value of the voltage to be tested generated by the voltage generation circuit 101. The voltage VMONx or the monitor voltage VMONx as the upper limit value is simultaneously supplied to the plurality of semiconductor devices 1. Each semiconductor device 1 internally compares the monitor voltage VMONx with the voltage generated by the voltage generation circuit 13 by the comparator 61 and holds the comparison result in the status holding circuit 63 as the status signal A. The status signal A held in the status holding circuit 63 of each semiconductor device 1 is taken into the test apparatus 100 simultaneously by issuing a status read command from the control unit 102, and the status signal A is passed by the control unit 102. It is determined whether there is a failure or not.

  The test apparatus 100 does not need a plurality of measurement circuits for measuring the voltage output from each semiconductor device unlike a general test apparatus. For this reason, a structure can be simplified. In addition, since a plurality of semiconductor devices 1 can be tested simultaneously, the test time can be shortened.

  According to the embodiment, the comparator 61 is provided inside the semiconductor device 1, and the voltage to be tested generated by the voltage generation circuit 13 in the semiconductor device 1 and the monitor voltage VMONx supplied from the test device 100 are obtained. The comparison is made by the comparator 61 and the comparison result is supplied to the test apparatus 100 as the status signal A. For this reason, the semiconductor device 1 does not supply the voltage generated by the voltage generation circuit 13 to the test device 100, but supplies a status signal indicating the comparison result to the test device 100, and the test device 100 supplies from the semiconductor device 1. It is determined whether the status signal supplied from the semiconductor device 1 is a pass or a fail without comparing whether or not the applied voltage is within the range of the specified value. Therefore, the configuration of the test apparatus can be simplified and the test time can be shortened.

  That is, according to the present embodiment, during the test, the semiconductor device 1 receives the command CMD1 indicating the voltage to be tested and the lower limit value from the test device 100, or the command CMD2 indicating the voltage to be tested and the upper limit value. The voltage VMONx indicating the lower limit value of the voltage to be tested or the voltage VMONx indicating the upper limit value is received from the test apparatus 100, and the voltage output from the voltage generation circuit 13 and the voltage VMONx indicating the lower limit value or the upper limit value are compared. The comparison result is supplied to the test apparatus as a status signal. For this reason, a test circuit that receives a voltage to be tested from a plurality of semiconductor devices 1 and determines whether the voltage is within a specified upper limit value and lower limit value in the test device, as in a general test device. There is no need to have. Therefore, it is possible to simplify the configuration of the test apparatus.

  In the case of a general test apparatus, the number of test circuits is smaller than the number of semiconductor chips on the wafer. For this reason, when testing the voltage supplied from each semiconductor device in the test apparatus, the test apparatus needs to sequentially test the voltages supplied from a plurality of semiconductor devices included in the wafer. Therefore, a long time is required for the test.

  On the other hand, in the case of this embodiment, the semiconductor device 1 has the test circuit 6 and, as shown in FIG. 3, the command and voltage are simultaneously supplied from the test device 71 to each semiconductor device 72. The status signal A output from 72 can be taken into the test apparatus 71 at the same time. For this reason, it is possible to greatly reduce the test time.

  Further, the monitor voltage VMONx output from the test apparatus 100 has little variation depending on the test apparatus. For this reason, when testing a plurality of wafers simultaneously using a plurality of test devices, each semiconductor device can be tested using an accurate voltage output from each test device, so an accurate test is performed. It is possible.

  In addition, the data inversion circuit 62 of the semiconductor device 1 inverts the comparison result (signal FLGTRIML) between the voltage output from the voltage generation circuit 13 by the comparator 61 and the lower limit monitor voltage VMONx and supplies the result to the status holding circuit 63. The comparison result (signal FLGTRIML) between the voltage output from the voltage generation circuit 13 by the comparator 61 and the upper limit monitor voltage VMONx is supplied to the status holding circuit 63 without being inverted. Therefore, the status holding circuit 63 can hold both the lower limit value and the upper limit value test result of the test target voltage as the status signal A = “1”. Therefore, the test apparatus can handle the pass result of the test of the upper limit value and the lower limit value as the stator signal A = “1”, so that the pass or fail can be determined at high speed.

  In the above embodiment, the case where the present embodiment is applied to the NAND flash memory has been described. However, the present embodiment is not limited to this, and it is needless to say that the embodiment can be applied to a semiconductor device that generates various voltages inside. Yes.

  In addition, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... NAND flash memory, 6 ... Test circuit, 13 ... Voltage generation circuit, 41, 42 ... Pad, 61 ... Comparator, 62 ... Data inversion circuit, 63 ... Status circuit, 100 ... Test apparatus.

Claims (7)

A first voltage generation circuit for generating a first monitor voltage for monitoring a lower limit voltage of the voltage to be tested in the semiconductor device and a second monitor voltage for monitoring the upper limit voltage;
A control unit that issues a first test command for testing the lower limit voltage and a second test command for testing the upper limit voltage;
The control unit supplies the first test command for testing the voltage of the lower limit value, and the first monitor voltage to the semiconductor device,
It is determined whether the first status signal supplied from the semiconductor device is pass or fail, and if it is pass, the second test command and the second monitor voltage are supplied to the semiconductor device,
A test device for determining whether the second status signal supplied from the semiconductor device is pass or fail;
A first pad for receiving first and second test commands supplied from the test apparatus;
A second pad for receiving first and second monitor voltages supplied from the test apparatus;
A second voltage generation circuit for generating the voltage to be tested based on the first and second test commands supplied to the first pad;
One voltage of the first or second logic level is compared by comparing the voltage to be tested supplied from the second voltage generating circuit with the first monitor voltage supplied from the second pad. A signal is output as the first status signal, and the voltage to be tested supplied from the second voltage generation circuit is compared with the second monitor voltage supplied from the second pad. A comparator that outputs one of the output signals of the first and second logic levels as the second status signal;
A test system comprising:   Based on the first test command, the output signal of the comparator is inverted and supplied to the first pad, and based on the second test command, the output signal of the comparator is output without being inverted. The test system according to claim 1, further comprising a data inverting unit. A holding unit that holds the first or second status signal output from the data inverting unit;
3. The test system according to claim 2, wherein the first or second status signal held in the holding unit is read by a command supplied from the test apparatus and is supplied to the test apparatus. A voltage generation circuit for generating a first monitor voltage for monitoring a lower limit voltage of the voltage to be tested of the semiconductor device and a second monitor voltage for monitoring the upper limit voltage;
A control unit that issues a first test command for testing the lower limit voltage and a second test command for testing the upper limit voltage;
The control unit supplies the first test command for testing the voltage of the lower limit value, and the first monitor voltage to the semiconductor device,
It is determined whether the first status signal supplied from the semiconductor device is pass or fail, and if it is pass, the second test command and the second monitor voltage are supplied to the semiconductor device,
A test apparatus for determining whether the second status signal supplied from the semiconductor device is pass or fail. A first pad for receiving first and second test commands supplied from a test apparatus;
A second pad for receiving first and second monitor voltages supplied from the test apparatus;
A voltage generation circuit for generating a voltage to be tested based on the first and second test commands supplied to the first pad;
The voltage to be tested supplied from the voltage generation circuit is compared with the first monitor voltage supplied from the second pad, and one output signal of the first or second logic level is set as the output signal. The first status signal is output as a first status signal, and the voltage to be tested supplied from the voltage generation circuit is compared with the second monitor voltage supplied from the second pad to compare the first and second voltages. A comparator that outputs one output signal of logic level as the second status signal;
A semiconductor device comprising:   Based on the first test command, the output signal of the comparator is inverted and supplied to the first pad, and based on the second test command, the output signal of the comparator is output without being inverted. 6. The semiconductor device according to claim 5, further comprising a data inverting unit. A holding unit that holds the first or second status signal output from the data inverting unit;
7. The semiconductor device according to claim 6, wherein the first or second status signal held in the holding unit is read by a command supplied from the test apparatus and is supplied to the test apparatus.

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