JP2013182565A - Information processor, microcontroller, information processing system, and information processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor, a microcontroller, an information processing system, and an information processing method which can shorten the time to be operable after a reset release signal is input.SOLUTION: An information processing device 100 includes: an operation setting terminal 101; a power supply terminal 102; a reset terminal 103; a first circuit 110 that operates on the basis of a first setting value; and a second circuit 120 that operates on the basis of a second setting value. The first circuit 110 obtains the first setting value from the operation setting terminal 101 in response to the input of power supply to the power supply terminal 102. After the input of power supply, the second circuit 120 obtains the second setting value from the operation setting terminal 101 in response to the input of a reset release signal to the reset terminal 103.

Description

  The present invention relates to an information processing device, a microcontroller, an information processing system, and an information processing method, and particularly relates to a reset control technique.

  Conventionally, there has been proposed an information processing apparatus that takes operation setting information from an operation setting terminal in accordance with a reset release signal and performs an operation based on the operation setting information.

  Patent Document 1 discloses a semiconductor integrated circuit capable of switching an operation mode by taking an operation mode setting signal as the operation setting information from an operation mode setting terminal. In this integrated circuit, the CPU starts the operation with a reset release signal input from the outside as a trigger, and thereafter the operation mode switching process is executed. Therefore, a certain time is required until the CPU starts operating in the set operation mode.

  FIG. 8 shows a configuration of an integrated circuit according to Patent Document 1. FIG. 9 shows a timing chart of the operation of the integrated circuit. When a reset release signal is input to the external reset terminal 18 (t0), the CPU 11 reads the counter value from the nonvolatile memory 13 via the memory controller 12 and stores it in the registers 14a to 14c (t1). When a pulse signal is input to the operation mode setting terminal 15 (t2), the multiplexers 17a to 17c compare the values of the pulse counter 16 and the registers 14a to 14c, and output a matching value H to the CPU 11 ( t3). The CPU 11 starts the operation in the operation mode corresponding to the value H.

  As described above, the integrated circuit according to Patent Document 1 takes in the pulse signal as the operation mode setting signal using the external reset release signal as a trigger and determines the operation mode of the CPU. It takes a certain amount of time.

  Patent Document 2 discloses a configuration for reducing the time required from the reset release to the start of the operation of the CPU as described above. The microcomputer according to Patent Document 2 identifies the type of reset, that is, whether it is a cold start or a warm start when reset is released. In the case of the warm start, the microcomputer omits the control parameter reading process by not initializing the tune data (corresponding to the operation setting information) already developed on the flash ROM.

  Patent Document 3 describes that default data (corresponding to the operation setting information) is loaded from the outside of an integrated circuit chip at power-on.

JP 2008-076173 A JP 2010-039812 A JP 2001-110711 A

  However, since the microcomputer according to Patent Document 2 initializes the flash ROM by using the reset release signal as a trigger at the time of cold start and reads the tune data, there is a problem that the startup time of the CPU is not shortened.

  Further, Patent Document 3 does not disclose or suggest a specific configuration for solving the problem of loading default data at power-on or an effect obtained by the configuration.

  All of the devices described in these patent documents collectively read operation setting information when a predetermined trigger such as a reset release signal is given. By the way, this operation setting information is often composed of a plurality of pieces of information, and these pieces of information are in a dependency relationship.

  For example, it is assumed that the operation setting information includes a first setting value and a second setting value. A device, for example, a microcontroller, reads these operation setting information at a time when a trigger is given. Thereafter, first, a first circuit in the apparatus, for example, a PLL (Phase Locked Loop) starts an operation such as a lockup count based on a first set value, for example, a set value of a multiplication factor and a lockup time. Next, a second circuit, for example, a CPU (Central Processing Unit) starts operation based on the second setting, for example, the setting value of the operation mode, and the frequency defined by the PLL. Thus, the microcontroller is ready for operation.

  As described above, a conventional device, for example, a microcontroller, collectively reads operation setting information including a plurality of pieces of information, and then sequentially executes setting operations based on the plurality of pieces of information. Therefore, it takes a certain time from when the trigger for reading the operation setting information is given until the microcontroller can operate.

  Further, a conventional apparatus, for example, a microcontroller, reads operation setting information after a predetermined trigger is given. However, this trigger input may be delayed for some reason. For example, when a microcontroller is incorporated as a part of the system, the control unit of the system uses a reset release signal as an operation start trigger of the microcontroller in order to synchronize the other components of the system with the microcontroller. There is a possibility of delaying the output time. At this time, the time from when the system and the microcontroller are turned on until the reset release signal is input to the microcontroller is delayed by the delay of the reset release signal.

  On the other hand, there is always a need to reduce the startup time of a microcontroller. Therefore, it is required to further shorten the time from when the reset release signal as a trigger is given until the microcontroller can operate. Further, even if the input of the reset release signal from the outside is delayed, it is desirable to minimize the influence on the time required from when the power is turned on until the microcontroller can operate.

  An information processing apparatus according to the present invention includes a power supply terminal for inputting power, a reset terminal for inputting a reset release signal, an operation setting terminal for inputting a first set value and a second set value, and the first A first circuit that operates based on the set value and a second circuit that operates based on the second set value, the first circuit serving as an input of the power supply to the power supply terminal. Accordingly, the first setting value is obtained from the operation setting terminal, and the second circuit is configured to perform the operation setting in response to an input of the reset release signal to the reset terminal after the power is input. The second set value is obtained from a terminal.

  In the information processing apparatus according to the present invention, the first circuit operates with the power-on as a trigger without waiting for the input of the reset-release signal, and the second circuit operates with the input of the reset-release signal as a trigger With this configuration, it is possible to shorten the time from when the reset release signal is input until the microcontroller becomes operable.

  A microcontroller according to the present invention includes a processor, a power supply terminal for inputting power, a reset terminal for inputting a reset release signal, an operation setting terminal for inputting a first set value and a second set value, A first circuit that obtains the first setting value from the operation setting terminal in response to an input of the power supply to the power supply terminal, and outputs first operation information based on the first setting value to the processor And after the input of the power supply, the second setting value is acquired from the operation setting terminal in response to the input of the reset release signal to the reset terminal, and the second operation based on the second setting value A second circuit for outputting information to the processor, the processor in response to the input of the first operation information and the second operation information, the first operation information and the second operation information Operation It is intended to start the operation based on.

  In the microcontroller according to the present invention, the first circuit operates with the power-on as a trigger without waiting for the input of the reset release signal, and the second circuit operates with the input of the reset release signal as a trigger. With this configuration, it is possible to shorten the time from when the reset release signal is input until the microcontroller becomes operable.

  An information processing system according to the present invention includes a control device, a first information processing device, and at least one second information processing device, wherein the control device includes the first information processing device and the first information processing device. A reset release signal indicating a timing at which the processing should be started, and the first information processing device includes a power supply terminal for inputting power and a reset terminal for inputting the reset release signal. , An operation setting terminal for inputting the first set value and the second set value, a first circuit operating based on the first set value, and a first circuit operating based on the second set value. The first circuit acquires the first set value from the operation setting terminal according to the input of the power supply to the power supply terminal, and the second circuit includes: After the power is input, the reset terminal That in response to input of the reset release signal, and acquires the second set value from the operation setting terminals.

  In the information processing system according to the present invention, the first circuit does not wait for the input of the reset release signal and operates with the power-on as a trigger, and the second circuit operates with the input of the reset release signal as a trigger With this configuration, it is possible to shorten the time from when the reset release signal is input until the microcontroller becomes operable.

  In the information processing method according to the present invention, the first circuit obtains the first set value from the operation setting terminal according to the input of the power supply to the power supply terminal, and the second circuit includes the power supply And a step of acquiring a second set value from the operation setting terminal in response to an input of a reset release signal to the reset terminal.

  In another information processing method according to the present invention, the control device supplies a reset release signal indicating a timing to start processing to the first information processing device and at least one second information processing device. A first circuit of the first information processing apparatus acquiring the first set value from an operation setting terminal in response to an input of power to the power terminal; and the first information processing. The second circuit of the apparatus includes a step of obtaining a second set value from the operation setting terminal in response to the input of the reset release signal to the reset terminal after the power supply is input.

  In these information processing methods according to the present invention, the first circuit does not wait for the input of the reset release signal and operates with the power-on as a trigger, and the second circuit triggers the input of the reset release signal. As a result, the time from when the reset release signal is input to when the microcontroller becomes operable can be shortened.

  According to the present invention, it is possible to provide an information processing apparatus, a microcontroller, an information processing system, and an information processing method that can shorten the time from when a reset release signal is input to when the signal becomes operable.

1 is a diagram illustrating a configuration of an information processing apparatus 100 according to a first embodiment. 1 is a diagram illustrating a configuration of a microcontroller 200 according to a first embodiment. FIG. 3 is a diagram illustrating processing of the microcontroller 200 according to the first embodiment. It is a figure which shows the structure of the information processing system 300 concerning Embodiment 2. FIG. FIG. 6 is a diagram illustrating a configuration of a microcontroller 400 according to a third embodiment. FIG. 10 is a diagram illustrating processing of the microcontroller 400 according to the third embodiment. FIG. 6 is a diagram illustrating a configuration of a microcontroller 500 according to a fourth embodiment. It is a figure which shows the structure of the conventional microcontroller. It is a figure which shows the process of the conventional microcontroller.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

<Embodiment 1>
First, the configuration of the information processing apparatus 100 according to the first embodiment of the present invention will be described with reference to FIG.

  The information processing apparatus 100 includes an operation setting terminal 101, a power supply terminal 102, a reset terminal 103, a first circuit 110, and a second circuit 120.

  The operation setting terminal 101, the power supply terminal 102, and the reset terminal 103 are all external input terminals. The operation setting terminal 101 is a terminal for inputting operation setting information for setting the operation of the information processing apparatus 100 from the outside. In the present embodiment, it is assumed that the operation setting information includes the first setting value and the second setting value. Here, the first set value is input to the operation setting terminal 101 at substantially the same time as the power is input to the power terminal 102 described later. The second set value is input to the operation setting terminal 101 at substantially the same time as a reset release signal is input to the reset terminal 103 described later. The power supply terminal 102 is a terminal for inputting power from the outside. The reset terminal 103 is a terminal for inputting a reset release signal for releasing the reset state of the information processing apparatus 100 from the outside.

  Both the first circuit 110 and the second circuit 120 are circuits for setting the operation of the information processing apparatus 100. The first circuit 110 detects input of power to the power terminal 102 and reads a first set value input to the operation setting terminal 101. Furthermore, the first circuit 110 performs a first setting process for setting the operation of the information processing apparatus 100 based on the acquired first setting value. The second circuit 120 detects the input of the reset release signal to the reset terminal 103 and reads the second setting value input to the operation setting terminal 101. Furthermore, the second circuit 120 performs a second setting process for setting the operation of the information processing apparatus 100 based on the acquired second setting value.

  FIG. 2 shows a microcontroller 200 as a specific example of the information processing apparatus 100.

  The microcontroller 200 includes an operation setting terminal 101, a power supply terminal 102, and a reset terminal 103. The microcontroller 200 also includes a power ON detection circuit 111 as a first circuit 110, a circuit operation speed capturing circuit 112, a circuit operation speed setting circuit 113, and a clock setting circuit 114. Further, the microcontroller 200 includes an operation mode setting circuit 121 as the second circuit 120. Furthermore, the microcontroller 200 includes a CPU 230 and a memory 240.

  The roles of the operation setting terminal 101, the power supply terminal 102, and the reset terminal 103 are the same as those of the information processing apparatus 100. That is, these terminals function as external input terminals for operation setting information, power supply, and reset release signal, respectively.

  The power ON detection circuit 111 is a circuit that detects input of power to the power terminal 102 and outputs a power ON detection signal to the circuit operation speed capturing circuit 112. The power ON detection circuit 111 outputs a power ON detection signal when, for example, the input voltage to the power terminal 102 exceeds a predetermined threshold.

  The circuit operation speed capturing circuit 112 captures operation setting information, more specifically the first set value, from the operation setting terminal 101 when a power ON detection signal is input from the power ON detection circuit 111, and circuit operation This is a circuit for outputting to the speed setting circuit 113.

  The circuit operation speed setting circuit 113 is a circuit that holds the first set value acquired by the circuit operation speed acquisition circuit 112 and outputs it to the clock setting circuit 114.

  The clock setting circuit 114 is a circuit that sets the clock frequency of the CPU 230, and is typically a PLL. The first set value output from the circuit operation speed setting circuit 113 includes a multiplication rate and a lockup time. The clock setting circuit 114 determines the multiplication rate of the clock pulse supplied to the CPU 230 based on this multiplication rate. Further, the clock setting circuit 114 performs a lockup count operation based on the lockup time.

  The operation mode setting circuit 121 fetches and holds operation setting information, more specifically, the second setting value from the operation setting terminal 101 when a reset release signal is input to the reset terminal 103, and outputs it to the CPU 230. Circuit.

  The CPU 230 is a control device that controls information processing in the microcontroller 200. The CPU 230 operates at a frequency based on the clock pulse supplied from the clock setting circuit 114. In addition, the CPU 230 determines an operation mode based on the second set value output from the operation mode setting circuit 121, and operates according to the operation mode.

  The memory 240 is a storage device that stores programs and data necessary when the CPU 230 performs information processing, and is, for example, a ROM, a RAM, and a cache memory.

  The operation mechanism of the microcontroller 200 will be described using the timing chart of FIG.

  S101: Power is input to the power terminal 102 (1). At this time, the power supply ON detection circuit 111 outputs a power supply ON detection signal when the power supply voltage exceeds a predetermined threshold (2). At this time, the power is also supplied to at least the circuit operation speed capturing circuit 112, the circuit operation speed setting circuit 113, and the clock setting circuit 114. Accordingly, these circuits 112 to 114 can perform a predetermined operation even before the reset release signal is input.

  The PLL as the clock setting circuit 114 starts the operation of the oscillator as soon as power is supplied (3). The oscillator operates at a stable frequency as the oscillation stabilization period elapses after the operation starts.

  When the power ON detection signal is input from the power ON detection circuit 111, the circuit operation speed acquisition circuit 112 acquires the first set value input to the operation setting terminal 101 (6, 7). The circuit operation speed setting circuit 113 outputs the first set value to the PLL 114 (7).

  S102: When the oscillation stabilization period ends, the PLL 114 starts the lockup count operation based on the first set value output from the circuit operation speed setting circuit 113, that is, the multiplication factor and the lockup time (4). The PLL 114 completes the lockup count operation after the lockup period, and starts supplying clock pulses to the CPU 230.

  S103: A reset release signal is input to the reset terminal 103 (5). At this time, the operation mode setting circuit 121 starts operation, and takes in the second set value input to the operation setting terminal 101 (6, 7). The operation mode setting circuit 121 outputs the second set value, that is, the operation mode to the CPU 230.

  S104: The CPU 230 starts operation (8). Here, the CPU 230 operates in accordance with the frequency based on the clock pulse supplied from the PLL 114 and the operation mode based on the second set value output from the operation mode setting circuit 121.

  In this manner, the microcontroller 200 performs the setting operation by taking in the first setting value before inputting the reset cancellation signal and taking in the second setting value after inputting the reset cancellation signal.

  The conventional general microcontroller stops all operations until the reset release signal is input, and starts the operation with the input of the reset release signal as a trigger. That is, the reset release signal has a meaning as a trigger signal for starting the operation of the entire microcontroller.

  However, the present inventor has found that the microcontroller includes a circuit that can operate without being affected by the reset release signal, that is, a circuit that performs a process that can be executed without waiting for the input of the reset release signal. It was discovered that a part of the setting information is information used in a circuit that is not affected by the reset release signal.

  Therefore, in this embodiment, the first circuit 110 (the circuit operation speed capturing circuit 112, the circuit operation speed setting circuit 113, and the clock setting circuit 114) is turned on without waiting for the input of the reset release signal. The second circuit 120 (operation mode setting circuit 121) operates as a trigger, and is configured to operate using a reset release signal input as a trigger. As a result, the time from when the reset release signal is input to when the microcontroller becomes operable can be shortened.

<Embodiment 2>
Next, the configuration of the information processing system 300 according to the second exemplary embodiment of the present invention will be described with reference to FIG.

  The information processing system 300 includes the microcontroller 200 according to the first embodiment as a component. The information processing system 300 includes a reset control IC 310 and sensor ICs 321 to 323.

  The reset control IC 310 is an IC that controls the operation of the information processing system 300, and controls the activation timing by outputting a reset release signal to the microcontroller 200 and the sensor ICs 321 to 323 at a predetermined timing.

  The sensor ICs 321 to 323 are ICs for controlling sensors that acquire various information inside and outside the automobile, for example. The sensor ICs 321 to 323 execute predetermined processing in cooperation with the microcontroller 200. The sensor ICs 321 to 323 start operation with a reset release signal output from the reset control IC 310 as a trigger.

  Subsequently, an operation mechanism of the information processing system 300 according to the second exemplary embodiment of the present invention will be described.

  The information processing system 300 is turned on. The power is supplied to the reset control IC 310, the microcontroller 200, and the sensor ICs 321 to 323. When the microcontroller 200 detects the power-on, the first circuit 110 (the circuit operation speed capturing circuit 112, the circuit operation speed setting circuit 113, the clock, and the like) according to the operation mechanism shown as S101 to S102 in the first embodiment. The setting circuit 114) performs a first setting value capturing operation.

  The reset control IC 310 outputs a reset release signal to the sensor ICs 321 to 323. The sensor ICs 321 to 323 start a predetermined initial operation with a reset release signal as a trigger. Upon completion of the initial operation, the sensor ICs 321 to 323 notify the reset control IC 310 to that effect. Here, the time required for the initial operation may vary depending on the situation.

  When the reset control IC 310 detects the completion of the initial operation in the sensor ICs 321 to 323, the reset control IC 310 outputs a reset release signal to the microcontroller 200. When the microcontroller 200 detects the input of the reset release signal, it takes in the second set value by the second circuit 120 (operation mode setting circuit 121) in accordance with the operation mechanism shown as S103 to S104 in the first embodiment. Perform the action.

  As described above, the microcontroller 200 performs the setting operation by taking in the first setting value before the reset release signal is output by the reset control IC 310 and the second setting value after the reset release signal is output.

  In an environment where power-on and reset release signal input are substantially simultaneous, microcontroller 200 is unlikely to have a significant difference in time from power-on to operation. .

  On the other hand, in the information processing system 300, the time from when the power is turned on until the reset release signal is given to the microcontroller 200 can vary depending on the situation. A conventional general microcontroller starts all operations after a reset release signal is input. Therefore, when the reset release signal is delayed, the microcontroller can operate after a time required for the operation setting process from the input of the reset release signal. On the other hand, the microcontroller 200 according to the present embodiment executes the first operation setting process in advance using power-on as a trigger. Thereafter, the remaining second operation setting process is executed with the reset release signal as a trigger. Therefore, even if the reset release signal is delayed, the microcontroller 200 can operate only after the time required for the second operation setting process has elapsed from the input of the reset release signal.

  That is, in this embodiment, the first circuit 110 (the circuit operation speed capturing circuit 112, the circuit operation speed setting circuit 113, and the clock setting circuit 114) waits for the input of the reset release signal from the reset control IC 310. The second circuit 120 (operation mode setting circuit 121) operates with the input of the reset release signal from the reset control IC 310 as a trigger. Thereby, even when the input of the reset release signal from the reset control IC 310 is delayed, the influence on the time from when the power is turned on until the microcontroller can be operated can be suppressed.

<Embodiment 3>
Next, the configuration of the microcontroller 400 according to the third embodiment of the present invention will be described with reference to FIG.

  The microcontroller 400 according to the third embodiment is characterized in that it includes a stop terminal 404, an oscillation circuit 414, and a count operation circuit 415. Other components, that is, operation setting terminal 101, power supply terminal 102, reset terminal 103, power ON detection circuit 111, circuit operation speed capturing circuit 112, circuit operation speed setting circuit 113, clock setting circuit 114, operation mode setting circuit 121, CPU 230, and memory 240 are the same as those in the first embodiment.

  The stop terminal 404 is a terminal for inputting a stop signal for operating the oscillation circuit 414.

  The oscillation circuit 414 is a clock generation circuit that operates in response to a stop signal input. The clock signal generated by the oscillation circuit 414 is used only inside the microcontroller 400.

  The count operation circuit 415 receives a clock signal generated by the oscillation circuit 414 and counts the number of clocks. Further, when the number of clocks reaches a predetermined threshold value, the count operation circuit 415 notifies the circuit operation speed capturing circuit 112 of a counter overflow.

  The operation mechanism of the microcontroller 400 will be described with reference to the timing chart of FIG.

  S301: Power is input to the power terminal 102 (1). At this time, the power ON detection circuit 111 outputs a power ON detection signal to the circuit operation speed capturing circuit 112 and the count operation circuit 415 when the power supply voltage is equal to or higher than a predetermined threshold (2). At this time, power is also supplied to at least the circuit operation speed capturing circuit 112, the circuit operation speed setting circuit 113, the clock setting circuit 114, the oscillation circuit 414, and the count operation circuit 415. Accordingly, these circuits 112 to 114, 414, and 415 can perform a predetermined operation even before the reset release signal is input.

  The PLL as the clock setting circuit 114 starts the operation of the oscillator as soon as power is supplied (3). The oscillator operates at a stable frequency as the oscillation stabilization period elapses after the operation starts.

  The count operation circuit 415 starts counting the number of clocks generated by the oscillation circuit 414 (7). However, at this time, the oscillation circuit 414 has not yet generated a clock signal.

  S302: A stop signal is input to the stop terminal 404 (5). With the input of the stop signal as a trigger, the oscillation circuit 414 starts generating the clock signal (6). The count operation circuit 415 counts the number of clocks generated by the oscillation circuit 414 (7).

  S303: The count operation circuit 415 outputs a counter overflow when the counted number of clocks reaches a predetermined threshold (8). The circuit operation speed capturing circuit 112 starts capturing the first set value input to the operation setting terminal 101 on condition that the power ON detection signal is input and the counter overflow is notified. Thereafter, the circuit operation speed setting circuit 113 outputs the first set value to the PLL 114 (10, 11).

  S304: When the oscillation stabilization period ends, the PLL 114 starts a lockup count operation based on the first set value output from the circuit operation speed setting circuit 113, that is, the multiplication rate and the lockup time (4). The PLL 114 completes the lockup count operation after the lockup period, and starts supplying clock pulses to the CPU 230.

  S305: A reset release signal is input to the reset terminal 103 (9). At this time, the operation mode setting circuit 121 starts operation and takes in the second set value input to the operation setting terminal 101 (10, 12). The operation mode setting circuit 121 outputs the second set value, that is, the operation mode to the CPU 230.

  S306: The CPU 230 starts operation (13). Here, the CPU 230 operates in accordance with the frequency based on the clock pulse supplied from the PLL 114 and the operation mode based on the second set value output from the operation mode setting circuit 121.

  Note that the microcontroller 400 does not necessarily include the power ON detection circuit 111. In this case, the count operation circuit 415 starts counting the number of clocks using a stop signal input to the stop terminal 404 as a trigger. In addition, the circuit operation speed capturing circuit 112 captures the first set value from the operation setting terminal 101 on condition that the count overflow circuit 415 notifies the count overflow.

  In the microcontroller 400 in the above-described embodiment, the oscillation circuit 414 starts operating with the input of the stop signal to the stop terminal 404 as a trigger. However, when the oscillation circuit 414 and the power ON detection circuit 111 are connected, The oscillation circuit 414 may be configured to start the operation with the input of the signal as a trigger. In this case, the stop terminal 404 is not necessarily provided.

  In the present embodiment, the oscillation circuit 414 operates with a stop signal input to the stop terminal 404 as a trigger, and the count circuit 415 detects a predetermined number of clock signals of the oscillation circuit 414 as a trigger. 110 (circuit operation speed capturing circuit 112, circuit operation speed setting circuit 113, clock setting circuit 114) operates. Thereby, after the power is turned on, the timing for taking in the first set value can be arbitrarily set. This is advantageous, for example, when a certain time is required until the power supply is stabilized.

  Further, according to the modification of the present embodiment, even if the power ON detection circuit 111 is not provided, it is possible to start taking in the first set value using a stop signal input to the stop terminal 404 as a trigger. As a result, even a microcontroller that does not include the power ON detection circuit 111 can capture the first set value without waiting for the input of the reset release signal.

<Embodiment 4>
Next, the configuration of the microcontroller 500 according to the fourth embodiment of the present invention will be described with reference to FIG.

  The microcontroller 500 according to the fourth embodiment is provided with a plurality of circuit operation speed setting circuits 113a to 113c, a plurality of clock setting circuits 114a to 114c, and the operation of the count operation circuit 415 and the circuit operation speed capturing circuit 112. Has characteristics. The other components, that is, the operation setting terminal 101, the power supply terminal 102, the reset terminal 103, the power ON detection circuit 111, the operation mode setting circuit 121, the CPU 230 and the memory 240, the stop terminal 404, and the oscillation circuit 414 are described in the third embodiment. This is the same as in FIG.

  Count operation circuit 415 in the present embodiment can generate counter overflow a plurality of times. That is, the count operation circuit 415 outputs a counter overflow when the number of clocks of the oscillation circuit 414 reaches a predetermined threshold value. Thereafter, the count operation circuit 415 continues to count the number of clocks, and outputs a counter overflow when the counted number of clocks reaches a predetermined threshold again. The count operation circuit 415 repeats this processing at least as many times as the circuit operation speed setting circuits 113a to 113c.

  The circuit operation speed acquisition circuit 112 according to the present embodiment performs the first setting in a predetermined order for each of the circuit operation speed setting circuits 113a to 113c every time the counter operation is notified of the counter overflow from the count operation circuit 415. Control to output the value.

  The circuit operation speed setting circuits 113a to 113c have the same configuration as the circuit operation speed setting circuit 113 in the third embodiment, and are connected to the same circuit operation speed acquisition circuit 112, respectively. In FIG. 7, the circuit operation speed setting circuits 113a to 113c are shown as a plurality of circuits, but they may be configured as one circuit capable of holding a plurality of first set values.

  Each of the clock setting circuits 114 a to 114 c has a configuration equivalent to that of the clock setting circuit 114 in the third embodiment, and each is connected to the same circuit operation speed capturing circuit 112.

  Next, the operation mechanism of the microcontroller 500 according to the fourth embodiment of the present invention will be described. For the sake of simplification of description, only differences from the third embodiment will be mainly described.

  First, the oscillation circuit 414 generates a clock signal with the input of a stop signal as a trigger.

  The count operation circuit 415 counts the number of clocks generated by the oscillation circuit 414 and generates counter overflow a plurality of times.

  The circuit operation speed capturing circuit 112 receives the first power ON detection signal from the power ON detection circuit 111 and the counter overflow notification from the count operation circuit 415, and inputs the first to the operation setting terminal 101. Import the set value. The circuit operation speed acquisition circuit 112 takes in the first set value every time the counter operation is notified of the counter overflow from the count operation circuit 415, and in response to each of the circuit operation speed setting circuits 113a to 113c in a predetermined order. The first set value taken in is output. Here, the first set value may be different for each capture. Therefore, a different first set value can be output to each of the circuit operation speed setting circuits 113a to 113c.

  When the circuit setting speed setting circuits 113a to 113c receive the first set value from the circuit operating speed fetch circuit 112, the circuit setting speed setting circuits 113a to 113c notify the clock setting circuits 114a to 114c connected thereto, respectively. To do. At this time, if the notified first setting values are different, the clock setting circuits 114a to 114c perform different operations.

  In the present embodiment, the count operation circuit 415 can fetch a plurality of first set values from one operation setting terminal 101 by causing the counter overflow to occur a plurality of times.

<Other embodiments>
It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  For example, in the fourth embodiment, the count operation circuit 415 generates the counter overflow a plurality of times, so that the circuit operation speed capturing circuit 112 sets the first set value from the one operation setting terminal 101 a plurality of times. An example is shown in which the data is fetched and supplied to the plurality of circuit operation speed setting circuits 113a to 113c.

  Here, the circuit operation speed capturing circuit 112 is connected to one circuit operation speed setting circuit 113 as in the first embodiment, instead of being connected to the plurality of circuit operation speed setting circuits 113a to 113c. You may do it.

  In this case, the circuit operation speed capturing circuit 112 captures one first set value supplied to the operation setting terminal 101 a plurality of times, and takes a large number of values among the captured first set values. The first setting value can be determined and output to the circuit operation speed setting circuit 113. Thereby, even if noise is mixed in the operation setting terminal 101, it is possible to prevent an unintended operation setting.

  In the same case, the circuit operation speed capturing circuit 112 captures a plurality of different first setting values supplied to the operation setting terminal 101, and the combination of these first setting values satisfies a predetermined condition. A configuration is made such that a predetermined setting value, for example, a setting value that means a transition to a non-public operation mode, is output only when the condition is satisfied or when the first setting value is input within a predetermined time. be able to. Thereby, it can suppress that the transition to the above-mentioned non-public operation mode etc. occurs unintentionally.

  Further, the captured first setting value or second setting value is stored in a predetermined register and can be read from the CPU 230 or the outside, so that the current operation mode can be confirmed by an application or the like. good.

  In the above-described embodiment, the hardware configuration has been described. However, the present invention is not limited to this, and arbitrary processing may be realized by causing a CPU (Central Processing Unit) to execute a computer program. Is possible. In this case, the computer program can be stored and provided to the computer using various types of non-transitory computer readable media. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

DESCRIPTION OF SYMBOLS 100 Information processing apparatus 101 Operation setting terminal 102 Power supply terminal 103 Reset terminal 110 1st circuit 120 2nd circuit 200 Microcontroller 111 Power supply ON detection circuit 112 Circuit operation speed taking-in circuit 113 Circuit operation speed setting circuit 114 Clock setting circuit 230 CPU
240 memory 300 information processing system 310 reset control IC
321 Sensor IC
322 Sensor IC
323 Sensor IC
400 Microcontroller 404 Stop terminal 414 Oscillation circuit 415 Count operation circuit 500 Microcontroller

Claims (9)

A power supply terminal for inputting power,
A reset terminal for inputting a reset release signal;
An operation setting terminal for inputting the first set value and the second set value;
A first circuit that operates based on the first set value;
A second circuit that operates based on the second set value,
The first circuit acquires the first set value from the operation setting terminal in response to an input of the power supply to the power supply terminal,
The second circuit acquires the second set value from the operation setting terminal in response to an input of the reset release signal to the reset terminal after the power is input. The information processing apparatus according to claim 1, wherein the first set value is a set value related to a process that can be started before the reset release signal is input. The first set value is a set value of an operation speed of the information processing apparatus,
The second setting value is a setting value of an operation mode of the information processing apparatus,
The first circuit is an operation speed setting circuit that determines an operation speed of the information processing device based on the first set value.
The information processing apparatus according to claim 1, wherein the second circuit is an operation mode setting circuit that determines an operation mode of the information processing apparatus based on the second setting value. A stop terminal for inputting a stop signal;
An oscillation circuit that starts generating a clock signal in response to the input of the stop signal to the stop terminal;
A count operation circuit that counts the number of clocks of the clock signal and outputs a notification signal when the number of clocks reaches a predetermined threshold;
The first circuit acquires the first set value from the operation setting terminal in response to an input of the power supply to the power supply terminal and an output of the notification signal from the count operation circuit, and starts operation. The information processing apparatus according to any one of claims 1 to 3. The count operation circuit outputs the notification signal every time the clock number reaches a predetermined threshold value,
5. The information processing according to claim 1, wherein the first circuit acquires the first set value from the operation setting terminal every time the notification signal is output from the count operation circuit. apparatus. A processor;
A power supply terminal for inputting power,
A reset terminal for inputting a reset release signal;
An operation setting terminal for inputting the first set value and the second set value;
The first setting value is acquired from the operation setting terminal according to the input of the power supply to the power supply terminal, and the first operation information based on the first setting value is output to the processor. Circuit,
After the power is input, the second setting value is acquired from the operation setting terminal in response to the input of the reset release signal to the reset terminal, and the second operation information based on the second setting value is obtained. A second circuit for outputting to the processor;
The processor is a microcontroller that starts an operation based on the first operation information and the second operation information in response to input of the first operation information and the second operation information. A control device;
A first information processing apparatus;
And at least one second information processing apparatus,
The control device supplies a reset release signal indicating a timing to start processing to the first information processing device and the second information processing device,
The first information processing apparatus includes:
A power supply terminal for inputting power,
A reset terminal for inputting a reset release signal;
An operation setting terminal for inputting the first set value and the second set value;
A first circuit that operates based on the first set value;
A second circuit that operates based on the second set value,
The first circuit acquires the first set value from the operation setting terminal in response to an input of the power supply to the power supply terminal,
The second circuit acquires the second set value from the operation setting terminal in response to an input of the reset release signal to the reset terminal after the power is input. A first circuit acquiring the first set value from an operation setting terminal in response to an input of a power supply to the power supply terminal;
A second circuit acquiring a second set value from the operation setting terminal in response to an input of a reset release signal to the reset terminal after the power is input; A step of supplying, to the first information processing device and at least one second information processing device, a reset release signal indicating a timing at which the control device should start processing;
The first circuit of the first information processing apparatus acquires the first set value from the operation setting terminal in response to an input of power to the power terminal;
The second circuit of the first information processing apparatus acquires a second set value from the operation setting terminal in response to an input of the reset release signal to a reset terminal after the power is input. Having an information processing method.

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