JP2013175586A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same capable of suppressing fluctuation in current-voltage characteristic in a linear region of a MOS transistor.SOLUTION: A semiconductor device includes: a silicon substrate 1; a gate oxide 11 provided on the silicon substrate 1; a gate electrode 13 provided on the gate oxide 11; n-type source 21 and drain 23 provided below both sides of the gate electrode 13 in the silicon substrate 1; and an n-type drift layer 5 provided in the silicon substrate 1 from below the gate electrode 13 to the drain 23. The drift layer 5 includes a first drift layer 5a which is disposed below the gate electrode 13 to contact with the gate oxide 11, and a second drift layer 5b which is disposed between the first drift layer 5a and the drain 23. An n-type impurity concentration in the first drift layer 5a is higher than an n-type impurity concentration in the second drift layer 5b.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a technique capable of suppressing fluctuation of current-voltage characteristics in a linear region of a MOS transistor.

  2. Description of the Related Art Conventionally, high voltage MOS transistors designed so as not to break even with high power are used for devices that handle high power, such as power devices and high-speed switching devices. An example of such a high voltage MOS transistor is disclosed in Patent Document 1. Patent Document 1 discloses a high-breakdown-voltage N-type MOS transistor having an N-type drift region. The N-type drift region is a low-concentration N-type impurity diffusion layer formed on the substrate. This N-type drift region relaxes the electric field between the source and the drain, and can withstand a high voltage.

JP 2007-27641 A

By the way, the present inventor has conducted various researches and developments on a high voltage MOS transistor having a drift region (hereinafter also referred to as a drift layer). It has been found that characteristic fluctuations (that is, deterioration) are likely to occur. This point will be described with reference to FIGS.
FIG. 4 is a cross-sectional view showing a configuration of a high-breakdown-voltage N-type MOS transistor 200 according to a reference example of the present invention. First, the configuration of the N-type MOS transistor 200 according to the reference example will be described. As shown in FIG. 4, a P-type well diffusion layer 103 is formed in the silicon substrate 101, and an N-type drift layer 105 is formed in the well diffusion layer 103. A gate oxide film 111 is continuously formed on the well diffusion layer 103 and the drift layer 105, and a gate electrode 113 is formed thereon. An N-type source 121 and drain 123 are formed below both sides of the gate electrode 113. In addition, field oxide films 106a and 106b are formed on the silicon substrate 101, and the gate electrode 113 and the drain 123 are separated by the field oxide film 106b.

In this reference example, a high breakdown voltage type N-type MOS transistor 200 includes a well diffusion layer 103, a drift layer 105, a field oxide film 106b, a gate oxide film 111, a gate electrode 113, a source 121 and a drain 123. Is configured. Next, Ids-Vds characteristics of the high breakdown voltage N-type MOS transistor 200 will be described.
FIG. 5 is a diagram schematically showing a result obtained by actually making a high breakdown voltage N-type MOS transistor 200 and actually measuring its Ids-Vds characteristics. The inventor applied a voltage to the gate electrode 113 to turn on the N-type MOS transistor 200, gradually increased the drain voltage Vds in this state, and measured the drain current Ids at that time. Such measurement was repeated many times. As a result, as shown in FIG. 5, it was found that the Ids-Vds characteristics deteriorate as the number of measurements increases. It has also been found that the degradation of the Ids-Vds characteristic is remarkable in the linear region and hardly seen in the saturation region. The present inventor believes that such a result is produced for the following reason.

  That is, when a drain current Ids is made to flow with the high breakdown voltage N-type MOS transistor turned on, electron-hole pairs are generated in a region where the channel electric field is high. When the MOS transistor is N-type, a part of the electrons (that is, hot carriers) in the electron-hole pair is taken into the gate oxide film from the channel. Here, the hot carrier injection part from the channel to the gate oxide film includes a junction part (that is, a PN junction part) between the P-type well diffusion layer and the N-type drift layer, and a drift layer that is over the channel. There are two possible areas, ie, the overlapping area (ie, the overlapping area).

  When the hot carrier injection portion is a PN junction portion, hot carriers are injected into the gate oxide film near the PN junction portion. In that case, the threshold voltage Vth, the mutual conductance Gm, etc. fluctuate, and the degradation of the Ids-Vds characteristic should be remarkable even in the saturation region. In FIG. 5, the degradation of the Ids-Vds characteristic is seen in the linear region and not in the saturation region. For this reason, the present inventor considered that the hot carrier injection portion is an overlap region. Based on this idea, the result of FIG. 5 can be explained by the following mechanism.

  That is, in the case of a high breakdown voltage N-type MOS transistor, the N-type impurity concentration in the N-type drift layer is very low. Therefore, as shown in FIG. 6, when hot carriers are injected into the gate oxide film 111 from the overlap region of the drift layer 105, N-type depending on the amount (charge amount) of injected hot carriers e−. The drift layer 105 is depleted from the surface in the depth direction. The greater the depletion of the drift layer 105, the narrower the current path through which the drain current Ids flows. For this reason, as shown in FIG. 5, it is considered that the degradation of the Ids-Vds characteristic appears remarkably in the linear region.

  On the other hand, in the saturation region, the drain voltage Vds has a larger influence on the drain current Ids than the amount of hot carriers injected into the gate oxide film 111. When the drain voltage Vds is sufficiently large, the drift layer 105 is completely depleted under the influence of the drain voltage Vds, and the drain current Ids is saturated. For this reason, as shown in FIG. 5, it is considered that the Ids-Vds characteristic was not deteriorated in the saturation region.

  Therefore, the present invention has been made in view of such knowledge and considerations, and provides a semiconductor device and a method for manufacturing the same that can suppress fluctuations in current-voltage characteristics in the linear region of a MOS transistor. The purpose is to do.

  In order to solve the above problems, a semiconductor device according to one embodiment of the present invention includes a semiconductor substrate, a gate insulating film provided over the semiconductor substrate, a gate electrode provided over the gate insulating film, A source and drain of a first conductivity type provided below both sides of the gate electrode of the semiconductor substrate; a drift layer of a first conductivity type provided from below the gate electrode to the drain of the semiconductor substrate; The drift layer is disposed under the gate electrode and is in contact with the gate insulating film; the second drift layer is disposed between the first drift layer and the drain; The impurity concentration of the first conductivity type in the first drift layer is higher than the impurity concentration of the first conductivity type in the second drift layer.

  With such a configuration, the first drift layer is a region overlapping with the channel in the drift layer (that is, an overlap region). The impurity concentration of the first conductivity type in the first drift layer is higher than the impurity concentration of the first conductivity type in the second drift layer (that is, the non-overlapping region). For this reason, even when hot carriers are injected into the gate insulating film, the overlap region of the drift layer is difficult to be depleted, and the current path through which the drain current flows can be suppressed from being narrowed. Therefore, it is possible to suppress the current-voltage characteristics from changing in the linear region of the MOS transistor. The “semiconductor substrate” of the present invention corresponds to, for example, a silicon substrate 1 described later. The “gate insulating film” corresponds to, for example, a gate oxide film 11 described later. Further, the “first conductivity type” corresponds to one of P type and N type.

  In the above semiconductor device, a second conductivity type well diffusion layer provided from below the source of the semiconductor substrate to below the drain; the source of the semiconductor substrate; the drift layer; And a second conductivity type impurity diffusion layer that is spaced from the source and is in contact with the first drift layer, wherein the impurity concentration of the second conductivity type in the impurity diffusion layer is determined by the well diffusion. It is characterized by being lower than the impurity concentration of the second conductivity type in the layer. With such a configuration, for example, a depletion layer formed on the source side of the overlap region can be further expanded to the source side. Thereby, it can contribute to the improvement of the withstand pressure | voltage of an overlap area | region. The “second conductivity type” of the present invention corresponds to the other of the P type and the N type. The “impurity diffusion layer” corresponds to, for example, a low-concentration impurity diffusion layer 9 described later.

  The semiconductor device may further include an insulating film provided on the semiconductor substrate and separating the gate electrode and the drain, and the insulating film is thicker than the gate insulating film. It is characterized by. With such a configuration, the breakdown voltage between the gate electrode and the drain can be increased and the capacitance between the gate electrode and the drain can be reduced. Thereby, the high breakdown voltage of the MOS transistor can be increased. In the linear region of the high-breakdown-voltage MOS transistor, it is possible to suppress fluctuations in current-voltage characteristics. The “insulating film” of the present invention corresponds to, for example, a field oxide film 6b described later.

  A method for manufacturing a semiconductor device according to another aspect of the present invention includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and the gate of the semiconductor substrate. Forming a first conductivity type source and drain under both sides of the electrode, and forming a first conductivity type drift layer from under the gate electrode to the drain of the semiconductor substrate, In the step of forming the drift layer, a first drift layer disposed under the gate electrode and in contact with the gate insulating film, a second drift layer disposed between the first drift layer and the drain, And the impurity concentration of the first conductivity type in the first drift layer is made higher than the impurity concentration of the first conductivity type in the second drift layer. With such a manufacturing method, it is possible to manufacture a semiconductor device capable of suppressing fluctuations in current-voltage characteristics in the linear region of the MOS transistor.

  According to the present invention, even when hot carriers are injected into the gate insulating film, the overlap region of the drift layer is unlikely to be depleted, and the current path through which the drain current flows can be suppressed from being narrowed. Therefore, it is possible to suppress the current-voltage characteristics from changing in the linear region of the MOS transistor.

1 is a diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present invention. The figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. The figure which shows the effect of embodiment typically. The figure which shows the structure of the N-type MOS transistor 200 which concerns on the reference example of this invention. The figure which shows typically the actual measurement result of an Ids-Vds characteristic regarding a reference example. The figure for demonstrating a subject.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof is omitted.
(1) Semiconductor Device FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, this semiconductor device includes, for example, a P-type silicon substrate 1 (P-Sub) 1, a P-type well diffusion layer (PWell) 3 provided on the silicon substrate 1, and a silicon substrate. 1, field oxide films 6 a, 6 b, 6 c provided in 1, a P-type impurity diffusion layer 7 for preventing PN inversion provided under field oxide film 6 a, and a contact P provided in well diffusion layer 3. A high-concentration impurity diffusion layer 8 of a type.

  Further, this semiconductor device includes a gate oxide film 11 provided on the silicon substrate 1, a gate electrode 13 provided on the gate oxide film 11, sidewalls 15 provided on both side surfaces of the gate electrode, gates N-type source 21 and drain 23 provided below both sides of electrode 13, N-type drift layer 5 provided in well diffusion layer 3, and P-type low-concentration impurity diffusion provided in well diffusion layer 3 And a layer 9. As shown in FIG. 1, in this semiconductor device, the well diffusion layer 3, the drift layer 5, the field oxide film 6b, the low-concentration impurity diffusion layer 9, the gate oxide film 11, the gate electrode 13, and the source 21 The high breakdown voltage N-type MOS transistor 100 is constituted by the drain 23.

The gate oxide film 11 is, for example, a silicon oxide film, and the thickness thereof is, for example, 10 to 30 nm. The gate electrode 13 is made of a polysilicon film doped with an impurity such as phosphorus, arsenic, or boron. The sidewall 15 is made of an insulating film such as a silicon oxide film or a silicon nitride film.
The source 21 is formed on one side of the gate electrode 13 and on the surface of the well diffusion layer 3 and its vicinity. The source 21 has, for example, an LDD structure, and includes a low concentration layer 21a doped with N-type impurities at a low concentration and a high concentration layer 21b doped with N-type impurities at a high concentration. The drain 23 is formed on the other side of the gate electrode 13 and on the surface of the drift layer 5 and in the vicinity thereof. The drain 23 is composed of a high concentration layer doped with N-type impurities at a high concentration.

Drift layer 5 is provided from below gate electrode 13, through field oxide film 6 b, and below drain 23. The drift layer 5 is disposed below the gate electrode 13 and is in contact with the gate oxide film 11. The drift layer 5 is disposed between the first drift layer 5 a and the drain 23 in the current path of the drain current Ids. It consists of a drift layer 5b. In this example, the second drift layer 5b is disposed from below the first drift layer 5a to below the drain 23. The impurity concentration of the N-type in the first drift layer 5a and _{N A,} when the impurity concentration of the N-type in the second drift layer 5b was _{N B, N A} has a value greater than _{N B (N A} > N _B ).

The low concentration impurity diffusion layer 9 is provided inside the well diffusion layer 3 and between the source 21 and the drift layer 5. The low concentration impurity diffusion layer 9 is separated from the source 21 and is in contact with the first drift layer 5a. The P-type impurity concentration in the low-concentration impurity diffusion layer 9 is lower than the P-type impurity concentration in the well diffusion layer 3.
The field oxide films 6a, 6b and 6c are provided on the silicon substrate. The thickness of the field oxide films 6a, 6b, 6c is, for example, 300 to 1000 nm. As will be described later, it is a silicon oxide film formed simultaneously by, for example, a LOCOS (local oxidation of silicon) method. In this example, the gate electrode 13 and the drain 23 are separated from each other by the field oxide film 6 b having a thickness larger than that of the gate oxide film 11. Thereby, the breakdown voltage BVdg between the gate electrode 13 and the drain 23 is improved and the capacitance Qdg between the gate electrode 13 and the drain 23 is reduced. Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described.

(2) Manufacturing Method of Semiconductor Device FIGS. 2A to 2D are cross-sectional views illustrating a manufacturing method of a semiconductor device according to the embodiment of the present invention. In FIG. 2A, first, a P-type well diffusion layer 3, field oxide films 6a, 6b, and 6c, and an N-type second drift layer 5b are sequentially formed on a P-type silicon substrate 1. . The well diffusion layer 3 and the drift layer 5b are formed by using a photolithography technique and an ion implantation technique, respectively. The field oxide films 6a, 6b, and 6c are formed by using, for example, a LOCOS method.

  Next, as shown in FIG. 2B, a resist pattern 31 is formed on the silicon substrate 1 by using a photolithography technique. Here, the resist pattern 31 is formed in a shape that opens above the region that becomes the channel of the MOS transistor and covers other regions. Next, N-type impurities such as phosphorus are ion-implanted into the silicon substrate 1 using the resist pattern 31 as a mask.

  Thereby, as shown in FIG. 2B, the first drift layer 5a is formed by doping the N-type impurity on the second drift layer 5b. In this ion implantation process, not only the upper portion of the second drift layer 5b but also the surface of the well diffusion layer 3 and its vicinity are doped with N-type impurities such as phosphorus, so that the P-type of the well diffusion layer 3 is canceled out. It is. Therefore, a P-type low-concentration impurity diffusion layer 9 having a P-type impurity concentration lower than that of the well diffusion layer 3 is formed. Thereafter, the resist pattern 31 is removed by ashing, for example.

  Next, as shown in FIG. 2C, a resist pattern 32 is formed on the silicon substrate 1 using a photolithography technique. Here, the shape is opened above the side of the low-concentration impurity diffusion layer 9 far from the first drift layer 5a and covers the other region (including the side close to the first drift layer 5a of the low-concentration impurity diffusion layer 9). Then, a resist pattern 32 is formed. Next, using this resist pattern 32 as a mask, a P-type impurity such as boron is ion-implanted into the silicon substrate 1. Thereby, as shown in FIG. 2C, the region of the low-concentration impurity diffusion layer 9 far from the first drift layer 5a is doped with the P-type impurity, and the N-type contained in the region is canceled out. . As a result, the region of the low-concentration impurity diffusion layer 9 is raised to the same level as the well diffusion layer 3 with respect to the P-type impurity concentration. Thereafter, the resist pattern 32 shown in FIG. 2C is removed by, for example, ashing.

  Next, a gate oxide film 11 is formed on the silicon substrate 1 as shown in FIG. The gate oxide film 11 is formed, for example, by thermally oxidizing the silicon substrate 1. Then, a gate electrode 13 is formed on the silicon substrate 1. The gate electrode 13 is formed, for example, by depositing a polysilicon film on the gate oxide film 11 and patterning the deposited polysilicon film. The polysilicon film is deposited by, for example, a CVD (chemical vapor deposition) method. The patterning of the polysilicon film is performed using, for example, a photolithography technique and an etching technique.

  Next, using the gate electrode 13 as a mask, an N-type impurity such as phosphorus is ion-implanted into the silicon substrate 1 to form a source low-concentration layer 21a (see FIG. 1). Subsequently, a sidewall 15 (see FIG. 1) is formed on the side surface of the gate electrode 13. Then, an N-type impurity such as phosphorus or arsenic is ion-implanted into the silicon substrate 1 using the gate electrode 13 and the sidewall 15 as a mask. Thus, the source high concentration layer 21b and the drain 23 are formed.

  Also, P-type impurities such as boron are ion-implanted into the P-well diffusion layer using photolithography and ion implantation techniques. Thereby, the P-type high-concentration impurity diffusion layer 8 (see FIG. 1). When forming a P-type MOS transistor (not shown) on the silicon substrate 1, the high-concentration impurity diffusion layer 8 may be formed by using the source and drain forming steps of the P-type MOS transistor. Through the above steps, the MOS transistor 100 shown in FIG. 1 is completed.

(3) According to the embodiments of the advantages the present invention embodiment, the first drift layer 5a (i.e., channels overlap, the overlap region) of the impurity concentration N _A of the N-type in the second drift layer 5b ( That is, higher than the N-type impurity concentration N _B of the non-overlapping region). For this reason, as shown in FIG. 3, even when hot carriers e− are injected into the gate oxide film 11, the overlap region of the drift layer 5 is not easily depleted, and the current path through which the drain current Ids flows becomes narrow. Can be suppressed. Therefore, the high breakdown voltage N-type MOS transistor 100 can suppress fluctuations in the Ids-Vds characteristics in the linear region.

  Further, between the N-type first drift layer 5a which is an overlap region and the P-type well diffusion layer 3, a P-type low-concentration impurity diffusion having a P-type impurity concentration lower than that of the well diffusion layer 3 Layer 9 is provided. For this reason, a depletion layer (not shown) formed on the source side of the overlap region can be further expanded to the source side. Thereby, it can contribute to the improvement of the withstand pressure | voltage of an overlap area | region.

(4) Other Embodiments In the above embodiment, the case where the high voltage MOS transistor 100 is an N-type has been described as an example. However, in the present invention, the high breakdown voltage type MOS transistor is not limited to the N type, and may be a P type. For example, in FIG. 1, the well diffusion layer 3, the high-concentration impurity diffusion layer 8, and the low-concentration impurity diffusion layer 9 may each be N-type, and the source 21, drain 23, and drift layer 5 may each be P-type. . Also in this case, if the P-type impurity concentration of the first drift layer 5a which is the overlap region is higher than the P-type impurity concentration of the second drift layer 5b which is not the overlap region, the overlap region is difficult to be depleted. The same effects as in the above embodiment are achieved.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Well diffusion layer 5 Drift layer 5a 1st drift layer 5b 2nd drift layer 6a, 6b, 6c Field oxide film 7 Impurity diffusion layer 8 High concentration impurity diffusion layer 9 Low concentration impurity diffusion layer 11 Gate oxide film 13 Gate Electrode 15 Side wall 21 Source 21a Low concentration layer 21b High concentration layer 23 Drain 31, 32 Resist pattern 100 High breakdown voltage type transistor

Claims (4)

A semiconductor substrate;
A gate insulating film provided on the semiconductor substrate;
A gate electrode provided on the gate insulating film;
A source and drain of a first conductivity type provided below both sides of the gate electrode of the semiconductor substrate;
A drift layer of a first conductivity type provided from the bottom of the gate electrode to the drain of the semiconductor substrate,
The drift layer is
A first drift layer disposed under the gate electrode and in contact with the gate insulating film;
A second drift layer disposed between the first drift layer and the drain;
The semiconductor device characterized in that the first conductivity type impurity concentration in the first drift layer is higher than the first conductivity type impurity concentration in the second drift layer. A second diffusion type well diffusion layer provided from below the source to the drain of the semiconductor substrate;
A second conductivity type impurity diffusion layer provided between the source of the semiconductor substrate and the drift layer, spaced from the source and in contact with the first drift layer;
2. The semiconductor device according to claim 1, wherein an impurity concentration of the second conductivity type in the impurity diffusion layer is lower than an impurity concentration of the second conductivity type in the well diffusion layer. An insulating film provided on the semiconductor substrate and separating the gate electrode and the drain;
The semiconductor device according to claim 1, wherein the insulating film is thicker than the gate insulating film. Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a source and drain of a first conductivity type under both sides of the gate electrode of the semiconductor substrate;
Forming a drift layer of a first conductivity type from under the gate electrode to the drain of the semiconductor substrate,
In the step of forming the drift layer,
A first drift layer disposed under the gate electrode and in contact with the gate insulating film;
Forming a second drift layer disposed between the first drift layer and the drain;
A method of manufacturing a semiconductor device, wherein an impurity concentration of a first conductivity type in the first drift layer is made higher than an impurity concentration of a first conductivity type in the second drift layer.

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