JP2013175014A - Address byte count determination device, address byte count determination method, program, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To determine an address byte count of a serial memory without writing determination data to the serial memory.SOLUTION: An address byte count determination device 10 comprises: an address generation unit 12 that assumes a maximum byte count and transmits in order a first address having the assumed maximum byte count and a second address which is obtained by inverting a specific bit of the first address, to a memory input/output unit 11; a first data string acquisition unit 13 that obtains a first data string from a first starting data value that is obtained first to a first ending data value that is detected as being different from the first starting data value; a second data string acquisition unit 14 that obtains a second data string from a second starting data value that is obtained first to a second ending data value that is detected as being different from the second starting data value; a comparison unit 15 that outputs a match/mismatch between the first data string and the second data string; and a control unit 16 that, when they do not match, outputs an address byte count on the basis of an address portion including the specific bit.

Description

  The present invention relates to an address byte number determination method for determining the number of address bytes in an externally connected SPI (Serial Peripheral Interface) standard serial memory and a determination apparatus thereof, for example, a method for determining the number of address bytes in a nonvolatile serial memory and the determination thereof. Relates to the device.

  In recent years, cost reduction has become an important issue for products equipped with ASIC (Application Specific Integrated Circuit). For example, in order to reduce costs related to the number of terminals and mounting area of ASIC and ROM (Read Only Memory) devices, a case where a nonvolatile serial memory with a small number of terminals is mounted as a boot ROM is increasing. The serial memory is characterized by a wide range of capacity variations and terminal position compatibility, and it is possible to select a serial memory device having the optimum capacity for each product even after the ASIC or mounting board is completed. This contributes to a reduction in development cost and product cost due to diversion of ASIC. For example, in the product development process, rewritable non-volatile serial such as EEPROM (Electrically Erasable Programmable Read Only Memory) or FLASH with sufficient capacity as boot ROM in the period until software perfection is improved Memory is used. After the software is completed, software destruction is prevented by a protect function provided in the nonvolatile serial memory. Furthermore, the cost can be reduced by switching to the minimum necessary small-capacity nonvolatile serial memory or an inexpensive mask ROM type serial memory.

However, the number of address bytes of the non-volatile serial memory includes a type such as 1/2/3. For this reason, the correct contents cannot be read from the serial memory unless an address having a width corresponding to the serial memory connected from the ASIC side is output. Further, if the number of address bytes is selected by external terminal input, the terminal cost increases. Furthermore, in the serial FLASH that conventionally has 3 address bytes, devices with 4 address bytes have recently appeared. For this reason, even if the products are equipped with the same ASIC, an increase in the situation where the optimum number of address bytes differs for each product is expected.
Therefore, it is desired that the user can select an optimal (inexpensive) nonvolatile serial memory for each product. Specifically, a means for determining the number of address bytes of the nonvolatile serial memory is required so that a terminal cost for selecting the number of address bytes does not occur.

As means for determining the number of address bytes of the serial memory, for example, Patent Document 1
A method of accessing a serial memory compliant with SPI and automatically determining the memory size of the serial memory is disclosed.
Further, in Patent Document 2, even when the storage capacity of the EEPROM is not known in advance, the storage capacity of the obtained EEPROM can be automatically determined, and the access sequence is determined by using the determination result. An EEPROM storage capacity determination apparatus and an EEPROM storage capacity determination method that can be performed are disclosed. In the patent document 2, in the start-up process, it is determined whether the data received serially by the serial interface with the first timing as the start timing matches the predetermined data. A method is used for determining whether data serially received by the serial interface matches predetermined data with timing as start timing.
Furthermore, Patent Document 3 discloses an information processing apparatus that can perform boot-up processing without depending on the address bit length of a slave device. In Patent Document 3, a method is used in which address data is input to the EEPROM and the number of bits of the address data input to the EEPROM is counted until the output level of the EEPROM reaches a predetermined value.

Japanese Patent No. 0374416 JP 2002-073411 A JP 2010-044638 A

For example, Patent Document 1 aims to provide a determination method capable of automatically determining the access mode, that is, the number of address bytes required by the memory, in a serial memory, in particular, an SPI-compliant serial memory.
FIG. 22A is a connection wiring diagram in which the serial memory access mode automatic determination device of Patent Document 1 accesses a serial memory having an interface compliant with SPI, and FIG. 22B is a flowchart of the access mode determination processing.

As shown in FIG. 22A, this discrimination device is composed of a CPU 2 and a pull-up resistor 3, and the DO, DI, SK, and CS ports of the serial memory 1 whose memory size is unknown and surrounded by the dotted line in FIG. Are respectively connected to corresponding I / O pins. The DO port is connected to the power supply circuit by the pull-up resistor 3 so that the potential is always high. In this circuit configuration, the procedure in which the CPU 2 determines the memory size of the memory 1 is, as shown in the flowchart of FIG. 22B, an initial data write process (f1), a determination data read process (f2), and a determination process (f3). This is realized by performing the steps in order.
In the initial data write process (f1), after the CS port is set from high level to low level, 4-byte zero (00h) is output from the CPU 2 to the DI port following the write command.

FIG. 23A is a list of read data for each access mode in the determination data read process (f2), and FIG. 23B is a detailed flowchart of the determination process.
In the determination data read process (f2), when the first and second zeros are input to the memory 1 following the read command, if the memory is in the access mode 1 in exchange for the second zero, the memory 0 Data zero (00h) is read from the address to the DO port.
On the other hand, when the memory is in access mode 2, the first and second zeros specify the upper and lower addresses, and when the memory is in access mode 3, the first and second zeros are The upper and middle addresses are designated.
In the case of the access modes 2 and 3, the pull connected to the DO port shown in FIG. 22A is performed until the address of the required number of bytes (2 bytes in the access mode 2 and 3 bytes in the access mode 3) is not input to the memory. The potential of the DO port is raised to high by the up resistor 3, and data in the state of FFh is output in hexadecimal.
Thus, data obtained from the DO port in exchange for the second zero is used as the first determination data.

Similarly, data read from the DO port in exchange for the third zero and the fourth zero are set as second and third determination data, respectively.
FIG. 23B is a detailed flowchart of the determination process. The determination process is performed based on the first to third determination data. As shown in the figure, if the first determination data is zero (00h), the memory is determined as the access mode 1 memory. . If the first determination data is non-zero and the second determination data is zero (00h), the access mode 2, the second determination data is also non-zero, and the third determination data is zero (00h). In this case, the access mode 3 is determined. If the third determination data is not zero, it is determined that the memory is faulty.

However, in Patent Document 1, it is necessary to write a specific value (0) to a part (address 0) of the nonvolatile serial memory by the initial data writing process (step f1). For this reason, there is a problem that the number of address bytes cannot be automatically determined for a mask ROM type or a non-rewritable nonvolatile serial memory that has been protected. In addition, in the discrimination methods of Patent Documents 2 and 3 described above, the same problem occurs because the discrimination method uses that the value received from the serial memory is a predetermined value.
As described above, in order to determine the number of address bytes of the serial memory, it is necessary to write determination data to the serial memory.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  The address byte number determination apparatus, method, and program according to one embodiment determine the address byte number by the following procedure, for example. First, assume the maximum number of bytes of the address of the serial memory. A first address having the maximum number of bytes is output to a serial memory, and in response to the output of the first address, as a first data string, from the first head data value acquired first, the first head data value and A data string until a different first tail data value is detected is read from the serial memory. Subsequently, a second address obtained by inverting the specific bit of the first address is output to the serial memory, and from the second head data value acquired first as a second data string according to the output of the second address A data string until a second tail data value different from the second head data value is detected is read from the serial memory. Then, when comparing the first data string and the second data string and detecting that the first data string and the second data string do not match, based on the address portion including the specific bit, Determine the number of serial memory address bytes.

  According to the embodiment, it is possible to provide means for enabling determination of the number of address bytes of the serial memory without writing determination data in the serial memory.

It is a block diagram which shows the structural example of the address byte number determination apparatus of one Embodiment. It is a figure which shows an example of the address of a serial memory. It is a flowchart which shows the operation example of the address byte number determination apparatus of one Embodiment. It is a block diagram which shows the system example (embodiment 1) of the semiconductor device using the address byte number determination apparatus of one Embodiment. 3 is a detailed configuration diagram illustrating an example of an address byte count detection module according to Embodiment 1. FIG. It is a detailed block diagram which shows an example of an SPI signal switching module. 6 is a flowchart illustrating an operation example of a CPU in the semiconductor device of FIG. 6 is a flowchart (first half) showing an operation example of determination of the number of address bytes of the serial memory in the address byte number detection module of the first embodiment. 6 is a flowchart (second half) illustrating an operation example of determination of the number of address bytes of the serial memory in the address byte number detection module according to the first embodiment. 6 is a flowchart (first half) showing a detailed operation example of obtaining the first data string information of the serial memory in the address byte count detection module of the first embodiment. 5 is a flowchart (second half) illustrating a detailed operation example of obtaining the first data string information of the serial memory in the address byte count detection module of the first embodiment. 6 is a flowchart (first half) showing a detailed operation example of acquiring second data string information of the serial memory in the address byte count detection module of the first embodiment. 6 is a flowchart (second half) illustrating a detailed operation example of acquiring second data string information of the serial memory in the address byte count detection module according to the first embodiment. FIG. 3 is a diagram illustrating an example of data contents of a serial memory having four address bytes connected to the semiconductor device of the first embodiment. 3 is a diagram illustrating an example of data contents of a serial memory having three address bytes connected to the semiconductor device of Embodiment 1. FIG. 3 is a diagram illustrating an example of data contents of a serial memory having two address bytes, which is connected to the semiconductor device of Embodiment 1. FIG. FIG. 3 is a diagram illustrating an example of data contents of a serial memory having an address byte number of 1 connected to the semiconductor device of the first embodiment. 6 is a timing chart (T511) showing an operation example when a serial memory having four address bytes is connected to the semiconductor device of the first embodiment. 6 is a timing chart (T512) showing an operation example when a serial memory having four address bytes is connected to the semiconductor device of the first embodiment. 6 is a timing chart (T521) showing an operation example when a serial memory having three address bytes is connected to the semiconductor device of the first embodiment. 6 is a timing chart (T522) showing an operation example when a serial memory having three address bytes is connected to the semiconductor device of the first embodiment. 6 is a timing chart (T523) illustrating an operation example when a serial memory having three address bytes is connected to the semiconductor device of the first embodiment. 6 is a timing chart (T531) illustrating an operation example when a serial memory having two address bytes is connected to the semiconductor device of the first embodiment. 6 is a timing chart (T532) showing an operation example when a serial memory having two address bytes is connected to the semiconductor device of the first embodiment. 6 is a timing chart (T533) showing an operation example when a serial memory having two address bytes is connected to the semiconductor device of the first embodiment. 6 is a timing chart (T534) showing an operation example when a serial memory having two address bytes is connected to the semiconductor device of the first embodiment. 6 is a timing chart (T541) showing an operation example when a serial memory having an address byte number of 1 is connected to the semiconductor device of Embodiment 1. 6 is a timing chart (T542) showing an operation example when a serial memory having an address byte number of 1 is connected to the semiconductor device of Embodiment 1. 5 is a timing chart (T543) illustrating an operation example when a serial memory having an address byte number of 1 is connected to the semiconductor device of Embodiment 1. 6 is a timing chart (T544) showing an operation example when a serial memory having one address byte is connected to the semiconductor device of the first embodiment. It is a block diagram which shows the other system example (Embodiment 2) of the semiconductor device using the address byte number determination apparatus of one Embodiment. 20 is a flowchart illustrating an operation example of the semiconductor device of FIG. It is a block diagram which shows the system example of the semiconductor device which performs a program. FIG. 10 is a connection wiring diagram for accessing a serial memory having an interface conforming to the SPI of Patent Document 1. 10 is an access mode determination processing flowchart of Patent Document 1; 10 is a list of read data for each access mode in determination data read processing of Patent Document 1. 10 is a detailed flowchart of the determination process of Patent Document 1.

  Hereinafter, embodiments will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

FIG. 1 shows an example of the configuration of an address byte number determination apparatus according to an embodiment. The address byte count determination device 10 includes a memory input / output unit 11, an address generation unit 12, a first data string acquisition unit 13, a second data string acquisition unit 14, a comparison unit 15, and a control unit 16. Although not shown in FIG. 1, the address byte number determination device 10 is mounted on, for example, a semiconductor device, and transmits and receives data to and from a serial memory that can be connected to the semiconductor device.
The memory input / output unit 11 serves as an interface with the serial memory. Specifically, an address is output to the serial memory, and a continuous data string is received from the serial memory according to the address.

The address generation unit 12 assumes the maximum number of bytes of the address of the serial memory, and first sends the first address having the maximum number of bytes to the memory input / output unit 11. Next, after the memory input / output unit 11 acquires data corresponding to the first address, the second address obtained by inverting the specific bit of the first address is sent to the memory input / output unit 11.
Here, in order to facilitate the description of the specific bit, it is used that the first and second addresses have a configuration having a maximum number of bytes of an address part having a size of 1 byte. In addition, when specifying each address part, it is expressed as the Xth address part (X is an integer from 1 to the maximum number of bytes). For example, when the maximum number of bytes is 3, the first and second addresses consist of three address parts from the first to the third.
The relationship between the number of address bytes and the address part will be specifically described with reference to FIG. In FIG. 2, the case of each address byte number 1 to 4 is shown as an example. It shows that the address having 1 to 4 address bytes has a configuration having address parts from the first to each address byte number.

Furthermore, the address of the serial memory may use all the areas (bits) of 1 to 4 address bytes, but may use a part of the area. For example, as the address of the serial memory, there are cases where the upper bits except for the least significant bit of the highest address part (first address part) are not used. FIG. 2 shows an example in which a part of the address area of the number of address bytes is not used. FIG. 2 shows a state in which an address area having 1 to 4 address bytes is composed of one or more address parts. In addition, of the address area, an area used as a bit for specifying an address is indicated by a hatched rectangular area. The black circle is the least significant bit of each address.
In each address of 1 to 4 address bytes, the least significant bit of the address part of the least significant byte (address part of the number of address bytes) is always used as a bit for specifying an address. It is done. For this reason, when the least significant bit (bit indicated by an arrow in FIG. 2) of each address part is used as the specific bit, the validity / invalidity of each address part can be reliably detected. For example, in FIG. 2, if the rightmost bit is valid, it can be determined that the number of address bytes is four.

  Therefore, the address generator 12 preferably uses the least significant bit of each address part of the first address as a specific bit. Furthermore, it is preferable that the address generation unit 12 first inverts the least significant bit of the address part having the maximum number of bytes as the specific bit, and sequentially inverts the least significant bit of the upper address part. As a result, the validity / invalidity is determined in order from the lower address part (in the case of a large address byte number), so that the number of address bytes can be determined efficiently. For the first address part, when it is detected that the other address part is invalid, it can be determined that the number of address bytes is one. Therefore, for the first address part, the number of address bytes can be determined without reversing the specific bit to determine validity / invalidity.

The first data string acquisition unit 13 acquires the first data string when the memory input / output unit 11 outputs the first address to the serial memory and reads data corresponding to the first address. The first data string acquisition unit 13 uses, as the first data string, first tail data that is different from the first head data value from the first head data value acquired first among the data strings read by the memory input / output unit 11. Get the data string until the value is detected.
The second data string acquisition unit 14 acquires the second data string when the memory input / output unit 11 outputs the second address to the serial memory and reads data corresponding to the second address. The second data string acquisition unit 14 uses, as the second data string, second tail data different from the second head data value from the first head data value acquired first in the data string read by the memory input / output unit 11. Get the data string until the value is detected.
The comparison unit 15 outputs a comparison result indicating whether the first data string and the second data string match or do not match.

The control unit 16 receives a clock signal and a reset signal from the outside, and controls the start and completion of the address byte count determination process. Further, when the control unit 16 receives the comparison result from the comparison unit 15 and detects that the comparison result does not match, the control unit 16 determines the number of address bytes of the serial memory based on the address portion including the specific bit, and determines the determined address byte Print a number. On the other hand, when the comparison result indicates coincidence, the control unit 16 controls the address generation unit 12 to send the second address with the specific bit changed to a different position to the memory input / output unit 11. The control unit 16 controls the second data string acquisition unit 14 to repeat acquisition of the second data string corresponding to the second address whose specific bit is changed until the address byte number is determined.
The control unit 16 determines the number of address bytes as follows.
When the comparison result is inconsistent and the address part lower than the address part including the specific bit is invalid, the control unit 16 determines the number of address bytes from the first to the address part including the specific bit. It is determined that This is a case where an address part including a specific bit and a higher-order address part are valid.
Further, when the comparison result is coincident and the address part from the second to the maximum number of bytes is invalid (invalid except for the first address part), the control unit 16 determines that the number of address bytes is It is determined that it is 1 byte.

  For example, when the address generation unit 12 sets specific bits in the higher-order address part in order from the maximum number of bytes, the control unit 16 detects the number of address bytes when detecting that the comparison result does not match Is determined to be the number of bytes from the first to the address part including the specific bit. Further, even if the comparison result is coincident, if the address portion from the second to the maximum number of bytes is invalid, the control unit 16 determines that the number of address bytes is 1 byte.

Next, the operation will be described with reference to FIG. FIG. 3 shows an operation example of the address byte number determination apparatus according to the embodiment.
Here, it is assumed that any component of the address byte count determination device 10, for example, the control unit 16 or the address generation unit 12 holds the assumed maximum number of bytes of the address of the serial memory. This process may be set in advance in the address byte count determination apparatus 10 or may be input from the outside at the start of the process. It is sufficient that at least the address generation unit 12 can generate the first address having the maximum number of bytes. For example, the address generation unit 12 may hold a preset value as the first address.
When the control unit 16 receives an instruction to start the address byte number determination process (for example, release of the reset signal) (S11), the address generation unit 12 generates a first address having the maximum number of bytes, and the memory input / output unit Send to 11. The memory input / output unit 11 outputs the first address to the serial memory (S12).
The memory input / output unit 11 reads the data string from the serial memory in response to the output of the first address, and the first data string acquisition unit 13 acquires the first data string (S13).

When detecting that the first data string has been acquired, the control unit 16 instructs the address generation unit 12 to generate a second address. The address generation unit 12 generates a second address obtained by inverting the specific bit of the first address in accordance with an instruction from the control unit 16 and sends the second address to the memory input / output unit 11. The memory input / output unit 11 outputs the second address to the serial memory (S14).
The memory input / output unit 11 reads the data string from the serial memory in response to the output of the second address, and the second data string acquisition unit 14 acquires the second data string (S15).
When the first and second data strings are held, the comparison unit 15 compares the first data string and the second data string, and outputs the comparison result to the control unit 16 (S16).
When the control unit 16 detects from the comparison result that the first data string and the second data string are inconsistent and the address part including the specific bit is valid (S17, YES), the control part 16 includes an address part including the specific bit. The number of address bytes of the serial memory is determined based on the above, the determination result is output, and the process is terminated (S18). On the other hand, if the comparison results match (S17, NO), the control unit 16 checks the validity / invalidity of the address part from the second to the maximum number of bytes (S19). When all the address parts from the second to the maximum number of bytes are invalid (S19, YES), the number of address bytes is 1 byte. Therefore, the control unit 16 determines the number of address bytes, and determines the determination result. The process is output and the process is terminated (S18).

  On the other hand, when there is an address part for which validity / invalidity is not determined in the address part from the second to the maximum number of bytes) (S19, NO), the control unit 16 sends the specific bit to the address generation unit 12 at a different position. The second address changed to is controlled to be sent to the memory input / output unit 11. When the address generation unit 12 is instructed to generate a new second address from the control unit 16, the address generation unit 12 generates a second address in which the position of the specific bit is changed, and the address byte number determination device 10 performs the above-described step S14 and subsequent steps. Repeat the process. At this time, the address generation unit 12 is instructed by the control unit 16 for the position of the specific bit. The control unit 16 controls the address generation unit 12 to repeat sending the second address in which the specific bit is changed to a different part to the memory input / output unit 11 until the number of address bytes can be determined.

For example, the control unit 16 sets the first specific bit of the second address as the least significant bit of the address part of the maximum number of bytes, and then generates the specific bit of the second address generated after that of the second address generated immediately before. The address generator 12 is controlled so as to be the least significant bit of the address part one level higher than the address part including the specific bit.
When the memory input / output unit 11 reads a data string in response to a new output of the second address to the serial memory, the second data string acquisition unit 14 is configured to acquire a new second data string. (S16). The comparison unit 15 is configured to update the comparison result when the second data string acquisition unit 14 newly acquires the second data string (S17).

In one embodiment, the serial memory assumes that multiple values (different values) are stored. This is to detect tail data that is different from the head data from which data acquisition is started.
The address byte number determination apparatus 10 has been described above with reference to FIGS. 1 to 3. In the following, a more specific embodiment of the address byte number determination device 10 and a configuration example when the address byte number determination device 10 of one embodiment is mounted on a semiconductor device will be described.

Embodiment 1. FIG.
* Configuration of Embodiment 1 FIG. 4 is a diagram illustrating a system configuration example of a semiconductor device using an address byte number determination device according to Embodiment 1. The system configuration example of the first embodiment includes a serial memory 101 and a semiconductor device 102 on which the address byte number determination device of one embodiment is mounted. The semiconductor device 102 is externally connected to the serial memory 101.
The semiconductor device 102 includes a clock generation module (CLKGEN) 103, a CPU 104, a ROM 105, a RAM (Random Access Memory) 106, a general-purpose input / output port (GPIO) 107, an address byte number detection module (ADDRESS BYTE DETECTOR) 108, and a clocked serial. An interface module (CLOCKED SERIAL INTERFACE) 109 and an SPI signal switching module (SEL) 110 are included. The address byte number detection module 108 is an aspect of the address byte number determination device. In the first embodiment, an example of mounting on the semiconductor device 102 is shown.

The clock generation module 103 outputs a clock signal N116 and a reset signal N117 to the system bus N115.
The CPU 104 is a bus master connected to the system bus N115, and accesses the ROM 105, RAM 106, general-purpose input / output port 107, and clocked serial interface module 109 via the system bus N115.
The ROM 105 is a bus slave connected to the system bus N115, and outputs data stored in the ROM as read data of the system bus N115 in response to a read access request from the system bus N115.
The RAM 106 is a bus slave connected to the system bus N115. The RAM 106 stores write data input from the system bus N115 in the RAM in response to a write access request from the system bus N115, and stores data stored in the RAM in response to a read access request from the system bus N115. Output as read data of the bus N115.

The general-purpose input / output port 107 is a bus slave connected to the system bus N115, receives the address byte count detection completion signal N113 and the address byte count detection result signal N114, and responds to a read access request from the system bus N115. The state of the address byte number detection completion signal N113 and the address byte number detection result signal N114 is output as read data of the system bus N115.
The address byte number detection module 108 receives a clock signal N116, a reset signal N117, and an address byte number detection data output signal N108, and receives an address byte number detection completion signal N113, an address byte number detection result signal N114, and an address byte number detection. Device selection signal N105, address byte count detection clock signal N106, and address byte count detection data input signal N107.

The clocked serial interface module 109 is a bus slave connected to the system bus N115, receives an SPI input / output data output signal N112, receives an SPI input / output device selection signal N109, and an SPI input / output clock signal. N110 and an SPI input / output data input signal N111 are output.
The SPI signal switching module 110 includes an address byte number detection device selection signal N105, an address byte number detection clock signal N106, an address byte number detection data input signal N107, an SPI input / output device selection signal N109, and an SPI input / output clock. In response to the signal N110, the SPI input / output data input signal N111, the serial memory data output signal N104, and the address byte number detection completion signal N113, the address byte number detection data output signal N108 and the SPI input / output data output signal N112 are received. The serial memory device selection signal N101, the serial memory clock signal N102, and the serial memory data input signal N103 are output.
The serial memory 101 receives a serial memory device selection signal N101, a serial memory clock signal N102, and a serial memory data input signal N103, and outputs a serial memory data output signal N104.

  Generally, a semiconductor device has a configuration in which a clocked serial interface module 109 is connected to a serial memory 101 to control data input / output. However, in this embodiment, the general-purpose input / output port 107, the address byte count detection module 108, the clocked serial interface module 109, and the SPI signal switching module 110 serve as an interface with the serial memory 101. In other words, since the semiconductor device 102 of this embodiment is equipped with the address byte count detection module 108 that is the address byte count determination device of this embodiment, the general-purpose input / output port 107 and the SPI signal switching module 110 are further provided. Prepare. It can be said that these components realize at least the following functions by the input / output described above.

The clocked serial interface module 109 functions as a serial interface unit that controls data input / output with the serial memory 101 in normal operation.
The address byte count detection module 108 is activated before the address byte count is determined, and determines the address byte count of the serial memory 101 connected to the semiconductor device 102.
The general purpose input / output port 107 outputs the content of the control signal for controlling the switching of the SPI signal switching module 110 to the system bus N115 in response to the access request. As the control signal, a signal indicating whether or not the address byte number detection module 108 detects the address byte number (address byte number detection completion signal N113 in FIG. 4) is used.
The SPI signal switching module 110 switches between the clocked serial interface module 109 and the address byte number detection module 108 in accordance with a control signal, and functions as a switch unit connected to the serial memory. Specifically, the SPI signal switching module 110 connects the address byte number detection module 108 and the serial memory 101 before the address byte number of the serial memory 101 is detected, and after the address byte signal is detected. The clocked serial interface module 109 and the serial memory 101 are controlled to be connected.

FIG. 5 is a detailed configuration diagram of the address byte count detection module 108.
The address byte count detection module 108 includes a serial transfer clock generation module (SKGEN) 201, a sequence control module (SEQ) 202, a byte selection module 203, a bit inversion control module 204, a parallel / serial conversion module 205, an AND gate 206, a serial / serial It comprises a parallel conversion module 207, 1-byte registers (REG) 208 to 211, counters (CONTER) 212 and 213, comparators (EQ) 214 to 218, and an AND gate 219.

The serial transfer clock generation module 201 receives the bus clock signal N116 and outputs the serial transfer clock signal N201. Thus, the serial transfer clock generation module 201 generates an internal clock in the address byte count detection module 108 based on the bus clock signal.
The sequence control module 202 receives a bus clock signal N116, a bus reset signal N117, a serial transfer clock signal N201, a comparison result output signal N225, a comparison result output signal N226, and a comparison result output signal N230, and outputs byte data. Selection signal N204, bit inversion control signal N206, data update control signal N208, clock output enable signal N209, address byte number detection device selection signal N105, reception data capture control signal N211, reception data capture control signal N212, reception data capture control A signal N213, a reception data capture control signal N214, a counter initialization signal N219, a count clock N220, a counter initialization signal N221, and a count clock N222 are output. As a result, the sequence control module 202 controls the start / end of the address byte count detection process and each component of the address byte count detection module 108.

The bit inversion control module 204 receives the address byte number detection address signal N202 and the bit inversion control signal N206, and outputs a bit inversion controlled address N207. Accordingly, the bit inversion control module 204 generates a first address having the maximum number of bytes and a second address obtained by inverting a specific bit of the first address.
The byte selection module 203 receives a 1-byte address byte number detection instruction code N203, a 4-byte bit inversion controlled address N207, and an output byte data selection signal N204, and outputs output byte data N205. Thereby, the byte selection module 203 selects the position of the byte to be sent to the serial memory 101 from the address.
The parallel / serial conversion module 205 receives the output byte data N205, the data update control signal N208, and the serial transfer clock signal N201, and outputs a data input signal N107 for detecting the number of address bytes.
The AND gate 206 receives the serial transfer clock signal N201 and the clock output permission signal N209, and outputs an address byte count detection clock signal N106.
Serial / parallel conversion module 207 receives serial transfer clock signal N201 and data output signal N108 for detecting the number of address bytes, and outputs received data N210.

The 1-byte register 208 receives the reception data N210 and the reception data capture control signal N211 and outputs captured reception data N215.
The 1-byte register 209 receives the reception data N210 and the reception data capture control signal N212, and outputs captured reception data N216.
The 1-byte register 210 receives the reception data N210 and the reception data capture control signal N213, and outputs captured reception data N217.
The 1-byte register 211 receives the reception data N210 and the reception data capture control signal N214, and outputs captured reception data N218.
The counter 212 receives the counter initialization signal N219 and the count clock N220, and outputs a count result N223.
The counter 213 receives the counter initialization signal N221 and the count clock N222, and outputs a count result N224.

The comparator 214 receives the captured reception data N215 and the captured reception data N216, and outputs a comparison result output signal N225.
The comparator 215 receives the captured reception data N217 and the captured reception data N218, and outputs a comparison result output signal N226.
The comparator 216 receives the captured reception data N215 and the captured reception data N217, and outputs a comparison result output signal N227.
The comparator 217 receives the captured reception data N216 and the captured reception data N218, and outputs a comparison result output signal N228.
Comparator 218 receives count result N223 and count result N224, and outputs comparison result output signal N229.
AND gate 219 receives comparison result output signal N227, comparison result output signal N228, and comparison result output signal N229, and outputs comparison result output signal N230.

Here, the configuration of FIG. 1 is associated with the configuration of FIG. 4 as follows.
The byte selection module 203, the parallel / serial conversion module 205, the AND gate 206, and the serial / parallel conversion module 207 constitute the memory input / output unit 11 and operate to control data input / output with the serial memory 101. .
The bit inversion control module 204 constitutes the address generation unit 12 and functions to generate addresses (first address and second address) to be output to the serial memory 101.
The 1-byte registers 208 and 209, the counter 212, and the comparator 214 constitute the first data string acquisition unit 13 and operate to acquire the first data string.
The 1-byte registers 210 and 211, the counter 213, and the comparator 215 constitute the second data string acquisition unit 14 and operate to acquire the second data string.
The comparators 216 to 218 and the AND gate 219 constitute a comparison unit 15 and outputs a comparison result indicating whether the first data string and the second data string match or do not match.
The serial transfer clock generation module 201 and the sequence control module 202 constitute the control unit 16 and determine the number of address bytes. In addition, each component is controlled to function so that the number of address bytes can be detected.

Here, in the first embodiment, the first data string is held as first data string information including the first head data value, the first tail data value, and the length (first data length) of the first data string. To do. Similarly, the second data string is held as second data string information including the second head data value, the second tail data value, and the length (second data length) of the second data string. Specifically, the following components are held.
The 1-byte register 208 holds the first head data value of the first data string. The 1-byte register 209 holds the first end data value of the first data string. The counter 212 holds the first data length. Here, the first data length is the total number of bytes of the first data string. The semiconductor device 102 reads data from the serial memory 101 byte by byte. Therefore, the value held by the counter 212 holds the number of times (acquisition number) that the semiconductor device 102 has acquired each data of the first data string until the first end data value is acquired from the first start data value. It can also be said.
Similarly for the second data string information, the 1-byte register 210 holds the second head data value of the second data string. The 1-byte register 211 holds the second end data value of the second data string. The counter 213 holds the second data length.
In addition, the AND gate 219 outputs a comparison result indicating a match when all the elements of the first data string information and the second data string information match based on the comparison results of the comparators 216 to 218. If any element does not match, a comparison result indicating mismatch is output.

FIG. 6 is a detailed configuration diagram illustrating an example of the SPI signal switching module 110.
The SPI signal switching module 110 includes selectors (SEL) 301 to 303, a buffer 304, and a buffer 305.
The selector 301 receives the address byte number detection device selection signal N105, the SPI input / output device selection signal N109, and the address byte number detection completion signal N113, and outputs a serial memory device selection signal N101.
The selector 302 receives the address byte number detection clock signal N106, the SPI input / output clock signal N110, and the address byte number detection completion signal N113, and outputs a serial memory clock signal N102.
The selector 303 receives the address byte number detection data input signal N107, the SPI input / output data input signal N111, and the address byte number detection completion signal N113, and outputs a serial memory data input signal N103.
The buffer 304 receives the serial memory data output signal N104 and outputs the address byte count detection data output signal N108.
The buffer 305 receives the serial memory data output signal N104 and outputs an SPI input / output data output signal N112.

* Operation of Embodiment 1 The operation of the semiconductor device 102 described with reference to FIGS. 4, 5, and 6 is illustrated in the flowcharts of FIGS. 7, 8A, 8B, 9A, 9B, 10A, and 10B, and FIGS. 14 data content examples, FIGS. 15A to 15B, FIGS. 16A to 16C, FIGS. 17A to 17D, and FIGS. 18A to 18D.
When the system of FIG. 4 is turned on, in the semiconductor device 102, the clock generation module 103 asserts the reset signal N117 and starts outputting the clock to the clock signal N116. Then, the clock generation module 103 deasserts the reset signal N117 after a predetermined time has elapsed.

FIG. 7 is a flowchart showing the operation of the CPU 104 in the semiconductor device 102 of this embodiment.
The CPU 104 reads the state of the address byte count detection completion signal N113 from the general-purpose input / output port 107 (step S101).
If the address byte count detection is completed (S102, YES), the process proceeds to the next step S103. If the address byte count detection is not completed (S102, NO), the process returns to step S101 to return to the address The process of reading the state of the address byte number detection completion signal N113 is repeated until the byte number detection is completed (step S102).
When the address byte number detection is completed, the CPU 104 reads the state of the address byte number detection result signal N114 from the general-purpose input / output port 107, and acquires the number of address bytes of the connected serial memory (step S103).
Thereafter, the CPU 104 operates the clocked serial interface module 109 to assemble an SPI bus cycle according to the acquired number of address bytes of the serial memory. As a result, the CPU 104 accesses the serial memory 101 (step S104).

8A and 8B are flowcharts showing the operation of the address byte count detection module 108 in the semiconductor device 102 of this embodiment.
In the initial state, the address byte number detection completion signal N113 is initialized to a low level, and a serial memory read instruction code (03h) used when detecting the number of address bytes is given as a fixed value. Here, it is assumed that the maximum number of bytes of the serial memory 101 is 4 bytes. For example, the sequence control module 202 initializes the address byte count detection completion signal N113 to a low level when the reset signal N117 is asserted, and starts a process of generating an address when the reset signal N117 is deasserted. In this manner, the bit inversion control module 204 is controlled. Thereby, a process for determining the number of address bytes is started.
First, the bit inversion control module 204 selects an arbitrary 4-byte value as the first address and supplies it to the bit inversion controlled address N207 (step S201). At this time, the bit inversion control signal N206 is deasserted, and the value of the address byte number detection address signal N202 is output as it is to the bit inversion controlled address N207. Here, the arbitrary 4-byte value serving as the first address may be a value previously stored in the address byte number detection module 108 or may be configured to use a value input from the outside. Also good. The maximum number of bytes is the same as an arbitrary 4-byte value.
Next, the first data string is read from the serial memory 101 using the first address, and the first data string information is acquired (step S202). A detailed flow for acquiring a data string in the serial memory will be described separately.
In the first data string information acquired in step S202, the first value (first head data value) read first is stored in the 1-byte register 208, and is read first after the second byte. A second value (first tail data value) different from the value stored in the 1-byte register 208 is stored in the 1-byte register 209. Further, the total number of bytes (first data length) read until the second value is stored from the first value is stored in the counter 212.
Next, the bit inversion control module 204 selects a value obtained by inverting bit 0 of the first address as the second address (S203). Here, bit 0 of the first address is the least significant bit of the address part (lowest address part) of the maximum number of bytes. At this time, the sequence control module 202 controls the bit inversion control signal N206. Thus, a value obtained by inverting bit 0 of the address byte number detection address signal N202 is output to the bit inversion controlled address N207.

When the second address is output to the serial memory 101, data string information is acquired from the serial memory 101 (step S204). A detailed flow for acquiring a data string in the serial memory will be described separately.
In the second data string information acquired in step S204, the first value (second head data value) read first is stored in the 1-byte register 210, and is read first after the second byte. A second value (second tail data value) different from the 1-byte register 210 is stored in the 1-byte register 211. Further, the total number of bytes (second data length) read until the second value is stored is stored in the counter 213.
Next, the comparators 216 to 218 perform matching confirmation between the first data string information obtained in step S202 and the second data string information obtained in step S204 (step S205). Data string information matching is confirmed by checking that all elements match. The comparator 216 compares the first values (first head data value and second head data value) of the first and second data string information. The comparator 217 compares the second values (first tail data value and second tail data value) of the first and second data string information. The comparator 218 compares the count values (first data length and second data length) of the total number of bytes of the first and second data string information. The AND gate 219 detects that the elements match, and outputs a match confirmation result of the first and second data string information to the comparison result output signal N230. The comparison result output signal N230 is input to the sequence control module 202.

If the first data string information and the second data string information do not match, it means that bit 0 of the address inverted in step S203 is a valid address bit in the serial memory 101. Accordingly, the sequence control module 202 determines that the number of address bytes of the connected serial memory 101 is 4 (step S206), and proceeds to the final step S216.
If the data string information matches, bit 0 of the address inverted in step S203 is an invalid address bit in the serial memory 101. Therefore, the sequence control module 202 performs control to proceed to the next step S207 in order to further determine the number of address bytes in the serial memory 101 using the new second address.

  The bit inversion control module 204 selects a value obtained by inverting bit 8 of the first address as a new second address (step S207). Here, bit 8 of the first address is the least significant bit of the third address part in the first address, and the specific bit is one address higher than the fourth (maximum number of bytes) address part one before. It will be set to the part. At this time, the sequence control module 202 controls the bit inversion control signal N206 so that the bit inversion control module 204 inverts bit 8 of the first address. As a result, a value obtained by inverting bit 8 of the address byte number detection address signal N202 is output to the bit inversion controlled address N207.

When the new second address is output to the serial memory 101, the second data string information corresponding to the new second address is acquired from the serial memory 101 (step S208). A detailed flow of acquiring a data string in the serial memory 101 will be described separately.
The second data string information acquired in step S208 is stored in the same manner as in step S204.
Next, the comparators 216 to 218 perform matching confirmation between the first data string information obtained in step S202 and the second data string information obtained in step S208 (step S209). Data string information matching is confirmed by checking that all elements match. Since the specific operations of the comparators 216 to 218 are the same as those in step S205, description thereof will be omitted.

If the data string information does not match, bit 8 of the address inverted in step S207 is a valid address bit in the serial memory 101. Therefore, the sequence control module 202 determines that the number of address bytes of the connected serial memory 101 is 3 (step S210), and proceeds to the final step S216.
If the data string information matches, bit 8 of the address inverted in step S207 is an invalid address bit in the serial memory 101. Accordingly, the sequence control module 202 performs control to proceed to the next step S211 in order to further determine the number of address bytes of the serial memory 101 using the new second address.
The bit inversion control module 204 selects a value obtained by inverting the bit 16 of the first address as the second address (step S211). Here, bit 16 of the first address is the least significant bit of the second address part in the first address, and the specific bit is set to the address part one higher than the previous third address part. become. At this time, the sequence control module 202 controls the bit inversion control signal N206. As a result, a value obtained by inverting bit 16 of the address byte number detection address signal N202 is output to the bit inversion controlled address N207.

When a new second address is output to the serial memory 101, new data string information is acquired from the serial memory 101 (step S212). A detailed flow of acquiring a data string in the serial memory 101 will be described separately.
The second data string information acquired in step S212 is stored in the same manner as in steps S204 and S208.
Next, the comparators 216 to 218 perform matching confirmation between the first data string information obtained in step S202 and the second data string information obtained in step S212 (step S213). Data string information matching is confirmed by checking that all elements match. Since the specific operations of the comparators 216 to 218 are the same as those in steps S205 and S209, description thereof will be omitted.

If the data string information does not match, the bit 16 of the address inverted in step S211 is a valid address bit in the serial memory 101. Accordingly, the sequence control module 202 determines that the number of address bytes of the connected serial memory 101 is 2 (step S214), and proceeds to the final step S216.
If the data string information matches, the bit 16 of the address inverted in step S211 is an invalid address bit in the serial memory 101. Accordingly, the sequence control module 202 determines that the number of address bytes of the connected serial memory 101 is 1 (step S215), and proceeds to the final step S216.
In the final step S216, the sequence control module 202 outputs a high level to the address byte number detection completion signal N113 to notify the outside of the completion of address byte number detection. In addition, the sequence control module 202 outputs the detected number of address bytes to the address byte number detection result signal N114.

Next, an operation in which the address byte number detection module 108 acquires the first data string information and the second data string information will be described.
9A and 9B are detailed flowcharts of the first data string information acquisition (step S202 in FIG. 8A) of the serial memory 101 in the address byte count detection module 108 of the present embodiment.
First, the sequence control module 202 outputs a counter initialization signal N219 and clears the counter 212 of the total number of bytes (step S301).
Next, the sequence control module 202 outputs a low level to the address byte count detection device selection signal N105 to start an SPI bus cycle (step S302).
Next, the sequence control module 202 transmits the address byte count detection instruction code N203 (step S303).
In accordance with the output byte data selection signal N204 output from the sequence control module 202, the byte selection module 203 outputs the value of the address byte count detection instruction code N203 to the output byte data N205.
Subsequently, when the data update control signal N208 is asserted by the sequence control module 202, the value of the output byte data N205 is stored in the parallel / serial conversion module 205, and the number of address bytes is synchronized with the serial transfer clock signal N201. The detection data input signal N107 is serially output in order from the MSB.

Next, the bits 31 to 24 of the address are transmitted (step S304). In accordance with the output byte data selection signal N204 output from the sequence control module 202, the byte selection module 203 outputs the values of bits 31 to 24 of the bit inversion controlled address N207 to the output byte data N205.
Subsequently, when the data update control signal N208 is asserted, the value of the output byte data N205 is stored in the parallel / serial conversion module 205. The parallel / serial conversion module 205 serially outputs the values stored in the address byte count detection data input signal N107 in order from the MSB in synchronization with the serial transfer clock signal N201.

Next, the bits 23 to 16 of the address are transmitted (step S305). In accordance with the output byte data selection signal N204 output from the sequence control module 202, the byte selection module 203 outputs the values of bits 23 to 16 of the bit inversion controlled address N207 to the output byte data N205.
Subsequently, when the data update control signal N208 is asserted, the value of the output byte data N205 is stored in the parallel / serial conversion module 205. The parallel / serial conversion module 205 serially outputs the values stored in the address byte count detection data input signal N107 in order from the MSB in synchronization with the serial transfer clock signal N201.

Next, bits 15 to 8 of the address are transmitted (step S306). In accordance with the output byte data selection signal N204 output from the sequence control module 202, the byte selection module 203 outputs the values of the bits 15 to 8 of the bit inversion controlled address N207 to the output byte data N205.
Subsequently, when the data update control signal N208 is asserted, the value of the output byte data N205 is stored in the parallel / serial conversion module 205. The parallel / serial conversion module 205 serially outputs the values stored in the address byte count detection data input signal N107 in order from the MSB in synchronization with the serial transfer clock signal N201.
Next, bits 7 to 0 of the address are transmitted (step S307). In accordance with the output byte data selection signal N204 output from the sequence control module 202, the byte selection module 203 outputs the value of bits 7 to 0 of the bit inversion controlled address N207 to the output byte data N205.
Subsequently, when the data update control signal N208 is asserted, the value of the output byte data N205 is stored in the parallel / serial conversion module 205. The parallel / serial conversion module 205 serially outputs the values stored in the address byte count detection data input signal N107 in order from the MSB in synchronization with the serial transfer clock signal N201.

Next, the serial / parallel conversion module 207 acquires 1-byte data (step S308).
Specifically, the serial / parallel conversion module 207 receives 8 bits of the address byte number detection data output signal N108 inputted in synchronization with the address byte number detection clock signal N106, and receives 1 byte of received data. N210 is obtained. The reception data N210 is stored in the 1-byte register 208 as a first value (first head data value) under the control of the reception data capture control signal N211.

Next, the counter 212 is incremented under the control of the count clock N220 (step S309).
Next, the serial / parallel conversion module 207 obtains subsequent 1-byte data (step S310).
Specifically, the serial / parallel conversion module 207 receives 8 bits of the address byte number detection data output signal N108 inputted in synchronization with the address byte number detection clock signal N106, and receives 1 byte of received data. N210 is obtained. The reception data N210 is stored in the 1-byte register 209 as a second value under the control of the reception data capture control signal N212.
Next, the counter 212 is incremented under the control of the count clock N220. (Step S311).

Next, the comparator 214 compares the first value with the second value (step S312). The comparator 214 outputs a result of comparing the captured reception data N215 and the captured reception data N216 as a comparison result output signal N225. The sequence control module 202 refers to the comparison result output signal N225. If they match (step S312: YES), the sequence control module 202 returns to step S310 and repeats the process. If they do not match (step S312: NO), the next step Control is performed to proceed to S313. When the comparison result output signal N225 indicates a match, the second value stored in the 1-byte register 209 is the first tail data.
Finally, the sequence control module 202 outputs a high level to the address byte count detection device selection signal N105 and ends the SPI bus cycle (step S313).
As described in steps S308 to S312, the sequence control module 202 holds the first head data value in the 1-byte register 208, and continues to the second of the first data string until the output of the comparator 214 indicates a mismatch. The first end data value is controlled to be held in the 1-byte register 209 by fetching it into the 1-byte register 209 in order from the acquired value.

10A and 10B are detailed flowcharts of the second data string information acquisition (step S204, step S208, and step S212 in FIG. 8B) of the serial memory 101 in the address byte count detection module 108 of the present embodiment.
First, the sequence control module 202 outputs the counter initialization signal N221 and clears the counter 213 for the total number of bytes (step S401).
Next, the sequence control module 202 outputs a low level to the address byte count detection device selection signal N105 to start an SPI bus cycle (step S402).
Next, the sequence control module 202 transmits the address byte count detection instruction code N203 (step S403).
In accordance with the output byte data selection signal N204 output from the sequence control module 202, the byte selection module 203 outputs the value of the address byte count detection instruction code N203 to the output byte data N205.
Subsequently, the data update control signal N208 is asserted by the sequence control module 202, the value of the output byte data N205 is stored in the parallel / serial conversion module 205, and is used for detecting the number of address bytes in synchronization with the serial transfer clock signal N201. The data input signal N107 is serially output in order from the MSB.

Next, address bits 31 to 24 are transmitted (step S404). In accordance with the output byte data selection signal N204 output from the sequence control module 202, the byte selection module 203 outputs the values of bits 31 to 24 of the bit inversion controlled address N207 to the output byte data N205.
Subsequently, the data update control signal N208 is asserted, and the value of the output byte data N205 is stored in the parallel / serial conversion module 205. The parallel / serial conversion module 205 serially outputs the values stored in the address byte count detection data input signal N107 in order from the MSB in synchronization with the serial transfer clock signal N201.

Next, the bits 23 to 16 of the address are transmitted (step S405). In accordance with the output byte data selection signal N204 output from the sequence control module 202, the byte selection module 203 outputs the values of bits 23 to 16 of the bit inversion controlled address N207 to the output byte data N205.
Subsequently, when the data update control signal N208 is asserted, the value of the output byte data N205 is stored in the parallel / serial conversion module 205. In synchronization with the parallel / serial conversion module 205 and the serial transfer clock signal N201, the value stored in the address byte count detection data input signal N107 is serially output in order from the MSB.
Next, the bits 15 to 8 of the address are transmitted (step S406). In accordance with the output byte data selection signal N204 output from the sequence control module 202, the byte selection module 203 outputs the values of the bits 15 to 8 of the bit inversion controlled address N207 to the output byte data N205.
Subsequently, when the data update control signal N208 is asserted, the value of the output byte data N205 is stored in the parallel / serial conversion module 205. In synchronization with the parallel / serial conversion module 205 and the serial transfer clock signal N201, the value stored in the address byte count detection data input signal N107 is serially output in order from the MSB.

Next, bits 7 to 0 of the address are transmitted (step S407).
In accordance with the output byte data selection signal N204 output from the sequence control module 202, the byte selection module 203 outputs the value of bits 7 to 0 of the bit inversion controlled address N207 to the output byte data N205.
Subsequently, when the data update control signal N208 is asserted, the value of the output byte data N205 is stored in the parallel / serial conversion module 205. In synchronization with the parallel / serial conversion module 205 and the serial transfer clock signal N201, the value stored in the address byte count detection data input signal N107 is serially output in order from the MSB.
Next, the serial / parallel conversion module 207 acquires 1-byte data (step S408).
Specifically, the serial / parallel conversion module 207 receives 8 bits of the address byte number detection data output signal N108 inputted in synchronization with the address byte number detection clock signal N106, and receives 1 byte of received data. N210 is obtained. The reception data N210 is stored in the 1-byte register 210 as the first value (first head data value) under the control of the reception data capture control signal N213.
Next, the counter 213 is incremented under the control of the count clock N222. (Step S409).

Next, the serial / parallel conversion module 207 obtains subsequent 1-byte data (step S410).
Specifically, the serial / parallel conversion module 207 receives 8 bits of the address byte number detection data output signal N108 inputted in synchronization with the address byte number detection clock signal N106, and receives 1 byte of received data. N210 is obtained. The reception data N210 is stored in the 1-byte register 211 as a second value under the control of the reception data capture control signal N214.

Next, the counter 213 is incremented under the control of the count clock N222. (Step S411).
Next, the comparator 215 compares the first value with the second value (step S412). The comparator 215 outputs the comparison result output signal N226 as a result of comparing the captured reception data N217 and the captured reception data N218. The sequence control module 202 refers to the comparison result output signal N226. If they match (step S412, YES), the sequence control module 202 returns to step S410 and repeats the processing. If they do not match (step S412, NO), the next step Control is made to proceed to S413. When the comparison result output signal N226 indicates coincidence, the second value stored in the 1-byte register 211 is the second tail data.
Finally, the sequence control module 202 outputs a high level to the address byte number detection device selection signal N105, and ends the SPI bus cycle (step S413).
As described in steps S408 to S412, the sequence control module 202 holds the second head data value in the 1-byte register 210, and continues to the second data string until the output of the comparator 215 indicates a mismatch. The second end data value is controlled to be held in the 1-byte register 211 by fetching it into the 1-byte register 211 in order from the value to be acquired.

  Here, a specific operation example will be described using a specific value held in the serial memory 101 and a timing chart of the determination operation of the address byte number detection module 108. 11 to 14 are diagrams showing examples of data contents of the serial memory 101 connected to the semiconductor device 102 of the present embodiment. 15A to 18D are timing charts showing an operation example when the serial memory 101 is connected to the semiconductor device 102 of the present embodiment. 11, 15A, 15B, 4 in FIGS. 11, 15A, 15B, 3 in FIGS. 12, 16A-16C, 2 in FIGS. 13, 17A-17D, 1 in FIGS. 14, 18A-18D, respectively. ing.

As shown in FIGS. 11 to 14, it is assumed that the serial memory 101 stores non-uniform values.
Timing charts indicated by reference numerals T511 to T544 shown in FIGS. 15A to 18D correspond to the processes of FIGS. 8A to 10B as follows. Timing charts T511, T521, T531, and T541 show a case where the first data string information corresponding to the first address is acquired by the process of step S202 of FIG. 8A (the flowcharts of FIGS. 9A and 9B). Timing charts T512, T522, T532, and T542 show a case where the second data string information corresponding to the second address is acquired by the process of step S204 of FIG. 8B (the flowcharts of FIGS. 10A and 10B). Timing charts T523, T533, and T543 show a case where the second data string information corresponding to the new second address is acquired by the process of step S208 of FIG. 8B (the flowcharts of FIGS. 10A and 10B). Timing charts T534 and T544 illustrate a case where second data string information corresponding to a new second address is acquired by the process of step S212 in FIG. 8B (the flowcharts in FIGS. 10A and 10B).
In FIGS. 15A to 18D, the first address is set to “0000FF00h”.

First, a case where the serial memory 101 having 4 address bytes is connected to the semiconductor device 102 will be described.
The serial memory 101 stores data shown in FIG.
In the timing chart T511 shown in FIG. 15A, the first data string information of the serial memory 101 is acquired using the first address (FIG. 8A, step S202).
First, the semiconductor device 102 outputs a low level to the address byte count detection device selection signal N101. Subsequently, the semiconductor device 102 inputs a 1-byte read instruction code (timing C1) and a 4-byte first address (timing C2 to C5) in synchronization with the serial memory clock signal N102. The signal N103 is sequentially output.
Subsequently, the semiconductor device 102 acquires the first value from the serial memory data output signal N104 in synchronization with the serial memory clock signal N102 (timing C6), and the second value having a data value different from the first value. The acquisition of the first data string is continued until the value is acquired (timing C10).
At this time, the serial memory 101 recognizes the read instruction code (timing C1) input to the serial memory data input signal N103 and the 4-byte address 0000FF00h (timing C2 to C5), and transfers the data at the corresponding address to the serial memory. The output of the data output signal N104 is started (timing C6).
Here, the semiconductor device 102 obtains first data string information in which the first value is 00h, the second value is BCh, and the count value is 5.

In the timing chart T512 shown in FIG. 15B, the second data string information of the serial memory 101 is acquired using the second address 0x0000FF01h obtained by inverting bit 0 of the first address 0000FF00h.
At this time, the serial memory 101 recognizes the read instruction code (timing C1) input to the serial memory data input signal N103 and the 4-byte address 0000FF01h (timing C2 to C5), and transfers the data at the corresponding address to the serial memory. The output of the data output signal N104 is started (timing C6).
Here, the semiconductor device 102 obtains second data string information in which the first value is 00h, the second value is BCh, and the count value is 4.

The first and second data string information obtained in the timing charts T511 and T512 do not match.
From this result, it is determined that the number of address bytes of the connected serial memory is 4.

Next, a case where the serial memory 101 having the address byte number 3 is connected to the semiconductor device 102 will be described.
The serial memory 101 stores data shown in FIG.
In the timing charts T521 and T522 shown in FIGS. 16A and 16B, the number of address bytes of the serial memory 101 is three. Therefore, the serial memory 101 recognizes the read instruction code (timing C1) input to the serial memory data input signal N103 and the upper 3 bytes of address 0000FFh (timing C2 to C4), and outputs data of the recognized address. Start (timing C5). On the other hand, the semiconductor device 102 reads the first and second data strings from the timing C6 in order to perform the process of outputting the address until the timing C5. As a result, in the timing charts T521 and T522, the semiconductor device 102 acquires information in which the first value is 00h, the second value is BCh, and the count value is 4, together with the first and second data string information.
The first data string information and the second data string information obtained in the timing charts T521 and T522 match.

In the timing chart T523 illustrated in FIG. 16C, the data string information of the serial memory 101 is acquired using the second address 0x0000FE00 obtained by inverting bit 8 of the first address 0000FF00h.
At this time, the serial memory 101 recognizes the read instruction code (timing C1) input to the serial memory data input signal N103 and the upper 3 bytes of address 0000FEh (timing C2 to C4), and outputs the data output of the corresponding address. Start (timing C5).
Here, the semiconductor device 102 reads the data string from the timing C6, and acquires new second data string information in which the first data is 00h, the second data is BCh, and the count value is 5.
The first and second data string information obtained in the timing charts T521 and T523 do not match.
From this result, it is determined that the number of address bytes of the connected serial memory is 3.
In the timing chart T523, the least significant byte of the address output from the semiconductor device 102 is set to zero in the above description. However, since the serial memory 101 never refers to the value of the least significant byte, any value may be used.

Next, a case where the serial memory 101 having the address byte number 2 is connected to the semiconductor device 102 will be described.
The serial memory 101 stores data shown in FIG.
In the timing charts T531, T532, and T533 shown in FIGS. 17A to 17C, the number of address bytes of the serial memory 101 is two. Therefore, the serial memory 101 recognizes the read instruction code (timing C1) input to the serial memory data input signal N103 and the upper 2 bytes of address 0000h (timing C2 to C3), and outputs the data output of the recognized address. Start (timing C4). On the other hand, the semiconductor device 102 reads the first and second data strings from the timing C6 in order to perform the process of outputting the address until the timing C5. As a result, in the timing charts T531 to T533, the semiconductor device 102 acquires information in which the first value is 00h, the second value is BCh, and the count value is 3, for both the first and second data string information.
The first data string information obtained in the timing charts T531, T532, and T533 and the two second data string information all match.

In the timing chart T534 illustrated in FIG. 17D, the data string information of the serial memory 101 is acquired using the second address 0x0001FF00 obtained by inverting the bit 16 of the first address 0000FF00h.
At this time, the serial memory 101 recognizes the read instruction code (timing C1) input to the serial memory data input signal N103 and the upper 2 bytes of address 0001h (timing C2 to C3), and outputs the data output of the corresponding address. Start (timing C4).
Here, the semiconductor device 102 reads the data string from the timing C6, and acquires new second data string information in which the first value is 00h, the second value is BCh, and the count value is 2.
The first and second data string information obtained in the timing charts T531 and T534 do not match.
From this result, it is determined that the number of address bytes of the connected serial memory is 2.
For the address output from the semiconductor device 102, the least significant 1 byte in the timing chart T533 and the least significant 2 bytes in the timing chart T534 are set to zero in the above description. However, any value may be used because the serial memory 101 does not refer to these values.

Finally, a case where the serial memory 101 having the address byte number 1 is connected to the semiconductor device 102 will be described.
The serial memory 101 stores data shown in FIG.
In the timing charts T541, T542, T543, and T544 shown in FIGS. 18A to 18D, the number of address bytes of the serial memory is one. Accordingly, the serial memory 101 recognizes the read instruction code (timing C1) and the upper 1 byte address 00h (timing C2) input to the serial memory data input signal N103, and starts outputting data of the recognized address ( Timing C3). On the other hand, the semiconductor device 102 reads the first and second data strings from the timing C6 in order to perform the process of outputting the address until the timing C5. As a result, in the timing charts T541 to T544, the semiconductor device 102 acquires information in which the first value is 00h, the second value is BCh, and the count value is 2, for both the first and second data string information.
The first data string information obtained from the timing charts T541 to T544 matches the three second data string information.

From this result, it is determined that the number of address bytes of the connected serial memory is 1.
For the address output from the semiconductor device 102, the least significant 1 byte in the timing chart T543 and the least significant 2 bytes in the timing chart T544 are set to zero in the above description. However, any value may be used because the serial memory 101 does not refer to these values.

* Mechanism and Effect of First Embodiment As described above, when the apparatus and method for determining the number of address bytes according to this embodiment are used, the address bytes of the serial memory 101 are read by reading the existing data stored in the serial memory 101. Determine the number. This does not require writing known determination data to the serial memory 101 for determining the number of address bytes of the serial memory 101. This produces an advantageous effect of determining the number of address bytes even in a mask ROM or a protected non-writable serial memory.
In addition, since it is not necessary to write the determination data to the serial memory 101, there is an effect that the data stored in the serial memory 101 is not destroyed.
Further, since it is not necessary to write determination data to the serial memory 101, an effect that the determination time of the number of address bytes does not increase even if the writing is slow, such as NOR type FLASH, EEPROM, or the like, also occurs.
Further, in the address byte number determination device according to the present embodiment, the address byte number is determined using only the data output from the serial memory without using the constant potential of the serial data output signal given by the pull-up resistor. . As a result, noise immunity is high, and an effect of eliminating the need for a pull-up resistor that maintains the constant potential of the serial data output signal at a high level.

Embodiment 2. FIG.
In the second embodiment, an aspect of a system in the case where the address byte number determination device of one embodiment is mounted on a semiconductor device using a memory controller type serial memory interface will be described.
* Configuration of Second Embodiment FIG. 19 is a diagram illustrating a system configuration example of a semiconductor device in which an address byte number determination device according to the second embodiment is mounted. The system configuration example of the second embodiment includes a serial memory 101 and a semiconductor device 401 on which the address byte number determination device of one embodiment is mounted. The semiconductor device 401 is externally connected to the serial memory 101.
The semiconductor device 401 includes a clock generation module 103, a CPU 104, a RAM 106, an address byte count detection module 108, an SPI memory controller module 402, an inverter 403, and an SPI signal switching module 110.
The SPI memory controller module 402 is a bus slave connected to the system bus N115, and receives the hold request signal N405, the address byte count detection result signal N114, and the SPI input / output data output signal N404, and receives the SPI input. An output device selection signal N401, an SPI input / output clock signal N402, and an SPI input / output data input signal N403 are output. The SPI memory controller module 402 has a function of controlling data input / output with the serial memory 101 after the number of memory bytes is detected.
Inverter 403 receives address byte count detection completion signal N113 and outputs hold request signal N405.
Since the components with the same reference numerals as those in FIG. 4 are the same, the description thereof is omitted.

* Operation of Second Embodiment The operation of the semiconductor device 401 described with reference to FIG. 19 will be described with reference to the flowchart of FIG.
When the system of FIG. 19 is turned on (step S701), in the semiconductor device 401, the clock generation module 103 asserts the reset signal N117 (step S702) and starts outputting the clock to the clock signal N116. When the reset signal N117 is asserted, the address byte number detection module 108 initializes the address byte number detection completion signal N113 to a deasserted state. Further, when address byte count detection completion signal N113 is deasserted, inverter 403 asserts hold request signal N405.
Then, the clock generation module 103 deasserts the reset signal N117 after a predetermined time has elapsed (step S703).
When the reset signal N117 is deasserted, the CPU 104 starts a boot process (step S704). On the other hand, the address byte count detection module 108 starts processing for determining the address byte count when the reset signal N117 is deasserted.
Then, the CPU 104 starts read access to the SPI memory controller module 402 via the system bus N115 to acquire the instruction code (step S705).
At this time, since the address byte count detection module 108 has not detected the address byte count, the address byte count detection completion signal N113 is deasserted, and the hold request signal N405 is asserted.
Since the hold request signal N405 is asserted (step S706, NO), the SPI memory controller module 402 suspends the serial memory bus cycle issuance and keeps the access request from the CPU 104 in the wait state.

Thereafter, when the detection of the number of address bytes of the connected serial memory 101 is completed, the address byte number detection module 108 outputs the detected address byte information to the address byte number detection result signal N114, and the address byte number detection completion signal N113. Is asserted.
The inverter 403 deasserts the hold request signal N405 because the address byte count detection completion signal N113 is asserted.
When the hold request signal N405 is deasserted (YES in step S706), the SPI memory controller module 402 starts a serial memory bus cycle that has been suspended (step S707). At this time, the bus cycle of the serial memory is assembled according to the number of address bytes indicated by the address byte number detection result signal N114, and data corresponding to the access request from the CPU 104 is acquired.
The SPI memory controller module 402 outputs data corresponding to the access request from the CPU 104 to the system bus N115, releases the wait, and completes the access from the CPU 104 (step S708).
Thereafter, in response to an access request from the CPU 104, the SPI memory controller module 402 outputs a value obtained from the serial memory 101 to the system bus N115.

* Effects of the second embodiment Even in the case of a memory controller type serial memory interface, as in the peripheral I / O type serial memory interface described in the first embodiment, the address is not written to the serial memory 101 without determining data. The number of bytes can be detected.

Embodiment 3. FIG.
In each of the above embodiments, when the specific address of the first address is determined to generate the second address, the specific bit is described as one. However, the present invention is not limited to this. For example, it does not exclude that two bits of one address part are determined.
Further, in each of the above embodiments, the specific bit of the second address is assigned to the upper address part one by one from the least significant bit of the address part of the maximum number of bytes among the plurality of address parts from the first to the maximum number of bytes. An example of operation that moves to the least significant bit in order has been described. However, it is not limited to this. For example, the least significant bit (or a plurality of bits including the least significant bit) of the address part in order from the second address part up to the maximum number of bytes is inverted to determine the validity / invalidity of each address part, and then the address It may be a procedure for determining the number of bytes. In this case, the number of address bytes is determined when the comparison result between the first data string information and the second data string information is inconsistent and the other upper address part is valid. In addition, when the comparison result is coincident and the address part from the second to the maximum number of bytes is invalid, the number of address bytes is determined as 1. An example of the operation is the same as the operation described with reference to FIGS.

Embodiment 4 FIG.
The address byte count determination apparatus and method described in each of the above embodiments, for example, the address byte count detection module 108 in FIG. 5 is not limited to being realized by hardware. It may be realized by a combination of hardware and software. It may be realized by any one of hardware, firmware, software, or a combination of two or more thereof.
For example, the address number determination method can be realized by a program that causes a computer to execute each process. For example, the program causes the computer to execute at least the following processes.

(1) A process of outputting the first address having the maximum number of bytes to the serial memory assuming the maximum number of bytes of the address of the serial memory.
(2) A data string from the first head data value acquired first as a first data string until a first tail data value different from the first head data value is detected according to the output of the first address Is read from the serial memory.
(3) A process of outputting the second address obtained by inverting the specific bit of the first address to the serial memory.
(4) According to the output of the second address, as the second data string, a data string from the first head data value acquired first until a second tail data value different from the second head data value is detected Processing to read from serial memory.
(5) Processing for comparing the first data string and the second data string.
(6) A process of determining the number of address bytes of the serial memory based on an address part including a specific bit when it is detected that the first data string and the second data string do not match.
These processes are the same as the operations described with reference to FIG. 3, and FIGS. 8A to 10B are examples of specific operations, and thus detailed description thereof is omitted.

Further, the program can be executed, for example, in the semiconductor device 801 shown in FIG. The configuration example of FIG. 21 is a configuration in which the general-purpose input / output port 107, the address byte count detection module 108, and the SPI signal switching module 110 are removed from the semiconductor device 102 shown in FIG. In addition, the clocked serial interface module 109 is configured to be directly connected to the serial memory 101.
In the semiconductor device 801, the program is stored in the ROM 105, and when the power is turned on, the program is read from the ROM 105. The program is executed under the control of the CPU 104. The program performs input / output with the serial memory 101 by the clocked serial interface module 109.
In the configuration example of FIG. 21, as shown in the semiconductor device 801, the address byte count determination method according to the embodiment is implemented by incorporating a program into the ROM 105 without adding a special circuit to the configuration of a general semiconductor device. It becomes possible to carry out.

  Further, in the above example, the program can be stored using various types of non-transitory computer readable media and supplied to the computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)) are included. The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

As described in the above embodiments, the apparatus and method for determining the number of address bytes according to an embodiment performs the following processing.
A method for determining the number of address bytes of a non-volatile serial memory compliant with SPI, assuming a maximum possible number of address bytes, starting a read cycle of the serial memory from the first address, and at least one data Obtaining a first data string (first byte string data) including a change. Assuming the maximum possible number of address bytes, the second data string including at least one data change is started by starting a read cycle of the serial memory from the second address obtained by inverting the specific bit of the first address. Obtain (second byte string data). Comparing the first data string and the second data string; When the comparison results match, it is determined that the address part including the specific bit is valid, and when the result does not match, it is determined that the address part including the specific bit is invalid.
By executing each of these processes, the number of address bytes in the serial memory is determined without writing determination data in the serial memory. This makes it possible to automatically determine the number of address bytes for a non-rewritable nonvolatile serial memory.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

101 Serial Memory 102, 401, 801 Semiconductor Device 103 Clock Generation Module 104 CPU
105 ROM
106 RAM
107 General-purpose I / O port 108 Address byte count detection module 109 Clocked serial interface module 110 SPI signal switching module 201 Serial transfer clock generation module 202 Sequence control module 203 Byte selection module 204 Bit inversion control module 205 Parallel / serial conversion module 206 AND gate 207 Serial / parallel conversion module 208, 209, 210, 211 1 byte register 212, 213 Counter 214, 215, 216, 217, 218 Comparator 219 AND gate 301, 302, 303 Selector 304, 305 Buffer 402 SPI Memory controller module 403 Inverter N101 Serial memory device selection signal N 02 Serial memory clock signal N103 Serial memory data input signal N104 Serial memory data output signal N105 Address byte count detection device selection signal N106 Address byte count detection clock signal N107 Address byte count detection data input signal N108 Address byte count Detection data output signal N109 SPI input / output device selection signal N110 SPI input / output clock signal N111 SPI input / output data input signal N112 SPI input / output data output signal N113 Address byte count detection completion signal N114 Address byte count detection result signal N115 System bus N116 Bus clock signal N117 Bus reset signal N201 Serial transfer clock signal N202 Address byte number detection address signal N203 Address byte count detection instruction code N204 Output byte data selection signal N205 Output byte data N206 Bit inversion control signal N207 Bit inversion controlled address N208 Data update control signal N209 Clock output enable signal N210 Reception data N211 Reception data capture control signal N212 Reception data Capture control signal N213 Received data capture control signal N214 Received data capture control signal N215 Captured received data N216 Captured received data N217 Captured received data N218 Captured received data N219 Counter initialization signal N220 Count clock N221 Counter initialization signal N222 Count Clock N223 Count result N224 Count result N225, N226, N227, N228, N229 Comparison result output signal N230 Comparison result output signal N401 SPI input / output device selection signal N402 SPI input / output clock signal N403 SPI input / output data input signal N404 SPI input / output data output signal N405 Hold request signal

Claims (16)

A memory input / output unit that outputs an address to a serial memory and receives a continuous data string from the serial memory according to the address;
Assuming the maximum number of bytes of the address of the serial memory, the first address having the maximum number of bytes is sent to the memory input / output unit, and then the second address obtained by inverting the specific bit of the first address is input to the memory. An address generation unit to be sent to the output unit;
In response to the output of the first address to the serial memory, a first tail data value different from the first head data value is detected from the first head data value first obtained through the memory input / output unit. A first data string acquisition unit for acquiring a first data string until
In response to the output of the second address to the serial memory, a second tail data value different from the second head data value is detected from the second head data value first obtained through the memory input / output unit. A second data string acquisition unit for acquiring a second data string until
A comparison unit that outputs a comparison result indicating whether the first data string and the second data string match or not; and
When detecting that the comparison result does not match, a control unit that outputs the number of address bytes of the serial memory based on an address portion including the specific bit;
A device for determining the number of address bytes. The control unit controls the address generation unit to send the second address in which the specific bit is changed to a different position to the memory input / output unit when the comparison result indicates a match;
The second data string acquisition unit acquires the second data string in response to a new output of the second address to the serial memory,
2. The address byte count determination according to claim 1, wherein the comparison unit is configured to update the comparison result when the second data string acquisition unit newly acquires the second data string. apparatus. If the first address consists of the first to the maximum number of bytes,
The address generation unit sets the first specific bit of the second address as the least significant bit of the address portion of the maximum number of bytes, and then generates the specific bit of the second address generated after that of the second address generated immediately before 3. The address byte number determination apparatus according to claim 2, wherein the least significant bit of the address part one higher than the address part including the specific bit is used.   3. The address byte number determination apparatus according to claim 2, wherein the address generation unit uses the least significant bit of any address part from the first to the maximum number of bytes of the first address as the specific bit.   4. The control unit according to claim 3, wherein when the comparison result does not match, the control unit determines that the number of address bytes is the number of bytes from the first to the address part including the specific bit. Address byte number determination device.   The control unit, when the comparison result is coincident and the specific bit is a second address part, determines that the number of address bytes is 1 byte. 3. The address byte count determination device according to 3.   The control unit controls the address generation unit to repeatedly send the second address in which the specific bit is changed to a different position to the memory input / output unit until the number of address bytes can be determined. The address byte number determination apparatus according to any one of claims 2 to 6, The first data string acquisition unit includes, as the first data string, a first data value indicating a length of the first data string, a first data value, and a first data value indicating a length of the first data string. Holds data column information,
The second data string acquisition unit includes, as the second data string, a second data length that includes the second head data value, the second tail data value, and a second data length indicating a length of the second data string. Holds data column information,
The comparison unit sets the comparison result to match when all the elements of the first data string information and the second data string information match, and when any element does not match, 2. The address byte number determination apparatus according to claim 1, wherein the comparison result is inconsistent. The first data string acquisition unit includes a first register that holds the first head data value, a second register that holds the first tail data value, a value held by the first register, and a second register A first comparator that compares a value to be measured, and a first counter that counts the first data length;
The second data string acquisition unit includes a third register that holds the second head data value, a fourth register that holds the second tail data value, a value held by the third register, and a fourth register A second comparator for comparing with a value to be performed, and a second counter for counting the second data length,
The control unit holds the first head data value in the first register, and sequentially outputs the first data value from the second value acquired in the first data string until the output of the first comparator indicates a mismatch. Until the second tail data value is held in the second register, the second head data value is held in the third register, and the output of the second comparator indicates a mismatch. 9. The control according to claim 8, wherein the second end data value is controlled to be held in the fourth register by taking the value into the fourth register in order from the second acquired value of the second data string. Address byte count determination device. Assuming the maximum number of bytes of the address of the serial memory, the first address having the maximum number of bytes is output to the serial memory,
According to the output of the first address, a data string from the first head data value acquired first to a first tail data value different from the first head data value is detected as the first data string. Read from serial memory,
A second address obtained by inverting a specific bit of the first address is output to the serial memory;
According to the output of the second address, a data string from the first leading data value acquired first to the second trailing data value different from the second leading data value is detected as the second data string. Read from serial memory,
Comparing the first data string and the second data string;
An address byte number determination method for determining the number of address bytes of the serial memory based on an address part including the specific bit when detecting that the first data string and the second data string do not match. When the first data string and the second data string match, the second address in which the specific bit is changed to a different position is output to the serial memory,
In response to the new output of the second address, the second data string is acquired,
Comparing the first data string and the newly acquired second data string;
11. The address byte number determination method according to claim 10, wherein output of the changed second address to the serial memory is repeated until the address byte number is determined. If the first address consists of the first to the maximum number of bytes,
The first specific bit of the second address is the least significant bit of the address part of the maximum number of bytes;
12. The specific bit of the second address generated thereafter is the least significant bit of the address portion one higher than the address portion including the specific bit of the second address generated immediately before. To determine the number of address bytes.   When it is detected that the first data string and the second data string do not match, the address byte number is the number of bytes from the first to the address part including the specific bit. 13. The method for determining the number of address bytes according to claim 12, wherein the number of address bytes is determined.   When the first data string and the second data string match and the specific bit is the second address part, the address byte number is 1 byte. 14. The method for determining the number of address bytes according to claim 12, wherein the determination is performed. On the computer,
Assuming the maximum number of bytes of the address of the serial memory, a process of outputting the first address having the maximum number of bytes to the serial memory;
According to the output of the first address, a data string from the first head data value acquired first to a first tail data value different from the first head data value is detected as the first data string. Reading from serial memory,
A process of outputting a second address obtained by inverting a specific bit of the first address to the serial memory;
According to the output of the second address, a data string from the first leading data value acquired first to the second trailing data value different from the second leading data value is detected as the second data string. Reading from serial memory,
A process of comparing the first data string and the second data string;
When detecting that the first data string and the second data string do not match, a process of determining the number of address bytes of the serial memory based on an address portion including the specific bit;
A program that executes A serial interface unit that controls input / output of data to / from the serial memory;
The address byte number determination device according to any one of claims 1 to 6, 8, and 9,
A semiconductor integrated device comprising: a switch unit that switches between the serial interface unit and the address byte number determination device and connects to a serial memory.

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