JP2013174942A - Cpu including multiple conditional flags - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CPU architecture and an instruction set that allow both program efficiency and memory space reduction to be achieved.SOLUTION: In a processor of the present invention, a single CPU comprises two conditional flags being a first flag whose flag value changes when the CPU executes an arithmetic operation, and a second flag whose flag value changes when data loading is performed. Accordingly, processing is branched on the flag change after the data loading by creating a machine language instruction which uses the second flag whose flag is updated at the loading time, and processing is performed with the flag value before the data loading after the loading by creating a machine language instruction which uses the first flag whose flag is not automatically updated at the loading time. Thus, zero determination and flag save become unnecessary, and a program can be developed which is simple in regard to both the case in which an update of the flag value at the loading time is unwanted and the case in which an automatic update is preferred.

Description

  The present invention relates to a CPU core used for a CPU, and relates to a technique related to a plurality of condition flags in a CPU utilized as an IP core.

  In general, the CPU register includes a flag register in addition to an accumulator, a general-purpose register, an index register, and the like. The accumulator is a register for storing the results of arithmetic operations and logical operations, whereas the flag register has a role of storing statuses representing various conditions generated as a result of the operations.

  Depending on the type of microprocessor, the relationship between the accumulator and the flag register is slightly different. That is, the value of a specific bit (zero flag) in the flag register changes as the Motorola 68 series CPU loads data into a register such as an accumulator, while the Intel 80 series CPU loads data into the register. At this time, the value of the zero flag or the like is not changed, the calculation is performed, and the value of the zero flag or the like is changed based on the calculation result.

  To create a program according to the application, it is necessary to branch the process using the value of the zero flag. However, 80 series CPU programmers load data once, and the data loaded by AND logic operation etc. We felt inconvenience because the zero flag would not change unless we added a step to determine if it was zero. On the other hand, as described above, when the data is loaded, the 68 system CPU does not hold the value of the zero flag. Therefore, when the branch processing is performed using the value of the zero flag, the zero flag value is stacked and stored in another register. Or, the data had to be loaded after being saved in the work area.

  The problem of such a zero flag change is not limited to the inconvenience of increasing the number of man-hours for programs created by 80-series and 68-series programmers. In other words, the increase in the number of program steps for flag change in the 80 system and the securing of a working area for saving the flag in the 68 system also lead to consumption of a large amount of memory space. Currently, the 80-series and 68-series CPUs are mainly used as embedded devices for various devices rather than general-purpose computer products. For example, for specific cores that control the probability of hitting in gaming machines such as pachinko machines. Often used for processors. In the case of gaming machines, the memory space is greatly limited due to the restrictions of the related game-related rules. Therefore, an increase in the memory space for coping with the change of the zero flag value is a problem that cannot be ignored.

  Therefore, the present invention has been made in view of the problems of the prior art, and an object thereof is to provide a CPU architecture and an instruction set that can achieve both program efficiency and memory space reduction.

  To achieve the above object, a CPU according to the present invention includes a CPU core that executes a given machine language instruction, and the CPU core is based on an instruction operation sequence determined according to the machine language instruction (i ) When an arithmetic logic operation is executed, the operation result is reflected in the bit (Z) corresponding to the first condition flag in the flag register, and (ii) when data is loaded into the register in the CPU core, The load result is reflected in the bit (TZ) corresponding to the second condition flag in the flag register.

More specifically, the CPU according to the present invention includes a CPU core that executes a given machine language instruction, and the CPU core manages state transitions in the CPU core and operates according to each state. A state control unit for generating a command, analyzing a machine language instruction input from the outside to generate an instruction decode, passing the instruction decode to the state control unit, and an internal state determined by the state control unit A central control unit that determines a sequence of instruction operations according to an operation instruction by transition, and an arithmetic logic unit (ALU) that executes arithmetic logic operations using a plurality of internal registers or external inputs as sources based on the instruction operation sequence from the central control unit ) And a plurality of flags that are set or reset by the state of the internal register or a predetermined instruction Anda more flags register,
The operation result of the arithmetic logic unit is reflected in the bit (Z) corresponding to the first condition flag in the flag register, and the result of the data load to the internal register is the second condition in the flag register. It is reflected in the bit (TZ) corresponding to the flag.

  In the CPU core according to the present invention, the calculation result of the arithmetic logic unit includes both a bit (Z) corresponding to the first condition flag and a bit (TZ) corresponding to the second condition flag. It is characterized by being reflected.

  The CPU according to the present invention includes two condition flags in one CPU core, such as a first condition flag whose flag value changes when an operation is executed and a second condition flag whose flag value changes when data is loaded. Thus, the first condition flag and the second condition flag can be used properly according to the situation. For example, if you want to branch processing by changing the flag after data loading, create a program with an instruction using the “second condition flag” that updates the flag at the time of loading, while changing the flag value before loading after data loading. If the process used is performed, a program is created with an instruction using a “first condition flag” whose flag is not automatically updated at the time of loading. Skillful use of the two flags eliminates the need for zero determination and flag saving program steps, and is concise for both cases where flag values need to be updated during data loading and when they can be automatically updated. You can assemble a program.

From the viewpoint of the space area to be used, the memory efficiency as a program area can be reduced, and the program step and work area for holding, saving, and restoring the flag state are not required, so the memory efficiency is greatly improved. Will be able to create a program.
Furthermore, the existing program can be expanded without modification by leaving the Z80 instruction that refers only to the first condition flag as it is, and the CPU core having an instruction configuration that adds an instruction that refers to the second condition flag. As a result, there is also an effect that compatibility between a plurality of programs is good.

It is a block diagram showing the structure of CPU and memory concerning one Embodiment of this invention. It is a block diagram inside a CPU according to an embodiment of the present invention. It is a figure which shows the breakdown of a flag register concerning one Embodiment of this invention. It is a figure explaining the flow of the data in CPU concerning one Embodiment of this invention in detail. FIG. 6 illustrates state transitions managed in a state control unit according to an embodiment of the present invention. FIG.

An embodiment of a CPU of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of the CPU 1 and the memory 4. The CPU 1 includes a CPU core unit 2 and a bus controller 3. The core unit 2 controls the bus controller 3 with a bus control signal, and exchanges read / write signals and input / output data with the memory unit 4. In addition, an interrupt signal (INT) / wait signal (WAIT) can be input to the CPU core unit 2, and a reset signal can be input to the CPU core unit 2 and the bus controller 3.

FIG. 2 is a block diagram showing an internal configuration of the CPU core unit 2 shown in FIG. The external input unit 10 in the CPU core unit 2 inputs an external signal (for example, reset, INT, WAIT, BUSREQ, etc.) and passes it to the state control unit 11. At this time, the reset signal is passed as an initialization signal for each unit including the central control unit 12 and the like.
The state control unit 11 manages the internal state transition shown in FIG. 5, determines the operation state of the CPU core 2, and issues an actual operation instruction to the central control unit 12. The internal state transition for each instruction starts from the instruction fetch state (1), and the next internal state transition is determined according to the result of instruction decoding performed by the central control unit 12 (for example, arithmetic processing, memory load, memory storage, etc.) Therefore, each instruction has a different internal state transition. Information on the state transition of each instruction is stored in the state control unit 11.

  The central control unit 12 reads the input data DI input from the memory unit 4 via the bus controller 3, passes it to the instruction decoder 13, and performs instruction analysis by the instruction decoder 13. When instruction analysis is completed in the instruction decoder 13 and the central control unit 12 passes the result of instruction decoding to the state control unit 11, the instruction operation is performed in accordance with the next operation instruction by the internal state transition determined in the state control unit 11. Are sequentially executed by the data path unit 14. Note that sequence information indicating what operation each instruction performs according to the instruction decoding result and the state instructed by the state control unit 11 is stored in the central control unit 12.

  The data path unit 14 includes a register bank 15. In this embodiment, the register bank 15 includes an accumulator register (A), a flag register (F), six registers (B, C, D, E, H, L), and an index register (IX, IY). , A stack pointer (SP) and a program counter (PC). It should be noted that the registers in the register bank 15 can be composed of a plurality of sets.

  FIG. 3 shows a breakdown example of the flag register (F). The F register 17 in the register bank 15 corresponds to the flag register (F) shown in FIG. The flag register (F) has a plurality of flags that are set / reset in the arithmetic result of the arithmetic unit ALU 16 or a specific instruction by the operation of the CPU.

In this embodiment, seven types of flags (7 bits) are shown. Bit D ₆ corresponds to the first condition flag flag value changes during execution. That is, the first condition flag is set when the result of the CPU core executing the arithmetic instruction becomes zero.
On the other hand, the bit D ₅ corresponds to the second condition flag flag value is changed during data loading. The operation of the second condition flag is set by determining the load data in the operation result by the addition instruction, the subtraction instruction, the logical operation instruction, the increment / decrement instruction and the load instruction.

In the present embodiment, the first condition flag is assigned to bit D ₆ and the second condition flag is assigned to bit D ₅ , but it goes without saying that it can be assigned to other bits. The other bits are, for example, D ₀ is a carry flag that is set when a carry or a carry occurs, and D ₇ is a sign flag that is set when the result of an operation is negative. Is not directly related to the above description, and the description thereof is omitted here.

The register bank 15 includes a destination selector (DSTsel) 17, an arithmetic logic unit (ALU) 16, and an address selector (ADDRESSsel) 18.
A destination selector (DSTsel) 17 outputs an input from the arithmetic logic unit (ALU) 16 to a register (B, C, D, E, H, L) or an external bus controller (not shown). The output signal DO to be passed to the memory unit 4 or the like is selected.

The source A selector (SRCAsel) 20 selects one register from a plurality of internal registers and determines it as an input A to the arithmetic logic unit (ALU) 16.
A source B selector (SRCBsel) 19 selects one of a plurality of internal registers and an external input DI input via an external bus controller (not shown) and inputs the selected input to the arithmetic logic unit (ALU) 16. B is determined.

  The arithmetic logic unit (ALU) 16 uses the source A (SRCA) selected by the source A selector (SRCAsel) 20 and the source B (SRCB) selected by the source B selector (SRCBsel) 19 to use the central control unit 12. Various operations of source A (SRCA) and source B (SRCB) are performed in accordance with the command operation from. The calculation result is output to the destination selector 17.

  An address selector (ADDRESSsel) 18 is a selector for selecting a memory address to be accessed. In the case of instruction fetch, a program counter (PC), in the case of an indirect address, BC, DE, HL (16 bits in pairs), IX, IY registers In the case of stack access, an SP is selected. In the case of directly specifying a memory address, an address register (not shown) for storing an operand read by a load / store instruction is selected.

Next, a specific example of instruction execution performed in the data path unit 14 described above will be shown.
For example, the machine language instruction of the “ADD A, B” instruction is composed of one instruction byte, and the instruction content is to add the contents of the A register and the B register and store them in the A register. When this instruction is executed, the CPU performs the following operations.
First, when the state of the CPU core 2 is instruction fetch, the state control unit 11 issues an instruction fetch instruction to the central control unit 12. In response to this instruction, the central control unit 12 operates the data path unit 14 to set the address indicated by the program counter (PC) in the address selector (ADDRESSsel) 18, thereby reading a 1-byte instruction from the memory 4, DI Enter via input. The input 1-byte instruction is passed to the decoder 13 for instruction analysis. At this time, in the program counter (PC), processing for instructing the next instruction fetch address is simultaneously performed.

  When the decoder 13 of the central control unit 12 passes the result analyzed as “ADD A, B” instruction to the state control unit 11, the state control unit 11 identifies that the operation state of the CPU core 2 is “calculation”. The central control unit 12 is instructed to add the contents of the B register to the A register. The central control unit 12 operates the data path unit 14 to add the contents of the B register to the A register.

  When the completion of a series of processing in the data path unit 14 and the central control unit 12 is notified to the state control unit 11, the state control unit 11 fetches the next instruction from “calculating” the state of the CPU core 2. And the cycle of instruction fetch and execution is sequentially repeated. During “execution”, the source A selector (SRCAsel) 20 selects the A register and the source B selector (SRCBsel) 19 selects the B register in the data path unit 14 that has received an instruction from the central control unit 12. The addition operation is executed by the arithmetic logic unit (ALU) 16 and the operation result is stored in the A register selected by the destination selector (DSTsel) 17.

FIG. 4 is a diagram for explaining the data flow in the data path unit 14 in detail.
The source A selector (SRCAsel) 20 is a selector circuit, and among the register contents stored in a plurality of registers in the register bank 15, data (SourceA) 41 set to the input A of the arithmetic / logic operation circuit 43 is It is selected by a source A selection signal from the central control unit 12.
A source B selector (SRCBsel) 19 is also a selector circuit, and among the register contents stored in a plurality of registers in the register bank 15 and the external input DI input from the memory unit 2 or the like via the external bus controller, Data (Source B) 42 set to the input B of the arithmetic / logic operation circuit 43 is selected by the source B selection signal from the central control unit 12. The source B selector (SRCBsel) 19 also selects data input to the operation result selector in parallel with the input B.

  The arithmetic / logical operation circuit 43 is in the arithmetic logic unit (ALU) 16 and performs various operations (addition, subtraction, logical sum, logical product, etc.). These operations are processed in parallel in the arithmetic / logic operation circuit 43, and the operation result is output to the register selected by the destination selector (DSTsel) 45 or the external output DO via the operation result selector 44.

  The operation result selector 44 has a circuit configuration in which an operation result can be selected from a plurality of operation results output from the arithmetic / logic operation circuit 43, or an external input DI from the source B selector 19 can be selected as an input. Yes. The selector output of the calculation result selector 44 is output in parallel to a Z determination circuit 46, a TZ determination circuit 47, and a destination selector (DSTsel) 45 as shown in the figure.

Here, the Z determination circuit 46 is a zero determination circuit for the above-described first condition flag, and determines whether all input data is zero or zero by a Z update signal. If zero determination reflects the Zflag flag register 17 (e.g., 1 is set to bit D _6).

The TZ determination circuit 47 is a zero determination circuit for a second condition flag provided separately from the Z determination circuit 46. Similar to the zero determination circuit, it is determined whether the input data is all zero or zero by the TZ update signal. For TZ determination circuit 47, not only at zero determination, (set for example, a 1 bit D ₅₎ is also reflected in TZflag flag register when data is loaded into a register in the register bank. As a result, Zflag and TZflag have the same flag value when there is an update at the time of calculation execution, and different values when there is an update at the time of load.

  The destination selector (DSTsel) 45 selects whether the output selected by the destination selection signal is stored in the register in the register bank 15 or the external output DO.

  In the case of the present embodiment, the first condition flag Zflag is updated at the time of calculation, and the second condition flag TZflag is updated at the time of calculation and when data is loaded into the register, using the following instruction: Further explanation will be given.

(Example 1: "ADD A, B" instruction)
The “ADD A, B” instruction is to execute an operation for storing the addition result of the A register and the B register in the register bank 15 in the A register. In the case of this instruction, the A register is selected as the source A41 and the B register is selected as the source B42 according to the instruction of the central control unit 12, and the operation is performed. Next, the result of addition is selected by the calculation result selector 44, and the Z determination result is set to Zflag by the Z determination circuit 46. The destination selector 45 selects the A register and stores the result in the A register. Therefore, the calculation result is reflected in the Z flag that is the first condition flag.

(Example 2: “LD A, (100h)” instruction)
The “LD A, (100h)” instruction is to execute an operation for loading the data at the address 100h into the A register. In this instruction, the source B selector 19 selects the external input DI, and the operation result selector 44 is the source. If B is selected, the destination selector 45 selects the A register, Z determination updates the previous Zflag, and TZ determination updates the result of the operation result selector 44, the data at address 100h is loaded into the A register. Although the Z flag does not change, the TZ determination circuit 47 determines whether the loaded data at the address 100h is zero or not, so that the result of loading the data is the TZ flag which is the second condition flag. It is reflected in.

  The processing configuration in which such Zflag is updated at the time of calculation and TZflag is updated at the time of calculation and when data is loaded into the register is consistent with the Intel 80 system operation and the Motorola 68 system operation, and reflects the compatibility of the operation of each CPU. doing. However, Zflag reflects the operation result of the arithmetic logic unit (Intel 80 system operation), and TZflag does not necessarily reflect the operation result of the arithmetic logic unit and the determination of the load data value to the register (Motorola 68 system operation). It is not limited. For example, TZflag may reflect only the determination of load data to the register.

  By the way, the source A selector 20, the source B selector 19, the operation result selector 44, the Z determination circuit 46, the TZ determination circuit 47, and the destination selector (DSTsel) 45 described above are respectively source A output from the central control unit 12. It operates upon receiving a selection signal, a source B selection signal, an operation result selection signal, a Z update signal, a TZ update signal, and a destination selection signal. These selection or update signals are output as a result of instruction decoding by the decoder 13 in the central control unit. Thereby, since the change of Zflag and TZflag can be defined for every instruction code, it becomes possible to create various combinations of instruction sets. As for the jump instruction, subroutine call, return instruction, and the like to be referred to, if an instruction for referring to Zflag and an instruction for referring to TZflag are prepared, program control under various conditions becomes possible.

  In this embodiment, the zero flag for determining whether the calculation result is zero or not has been described. However, the same circuit configuration is realized by configuring the other flags to have the same determination circuit and holding circuit. it can.

It has already been described that the state control unit 11 manages the internal state transition shown in FIG. 5 and that the next internal state transition is determined according to the result of instruction decoding by the decoder 13 in the central control unit 11. However, each internal state will be briefly described below.
The state of the CPU core 2 can be defined as shown below, and the state transitions to each execution cycle by a control signal or instruction of the CPU.
1. Reset state A state in which all internal states are cleared and the CPU core 2 is initialized.
2. Instruction fetch Reads an instruction from memory and analyzes the instruction.
3. Memory load Reads data from the memory at the specified address into the internal register.
4). Memory store Writes internal register data to the memory at the specified address.
5. Arithmetic operations are performed on internal registers.
6). HALT
CPU core 2 is stopped. It is released by an external control signal such as reset or interrupt.

The CPU core 2 that has started operating in response to the reset signal reads an instruction from the memory in an instruction fetch cycle and decodes (analyzes) the instruction. If the decoded instruction is a load instruction, the CPU core 2 loads the memory in accordance with a memory load cycle for loading data from the memory, and performs the next instruction fetch. Next, if the fetched instruction is an operation, the operation is performed, and if the instruction is to be stored in the memory after the operation, a cycle called memory store is executed. As described above, the CPU core 2 executes instructions as needed by combining the selector selection signals selected by the instruction decoder 13 in the central control unit 12 according to the state in the state transition unit.
In the present embodiment, the state of the CPU core 2 has been described as the above six states. However, it should be noted that this state division is not limited to this, and there may be various states depending on the design of the CPU. I want.

  According to the present embodiment, the CPU core 2 includes two flags, Zflag and TZflag, so that the flag value does not change even when the data is loaded, and the flag flag changes when the data is loaded. On the other hand, the value of the load data can be reflected by one instruction. Therefore, if the conditional branch instruction refers to Zflag and the one that refers to TZflag, prepare each and select which flag to refer to according to the ease of program creation and the ease of use of the programmer. good.

With respect to this point, it is possible to achieve the same processing result by setting Zflag to one without TZflag and preparing an instruction that changes Zflag and an instruction that does not change Zflag for the load instruction. However, since the number of load instructions such as load from memory and load between registers is several times larger than the number of conditional branch instructions such as jumps and subroutine calls, the load instruction can be obtained by using a method having only one Zflag. The number will increase dramatically. In the case of an 8-bit CPU, the machine language instruction configuration is basically 1 byte consisting of 8 bits, but if it cannot be implemented with 1 byte, it will be a configuration of 2 bytes or more. At present, only 256 instructions can be defined in one byte, so an instruction set is defined by a combination of two or more bytes. Even if the instruction is 1 byte, there are 2 byte instructions and 3 byte instructions because the address information to be specified requires 1 byte or 2 bytes.
In order to provide a CPU architecture and an instruction set that can achieve both the program efficiency and the reduction in memory space, which are the object of the present invention, it is desirable to reduce the number of programs by using instructions with a small instruction configuration. The key factor is whether or not it can be programmed. Considering this, it can be said that the condition flag configuration of the present invention can greatly reduce the number of machine language instructions.

  The present invention is particularly beneficial when applied to a CPU in a gaming machine such as a pachinko machine.

1 CPU
2 CPU core 3 Bus controller 4 Memory unit 11 State control unit 12 Central control unit 13 Decoder 14 Data path unit 15 Register bank 16 ALU
17 Flag register

Claims (3)

A CPU having a CPU core for executing a given machine language instruction,
The CPU core is based on an instruction operation sequence determined in accordance with the machine language instruction. (I) When an arithmetic logic operation is executed, a bit (Z) corresponding to the first condition flag in the flag register when an arithmetic logic operation is executed. (Ii) When data is loaded into a register in the CPU core, the load result is reflected in the bit (TZ) corresponding to the second condition flag in the flag register. CPU.   2. The CPU according to claim 1, wherein the calculation result is reflected in both a bit (Z) corresponding to the first condition flag and a bit (TZ) corresponding to the second condition flag. The CPU core is
A state control unit that manages state transitions in the CPU core and creates operation instructions according to each state;
Analyzing a machine language instruction input from the outside to create an instruction decode, passing the instruction decode to the state control unit, and performing an instruction operation according to an operation instruction by an internal state transition determined by the state control unit A central control unit for determining the sequence;
An arithmetic logic unit (ALU) that performs arithmetic logic operations using a plurality of internal registers or external inputs as sources based on a command operation sequence from the central control unit;
One or more flag registers having a plurality of flags that are set or reset by a state of the internal register or a predetermined instruction;
Including
The operation result of the operation logic unit is reflected in the bit (Z) corresponding to the first condition flag in the flag register,
The result of data loading to the internal register is reflected in the bit (TZ) corresponding to the second condition flag in the flag register.
The CPU according to claim 1, wherein the CPU is characterized.

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