KR100244210B1 - Method for design of microprocessor with multi-stage pipeline type - Google Patents

Abstract

The microprocessor design method with multi-stage pipelined phrases is divided into multiple instructions at the assembler / compiler level so that the execution of the special instructions is composed of instructions that use only the basic stage. To do it. In order to perform such an operation, a step of compiling a command corresponding to a special instruction into an OP-CODE consisting of only a basic stage is performed. The status bit is assigned to distinguish that the current instruction is part of a special instruction. step; On the hardware side, the operation is performed continuously for the step in which the status bit is given when an interrupt or exception occurs while the instruction is executed, and when the operation is completed, an interrupt or exception operation is performed. Therefore, by using only the basic stage, the control logic is simplified to significantly reduce the gate size, and the critical path is reduced, allowing the design of high speed processors.

Description

Method for design of microprocessor with multi-stage pipeline type}

The present invention relates to a method of designing a microprocessor having a multi-stage pipeline structure. In particular, the present invention relates to a basic progress rule for an instruction that deviates from the basic rule of a pipeline. The present invention relates to a microprocessor design method having a multi-stage pipeline structure that divides and processes an instruction so that the instruction can be executed by itself.

First, referring to the pipeline, a method of improving the processing speed of a microprocessor by performing an operation of another instruction before execution of one instruction in a microprocessor such as a general PC is completed.

In other words, the execution of the command is divided into several independent steps, and several commands are executed simultaneously in steps.

For example, it is a kind of pipeline to decode a command and execute the command while prefetching the next command to be executed.

The pipeline can be expected to improve speed by the number of stages, but there is a problem in that the pipeline cannot be increased much because there is a limit in subdividing the execution stage of the instruction.

In addition, the stage refers to a step of processing to allow parallel execution of instructions in the pipeline, and stages of the pipeline are divided into three stages, four stages, and five stages according to types of instructions. do.

Here, the special command is excluded.

The three-stage is divided into Instruction Fetch (IF), Instruction Decoder (ID), and Instruction Execution (EX), and the four-stage is divided into the IF, ID, EX, and Memory Access (MA).

The 5-stage can classify pipeline rules into the IF, ID, EX, MA, and WB (Write Back).

Here, the IF-stage is a stage where the CPU of the computer brings data into the CPU to execute an OP-CODE or data stored in a memory, that is, a memory, and the ID-stage is in the IF stage. It is a stage that decodes imported data according to predetermined rules.

The EX stage is a stage for calculating an address and performing a data operation operation according to a decoding rule of the ID stage, and the MA stage accesses data from a memory. A stage created by an instruction that includes memory access, and a WB-stage, is a stage for writing the result of the memory access data to a register.

In this case, the WB-stage is a stage produced by an instruction including a memory load.

Currently, even when the code of a part of an ordinary machine language indicating an operation, that is, an OP-CODE (Operation Code), the basic pipeline rule is broken, that is, a special command is input to the decoder of the microprocessor as it is. The complexity of control logic and the addition of registers to store temporary data increases the size of the gates in processor design.

In addition, as the complexity of the control logic increases, the critical path has been extended, which has been one of constraints in designing a high speed processor.

Here, looking at one example, the SH3 microprocessor from Hitachi is a processor having a five-stage (IF, ID, EX, MA, WB) as the basic pipeline, the basic structure is shown in FIG. .

1 is a view showing the basic structure of a pipeline having a typical five-stage.

Here, the instruction is composed of data transfer, arithmetic, logic, shift, and system control instructions.

Most of the instructions can be designed so as not to deviate from the basic pipeline rules, but the instructions in AND.B, OR.B ..., TRAPA, Multiply Instruction, RTE, INTERRUPT or exception are shown in FIG. Command violates the default Pibrain flow.

The progress of the pipeline for them will be described with reference to FIG. 2.

FIG. 2A is a diagram illustrating a pipeline performing method for an AND.B instruction in a pipeline having a five-stage according to the prior art, FIG. 2B is a TRAPA instruction, FIG. 2C is a multiply instruction, and FIG. 2D is an RTE instruction. A diagram illustrating a pipeline execution method for the present invention.

Referring to the method of performing the AND.B instruction illustrated in FIG. 2A, first, an OP-CODE for an AND.B stored in a memory is fetched from the IF stage to the processor.

After fetching the OP-CODE, the fetched OP-CODE is input to a decoder in the processor to decode in the ID-stage according to the decoding rule.

At this time, another decode is simultaneously fetched from the IF2-stage.

The address leaving the decoded AND.B instruction to the outside is calculated at the EX _1- stage, the data stored in the external memory is read at the MA-stage, and the AND operation is performed at the EX ₂ -stage.

The result is then stored back in external memory at the MA ₂ stage.

At this time, while the EX ₁ stage is performed, the OP-CODE of another instruction fetched from the IF2 stage is decoded, and during the MA ₁ stage operation and the EX ₂ stage operation, that is, during the two stage cycle, Stall the EX2-stage operation for the instruction and perform the EX2-stage operation simultaneously with the MA ₂ -stage operation.

And. Another way to perform the command is to repeat in the same way as above.

The AND.B instruction takes 3 AND.B execution cycles as shown in FIG. 2A. Here, the execution cycle means the number of stages between the EX-stage of the AND.B instruction and the EX-stage of the next instruction.

Instructions having such a pipeline execution process include OR.B, TST.B, XOR.B, and TAS.B as well as AND.B.

Next, a pipeline execution method for the TRAPA command of FIG. 2B will be described.

First, the TRAPA instruction fetches the OP-CODE for the TRAPA instruction stored in the memory from the IF1-stage to the processor.

After fetching the OP-CODE, the fetched OP-CODE is input to the decoder in the processor to decode in the ID1-stage according to the decoding rule.

The data of the program counter (PC) in the processor is temporarily stored in the SPC register, and the data stored in the status register of the processor is temporarily stored in the SSR register.

In addition, it is in the preserved mode to prevent the occurrence of the next exception and simultaneously starts the exception service routine by storing a start address of an exception service routine in the program counter.

Here, 6 TRAPA execution cycles are required to execute the TRAPA command. Here, the execution cycle means the number of stages between the EX-stage of the TRAPA instruction and the EX-stage of the next instruction.

Instructions having a pipeline execution process as described above include not only TRAPA but also INTERRUPT and EXEPTION.

Next, referring to the pipeline execution method for the multiply command of FIG. 2C, first, the OPp CODE for the multiply command stored in the memory is fetched from the IF1-stage.

After fetching the OP-CODE, the fetched OP-CODE is input to the decoder in the processor to decode in the ID1-stage according to the decoding rule.

At this time, the decoding is performed on the ID1-stage and an OP-CODE for another command is fetched.

Then, the address for reading the data to be performed is calculated in the EX1-stage, and the data stored in the memory is read in the MA _{1 and} MA ₂ -stages according to the calculated address value, and then three mm-stages ( Multiplying the data read in mm1, mm2, and mm3) and storing the result in a dedicated register of the multiplier in the processor.

Meanwhile, the address is calculated in the EX1-stage and the OP-CODE for another instruction fetched in the IF2-stage is decoded.

During the MA ₁ -stage operation, that is, during one stage cycle, the EX2-stage operation is stalled for another instruction and the EX2-stage operation is performed simultaneously with the execution of the MA ₂ -stage operation. .

At this time, it takes 2 multiply cycles to perform the multiply command as shown in Figure 2c.

Instructions having a pipeline execution process as described above include TRAPA, Interrupt, Exception, and the like.

In addition, referring to the pipeline execution method of the RTE instruction illustrated in FIG. 2D, first, an OP-CODE for the RTE instruction stored in the memory is fetched from the IF1-stage.

After fetching the OP-CODE, the fetched OP-CODE is input to the decoder in the processor to decode in the ID1-stage according to the decoding rule.

At this time, while decoding is performed on the ID1-stage, OP-CODE for another instruction is fetched from the IF2-stage.

Then, the data stored in the register is stored in the status register, the data value stored in the other register is promoted to the program counter, and the program is executed from the address by the program counter.

In this case, during the EX ₂ -stage operation, that is, during two stage cycles, the EX ₂ -stage operation for another instruction is stalled.

At this time, the RTE instruction takes 3 RTE execution cycles as shown in FIG. 2C. Here, the execution cycle means the number of stages between the EX ₁ stage of the RTE instruction and the EX ₂ stage of the next instruction.

In summary, the above-described methods have the following rules.

Execution for AND.B, OR.B, TST.B, XOR.B, and TAS.B Instructions The sequence is executed in the order of IF ID EX ₁ MA ₁ EX ₂ MA ₂ and in the case of TRAPA, INTERRUPT, EXCEPTION The stage sequence proceeds in the order of IF ID EX ₁ EX ₂ EX ₃ EX ₄ .

In addition, in the case of the MULTIPLY instruction, the execution stage sequence is performed in the order of IF ID EX MA ₁ MA ₂ mm mm, and in the case of the RTE instruction, the execution stage sequence is performed in the order of IF ID EX ₁ EX ₂ .

If we build the processor to meet the above instructions, AND.B will have to go through the basic pipeline flow to the MA and back to the previous stage, EX ₂ .

Therefore, the next command following the command is to proceed after stalling for two-stage as shown in FIG. 2A.

In addition, in the case of the TRAPA, INTERRUPT, and EXCEPTION commands, the pipeline proceeds as shown in FIG. 2B. Therefore, the information decoded in the ID-stage must be retained until the end of the last EX-stage. Similarly, the next command must be stalled. will be.

In addition, since there are two MA-stages in the case of multiply, as shown in FIG.

In addition, in the case of RTE, as shown in FIG. 2D, one cycle stall is inevitable.

Here, in the case of another processor, that is, an ARM processor, if the LOAD, STORE, and BRANCH instructions break the basic pipeline of the three-stage, they must be stalled for a certain cycle when performing the EX-stage for the next instruction. It is.

In addition, in a processor with a multi-stage as the primary pipeline, the configuration of the OP-CODE can always occur as long as it breaks the basic pipeline flow.

The pipeline design method in the processor according to the related art has a problem in that the control of each stage is complicated due to a problem in that the basic pipeline rule is broken when a special instruction is executed as described above.

In addition, as the control becomes more complex, a problem arises in that the number of gates in the processor is increased and the chip itself is increased, thereby increasing power consumption.

Accordingly, the present invention has been made to solve the above-described problems according to the prior art, the object of the present invention is to assembler / compiler so that the execution is composed of instructions that use only the basic stage for the pipeline for performing a special instruction The present invention provides a microprocessor design method having a multi-stage pipeline structure that divides and processes a plurality of instructions in a (assembler / compiler) dimension.

1 shows a structure of a pipeline having a typical five-stage.

2a to 2d is a view showing a pipeline performing method for each special command according to the prior art

3A to 3D are diagrams illustrating a pipeline performing method for each special instruction according to the present invention.

4 is an operational flowchart illustrating a microprocessor design method having a multi-stage pipeline structure according to the present invention.

A microprocessor design method having a multi-stage pipeline structure according to the present invention is characterized in that, in the microprocessor design method, a step of compiling an instruction corresponding to a special instruction into an OP code consisting of only basic stages of pipeline processing, Assigning a state bit to the instruction to distinguish that the instruction to be executed is part of a special instruction, and continuously performing the operation on the step where the status bit is given when an interrupt or exception occurs while the instruction is being executed And performing an interrupt or exception operation when the operation is completed.

Hereinafter, a method for designing a microprocessor having a multi-stage pipeline structure according to the present invention will be described.

3 is a diagram illustrating a pipeline execution method for each special instruction, in which FIG. 3A illustrates an AND.B instruction, FIG. 3B illustrates a TRAPA instruction, FIG. 3C illustrates a multiply instruction, and FIG. 3D illustrates a pipeline performing procedure. The figure shown.

First, a method of performing a pipeline in the AND.B instruction illustrated in FIG. 3A will be described.

First, each OP-CODE is compiled into the memory according to the steps so that the execution of the AND.B instruction can be divided and processed.

Here, the AND.B instruction may be divided into two instructions.

The AND.B instruction fetches the first OP-CODE for AND.B stored in memory to the processor at IF ₁ -stage.

After fetching the first OP-CODE, the fetched first OP-CODE is input to a decoder in the processor to decode in the ID ₁ -stage according to a decoding rule.

At this time, the second OP-CODE for the AND.B instruction is simultaneously fetched from the IF ₂ stage.

The memory address is calculated in the EX _1- stage to output the decoded first OP-CODE to the outside, that is, stored in one memory, and the data stored in the other external memory is read from the MA ₁ -stage. .

Here, the address of the memory is calculated at the EX ₁ stage, and the second OP-CODE closed at the IF ₂ stage is input to the decoder to decode at the ID ₂ stage and AND.B at the EX ₂ stage. After the AND calculation for the instruction, the calculated data is written to memory in the MA ₂ -stage.

At this time, a stall is generated for one cycle between the ID ₂ stage and the EX ₂ stage during the MA ₁ stage.

This stall is caused by a one-cycle stall by the data hazard caused by performing an AND operation on the data read from the memory due to the characteristic of the AND.B instruction.

When the AND.B instruction is executed, the execution step is divided into two steps as described above, in which the status bit " 1 " for executing the special instruction is given by the compiler.

That is, even when an interrupt or an exception occurs while the two steps are being performed, the instruction (AND.B) operation is performed for the step given the status bit without interrupting the execution operation, and the interrupt and exception are performed in subsequent operations. Can be done.

Here, the cycle of performing the AND.B instruction as shown in FIG. 3A takes 3 AND.B cycles as shown in FIG. 2A.

And even if this command uses only the existing OP-CODE of SH7708, 8 commands are needed and can be divided into 8 cycles.

For example, suppose that AND.B of SH7708 above has AND.B #imm, @ (R ₀ , GBR).

This operation is performed by reading the data of (R ₀ + GBR) address and ANDing with the #imm value as shown in FIG. 2A, and then writing the operation result back to (R ₀ + GBR) address.

Therefore, if the above command is divided using only the OP-CODE of SH3 7708, it is as follows.

1.STC GBR, R3

2.MOV.W @ (R0, R3), R2

3.MOV R0, R4

4.MOV R2, R0

5.AND # imm, R0

6.MOV R0, R2

7.MOV R0, R2

8. MOV.W can be divided into R2, @ (R0 + R3).

The above procedure seems very complicated, but the above is only when using the OP code of the SH3 7708.

However, using only the existing OP-CODE of SH7708 increases 5 performance cycles, but the hardware is properly configured to fit the basic pipeline structure, so that the OP-CODE is well constructed, and in fact, the basic operation of memory lead, AND operation, and memory write. Only configuration is possible.

In other words, by dividing the pipeline configuration as shown in FIG. 2A into two operations as shown in FIG. 3A, the same cycles may be used and the structure may be changed without violating the basic pipeline flow shown in FIG. 1.

3B is a diagram illustrating a pipeline execution method for a special command, that is, a TRAPA command.

First, each OP-CODE is divided and compiled into memory so that the execution of the TRAPA instruction can be divided and processed.

Here, the TRAPA command may be divided into four commands.

First, the first instruction for the TRAPA instruction stored in the memory, that is, the first OP-CODE, is fetched from the IF ₁ stage to the processor.

After fetching the first OP-CODE, the fetched first OP-CODE is input to a decoder in the processor to decode in the ID ₁ -stage according to a decoding rule.

At this time, the second OP-CODE for the TRAPA command is simultaneously fetched from the IF ₂ stage.

On the EX ₁ stage, the data of the program counter (PC) is temporarily stored in one register, and #imm (immediate) is written to the memory on the MA ₁ stage.

At this time, the second OP-CODE fetched at the same time as the operation of the EX ₁ stage is input to the decoder to perform decoding on the ID ₂ stage.

After decoding, the data stored in the status register at the EX ₂ stage is written to one register.

In addition, at the same time as the decoding operation in the ID ₂ stage, the IF ₃ stage fetches a third OP-CODE for executing a third instruction, that is, a TRAPA instruction, and simultaneously fetches the third OP-CODE for performing the EX ₂ stage. It is to decode the OP-CODE.

After decoding, the EX ₃ stage writes a specific value to the status register.

Meanwhile, at the same time as the decoding operation in the ID _3- stage, in the IF ₄ -stage, the fourth OP-CODE for the fourth instruction, that is, the TRAPA instruction, is fetched, and the fourth OP is fetched at the same time as the execution of the EX _3- stage. It decodes the code at the ID ₄ stage, and jumps to VBR + h'100 at the EX ₄ stage after decoding to complete the operation of the pipeline of the TRAPA instruction.

In this case, the execution of the pipeline for commands other than the TRAPA command is performed after the pipeline execution of the TRAPA command is completed.

In this case, when the pipeline is executed for the TRAPA instruction, the execution stage is divided into four stages as described above. Each of the four stages is provided with a status bit "1" for executing a special instruction.

That is, even when an interrupt or an exception occurs while step 4 is performed, the step (TRAPA) operation can be performed in the step where the status bit is given and the interrupt and exception can be performed in the subsequent operation. have.

Here, as shown in FIG. 3B, the cycle of executing the TRAPA instruction takes 6 TRAPA execution cycles as shown in FIG. 2B.

3C is a diagram illustrating a pipeline execution method for a special command, that is, a multiply command.

First, divide and compile each OP-CODE in memory according to the steps so that multiply instruction can be divided and processed.

Here, the multiply command may be divided into three commands.

First, the first instruction for the multiply instruction stored in the memory, that is, the first OP-CODE, is fetched from the IF ₁ stage to the processor.

After fetching the first OP-CODE, the fetched first OP-CODE is input to a decoder in the processor to decode in the ID ₁ -stage according to a decoding rule.

At this time, the second OP-CODE for the multiply command is simultaneously fetched from the IF ₂ stage.

EX ₁ Gives an operand to a multiplier configured outside the processor on the stage.

At this time, at the same time as the operation of the EX ₁ -stay, the ID ₂ -stage decodes the second OP-CODE fetched from the IF ₂ -stage.

After the execution of the EX ₁ stage, the MA ₁ stage is written to the memory.

At this time, the MA ₁ stage is performed at the same time, the EX ₂ stage gives another operand to the multiplier, and writes to the memory in the MA ₂ stage.

Meanwhile, the third OP-CODE for the multiply instruction is fetched at the same time as the ID ₂ -stage operation is performed, and the third OP-CODE fetched at the IF ₃ -stage is simultaneously decoded at the same time as the EX _-2 -stage operation.

After that, the multiplier operation is performed by an external multiplier.

At this time, the performance of the pipeline for the instruction other than the multiply instruction is to perform the pipeline operation by fetching the OP-CODE of another instruction at the same time as decoding is performed in the ID ₃ stage.

In this case, when the pipeline is executed for the multiply instruction, the execution step is divided into three steps as described above. Each of the three steps is provided with a status bit "1" for executing a special command.

That is, even when an interrupt or an exception occurs while the four steps are performed, the step of applying the status bit may perform a multiply operation and may perform an interrupt and exception in subsequent operations. have.

In this case, as shown in FIG. 3C, one cycle is used more than the execution cycle of the Multiply instruction shown in FIG. 2C, but the same cycle is used when the multiply operation is performed while giving an operand to the multiplier. will be.

3D illustrates a pipeline execution method for a special instruction, that is, an RTE instruction.

In this case, the RTE instruction is divided into two instructions and thus the status bit is also given to only two instructions.

In addition, the performance cycle also takes three cycles as shown in FIG.

In addition to the above-described command, the operation is performed in the same manner as described above.

Stalls due to data hazards and MA / IF stage collisions described above in the present invention are inevitable in any structure, and thus the same applies to the present invention.

And, when an interruption or exception occurs, it may be necessary to finish the current command or not. Therefore, when the interrupt or exception occurs in the special command, the current command is part of the special command. A status bit is given on the OP-CODE to indicate that.

In other words, in the instruction in which the status bit for the special instruction is set to '1' so that the operation can be performed in the same way as the existing program, the interrupt or exception is not executed during the instruction execution.

Using the above structure is a burden on the compiler / assembler, and when the program is compiled in machine language, the code length becomes longer.

This is because it divides the structure into the steps of executing basic instructions, and when the interrupt or exception occurs, a status bit is entered in the op-code to determine whether the instruction being executed is divided into one instruction or not. to be.

Briefly summarizing the present invention described above with reference to FIG. 4, first, an op-code for one command is divided into respective commands for each execution step (S101).

In order to distinguish that the instruction currently being executed is a part of a special instruction, a status bit is given to each stage to be divided for the one instruction (S102), and when the interrupt or exception occurs while the instruction is executed, the status bit is added. For the given step, the operation is continuously performed, and when the operation is completed, an interrupt or exception operation is performed (S103).

In the design of the processor, there is no need to create the temporary storage registers needed for special instructions, and there is no need for control logic.

Therefore, the method for designing a microprocessor having a multi-stage pipeline structure according to the present invention can significantly reduce the gate size and reduce the critical path due to the simplified control logic, thereby enabling the design of a high speed processor. There is an advantage.

Claims (1)

In the microprocessor design method, Compile the instructions corresponding to the special instructions into OP codes consisting only of the basic stage of the pipeline processing, Giving a status bit to the instruction to distinguish that the instruction to be executed is part of a special instruction, Multi-stage pipe comprising the step of continuously performing the operation for the step given the status bit when the interrupt or exception occurs while the instruction is executed, and performing the interrupt or exception operation when the operation is completed. Microprocessor design method with line structure.

Images