JP2013172431A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LC oscillator that is precisely temperature-compensated at a reduced chip cost and with a reduced power consumption.SOLUTION: A capacitor connected in parallel with an inductor (L) of the LC oscillator includes: a first variable capacitance element pair (C10, C11) having their respective first terminals connected in common and their respective second terminals connected to opposite ends of the inductor; and a second variable capacitance element pair (C20, C21) having their respective first terminals connected to the opposite ends of the inductor and their respective second terminals connected in common. A first voltage source (30) applies a voltage to the common junction of the first terminals of the first variable capacitance element pair (C10, C11), and a second voltage source (40) applies a temperature-dependent voltage (PTAT voltage) to the common junction of the second terminals of the second variable capacitance element pair (C20, C21).

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with an oscillation circuit.

  In a clock generator having an LC oscillator (for example, an LC parallel resonant circuit of an inductor L and a capacitor C, also referred to as a “tank circuit”) mounted in a semiconductor chip, variations in manufacturing process, power supply voltage, temperature The error of the resonance frequency (oscillation frequency) is corrected mainly by adjusting the capacitance value (capacitance) of the capacitor C of the LC resonator with respect to the fluctuation. The resonance frequency f of an ideal LC oscillator is given by the following equation (1).

・・・（１）

... (1)

  Compensation for semiconductor manufacturing process variations is achieved by measuring the oscillation frequency of the LC oscillator and selecting an appropriate C value in the semiconductor manufacturing process selection process (wafer test, etc.). To do.

  As is well known, for example, a constant voltage source (reference voltage) such as a band gap reference circuit is used for the compensation for the power supply voltage fluctuation.

  A variable capacitance element (varactor) whose capacitance value is variable with a control voltage is used as the capacitance of the LC oscillator, and is proportional to the PTAT current source (Proportional To Absolute Temperature) proportional to the temperature (absolute temperature) or to the temperature (absolute temperature). A technique is generally used in which the control voltage is varied using a PTAT voltage source to compensate the oscillation frequency of the LC oscillator.

  For example, Patent Document 1 (Japanese Patent Publication No. 2007-53471) discloses a capacitor (capacitor module: part of a VCO (Voltage Controlled Oscillator)) having an LC parallel resonant circuit (tank circuit). 2 (Cap_tune in FIG. 2 of Patent Document 1) discloses a configuration in which a voltage Vcm from a PTAT voltage source (PTAT voltage source) is applied to a connection point of a varactor (In FIG. 3 of Patent Document 1, the output of the PTAT voltage source) The voltage Vcm is applied to the common anode of the varactor via a low-pass filter and a buffer). That is, the temperature compensation of the capacitance is performed by giving the output voltage Vcm of the PTAT voltage source (Vcm has a temperature dependence that substantially compensates the varactor temperature dependence). However, in practice, Vcm includes an error factor, and as a result, an error occurs in the oscillation frequency of the VCO. In Patent Document 1, this Vcm error factor is not considered.

Special table 2007-531471 gazette

  The analysis of related technology is given below.

  In the PTAT voltage source disclosed in Patent Document 1 (FIG. 4 of Patent Document 1), Nch or PchMOS transistors are generally used for the switches TC1 to TCn. As is well known, a MOS transistor has a leakage current, and the current value of the leakage current varies depending on, for example, the power supply voltage and the ambient temperature (normally, the variation is not primary dependent). Recently, a MOS transistor with a short gate length is used in order to cope with the progress of miniaturization of a semiconductor process, a reduction in area, and a reduction in power consumption, and a leakage current at the time of off (for example, a current flows from the gate to the source of the MOS transistor). Gate / tunnel current and channel leak current (subthreshold current) flowing from drain to source increase. The semiconductor device is set to a standby state except during operation to reduce power consumption, but leakage current in the standby state increases. Further, the influence of the leakage current of the semiconductor device during the operation of the low power supply voltage is increased.

  In Patent Document 1, even if a constant voltage source such as a band gap reference circuit is used, constant temperature dependence and power supply voltage dependence cannot be avoided, and the output voltage Vcm of the PTAT voltage source due to changes in ambient temperature and power supply voltage. Is affected, leading to an error in the oscillation frequency of the VCO.

  On the other hand, in order to reduce errors due to temperature dependence, power supply voltage dependence, etc., it is generally disadvantageous in terms of area and power consumption to use a highly accurate constant voltage source.

  Further, on the oscillation operating point side of the LC resonator, the operating point potential (midpoint potential of the complementary oscillation output) fluctuates depending on the temperature, which causes an oscillation frequency error. The fluctuation of the operating point potential of the LC oscillator is caused by the temperature-dependent characteristics of the PchMOS transistor and the NchMOS transistor used in the amplifier circuit in the LC resonator being different from each other or the current value of the leakage current being different depending on the temperature. .

  According to one aspect, an oscillator including a resonant circuit of an inductor and a capacitor is provided, and the capacitor is connected with the first terminals facing each other, and the second terminal opposite to the first terminal is connected to the second terminal. A first variable capacitive element pair composed of first and second variable capacitive elements connected to nodes at both ends of the inductor is connected to each other with the second terminals facing each other, and the first variable capacitive element on the opposite side of the second terminal. A second variable capacitive element pair comprising third and fourth variable capacitive elements each having one terminal connected to a node at both ends of the inductor, and further, the first terminal of the first variable capacitive element pair A first voltage source that applies a first voltage to a connection node between them, a second voltage source that applies a second voltage to a connection node between the second terminals of the second variable capacitance element pair, and Provided by semiconductor devices with It is.

  According to the embodiment, for example, it is possible to provide a semiconductor device with reduced power consumption, improved accuracy, and reduced cost. Note that the effects and the like of the embodiments other than those described above will be apparent to those skilled in the art from the embodiments and drawings disclosed below.

It is a figure explaining one Embodiment. It is a figure explaining a comparative example. 1 is a diagram illustrating a configuration of Example 1. FIG. FIG. 3 is a diagram illustrating an example of a layout of Example 1. It is a figure which shows the varactor part of the layout of Example 1. FIG. It is a figure explaining the Example 1 (varactor capacity | capacitance at the time of an operating point fluctuation | variation). It is a figure (varactor capacity at the time of temperature fluctuation) explaining Example 1. FIG. 6 is a diagram illustrating a configuration of Example 2. FIG. It is a figure explaining the Example 2 (varactor capacity at the time of temperature rise). 6 is a diagram illustrating a configuration of Example 3. FIG. It is a figure which shows the example of the characteristic of a varactor. It is a figure which shows the example of the characteristic of an on-chip oscillator (no compensation). FIG. 10 is a diagram for explaining Example 3 (example of characteristics after primary compensation); FIG. 10 is a diagram for explaining Example 3 (example of characteristics after fine adjustment); FIG. 10 is a diagram showing a configuration of Example 4. It is a figure which shows the capacity | capacitance change of the varactor at the time of the operating point change in LC oscillator.

  Hereinafter, embodiments will be described. Referring to FIG. 1, an LC oscillator mounted on a semiconductor device (chip) 1 includes a capacitor connected in parallel with an inductor (L), and a first variable capacitance element pair (first and second variable capacitance elements). (Varactor elements) C10, C11) and a second variable capacitor element pair (third and fourth variable capacitor elements (varactor elements) C20, C21). The first terminals of the first and second varactor elements (C10, C11) are connected to face each other, and the second terminal opposite to the first terminal is connected to both end nodes (N1, N2) of the inductor (L). Connect the second terminals of the third and fourth varactor elements (C20, C21) facing each other, and connect the first terminal opposite to the second terminal to both ends of the inductor (L). Yes.

  The output voltage of the first voltage source VCNT1 (T) is applied to the connection node (N0) of the first terminal of the first and second varactor elements (C10, C11) as a control voltage for changing the capacitance value of the varactor. Applied.

  The output voltage of the second voltage source VCNT2 (T) is applied to the connection node (N3) of the second terminal of the third and fourth varactor elements (C20, C21) as a control voltage for changing the capacitance value of the varactor. Applied.

  The output voltages of the first and second voltage sources VCNT1 (T) and VCNT2 (T) vary depending on, for example, the power supply voltage and temperature. The operating point of the oscillation waveform of the LC oscillator also varies depending on the power supply voltage and temperature. Note that the output voltage of the second voltage source VCNT2 (T) may be, for example, a voltage (PTAT voltage) proportional to the absolute temperature, as described in an embodiment described later. Further, the output voltage of the first voltage source VCNT1 (T) may be, for example, a voltage (CTAT voltage) dependent on the absolute temperature in a complementary manner, as will be described later in an embodiment.

  Constant voltages from a low drop out regulator (LDO) are supplied to the first and second voltage sources VCNT1 (T) and VCNT2 (T).

  A reference voltage used in the LDO (this reference voltage is compared with a voltage obtained by dividing the output voltage output from the LDO to its output terminal by a voltage dividing resistor, and the dropper FET inserted between the input and output is used. For example, in the case of a bipolar process, the on-resistance is generated by a band gap reference circuit (for example, a silicon band gap voltage: 1.205 V is output) or the like. In the case of an LDO with a CMOS (complementary MOS (Metal Oxide Semiconductor)) structure, a CMOS bandgap reference circuit using a CMOS process (for example, a p-type substrate, an n-well process, etc.) (using a pnp transistor with a collector connected to GND) It is good also as a structure provided with.

  In FIG. 1, when the potential at the oscillation operating point of the LC oscillator (for example, the midpoint potential (DC potential) of the complementary output of the LC oscillator in FIG. 1) drops due to fluctuations in the power supply voltage, ambient temperature, etc., the first varactor The difference voltage between the voltage at the second terminal (node N1) of the element C10 and the voltage at the first terminal (node N0) decreases. Although not particularly limited, for example, when the second terminal of the varactor element C10 is G (gate) and the first terminal is B (bulk terminal: well contact), the voltage VG of the second terminal G and the first terminal (B) The difference voltage Vgb (= VG−VB) of the voltage VB decreases. Similarly, the difference voltage Vgb (= VG−VB) between the voltage of the second terminal G (node N2) of the second varactor element C11 and the voltage of the first terminal B (node N0) decreases. As a result, as shown in FIG. 16, for example, the capacitance values of the first and second varactor elements C10 and C11 are reduced to C−ΔC (where ΔC> 0).

FIG. 16 shows the characteristics of the capacitance value C and the inter-terminal voltage Vgb of the first and second varactor elements C10 and C11. Although not particularly limited, the first to fourth varactor elements C10, C11, C20, and C21 may be constituted by, for example, accumulation mode MOS varactors formed in an N well of a P-type semiconductor substrate. In this case, the well contact (N ⁺ ) of the N well of the P-type semiconductor substrate is a B terminal (bulk terminal), and a gate electrode provided on the substrate surface between the well contacts (N ⁺ ) via a gate insulating film is G When the gate terminal G is higher than the potential of the bulk terminal B (Vgb> 0), it is in an accumulation state (no depletion layer), and the capacitance value is Cox × L × W (Cox is The capacitance per unit area of the gate insulating film, W is the gate width, and L is the gate length). When Vgb <0, a depletion layer is formed, and when the capacitance of the depletion layer is Cd, the capacitance value C is 1 / C = 1 / Cox + 1 / Cd (hence C <Cox).

  Contrary to the first varactor element C10, when the potential at the oscillation operating point decreases, the difference voltage Vgb between the voltage VG at the G terminal (node N3) and the voltage VB at the B terminal (node N1) of the third varactor element C20. (= VG−VB) increases, and the capacitance value increases to C + ΔC. The same can be said for the fourth varactor element C21.

  Since the first varactor element pair (C10, C11) and the second varactor element pair (C20, C21) are connected in parallel, fluctuations in the total capacitance value are suppressed. In FIG. 1, the total capacitance value of the capacitors connected in parallel to the inductor L is given by Equation (2).

・・・（２）

... (2)

・・・（３）
となる。 In FIG. 1, when C10 = C11 = C20 = C21 = C, the total capacitance value of the capacitors connected in parallel to the inductor L from the equation (2) is

... (3)
It becomes.

・・・（４）
となり、式（３）と同一であることが分かる。すなわち、図１の構成により、総容量値Ｃの変動は抑制され、ＬＣ共振器の共振周波数の変動は抑制される。 In FIG. 1, when C10 and C11 both decrease by ΔC and both C20 and C21 increase by ΔC due to the decrease of the oscillation operating point potential, the total capacitance value connected in parallel to the inductor L from Equation (2) is

... (4)
Thus, it can be seen that this is the same as equation (3). That is, with the configuration of FIG. 1, fluctuations in the total capacitance value C are suppressed, and fluctuations in the resonance frequency of the LC resonator are suppressed.

  On the other hand, as a comparative example, in the case of the configuration shown in FIG. 2 (in FIG. 2, C20 and C21 in FIG. 1 are not provided), the constant voltage source VCNT is also dependent on the power supply voltage and temperature. As the operating voltage (the oscillation waveform of the LC oscillator) changes, Vgb of the varactor element changes and the capacitance value fluctuates, causing an error. Further, the constant voltage source VCNT increases the leakage current at a high temperature and becomes an error factor. For example, when there is a voltage drop on the operating point (node N1) side, as shown in FIG. 16, the capacitance value C of the varactor decreases to C−ΔC (where ΔC> 0), and the oscillation frequency changes.

・・・（５）
となり、図２のＬＣ並列共振器の共振周波数ｆは、

・・・（６）
で与えられる。 In FIG. 2, when C10 ′ = C11 ′ = C ′, the total capacitance value connected in parallel to the inductor L is

... (5)
The resonance frequency f of the LC parallel resonator shown in FIG.

... (6)
Given in.

In FIG. 1, when C10 = C11 = C20 = C21 = C, the total capacitance value is C from Equation (3), but the resonance frequency of the LC oscillator of FIG. 1 is set to the resonance frequency f of the LC oscillator of FIG. Is equal to
C = C ′ / 2 (7)
It becomes.

  That is, in FIG. 1, the capacitance value C of the first to fourth varactor elements C10, C11, C20, C21 is half the capacitance value C ′ of the varactor elements C10 ′, C11 ′ of FIG. The gate size (gate width W) is half.

  In equation (5), when the capacitance values of C10 ′ and C11 ′ decrease by ΔC ′ due to the decrease in the oscillation operating point potential, the total capacitance value connected in parallel to the inductor L is given by equation (8). .

・・・（８）

... (8)

  That is, in FIG. 2, the capacitance value of C10 ′ and C11 ′ decreases by ΔC ′ due to the decrease of the oscillation operating point potential, so that the total capacitance value connected in parallel to the inductor L decreases by ΔC ′ / 2. The resonance frequency of the LC resonator changes.

  1 and 2, the inverters INV1 and INV2 are connected in series between the power supply VDD and VSS, the gate terminals are connected to form an input node, and the drain terminals are connected to form an output node. It consists of a CMOS transistor consisting of a transistor and an NMOS transistor (NMOS transistors form a cross-coupled pair in which the sources are connected in common and connected to VSS and the gate is cross-connected to the other drain, and the PMOS transistors are connected to the source. Are connected in common and connected to the power supply VDD, forming a cross-coupled pair in which the gate is cross-connected to the other drain).

  As shown in FIG. 1, according to the present embodiment, the first and second varactors connected in parallel to both ends of L of the temperature compensated LC-VCO corresponding to a small area, low power consumption, and high accuracy. Primary temperature compensation by PTAT, etc. (capacitance is compensated by a voltage linear with temperature, and oscillation frequency is compensated by reversing the connection direction of the elements C10, C11 and the third and fourth varactor elements C20, C21. Oscillation frequency error that cannot be compensated for with () can be suppressed. In the following, description will be made in accordance with examples.

<Example 1>
FIG. 3 is a diagram illustrating the configuration of the first embodiment. Referring to FIG. 3, an inductor L and first and second varactor elements C <b> 10 and C <b> 11 (first varactor element pair) in which terminals are connected to face each other and a G terminal is connected to both ends of the inductor L, The third and fourth varactor elements C20 and C21 (second varactor element pair) in which the G terminals are connected to face each other and the B terminal is connected to both ends of the inductor L, the constant voltage source 20, and variable A voltage source (first voltage source) 30 and a PTAT variable voltage source (second voltage source) 40 are provided. The constant voltage source 20, the variable voltage source (first voltage source) 30, and the PTAT variable voltage source (second voltage source) 40 correspond to the LDO, VCNT1 (T), and VCNT2 (T) in FIG. 1, respectively. To do. Although not particularly limited, each varactor element has, for example, two well contacts of an n well provided in a p-type semiconductor substrate connected in common to form a B terminal via a gate insulating film on the substrate surface between the two well contacts. When the voltage Vbg between the B terminal and the G terminal is negative (therefore, when the voltage Vgb is positive), the storage state is set (capacitance value = Capacitance of gate insulating film (Cox) × gate area (L × W)).

  C10 and C11 are a varactor element pair for adjusting the oscillation frequency of the LC oscillator. The first control voltage Vcnt1 is applied to the connection point N0 of the B terminals (second terminals) of the varactor elements C10 and C11. The first control voltage Vcnt1 is supplied from the variable voltage source 30.

  C20 and C21 are a varactor element pair for performing temperature compensation. A second control voltage Vcnt2 having temperature dependence is applied to the connection point N3 of the B terminals of C20 and C21. The second control voltage Vcnt2 is supplied from a PTAT variable voltage source 40 that outputs a voltage (PTAT (Proportional to Absolute Temperature) voltage: Vptat (T)) that is directly proportional to the absolute temperature. The first to fourth varactor elements C10, C11, C20, and C21 use MOS varactors, have the same size (gate size), and have the same terminal voltage (for example, Vgb), temperature, and the like. The same capacity value is set.

  The variable voltage source 30 receives the oscillation frequency adjustment signal and the temperature compensation intensity adjustment signal, receives the constant voltage VDDA from the constant voltage source 20 as the operation power supply voltage, and outputs the voltage Vcont1.

  A second control voltage Vcnt2 supplied from the PTAT variable voltage source 40 that outputs a voltage that is directly proportional to the absolute temperature is supplied to the connection node N3 of C20 and C21.

  The PTAT variable voltage source 40 receives an oscillation frequency adjustment signal and a temperature compensation intensity adjustment signal, further receives a constant voltage VDDA from the constant voltage source 20 as an operation power supply voltage, and outputs a voltage Vcont2.

  The oscillation frequency adjustment signal and the temperature compensation intensity adjustment signal are supplied from the adjustment signal output circuit 111 on the same chip, for example. Although not particularly limited, the oscillation frequency adjustment signal and the temperature compensation intensity adjustment signal are determined by, for example, a trimming stage of the semiconductor device (chip), for example, a fuse program (blown) (not shown) in the adjustment signal output circuit 111. It is a fixed value. The trimming function may be provided outside the chip (for example, a tester or another semiconductor chip for trimming) in addition to the configuration mounted in the semiconductor device (chip).

  The constant voltage source 20 (consisting of a band gap reference circuit BGR and a voltage amplifier VAMP, etc.) is supplied with a voltage (VDD) such as 2.5V and supplies a constant voltage (VDDA) such as 1.0V lower than 2.5V. The voltage is output and supplied to the variable voltage source 30 and the PTAT variable voltage source 40.

  By controlling the oscillation frequency adjustment signal, the output voltage Vcnt1 of the variable voltage source 30 is varied, the capacitance values of C10 and C11 are varied by the output voltage Vcnt1 of the variable voltage source 30, and the LC oscillator (LC parallel resonant circuit L + ( The oscillation frequency of C10, C11, C20, C21)) changes.

  By selecting the optimum oscillation frequency adjustment signal, the desired oscillation frequency (resonance frequency of the LC resonator) can be obtained when there is no change in temperature and power supply voltage.

  The PTAT variable voltage source 40 outputs a voltage Vptat (T) proportional to the temperature. The error of the oscillation frequency can be first corrected. The degree of correction of the oscillation frequency error is controlled by a temperature compensation intensity adjustment signal.

  Due to the change in the power supply voltage VDD and the ambient temperature, an error that cannot be controlled by the oscillation frequency adjustment signal or the temperature compensation intensity adjustment signal occurs in Vcnt1 and Vcnt2 for the following reason.

A change in the constant voltage VDDA from the constant voltage source 20 due to a change in the power supply voltage VDD or temperature.

Generation of leakage current in the variable voltage source 20 and the PTAT variable voltage source 40.

  Therefore, Vcnt1 and Vcnt2 can be expressed as in equations (9) and (10), respectively.

Vcnt1 = Vcnst + Verr1 (V, T) (9)
Vcnt2 = Vptat (T) + Verr2 (V, T) (10)

  Here, Vcnst is a variable voltage controlled by the oscillation frequency adjustment signal (independent of temperature and VDD voltage).

  Vptat (T) is a variable voltage proportional to the absolute temperature T controlled by the oscillation frequency adjustment signal and the temperature compensation intensity adjustment signal (it depends on the temperature but does not depend on the power supply voltage VDD).

  Verr1 (V, T) is an error voltage generated in Vcnt1 due to variations in the ambient temperature T and the power supply voltage VDD.

  Verr2 (V, T) is an error voltage generated in Vcnt2 due to ambient temperature T and power supply voltage VDD fluctuation.

  When the variable voltage source 30 and the PTAT variable voltage source 40 are configured similarly, for example, when the variable voltage source 30 is configured with a PTAT voltage source whose temperature dependence is the weakest (= 0), Verr1 (V, T) And Verr2 (V, T) show similar power supply voltage dependency characteristics and temperature dependency characteristics.

  According to the present embodiment, the connection direction of the varactor element pair is reversed between the first varactor element pair (C10, C11) and the second varactor element pair (C20, C21), whereby C10 by the error voltage Verr1. , C11 capacitance change ΔC can be canceled by C20 and C21 capacitance change ΔC due to error voltage Verr2. As a result, an error in the oscillation frequency can be suppressed.

  4 and 5 are diagrams showing an example of the layout of the inductor L, the capacitors C10, C11, C20, and C21 and the driver (Driver) 10 shown in FIG. In FIG. 4, a driver corresponds to the driver 10 of FIG. FIG. 5 shows an enlarged view of the varactor part. VCNT1 is commonly connected to B terminals (bulk terminals) of C10 and C11, and Vcnt2 is commonly connected to G terminals (gate terminals) of C20 and C21.

  FIG. 6 is a diagram for explaining the first embodiment. The vertical axis represents one capacitance value of the varactor elements C10 and C11 and C20 and C21. Since the connection direction of C10 and C11 and the connection direction of C20 and C21 are opposite, VCNT1 [V] on the horizontal axis corresponds to the voltage (Vbg) between C10 and C11, and VCNT2 [V] Is proportional to the voltage between the G-B terminals (Vgb) of C20 and C21. The capacitance values of C10 and C11, C20 and C21, and the characteristics of VCNT1 and VCNT2 are symmetrical with respect to the intersection. When the operating point is lowered, the capacitance values of C10 and C11 decrease, the capacitance values of C20 and C21 increase, and the fluctuation of the total capacitance value is alleviated.

  FIG. 6 shows an example when the potential at the oscillation operating point is lowered. However, when the potential at the oscillation operating point is increased or when the potential changes on the VCNT side, the capacitance values of C10 and C11 increase and decrease, and C20 and C21. The direction of increase / decrease in the capacitance value is opposite to each other (that is, when one increases, the other decreases), and the variation in the total capacitance value is reduced as described above.

  When the oscillation operating point potential of the LC oscillator drops when the temperature rises, the capacitance-temperature characteristics of C10 and C11 and the capacitance-temperature characteristics of C20 and C21 are as shown in FIG. In FIG. 7, the vertical axis represents capacitance values of C10, C11 and C20, C21, and the horizontal axis represents temperature Tj. The capacitance values of C20 and C21 change depending on the temperature T by the voltage Vcnt2 (Vptat (T) + Verr2 (T, VDD)) that changes depending on the temperature (absolute temperature) from the PTAT variable voltage source 40. . For example, when the temperature Tj rises and the potential at the operating point falls, the capacitance values of C10 and C11 decrease. On the other hand, the capacitance values of C20 and C21 increase by applying a voltage Vptat (T) proportional to the absolute temperature when the temperature Tj rises. Also, the capacitance values of C10 and C11 vary depending on the temperature T according to Vcnt1 (Vconst (T) + Verr1 (T, VDD)) from the variable voltage source 30. When the potential at the operating point decreases when the temperature rises, the capacitance values of C10 and C11 decrease, but the capacitance values of C20 and C21 increase.

  The change in the characteristics of the capacitance values of the varactor elements C10 and C20 with respect to the temperature Tj is symmetrical with respect to the vertical axis passing through the intersection. Therefore, the temperature fluctuations in the capacitance values of the parallel capacitors C10 + C20 and C11 + C21 are canceled out, and the capacitance of C10 + C20 It can be seen that the fluctuation can be kept small, as shown in the temperature-to-temperature characteristic and the capacity-to-temperature characteristic of C11 + C21.

<Example 2>
FIG. 8 is a diagram illustrating the configuration of the second embodiment. If even greater temperature dependency adjustment is required than in the disclosed first embodiment, the Vcnt1 side can also have temperature dependency. In this case, a CTAT (Complementary To Absolute Temperature) variable voltage source 50 that outputs a voltage that is complementary and proportional to the absolute temperature (the voltage decreases as the absolute temperature increases) is used as Vcnt1. By generating Vcnt1 with the CTAT variable voltage source 50, C10 and C11 are also made temperature dependent.

  Vcnt1 and Vcnt2 can be expressed as equations (11) and (12), respectively.

Vcnt1 = Vctat (−T) + Verr1 (V, T) (11)
Vcnt2 = Vptat (T) + Verr2 (V, T) (12)

  According to the present embodiment, as shown in FIG. 9, the temperature dependence of the capacitance value can be increased and a large temperature compensation amount can be obtained. In FIG. 9, the vertical axis represents capacity, and the horizontal axis represents VCNT1 and VCNT2.

  When the temperature rises, the CTAT voltage Vctat (−T) falls, so the voltage Vcnt1 falls, the PTAT voltage Vptat (T) rises, and thus the voltage Vcnt2 rises.

As the voltage Vcnt1 decreases, the capacitance values of C10 and C11 decrease,
As the voltage Vcnt2 increases, the capacitance values of C20 and C21 decrease.

  For this reason, the fluctuation of the capacity when the temperature rises is twice that of the first embodiment, and the temperature dependent adjustment range is expanded.

  The PTAT variable voltage source 40 and the CTAT variable voltage source 50 receive the constant voltage VDDA from the constant voltage source 20, receive the oscillation frequency adjustment signal and the temperature compensation intensity adjustment signal in common, and the voltages of the equations (11) and (12). Vcnt1 and Vcnt2 are generated and output. The PTAT variable voltage source 40 has a first oscillation frequency adjustment signal, a first temperature compensation intensity adjustment signal, and a CTAT variable voltage source 50 has a second oscillation frequency adjustment signal, a second oscillation frequency adjustment signal, and a second oscillation frequency adjustment signal. Needless to say, the temperature compensation intensity adjustment signal may be received.

<Example 3>
FIG. 10 is a diagram illustrating the configuration of the third embodiment. The third embodiment enables finer control than the first and second embodiments. It is desirable that C10, C11, C20, and C21 have the same size, and C30, C31, C40, and C41 have the same size. The sizes of C10 + C30, C11 + C31, C20 + C40, and C21 + C41 may be the same. The voltages Vcnt1, Vcnt2, Vcnt3, and Vcnt4 have independent control signals, and have independent center voltages and temperature-dependent strengths. CTAT variable voltage source 50 _1, the oscillation frequency adjustment signal 1, receives the temperature compensation intensity adjustment signal 1, the voltage Vcnt1 comprising CTAT voltage VCTAT (T) C10 and C11 of the connection point (e.g. C10, C11 B terminals of each other Applied to the connection point). PTAT variable voltage source 40 _1, the oscillation frequency adjustment signal 2, receives the temperature compensation intensity adjustment signal 2, the connection point of the voltage Vcnt2 containing PTAT voltage Vptat (T) C20 and C21 (e.g. C20, C21 between the G terminal of the Applied to the connection point). CTAT variable voltage source 50 _2, the oscillation frequency adjustment signal 3, the received temperature compensation intensity adjustment signal 3, connection points of the voltage Vcnt3 comprising CTAT voltage Vctat2 (T) C30 and C31 (e.g. C30, C31 B terminals of each other Applied to the connection point). PTAT variable voltage source 40 _2, the oscillation frequency adjustment signal 4, the receiving the temperature compensating intensity adjustment signal 4, the connection point of the PTAT voltage Vptat2 voltage Vcnt4 comprising (T) C40 and C41 (e.g. C40, C41 between the G terminal of the Applied to the connection point). The oscillation frequency adjustment signals 1 to 4 and the temperature compensation intensity adjustment signals 1 to 4 are output from an adjustment signal output circuit (not shown). The oscillation frequency adjustment signals 1 to 4 and the temperature compensation intensity adjustment signals 1 to 4 are, for example, a program (blowout) of a fuse (not shown) in the adjustment signal output circuit at the trimming stage of the semiconductor device, for example, as in the first embodiment. It is a fixed value determined by the above.

  The varactor elements C10, C11, C20, and C21 perform primary temperature compensation by setting Vcnt1 and Vcnt2 so that they are in the linear approximation region of the varactor.

The varactor elements C30, C31, C40, and C41 are configured with a size smaller than the varactor elements C10, C11, C20, and C21 (small gate size), and perform fine adjustment that cannot be corrected by the primary temperature compensation. Since Vcnt3 and Vcnt4 do not use the linear region of the varactor, adjustments such as increasing the compensation strength only at a high temperature and decreasing the compensation strength at a low temperature are possible. Compensation strength, in CTAT variable voltage source ₅₀ 2, PTAT variable voltage source 40 ₂ is set by the temperature compensating intensity adjustment signal 3,4.

  FIG. 11 shows an example of the capacitance value-terminal voltage (CV characteristic) of the MOS varactor element. The CV characteristic of FIG. 11 is inversely related to the capacitance value with respect to the CV characteristic of FIG. 16 and the inter-terminal voltage. In FIG. 11, the horizontal axis is the inter-terminal voltage of the varactor element in FIG. Vbg. In FIG. 16, the horizontal axis represents the voltage Vgb between terminals of the varactor element. The vertical axis in FIG. 11 is the capacitance value. In FIG. 11, when Vbg is 0 or less, the storage state is established. Also in this embodiment, primary compensation is performed using Vbg (voltage between the bulk terminal B and the gate terminal G) in the “linear approximation region” of FIG.

  In the linear approximate region in the middle of the CV characteristic curve, the capacitance value of the varactor element is substantially proportional to Vbg, and the capacitance value increases when the temperature decreases and decreases when the temperature increases.

  In this embodiment, the capacitance value of the varactor element is changed in proportion to the temperature (absolute temperature) by using Vptat (T) from the PTAT variable voltage source 40 in correspondence with the linear approximation region.

In the nonlinear region (1) on the side where Vbg is lower than the linear approximation region,
When the temperature drops, the capacitance value does not change,
As the temperature rises, the capacitance value decreases.

In the nonlinear region (2) where Vbg is higher than the linear approximation region,
When the temperature rises, the capacitance value does not change,
When the temperature falls, the capacity value increases.

  FIG. 12 shows a characteristic example of an on-chip oscillator without temperature compensation (see FIG. 2) as a comparative example. In FIG. 12, the horizontal axis represents temperature, and the vertical axis represents the oscillation frequency error (error from the ideal characteristic of the actual characteristic).

  FIG. 13 is a diagram illustrating the characteristic after the primary compensation in the present embodiment. In FIG. 13, the horizontal axis represents temperature, and the vertical axis represents the oscillation frequency error (error from the ideal characteristic of the actual characteristic). In this embodiment, primary compensation is performed as shown in FIG. In FIG. 13, the “actual characteristic” indicated by the thick solid line indicated by the primary compensation arrow is obtained by performing the primary compensation on the “actual characteristic” in FIG. 12 with respect to the temperature (the capacity of the varactor in the linear approximation region). And temperature compensation by PTAT voltage).

The linear approximation region is not completely linear, and deviates from ideal characteristics due to the influence of the leakage current and the constant voltage source error described above. Therefore, in this embodiment, the varactor elements C30, C31, C40, and C41 of FIG. 10A are provided corresponding to the “nonlinear region” of FIG.
Fine tuning selectively performed only at high temperatures, and
Fine adjustment that is selectively performed only at low temperatures,
Vcnt3 is applied to varactor elements C30 and C31,
This is performed on the varactor elements C40 and C41 by Vcnt4.

  As a result, according to the present embodiment, as shown in FIG. 14, the oscillation frequency characteristic is flat (oscillation frequency is constant regardless of temperature) in the entire temperature range from low temperature to high temperature. According to the present embodiment, errors can be further suppressed by performing fine adjustment in this way.

  By selecting the orientation of the varactor element, the PTAT voltage Vptat, and the CTAT voltage Vctat, it is possible to selectively increase the capacity value (or decrease the capacity value) only at a high temperature (or at a low temperature).

  Fine adjustment is possible by changing at least one of the sizes (gate sizes) of the varactor elements C30, C31, C40, and C41 to be different from the others.

<Example 4>
FIG. 15 is a diagram illustrating an example of a semiconductor chip 100 including the oscillator according to the present embodiment. A clock signal is differentially supplied from the oscillator 101 to a module that requires a high-speed clock such as Serdes. A clock signal obtained by dividing the clock of the oscillator 101 by a divider 102 is supplied to the PLL 103 as a reference clock signal. The output of the frequency dividing circuit 102 is distributed to an internal circuit via a CTS (Clock Tree Synthesis) buffer 104 as a system clock.

  According to the above embodiment, the oscillator 101 that generates a clock signal with a high-precision oscillation frequency without requiring a reference clock on the semiconductor device is different from each other with respect to the varactor element pair connected in parallel between both ends of the inductor L. By providing a plurality of pairs of varactor elements connected in the direction, it is possible to suppress the influence of errors due to fluctuations in power supply voltage, leakage current, and the like. The varactor control voltage may have both a linear approximation region for primary compensation and a non-linear region for fine adjustment that cannot be compensated only by the primary compensation.

  In the above embodiment, an example of a variable capacitance element constituting an LC resonator capacitor has been described based on an example of an accumulation mode MOS varactor formed on a p-type substrate. Of course, it is not a thing. Furthermore, the variable capacitance element is not limited to the accumulation mode MOS varactor.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) can be combined or selected within the scope of the claims of the present invention. . That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Driver 20 Constant voltage source 30 Variable voltage source 40 PTAT variable voltage source 50 CTAT variable voltage source 100 Semiconductor chip 101 Oscillator 102 Frequency divider 103 PLL
104 CTS
105 Serdes
111 Adjustment signal output circuit

Claims (10)

It has an oscillator including an inductor and capacitor resonance circuit,
The capacitor is
First variable terminals composed of first and second variable capacitance elements in which the respective first terminals are connected to face each other and the second terminal opposite to the first terminal is connected to nodes at both ends of the inductor, respectively. A capacitive element pair;
A second variable capacitor composed of third and fourth variable capacitance elements in which the respective second terminals are connected to face each other and the first terminal opposite to the second terminal is connected to the nodes at both ends of the inductor, respectively. A capacitive element pair;
With
A first voltage source for applying a first voltage to a connection node between the first terminals of the first variable capacitance element pair;
A second voltage source for applying a second voltage to a connection node between the second terminals of the second variable capacitance element pair;
A semiconductor device including: The first voltage source includes a variable voltage source that receives a constant voltage from a constant voltage source and generates the first voltage;
2. The variable voltage source according to claim 1, wherein the second voltage source includes a variable voltage source that receives a constant voltage from the constant voltage source, generates a voltage proportional to temperature (PTAT voltage), and outputs the voltage as the second voltage. Semiconductor device. The first voltage source receives a constant voltage from the constant voltage source and generates a voltage proportional to temperature (PTAT voltage) as the first voltage;
3. The semiconductor device according to claim 2, wherein the error voltage of the first and second voltages due to temperature and power supply voltage fluctuations exhibits equivalent characteristics with respect to power supply voltage characteristics and temperature dependence characteristics. The first voltage source includes a variable voltage source that receives a constant voltage from a constant voltage source, generates a voltage complementary to a temperature (CTAT voltage), and outputs the voltage as the first voltage;
2. The variable voltage source according to claim 1, wherein the second voltage source includes a variable voltage source that receives a constant voltage from the constant voltage source, generates a voltage proportional to temperature (PTAT voltage), and outputs the voltage as the second voltage. Semiconductor device.   Each of the first and second voltage sources includes an oscillation frequency adjustment signal for adjusting an oscillation frequency error of the oscillator, and a temperature compensation intensity adjustment signal for correcting the oscillation frequency error according to temperature. 5. The semiconductor device according to claim 1, wherein each of the first and second voltages is variably generated based on the first and second voltages. A plurality of sets of the first variable capacitance element pair and the second variable capacitance element pair,
Common connection of the first voltage source for applying the first voltage to a common connection point of the first terminals of the first variable capacitive element pair and the second terminal of the second variable capacitive element pair 6. The semiconductor device according to claim 1, further comprising a plurality of sets of the second voltage sources that apply the second voltage to a point. 7.   Among the plurality of sets of the first and second voltage sources, at least one set of the first voltage to which the first and second voltages are applied from at least one set of the first and second voltage sources, respectively. 7. The semiconductor device according to claim 6, wherein the variable capacitance element pair and the second variable capacitance element pair perform temperature compensation in a linear approximation region in which the capacitance value changes linearly with voltage in a capacitance value vs. voltage characteristic curve.   Of the plurality of sets of the first and second voltage sources, the first and second voltages are applied from at least one other set of the first and second voltage sources, respectively. The temperature of the linear approximation region by the at least one pair of the first variable capacitor element pair and the second variable capacitor element pair is determined by the first variable capacitor element pair and the second variable capacitor element pair. The semiconductor device according to claim 7, wherein fine adjustment of an area that cannot be corrected by compensation is performed. The size of the variable capacitive elements of the first variable capacitive element pair and the second variable capacitive element pair of the first set is the same,
The sizes of the variable capacitance elements of the first variable capacitance element pair and the second variable capacitance element pair in the second and subsequent sets are the same as the first variable capacitance element pair and the second variable capacitance of the first set. The semiconductor device according to claim 8, wherein the semiconductor device is smaller than a size of the variable capacitor of the capacitor pair. Each of the plurality of first voltage sources corrects a corresponding signal among a plurality of oscillation frequency adjustment signals for adjusting an error of the oscillation frequency of the oscillator and the error of the oscillation frequency according to temperature. Each of the plurality of temperature compensated intensity adjustment signals and generating each of the plurality of first voltages,
Each of the plurality of second voltage sources receives a corresponding signal among the plurality of oscillation frequency adjustment signals and a corresponding signal among the plurality of temperature compensation intensity adjustment signals, and each of the plurality of second voltages. The semiconductor device according to claim 8, wherein the semiconductor device is generated.

Images