JP2013168558A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SIP semiconductor device which inhibits excessive concentration of signal lines without increase in area or in the number of processes.SOLUTION: A semiconductor device comprises: a wiring substrate SUB on which connection pads are arranged; and a semiconductor chip CHP1 on which electrode pads are arranged. A magnitude relation among a first distance, a second distance and a third distance respectively between a first wiring substrate edge SE1, a second wiring substrate edge SE2 and a third wiring substrate edge SE3 which are outer edges of the wiring substrate, and a first chip edge CE1, a second chip edge CE2 and a third chip edge CE3 which are outer edges of the semiconductor chip and opposite to the first, second and third wiring substrate edges, respectively, is equal to a magnitude relation among a first number of signal wires, a second number of signal wires and a third number of signal wires which are the number of signal wires WR which connect the electrode pads and the connection pads and extend from the electrode pads in a direction toward the first, second and third chip edges, respectively. At least two distances among the first, second and third distances are different from each other.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor is mounted on a substrate.

  In recent years, development of a semiconductor device having a so-called SIP (System In Package) structure in which semiconductors as a plurality of integrated circuits (LSIs: Large Scale Integration) are mounted on a single wiring board has been promoted. Here, mounting means a process of electrically connecting a plurality of connection pads formed on a wiring board and a plurality of electrode pads formed on a semiconductor mounted on the wiring board by signal lines.

  A conventional SIP structure is disclosed, for example, in International Publication No. 2006/030517 (Patent Document 1). Here, there is disclosed a semiconductor device formed so that the number of signal lines extending from the electrode pad to the region facing each side is equal.

International Publication No. 2006/030517 Pamphlet

  In the conventional SIP structure, since the semiconductor is arranged at the center of the wiring board, there is little problem in the arrangement of the signal lines due to the signal lines becoming overcrowded on the wiring board. However, in recent years, as the degree of integration increases, a plurality of semiconductors are mounted on a single wiring board. As a result, the semiconductor is biased in one direction on the wiring board (an end portion on the wiring board). It is often arranged at a position close to). As a result, the signal line extending from the semiconductor in a direction where the distance between the edge of the semiconductor and the edge of the wiring board is short or the area between the outer edge of the semiconductor and the outer edge of the wiring board is small. There is a possibility that the signal lines will be difficult to arrange due to overcrowding.

  For example, the above-mentioned problem can be avoided by increasing the distance or expanding the area in the direction where the distance is short and the area is small. However, in this case, since the size of the wiring board becomes large, there is a possibility that the result is contrary to the high integration of SIP.

  In Patent Document 1, as a countermeasure, an opening that penetrates from one main surface of the wiring board to the other main surface is provided, and a signal line on one main surface side is provided on the other main surface side through the opening. By being routed, it is possible to prevent the signal lines from becoming overcrowded on the wiring board. However, a pad for connecting a signal line to the other main surface side in addition to the one main surface side of the wiring board is required, which may complicate the process.

  The following embodiments have been made in view of the above-described problems, and provide a semiconductor device having a so-called SIP structure in which signal line congestion is suppressed without increasing the area or increasing the number of processes. belongs to.

  According to one embodiment, a rectangular wiring board on which a plurality of connection pads are arranged and a rectangular semiconductor on which a plurality of electrode pads are arranged are provided. The wiring board has a first wiring board edge, a second wiring board edge, and a third wiring board edge on its outer edge, and the semiconductor has a first semiconductor edge and a second wiring edge on its outer edge. A semiconductor edge and a third semiconductor edge. A first distance that is the distance between the first wiring board edge and the first semiconductor edge, and a second distance that is the distance between the second wiring board edge and the second semiconductor edge. And the third distance, which is the distance between the third wiring board edge and the third semiconductor edge, is such that the first, second and third semiconductor edges from the electrode pad respectively. The number of signal lines extending in the direction toward the first line is equal to the first line number, the second line number, and the third line number. Note that at least two of the first, second, and third distances are different from each other.

  According to another embodiment, the ratio between the first distance and the second distance is equal to the ratio between the first number and the second number. Note that the first distance and the second distance are different from each other.

  According to still another embodiment, the first region surrounded by the first wiring board edge, the first semiconductor edge, and the line connecting the end points on the same side among these end points; A second region surrounded by a second wiring substrate edge, a second semiconductor edge, and a line segment similar to the above, a third wiring substrate edge, a third semiconductor edge, and the above And a third region surrounded by the same line segment as each other (the first area, the second area, and the third area, respectively) have a size relationship of the first number and the second number, respectively. It is equal to the magnitude relationship between the number and the third number. Note that at least two of the first, second, and third distances are different from each other.

  According to still another embodiment, the ratio between the first area and the second area is equal to the ratio between the first number and the second number. Note that the first distance and the second distance are different from each other.

  According to the above-described embodiment, in the semiconductor device having the SIP structure, the number of signal lines extending in the direction in which the distance is short (the area is small) is reduced. For this reason, it is possible to suppress overcrowding of the signal lines without expanding the area or increasing the number of processes.

It is a schematic plan view which shows the aspect which looked at the semiconductor device (except mold resin) concerning this Embodiment from the upper part. It is a schematic sectional drawing in the part which follows the II-II line of FIG. FIG. 3 is a schematic plan view showing a connection mode between the semiconductor and the wiring board in the first embodiment. FIG. 4 is a schematic enlarged plan view (upper) of a region IV surrounded by a dotted line in FIG. 3 and a schematic cross-sectional view (lower) showing a mode in which a signal line connects a connection pad and an electrode pad. 3 is a schematic plan view showing distances corresponding to respective edges of the semiconductor in the first embodiment. FIG. It is a schematic plan view which shows the connection aspect of the semiconductor and wiring board as a modification of FIG. 6 is a schematic plan view showing a connection mode between a semiconductor and a wiring board in a second embodiment. FIG. FIG. 10 is a schematic plan view showing an area corresponding to each edge of a semiconductor in a third embodiment. FIG. 6 is a schematic plan view showing an arrangement of semiconductors as a modified example of FIG. 5 and distances and areas corresponding thereto.

Hereinafter, the present embodiment will be described with reference to the drawings.
(Embodiment 1)
First, a semiconductor device having an SIP structure will be described as this embodiment.

  Referring to FIG. 1, the semiconductor device SP of the present embodiment has a so-called SIP structure and is mounted on a mounting board mounted on an electronic device. The semiconductor device SP mainly includes a wiring substrate SUB, semiconductor chips CHP1, CHP2, and CHP3 (semiconductor), and an external connection terminal ECT.

  The wiring substrate SUB is a substrate that supports the entire semiconductor device SP and is made of a generally known material for the substrate. The wiring board SUB is, for example, a rectangular plate shape in plan view. The semiconductor chips CHP1, CHP2, and CHP3 are disposed above one main surface (first main surface) of the wiring substrate SUB (upper side in the drawing). The semiconductor chips CHP1, CHP2, and CHP3 are, for example, logic chips such as microprocessors or memory chips such as flash memories, and have a wafer form made of a single crystal such as silicon. That is, the semiconductor chips CHP1, CHP2, and CHP3 are all used as so-called LSIs. The semiconductor chips CHP1, CHP2, and CHP3 in FIG. 1 are cut (diced) into a desired size and have a rectangular shape (for example, a square or a rectangle) in plan view.

  The plurality of external connection terminals ECT are arranged at regular intervals on the other main surface (lower side in the drawing) of the wiring board SUB. The external connection terminal ECT has a spherical shape made of, for example, solder balls, and electrically connects the semiconductor device SP and a mounting substrate (not shown) on which the semiconductor device SP is mounted.

  Referring to FIG. 2, semiconductor chips CHP1, CHP2, and CHP3 are mounted above bumps BMP above the first main surface of wiring board SUB. The bump BMP is preferably formed of, for example, solder. For example, in semiconductor chips CHP1 and CHP2, the main surface on which electrode pads (not shown in FIG. 2) are arranged is opposed to wiring substrate SUB (the main surface on which electrode pads are arranged is directed downward), and the electrode pads and wiring substrate It is preferable that the connection pads (not shown in FIG. 2) of the SUB are electrically connected by the bumps BMP. Further, the semiconductor chips CHP1, CHP2, and CHP3 arranged on one main surface of the wiring board SUB may be filled with the mold resin RSN.

  In the following, the semiconductor chip CHP1 is considered among the semiconductor chips CHP1, CHP2, and CHP3. Referring to FIG. 3, the semiconductor chip CHP1 is arranged at a position deviated to the left from the center of the wiring board SUB in plan view. This is because, as shown in FIG. 1 described above, in the semiconductor device SP, a plurality of semiconductor chips CHP1, CHP2, and CHP3 are arranged on the main surface of the wiring board SUB at intervals.

  The left, lower, right, and upper outer edges of the wiring board SUB in plan view are respectively connected to the first wiring board edge part SE1, the second wiring board edge part SE2, the third wiring board edge part SE3, and the fourth wiring board SUB. Let it be a wiring board edge SE4. Each of these corresponds to a boundary portion of the main surface of the wiring board SUB that represents one side of the outer edge of the rectangular wiring board SUB. As shown in FIG. 3, the left, lower, right, and upper outer edges of the semiconductor chip CHP1 in plan view are respectively defined as a first chip edge CE1, a second chip edge CE2, and a third chip edge CE3. And a fourth chip edge CE4. Each of these corresponds to a boundary portion of the main surface of the semiconductor chip CHP1 that represents one side of the outer edge of the rectangular semiconductor chip CHP1. The first chip edge CE1 is at the first wiring board edge SE1, the second chip edge CE2 is at the second wiring board edge SE2, and the third chip edge CE3 is at the third wiring board edge. In the part SE3, the fourth chip edge part CE4 represents an edge part facing the fourth wiring board edge part SE4.

  3 and 4, on one main surface (second main surface) of semiconductor chip CHP1 (on the upper side in the figure), a plurality of power supply terminals PWR and ground terminals GND are spaced at regular intervals. Although not shown, electrode pads are arranged. The power supply terminal PWR collectively shows terminals for supplying power to a semiconductor element such as a MOS (Metal Oxide Semiconductor) transistor (not shown) formed on the main surface of the semiconductor chip CHP1. The ground terminal GND collectively represents terminals for supplying a ground potential with respect to a potential applied to the semiconductor element of the semiconductor chip CHP1.

  The electrode pad is a terminal for electrically connecting the semiconductor element on the semiconductor chip CHP1 and the wiring board SUB. The electrode pad is connected to the wiring board SUB via the bump BMP, and the external connection terminal ECT (or the external connection terminal) electrically connected to the connection pad not shown in FIG. 4 via the signal line WR in the wiring board SUB. It is electrically connected to an external connection electrode (not shown) that is electrically connected to the ECT. As a result, the semiconductor chip CHP1 is electrically connected to the mounting substrate outside the semiconductor device SP. As an example, FIG. 4 shows an aspect in which the upper signal line WR1 (made of the same material as the signal line WR and used in the same manner as the signal line WR) in FIG. 4 electrically connects the bump BMP and the external connection terminal ECT. A cross-sectional view is shown below. In FIG. 4, the electrode pad is disposed so as to contact the bump BMP, for example, in a position overlapping with the bump BMP, and the connection pad is connected to the external connection terminal ECT, for example, in a position overlapping with the external connection terminal ECT. Arranged to be in contact with the ECT.

  As shown in FIG. 3, each electrode pad on the relatively outer side in plan view of the semiconductor chip CHP1 is classified into four types according to the direction in which the signal line WR extending from each electrode pad extends. That is, N1 (first number) signal lines WR extending in the direction from the electrode pad toward the first chip edge CE1 (leftward in FIG. 3) and toward the second chip edge CE2 (downward in FIG. 3). N2 (second number) signal lines WR extending in the direction, N3 (third number) signal lines WR extending in the direction toward the third chip edge CE3 (rightward in FIG. 3), and the fourth N4 (fourth) signal lines WR extending in a direction toward the chip edge CE4 (upward in FIG. 3).

  The signal line WR extending from the electrode pad via the bump BMP basically extends in a direction toward the outside of the semiconductor chip CHP1. Therefore, the signal line WR extends from the electrode pad in a direction toward one of the four edge portions CE1, CE2, CE3, and CE4 of the semiconductor chip CHP1.

  Referring to FIG. 5, here, as shown in FIGS. 3 and 4, the chip edges CE1, CE2, CE3, and CE4 of the semiconductor chip CHP1 are substantially parallel to the edges SE1, SE2, SE3, and SE4 of the wiring board SUB. Consider the case where they are arranged so that A distance L1 between the first chip edge CE1 and the first wiring board edge SE1 facing the first chip edge CE1 is defined. Similarly, the distance L2 between the second chip edge CE2 and the second wiring board edge SE2 facing the second chip edge CE2 and the third chip edge CE3 and the third wiring board edge SE3 facing it. A distance L3 and a distance L4 between the fourth chip edge portion CE4 and the fourth wiring board edge portion SE4 facing the fourth chip edge portion CE4 are defined. The distances L1, L2, L3, and L4 are all from one point on either the (first to fourth) chip edge and the (first to fourth) wiring board edge to the other. Corresponds to the length of the perpendicular drawn down to one point.

  At this time, in the example of FIG. 5, the distance L1 is the shortest and the distance L3 is the longest among the distances L1, L2, L3, and L4. The distance L2 and the distance L4 are longer than the distance L1 and shorter than the distance L3, and the distance L2 and the distance L4 are substantially the same length.

  In this case, the number N1 of signal lines WR extending in the direction toward the first chip edge CE1 corresponding to the distance L1 is the smallest, and the second and fourth chip edges CE2 and CE4 corresponding to the distances L2 and L4. The number N2 and N4 of signal lines WR extending in the direction toward N2 is small following N1. The number N3 of signal lines WR extending in the direction toward the third chip edge CE3 corresponding to the distance L3 is the largest.

  Therefore, even when the same semiconductor chip CHP1 and wiring substrate SUB as in FIG. 3 are used, the semiconductor chip is located at a position where the distance L2 is shorter than FIG. 3 and the distance L4 is longer than FIG. When CHP1 is arranged, the number of signal lines WR of each classification is adjusted so that N2 is smaller and N4 is larger than in FIG. For this reason, in the case of FIG. 6, for example, the upper right electrode pad in FIG. 3 (included in N3 in FIG. 3) is adjusted to be included in N4.

  As described above, in the present embodiment, each of the four wiring board edge portions SE1, SE2, SE3, and SE4 and the distance between each of the chip edge portions CE1, CE2, CE3, and CE4 facing each of them is L1, respectively. The number of signal lines WR (N1, N2, N3, N4) extending from the electrode pads to the respective directions (four directions) in which the chip edges CE1 to CE4 are arranged is determined by the magnitude relationship between L2, L3, and L4. ) To be equal to the magnitude relationship.

  More generally, in the present embodiment, at least any three directions are considered, and the above distances in the three directions are not all the same (at least two of the above three distances are different from each other). In this case, the magnitude relationship between the distances and the magnitude relationship between the number of signal lines WR extending in each direction are the same. That is, for example, the numbers N1, N2, and N3 of the signal lines WR extending in the direction toward the first, second, and third chip edge portions CE1, CE2, and CE3 are equal to the distances L1, L2, and L3. More specifically, for example, when N1> N2> N3, L1> L2> L3. The same relationship holds when any other three directions are selected.

  However, when the distances are the same, the number of signal lines WR is not necessarily the same. For example, N1> N2 may be set when L1 = L2.

  In the present embodiment, when all four directions are considered, it is more preferable that the same relationship as in the case of the three directions is satisfied. That is, the number N1, N2, N3, and N4 of signal lines WR extending in the direction toward the first, second, third, and fourth chip edge portions CE1, CE2, CE3, and CE4, and the distances L1, L2, and L3 , L4 are equal in magnitude. For example, when N1> N2> N3> N4, L1> L2> L3> L4.

  4 and 5, the N1 signal lines WR extending in the direction toward the first chip edge portion CE1 corresponding to the shortest distance L1 are first output from each electrode pad. Although it goes to the edge part CE1, it bends in the middle and then extends in a direction toward the second chip edge part CE2. The signal line WR is connected to a connection pad arranged in the vicinity of the second chip edge portion CE2 (in a region facing the second chip edge portion CE2).

  In this case, the signal line WR is a region closest to the electrode pad (however, as shown in the region RG in FIG. 4, the first chip edge from the electrode pad as seen in the signal line WR extending from a part of the electrode pads). It is considered that the region extends in a direction toward the first chip edge CE1, which is a direction extending in a region that extends further in the diagonal direction than the region extending in the direction toward the portion CE1.

  The reason why the signal line WR extending in the direction toward the first chip edge CE1 is bent in the middle is based on the following reason. Referring to FIG. 4, in the main surface of semiconductor chip CHP1, a region in the vicinity of chip edge portion CE1 corresponding to the shortest distance L1 based on the above definition has a wiring region and a wiring prohibition region. ing. The wiring area is an area where the signal line WR is arranged on the first main surface of the wiring board SUB, and the wiring prohibition area is an arrangement where the signal line WR is allowed from the viewpoint of affecting the wiring in the manufacturing process of the wiring board. It is an area that is not done.

  In the above, the existence of the semiconductor chips CHP2 and CHP3 other than the semiconductor chip CHP1 that is currently considered is ignored, and only the distance between each edge of the semiconductor chip CHP1 and each edge of the wiring substrate SUB facing the semiconductor chip CHP1 is considered. We are discussing. Actually, the number of signal lines WR that can be extended in each direction may vary depending on the size and arrangement of other semiconductor chips such as the semiconductor chips CHP2 and CHP3.

Here, the effect of this Embodiment is demonstrated.
When the distances L1 to L4 are not all the same distance as in the present embodiment, the number of signal lines WR extending in the direction from each electrode pad toward each chip edge CE1 to CE4 is set to each chip edge CE1 to CE4. By adjusting so that the distances L1 to L4 are equal to each other and the wiring board edge portions SE1 to SE4, it is possible to suppress the possibility that the signal line WR becomes overcrowded on the main surface of the wiring board SUB. it can. That is, for example, the number of signal lines WR extending in the direction of a region having a short distance can be reduced. For this reason, even when the signal line WR is routed through an opening penetrating from one main surface of the wiring substrate SUB to the other main surface, the signal lines WR are not mixed with each other, and the semiconductor chip CHP1 and the wiring substrate SUB. Can be electrically connected.

  Further, it is not necessary to expand the area of the main surface of the wiring board SUB for the purpose of reducing the area where the signal lines WR are densely arranged, and the high integration of the semiconductor device SP can be promoted.

(Embodiment 2)
In the present embodiment, a relationship that holds particularly in at least two arbitrary directions will be described.

  Referring to FIG. 7, a plurality of electrode pads are classified into four types by being surrounded by rectangles A, B, C, and D according to the direction in which signal line WR connected thereto extends from here. . In the present embodiment, the number N1 of signal lines extending in the direction toward the first chip edge portion CE1 is 12, and the number N2 of signal lines extending in the direction toward the second and fourth chip edge portions CE2 and CE4. , N4 is 48, and the number N3 of signal lines extending in the direction toward the third chip edge CE3 is 96. That is, N1: N2: N3: N4 = 1: 4: 8: 4.

  Referring to FIG. 7 and FIG. 5 again, for example, when L1: L2: L3; L4 = 1: 4: 8: 4, N1: N2: N3: N4 = 1: 4: 8: 4 In this way, the same effect as in the first embodiment can be obtained. In the present embodiment, not only the magnitude relationship but also the number of signal lines WR is adjusted so as to have a proportional relationship, so that the same effect as in the first embodiment can be further enhanced.

  More generally, in the present embodiment, when at least two arbitrary directions are considered and the distances in the two directions are different (not the same) from each other, the distances in the two directions are The ratio is equal to the ratio of the number of signal lines WR extending in the direction toward each of the two distances. In other words, the distance in each of the two directions is proportional to the number of signal lines WR extending in each of the two directions. For example, the above proportional relationship may be established between L1: L2 and N1: N2. That is, L1: L2 = N1: N2. The same relationship may be established when any other two directions are selected.

  The present embodiment is different from the first embodiment only in each point described above. In other words, all the configurations, conditions, procedures, effects, and the like that have not been described above in the present embodiment are the same as those in the first embodiment.

(Embodiment 3)
In the present embodiment, the relationship between the area corresponding to each chip edge and the number of signal lines WR in the same semiconductor device SP as in the first embodiment will be described.

  Referring to FIG. 8, attention is paid to the end points EP of the four wiring board edge portions SE1 to SE4 of the wiring board SUB and the end points EP of the four chip edge portions CE1 to CE4 of the semiconductor chip CHP1. The end points EP mean one end and the other end of each of the wiring board edge portions SE1 to SE4 and the chip edge portions CE1 to CE4.

  By connecting each of the four end points EP of the wiring board SUB to the end point EP of the four end points EP of the semiconductor chip CHP1 facing the end point EP of each wiring board SUB, four line segments SL are formed. . These four line segments SL are radial from the four end points EP of the semiconductor chip CHP1 toward the four end points of the wiring substrate SUB (in the direction from each edge of the semiconductor chip CHP1 to each edge of the wiring substrate SUB. That is, it extends outward). Furthermore, in other words, the four line segments SL are formed by connecting the four end points EP of the wiring board SUB and the four end points EP of the semiconductor chip CHP1 in a one-to-one relationship so that the end points EP do not cross each other. Two line segments SL are arranged.

  More specifically, for example, when focusing on the first wiring board edge SE1 and the first chip edge CE1, the line segment SL is a pair of end points EP of the first wiring board edge SE1 and the first edge EP. It is formed by connecting a pair of end points EP of one chip edge portion CE1. At this time, a line segment SL is formed by connecting the end points EP on the same side of the end points EP of the first wiring board edge SE1 and the end points EP of the first chip edge CE1. For example, the line segment SL is formed by connecting the left end point EP of the first wiring board edge SE1 and the left end point EP of the first chip edge CE1.

  A trapezoidal region (first region) surrounded by the wiring substrate edge SE1, the chip edge CE1, and the two line segments SL extending from the respective pair of end points EP is formed. Similarly, a trapezoidal shape surrounded by each of the wiring board edge portions SE2, SE3, SE4, each of the chip edge portions CE2, CE3, CE4, and two line segments SL extending from the respective pair of end points EP. Regions (second region, third region, and fourth region, respectively) are formed. The area S1 (first area) of the first region, the area S2 (second area) of the second region, the area S3 (third area) of the third region, and the area of the fourth region S4 (fourth area) is defined.

  In the present embodiment, as in the above embodiment, the size relationship of the areas of the first to fourth regions S1 to S4 to which the four types of signal lines WR extending from the electrode pads are directed is the same as in the above embodiment. These four types of signal lines WR are adjusted so as to be equal to the magnitude relationship of the number (N1, N2, N3, N4) of each.

  That is, in FIG. 8, the area S1 is the smallest and the area S3 is the largest. The area S2 and the area S4 are larger than the area S1 and smaller than the area S3, and the area S2 and the area S4 are substantially the same size.

  Therefore, in this case, the number N1 of the signal lines WR extending in the direction toward the first chip edge CE1 corresponding to the area S1 is the smallest, and the second and fourth chip edges CE2 and CE4 corresponding to the areas S2 and S4. The number N2 and N4 of signal lines WR extending in the direction toward N2 is small following N1. The number N3 of signal lines WR extending in the direction toward the third chip edge CE3 corresponding to the area S3 is the largest. Here, similarly to the first embodiment, the N1 signal lines WR (bent in the middle) in FIG. 4 are considered to extend in the direction toward the first region.

  Also in this case, in the present embodiment, at least arbitrary three directions are considered, and the areas corresponding to the respective directions are not all the same (at least two of the three areas are different from each other), A similar magnitude relationship is established between the area of each of the first to fourth regions and the number of signal lines WR extending in the direction toward each of the first to fourth regions. That is, instead of the distance of the first embodiment, the area is used in this embodiment to consider the magnitude relationship of the number of signal lines WR. Further, when all four directions are considered, it is more preferable that the same relationship as in the case of the four directions is satisfied. That is, toward the areas S1, S2, S3, S4 and the first, second, third, and fourth regions (first, second, third, and fourth chip edge portions CE1, CE2, CE3, and CE4). The magnitude relationship between the number N1, N2, N3, and N4 of signal lines WR extending in the direction is the same.

  However, when the areas are the same, the number of signal lines WR is not necessarily the same. For example, N1> N2 may be satisfied when S1 = S2.

  In the above, the presence of the semiconductor chips CHP2 and CHP3 other than the semiconductor chip CHP1 to be considered at present is ignored, and each edge of the semiconductor chip CHP1 and each edge and line segment of the wiring substrate SUB opposite to the edge are surrounded. The discussion takes into account only the area of the region. Actually, the number of signal lines WR that can be extended in each direction may vary depending on the size and arrangement of other semiconductor chips such as the semiconductor chips CHP2 and CHP3.

  As described above, even when the number of signal lines WR is adjusted using the areas S1 to S4 instead of the distances L1 to L4, the same effects as those of the first embodiment can be obtained.

  Referring to FIG. 9, for example, each chip edge portion CE1, CE2, CE3, CE4 of semiconductor chip CHP1 is arranged to have an inclination angle with respect to each edge portion SE1, SE2, SE3, SE4 of wiring substrate SUB. Think about the case. In this case, since it is difficult to define the distances L1 to L4 as shown in FIG. 5, by defining the areas S1 to S4 as in the present embodiment, the number of signal lines WR extending in each direction can be reduced. It is preferable to adjust.

  The present embodiment is different from the first embodiment only in each point described above. In other words, all the configurations, conditions, procedures, effects, and the like that have not been described above in the present embodiment are the same as those in the first embodiment.

(Embodiment 4)
In the present embodiment, the proportional relationship that holds in the same manner as in the second embodiment even when the number of signal lines WR is adjusted using the areas S1 to S4 as in the third embodiment will be described.

  Referring to FIG. 7 again, for example, when S1: S2: S3: S4 = 1: 4: 8: 4, N1: N2: N3: N4 = 1: 4: 8: 4 as described above. To be. That is, a proportional relationship is established between the area and the number of signal lines WR. In this way, the same effects as in the first and second embodiments can be obtained.

  More generally, in the present embodiment, when at least two arbitrary directions are considered and the areas in the two directions are different (not the same) from each other, the area of each of the two directions is The ratio is equal to the ratio of the number of signal lines WR extending in the direction toward each of the two areas. In other words, the area in each of the two directions and the number of signal lines WR extending in the two directions are in a proportional relationship. For example, the proportional relationship may be established between S1: S2 and N1: N2. That is, S1: S2 = N1: N2. The same relationship may be established when any other two directions are selected.

  The present embodiment is different from the second and third embodiments only in the points described above. In other words, all the configurations, conditions, procedures, effects, and the like that have not been described above in the present embodiment are the same as those in the second and third embodiments.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  BMP bump, CE1 first chip edge, CE2 second chip edge, CE3 third chip edge, CE4 fourth chip edge, CHP1, CHP2, CHP3 semiconductor chip, ECT external connection terminal, EP end point , GND ground terminal, MUT mounting material, PWR power supply terminal, RSN mold resin, SE1 first wiring board edge, SE2 second wiring board edge, SE3 third wiring board edge, SE4 fourth wiring board Edge, SL line segment, SP semiconductor device, SUB wiring board, WR signal line.

Claims (5)

A rectangular wiring board having a first main surface and having a plurality of connection pads disposed on the first main surface;
A rectangular semiconductor chip disposed above the first main surface of the wiring board, having a second main surface and having a plurality of electrode pads disposed on the second main surface;
A first distance that is a distance between a first wiring board edge that is an outer edge of the wiring board and a first chip edge that is an outer edge of the semiconductor chip facing the first wiring board edge; A second distance that is a distance between a second wiring board edge that is an outer edge of the wiring board and a second chip edge that is an outer edge of the semiconductor chip facing the second wiring board edge; A third distance that is a distance between a third wiring board edge that is an outer edge of the wiring board and a third chip edge that is an outer edge of the semiconductor chip facing the third wiring board edge. The magnitude relationship is the number of the signal lines extending in the direction from the electrode pad toward each of the first, second and third chip edges among the signal lines connecting the electrode pad and the connection pad. Each of the first number, the second number and the third number Equal to small relationship,
A semiconductor device, wherein at least two of the first, second, and third distances are different from each other.   The fourth wiring board edge, which is the outer edge of the wiring board other than the first, second, and third wiring board edges, and the semiconductor chip other than the first, second, and third chip edges. The relationship between the fourth distance, which is the distance from the fourth chip edge that is the outer edge, and each of the first, second, and third distances is as follows. 2. The semiconductor device according to claim 1, wherein the fourth number, which is the number of the signal lines extending in the direction toward the first line, is equal to each of the first, second, and third numbers. A rectangular wiring board having a first main surface and having a plurality of connection pads disposed on the first main surface;
A rectangular semiconductor chip disposed above the first main surface of the wiring board, having a second main surface and having a plurality of electrode pads disposed on the second main surface;
A first distance that is a distance between a first wiring board edge that is an outer edge of the wiring board and a first chip edge that is an outer edge of the semiconductor chip facing the first wiring board edge; A second distance that is a distance between a second wiring board edge that is an outer edge of the wiring board and a second chip edge that is an outer edge of the semiconductor chip opposite to the second wiring board edge. The ratio is the number of the signal lines extending from the electrode pad in the direction toward each of the first and second chip edges among the signal lines connecting the electrode pad and the connection pad. Equal to the ratio of the number of
The semiconductor device, wherein the first distance and the second distance are different from each other. A rectangular wiring board having a first main surface and having a plurality of connection pads disposed on the first main surface;
A rectangular semiconductor chip disposed above the first main surface of the wiring board, having a second main surface and having a plurality of electrode pads disposed on the second main surface;
A first wiring board edge that is an outer edge of the wiring board; a first chip edge that is an outer edge of the semiconductor chip facing the first wiring board edge; the first wiring board edge; A first region surrounded by a line segment connecting the end points on the same side of each pair of end points with the first chip edge, and a second wiring board edge that is an outer edge of the wiring board And a second chip edge that is an outer edge of the semiconductor chip opposite to the second wiring board edge, a pair of the second wiring board edge, and the second chip edge. The second region surrounded by the line segment connecting the end points on the same side among the end points, the third wiring substrate edge that is the outer edge of the wiring substrate, and the third wiring substrate edge. Third chip edge, third wiring board edge and third chip which are outer edges of the semiconductor chip A first area, a second area, and a third area, each of which is an area of a third region surrounded by a line segment connecting the end points on the same side of each pair of end points The size relationship is the number of signal lines extending in the direction from the electrode pad toward each of the first, second, and third regions among the signal lines connecting the electrode pad and the connection pad. Each is equal to the magnitude relationship of the first number, the second number, and the third number,
A semiconductor device, wherein at least two of the first, second, and third areas are different from each other. A rectangular wiring board having a first main surface and having a plurality of connection pads disposed on the first main surface;
A rectangular semiconductor chip disposed above the first main surface of the wiring board, having a second main surface and having a plurality of electrode pads disposed on the second main surface;
A first wiring board edge that is an outer edge of the wiring board; a first chip edge that is an outer edge of the semiconductor chip facing the first wiring board edge; the first wiring board edge; A first region surrounded by a line segment connecting the end points on the same side of each pair of end points with the first chip edge, and a second wiring board edge that is an outer edge of the wiring board And a second chip edge that is an outer edge of the semiconductor chip opposite to the second wiring board edge, a pair of the second wiring board edge, and the second chip edge. The ratio between the first area and the second area, which is the area of the second region surrounded by the line segment connecting the end points on the same side among the end points, is the electrode pad and the connection pad. Of the signal lines connecting the first and second regions from the electrode pad to the first and second regions. Equal to the ratio between the first number and the second number, respectively is the number of the signal lines extending in a direction,
The semiconductor device, wherein the first area and the second area are different from each other.

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