JP2003332520A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve EMS resistance and reduce spurious radiation noise by adding a capacity between power sources without increasing a mounting area. <P>SOLUTION: A first semiconductor chip 104 is mounted and fixed on a die pad 103. A second semiconductor chip 105 is face-down arranged face to face with the first chip 104. The first chip 104 is connected with the second chip 105 via bumps 102. A capacitance element 106 between power sources is disposed in the second chip 105 and connected with a lead 100 via bonding wire 101. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multifunctional semiconductor device such as a system LSI having a plurality of semiconductor chips mounted in the same package.

[0002]

2. Description of the Related Art Due to the progress of semiconductor technology, system
A system LSI realized on one semiconductor chip has become the mainstream. In a system LSI, a DRAM, a flash memory, etc. are often mixedly mounted on the chip. But,
In the embedded memory, the speed of miniaturization is slower than that of the logic part, and it takes a long time to develop the embedded process.

Under these circumstances, a technique for realizing a system LSI by encapsulating a plurality of semiconductor chips having different diffusion processes in the same package is drawing attention. The form is various and can be roughly classified into two types.

First, bumps are formed by disposing another chip (child chip; second semiconductor chip) on the surface of a base semiconductor chip (parent chip; first semiconductor chip) so as to face each other. It is a method of connecting via. This is called the face-down method because the surface of the child chip faces downward.

The second method is to bond the back surface of the child chip onto the parent chip. Chips are connected directly or by bonding wires via leads.
This is called a face-up method because the surface of the child chip faces upward.

[0006]

However, due to the miniaturization of the process rule due to the recent technological progress, the lowering of the power supply voltage and the higher operating frequency have been accelerated. Radiation noise increases due to speeding up and voltage reduction due to such miniaturization, and conversely, resistance to external noise is decreasing.

Therefore, as a measure against noise, a technique of widening the wiring width to reduce the power supply wiring resistance or forming a MOS capacitor in a chip and inserting it between power supplies is widely used. Wide the wiring width to reduce the power supply wiring resistance,
If a sufficient capacity is inserted into the chip as a countermeasure against noise, there is a problem that the increase in chip size cannot be avoided.

Further, the heat generation of the chip increases as the operating frequency increases. In particular, in the technology of mounting a plurality of chips in the same package, semiconductor chips are stacked in the vertical direction and mounted. In this case, the mounting density in the chip increases, the amount of heat generated is large, and heat dissipation becomes difficult.

Further, when a plurality of chips are stacked and mounted in the same package, if the areas of the chips are the same, the bonding pad of the parent chip is hidden by the child chip.
There is a problem that the wire connection to the lead becomes impossible and the external connection cannot be made.

Further, in the circuit section in the semiconductor chip which requires the high potential side power source or the low potential side power source, the power source wiring connected to the bonding pad wire-connected to the high potential side power source or the low potential side power source is provided in the chip. Wiring. In that case, the width of the metal wiring has been widened because it is necessary to reduce the power supply current density in order to prevent electromigration that causes disconnection. However, if this wiring region is secured in the chip, it becomes difficult to reduce the chip area.

Further, there is a system in which a switch such as a metal option is provided when a function-variable control circuit for switching a function by switching a power supply potential is formed on a chip. In this case, it is necessary to change the metal wiring mask for switching the functions described above, and it is inevitable that the cost for manufacturing the mask is increased. In addition, since it is a change from the metal mask process, the turnaround time (TAT: Turn Aro) from receiving an order from a customer to supplying a product
There is a problem that und Time) becomes long.

An object of the present invention is to solve the above problems in the prior art.

[0013]

In order to solve the above problems, the present invention takes the following means.

As a first solution, the semiconductor device according to the present invention comprises a plurality of semiconductor chips stacked on each other and electrically connected to each other, and at least one of the plurality of semiconductor chips is an inter-power-source capacitance element. It is configured with.

According to this structure, the semiconductor chip provided with the inter-power-source capacitance element can suppress the power-source potential fluctuation caused by the intrusion of external noise. Further, the semiconductor chip provided with the inter-power-source capacitance element covers the other semiconductor chips, so that the shielding effect is exerted, and unnecessary radiation noise from the first semiconductor chip to the outside of the package can be reduced.

The configuration of the first solving means is preferably the following on a more specific level.

One of them is provided with a first semiconductor chip and a second semiconductor chip which is arranged so as to face the first semiconductor chip and is electrically connected to the first semiconductor chip via a bump.
The semiconductor device in which the power supply wiring and the inter-power supply capacitive element are formed on either one of the semiconductor chip and the second semiconductor chip.

The second includes a first semiconductor chip and a second semiconductor chip arranged on the first semiconductor chip and electrically connected via a bonding wire, and the first semiconductor chip is provided. A semiconductor device in which a power supply wiring and an inter-power supply capacitive element are formed on either one of the chip and the second semiconductor chip.

The difference between the first and the second is that the connection between the first semiconductor chip and the second semiconductor chip is a bump or a bonding wire. In the former case, both semiconductor chips face each other, and in the latter case, both semiconductor chip surfaces face in the same direction. In any case, similarly to the above, the semiconductor chip equipped with the inter-power supply capacitance element suppresses fluctuations in the power supply potential due to the intrusion of external noise, and the shield effect of the chip itself prevents unwanted radiation noise to the outside of the package. Reduce.

As a second solution, the semiconductor device according to the present invention comprises a plurality of semiconductor chips stacked on each other and electrically connected to each other, and at least one set of adjacent semiconductor chips among the plurality of semiconductor chips is A semiconductor chip diffused with a P substrate material and a semiconductor chip diffused with an N substrate material, and these two semiconductor chips are laminated so as to face each other with a capacitive element interposed therebetween. There is.

According to this structure, in the two semiconductor chips that are adjacent to each other in the stacked state, the respective substrate materials have the P-type and N-type polarities opposite to each other. Therefore, if they are opposed to each other on the back side and an insulator is interposed between the two, a substantial capacitive element is eventually formed. Therefore, while suppressing fluctuations in power supply potential due to intrusion of external noise,
For the arrangement of the capacitive elements required for that purpose, the inter-power-source capacitance can be inserted without increasing the mounting area.

As a third means for solving the problem, the semiconductor device according to the present invention is arranged to face the first semiconductor chip mounted on the die pad and electrically connected to the first semiconductor chip via bumps. And a second semiconductor chip, and the area of the second semiconductor chip is larger than that of the first semiconductor chip.

According to this structure, the second semiconductor chip on the die pad arranged opposite to the first semiconductor chip occupies a position closer to the surface of the package than the first semiconductor chip. Since the chip area of the second semiconductor chip is larger than that of the first semiconductor chip, the efficiency of heat radiation from the package surface is improved. If a heat dissipation device such as a heat sink is added to the back surface of the second semiconductor chip, the heat dissipation efficiency will be further improved.

In the above-mentioned preferred mode, the heat radiation material is filled in the gap between the die pad and the second semiconductor chip. According to this, the heat dissipation efficiency from the lower surface of the package can be improved.

As a fourth solution, the semiconductor device according to the present invention is arranged so as to face the first semiconductor chip mounted on the die pad and electrically connected via a bump. A second semiconductor chip, the size of the second semiconductor chip is substantially the same as the size of the first semiconductor chip, and the second semiconductor chip is arranged in the chip surface direction. The first
Of the semiconductor chips are arranged so as to be offset from each other.

According to this structure, the bonding pad in the peripheral region which does not overlap the second semiconductor chip is exposed on the upper surface of the first semiconductor chip, and similarly, the second bonding pad is also formed.
Since the bonding pad in the peripheral region which does not overlap with the first semiconductor chip is exposed on the lower surface of the semiconductor chip, the both semiconductor chips can be connected to the lead via the bonding wire.

As described above, widening the metal wiring as a measure against electromigration makes it difficult to reduce the chip area. Further, the change of the metal wiring mask for the variable function control circuit causes an increase in cost and an increase in turnaround time.

Therefore, the present invention takes the following means as a fifth solution. That is, in a semiconductor device in which a plurality of bonding pads are formed on the surface of a semiconductor chip, a bonding pad wire-connected to a high-potential-side power source and a low-potential-side power source is replaced with another bonding pad (in-chip bonding) in the same semiconductor chip. The pad is connected via a bonding wire (bonding wire in a chip).

According to this structure, since the power supply current density can be sufficiently reduced by the bonding wire in the chip when the power supply current density is reduced to prevent electromigration, it is possible to eliminate the need to widen the width of the metal wiring in the chip. . As a result, the chip area can be reduced. Further, since the potential of the in-chip bonding pad can be changed by switching the connection destination of the in-chip bonding wire, it is not necessary to switch the connection by changing the mask such as the mask option, and it is possible to reduce the cost and the turnaround time.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view and a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention.

In FIG. 1, 100 is a lead for electrically connecting the inside and the outside of the package, 101 is a bonding wire, 102 is a bump, 103 is a die pad for mounting and fixing a semiconductor chip, and 104 is a first semiconductor chip. (Parent chip), 105 is a second semiconductor chip (child chip). The die pad 103 constitutes a part of a lead frame, and the first semiconductor chip 104 is placed and fixed on the die pad 103 face up. The bonding pad of the first semiconductor chip 104 is electrically connected to the lead 100 via the bonding wire 101. The second semiconductor chip 105 is arranged face down on the first semiconductor chip 104, and the first semiconductor chip 104 and the second semiconductor chip 105 are electrically connected via the bumps 102. . A capacitance element 106 for inter-power MOS capacitance is formed inside the second semiconductor chip 105.
Are wirings 107, bumps 102 in the second semiconductor chip,
The high-potential-side power supply VD via the wiring 108, the bonding wire 101, and the lead 100 in the first semiconductor chip
D, connected to the low-potential-side power supply VSS.

With the above configuration, the second semiconductor chip 1
The inter-power MOS capacitance of the capacitive element 106 formed in 05 absorbs power noise intruding from the outside, and improves the EMS resistance. In addition, the second fixed to the power supply potential
The semiconductor chip 105 of the first semiconductor chip 104
The effect of reducing unnecessary radiation noise radiated from the package to the outside of the package can be obtained. In addition, the first semiconductor chip 10
Since the MOS capacitance on 4 can be reduced, the mounting area can be reduced.

(Second Embodiment) FIG. 2 is a sectional view and a plan view showing the structure of a semiconductor device according to a second embodiment of the present invention.

The second embodiment is different from the first embodiment in the following points. The second semiconductor chip 105 is directly mounted face-up on the upper surface of the first semiconductor chip 104 which is mounted face-up on the die pad 103. The capacitive element 106 in the second semiconductor chip 105 is connected to the bonding pad 102a on the first semiconductor chip 104 via the bonding wire 101a, and the first semiconductor chip 10 is further connected.
It is connected to the lead 100 via the wiring 108 in 4 and the bonding wire 101. In the case of the first embodiment, the first semiconductor chip 104 and the second semiconductor chip 1
In the present embodiment, the surface of the first semiconductor chip 104 and the surface of the second semiconductor chip 105 are in the same direction. Since other configurations are similar to those of the first embodiment shown in FIG. 1, the same parts are allotted with the same reference numerals and the description thereof will be omitted.

Also in the present embodiment, the same operational effects as in the case of the first embodiment are exhibited.

(Third Embodiment) FIG. 3 is a sectional view and a plan view showing the structure of a semiconductor device according to a third embodiment of the present invention.

In FIG. 3, 200 is a lead for electrically connecting the inside and the outside of the package, and 201, 201a.
Is a bonding wire, 203 is a wiring board, and 204 is P
A P substrate chip (first semiconductor chip) diffused with the substrate material and 205 are N substrate chips (second semiconductor chip) diffused with the N substrate material. The first semiconductor chip 204 is electrically and mechanically connected to the wiring board 203 via the bumps 202, and the second semiconductor is provided with the capacitive element (insulator) 206 interposed on the first semiconductor chip 204. Chips 205 are stacked. The first semiconductor chip 204 and the second semiconductor chip 205 are stacked with their back surfaces facing each other (that is, back-to-back). The first semiconductor chip 204 is connected to the leads 200 arranged around the wiring board 203 via the bonding wires 201,
The second semiconductor chip 205 is connected to the second semiconductor chip 205 via the bonding wire 201a.

With the above configuration, the back surface of the first semiconductor chip 204 which is a P substrate chip (low potential VSS) and the back surface of the second semiconductor chip 205 which is an N substrate chip (high potential VDD) are insulators 206. Are facing each other. This results in the formation of a substantial capacitive element 206. Therefore, the structure is such that the inter-power-source capacitance is inserted without increasing the mounting area. As a result, it absorbs power supply noise that enters from the outside,
It is possible to improve the EMS resistance.

(Fourth Embodiment) FIG. 4 is a sectional view and a plan view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.

In FIG. 4, 300 is a lead for electrically connecting the inside and the outside of the package, 301 is a bonding wire, 302 is a die pad forming a part of a lead frame, 303 is a semiconductor chip, and 310 to 316 are chips. In-chip bonding pad formed inside,
320, 321, 322 are in-chip bonding wires, and 330 is a variable function control circuit.

The semiconductor chip 303 is placed and fixed face-up on the die pad 302. Bonding pads around the semiconductor chip 303 are electrically connected to the leads 300 via bonding wires 301. The in-chip bonding pads 310 and 314 are connected to the high potential side power supply VDD, and the in-chip bonding pads 312 and 316 are connected to the low potential side power supply VSS.

In-chip bonding pads 310, 31
1 are connected to each other via in-chip bonding wires 320, and in-chip bonding pads 312, 313
Are connected to each other via in-chip bonding wires 321, and in-chip bonding pads 314 and 315 are connected to each other via in-chip bonding wires 322. Then, the in-chip bonding pad 31
A variable function control circuit 330 is connected to the control circuit 5. The control circuit 330 is used for the bonding pad 31 in the chip.
It is a circuit whose function can be switched by the potential of 5.

In the semiconductor device configured as described above, in order to switch the function of the variable function control circuit 330, the power supply connection to the in-chip bonding pad 315 by the in-chip bonding wire 322 is changed to the in-chip bonding pad 314. Switching to the in-chip bonding pad 316. That is, the function is switched depending on whether it is connected to the high potential side power source VDD or the low potential side power source VSS.

As described above, in the present embodiment, the power supply wiring inside the chip is performed by the bonding wire inside the chip. As a result, it is possible to eliminate the power supply wiring, which has required a wide wiring in the conventional semiconductor chip, and to reduce the chip area. Further, the switching of the potential of the in-chip bonding pad can be easily realized by switching the connection destination of the in-chip bonding wire.

(Fifth Embodiment) FIG. 5 is a sectional view showing a structure of a semiconductor device according to a fifth embodiment of the present invention.

In FIG. 5, 400 is a first semiconductor chip, and 401 is a second semiconductor chip having a chip area larger than that of the first semiconductor chip 400. Reference numeral 402 is a bump, 403 is a die pad, 404 is a heat dissipation material, and 405 is a heat sink for heat dissipation.

The first semiconductor chip 400 is formed on the upper surface of the die pad 403 which constitutes a part of a lead frame (not shown).
Is mounted face-up and fixed, and the second semiconductor chip 4 having a larger area than the first semiconductor chip 400 is mounted.
01 are arranged face-down, and the first semiconductor chip 400 and the second semiconductor chip 401 are bumps 40.
It is electrically connected via 2. In that case, the second
The heat radiation material 404 is filled in the gaps between the semiconductor chip 401, the die pad 403, and the first semiconductor chip 400. The heat sink 405 is placed and fixed on the back surface of the second semiconductor chip 401. In addition,
In the molded state, the heat radiation fins 405a of the heat sink 405 are exposed to the outside of the molding resin.

In the semiconductor device configured as described above, the second semiconductor chip 401 directly joined to the heat sink 405 has a larger chip area and therefore a larger amount of heat radiation than the first semiconductor chip 400. Higher heat dissipation efficiency can be obtained as compared with the case where it is reversed.

(Sixth Embodiment) FIG. 6 is a sectional view and a plan view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.

In FIG. 6, reference numeral 500 denotes leads for electrically connecting the inside and the outside of the package, 501 and 501a.
Is a bonding wire, 502 is a die pad, 503 is a first semiconductor chip, 504 is a second semiconductor chip, 5
Reference numeral 05 is a bump.

The first semiconductor chip 503 is mounted face-up and fixed on the die pad 502. First
The second semiconductor chip 50 with respect to the semiconductor chip 503 of
4 is facing down, but in this case,
The second semiconductor chip 504 is the first semiconductor chip 503.
The second semiconductor chip 504 has the same shape and the same chip size as that of the first semiconductor chip 504, and is disposed so as to face the first semiconductor chip 503 in a state of being displaced along the chip surface direction. The second semiconductor chip 504 and the first semiconductor chip 503 are electrically connected via the bumps 505. Then, the bonding pads on the periphery of the upper surface of the first semiconductor chip 503 are electrically connected to the leads 500 via the bonding wires 501, and the second semiconductor chip 504.
Bonding pads around the lower surface of the are electrically connected to the leads 500 via the bonding wires 501a.

In the semiconductor device of the present embodiment configured as described above, even when two semiconductor chips 503 and 504 having the same chip area are stacked, the bonding pad of each semiconductor chip can be exposed. It becomes possible to connect to the lead via the bonding wire.

[0054]

According to the present invention, firstly, at least one semiconductor chip among a plurality of stacked semiconductor chips has an inter-power-source capacitance element,
Capacitors between power supplies can be inserted without increasing the mounting area, and as a result, fluctuations in power supply potential due to intrusion of external noise are suppressed, and EMS (Electro-Magnet
ic Susceptibility: The effect of improving resistance. Further, since the chip having the capacitance is fixed to the power supply potential, the effect of reducing unnecessary radiation noise radiated to the outside of the package due to the shield effect is obtained.

Second, at least one set of adjacent semiconductor chips among the plurality of stacked semiconductor chips is a semiconductor chip diffused with a P substrate material and a semiconductor chip diffused with an N substrate material, and these two semiconductor chips are combined. By stacking the chips facing each other with the capacitive element interposed between the chips, the mounting area is not increased,
Capacitors can be inserted between VDD (back surface of N substrate) and VSS (back surface of P substrate), and as a result, fluctuations in power supply potential due to intrusion of external noise are suppressed and EMS resistance is improved.

Thirdly, the area of the second semiconductor chip on the upper side of the first semiconductor chip and the second semiconductor chip which are bump-connected in the opposed arrangement state is smaller than the area of the first semiconductor chip on the lower side. Since the second semiconductor chip on the side close to the package surface is large, the heat dissipation efficiency is improved. Further, by filling the space between the die pad and the second semiconductor chip with the heat dissipation material,
The effect of improving the heat radiation efficiency from the lower surface of the package is obtained.

Fourth, by shifting two semiconductor chips of substantially the same size in the chip surface direction to expose the bonding pads in the peripheral region, even in a semiconductor device in which two semiconductor chips of substantially the same size are stacked, It is possible to connect the semiconductor chip to the lead via the bonding wire.

Fifth, by connecting the bonding pads formed on the semiconductor chip to each other by bonding wires, the power supply current density can be sufficiently reduced by the bonding wires in the chip in the electromigration countermeasure, so that the metal wiring in the chip is reduced. It is not necessary to increase the width, and the chip area can be reduced. Also,
Since the potential of the in-chip bonding pad can be changed by switching the connection destination of the in-chip bonding wire, it is not necessary to switch the connection by changing the mask such as the mask option, and the cost and turnaround time can be shortened.

[Brief description of drawings]

FIG. 1 is a sectional view and a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view and a plan view showing a structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view and a plan view showing the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a sectional view and a plan view showing a structure of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a structure of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view and a plan view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.

[Explanation of symbols]

100, 200, 300, 500: Leads 101, 101a, 201, 201a, 301, 50
1, 501a: bonding wires 102, 202, 402, 505: bumps 102a: bonding pads 103, 302, 403, 502: die pads 104, 204, 400, 503: first semiconductor chips 105, 205, 401, 504: first 2 semiconductor chip 106: Capacitance element 203: Wiring board 204: N board chip 205: P board chip 206: Capacitance element (insulator) 303: Semiconductor chips 310 to 316: In-chip bonding pads 320 to 322: In-chip bonding wires 330: variable function control circuit 403: die pad 404: heat dissipation material 405: heat sink

Claims (8)

[Claims] 1. A semiconductor device comprising a plurality of semiconductor chips stacked on each other and electrically connected to each other, wherein at least one of the plurality of semiconductor chips comprises an inter-power-source capacitance element. 2. A first semiconductor chip, and a second semiconductor chip which is arranged to face the first semiconductor chip and is electrically connected via a bump, the first semiconductor chip and the first semiconductor chip A semiconductor device in which a power wiring and an inter-power capacitive element are formed on either one of the second semiconductor chips. 3. A first semiconductor chip, and a second semiconductor chip disposed on the first semiconductor chip and electrically connected via a bonding wire, the first semiconductor chip and A semiconductor device in which a power wiring and an inter-power capacitive element are formed on either one of the second semiconductor chips. 4. A semiconductor chip and an N substrate having a plurality of semiconductor chips stacked on each other and electrically connected to each other, wherein at least one set of adjacent semiconductor chips among the plurality of semiconductor chips is diffused with a P substrate material. A semiconductor device having a semiconductor chip diffused with a material, and these two semiconductor chips are laminated so as to face each other with a capacitive element interposed therebetween. 5. A first semiconductor chip mounted on a die pad, and a second semiconductor chip which is arranged so as to face the first semiconductor chip and is electrically connected via a bump, The area of the second semiconductor chip is the first
Semiconductor device that is larger than the semiconductor chip of. 6. The semiconductor device according to claim 5, wherein a gap between the die pad and the second semiconductor chip is filled with a heat dissipation material. 7. A first semiconductor chip mounted on a die pad, and a second semiconductor chip which is arranged so as to face the first semiconductor chip and is electrically connected via a bump, wherein the second semiconductor chip is provided. The size of the semiconductor chip is
And a semiconductor device in which the second semiconductor chip is arranged so as to face the first semiconductor chip in the chip surface direction in a shifted state. 8. A plurality of bonding pads are formed on the surface of a semiconductor chip, and a bonding pad wire-connected to a high potential side power source and a low potential side power source is bonded to another bonding pad in the same semiconductor chip. A semiconductor device connected via a wire.