JP2013166058A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of reducing malfunction of a CPU.SOLUTION: A game machine has a main control segment (60). A main conversion power supply (VCC5V) generated by converting main power supply (DC12V) generated in a power supply segment to a different voltage, and a backup power supply (VBB) generated in the power supply segment are supplied to a CPU (600) arranged in the main control segment (60). A diode (D30) is connected between a power supply line of the main conversion power supply (VCC5V) and a power supply line of the backup power supply (VBB).

Description

  The present invention relates to a gaming machine such as a pachinko machine, an arrangement ball machine, a sparrow ball game machine, and a slot, and more particularly to a gaming machine that reduces malfunction of a CPU.

  As a conventional gaming machine such as a pachinko machine, for example, a gaming machine described in Patent Document 1 is known. This gaming machine has a main control board mainly responsible for game control, a payout control board for paying out game balls based on control commands from the main control board, and a power supply voltage required for each such board. A power supply board is provided. Each of the main control board and the payout control board is equipped with a CPU, and this CPU has a power supply (5 V) used during normal operation and when the power supply is interrupted for some reason. A backup power supply (5 V) for maintaining the stored contents of the RAM built in the CPU is separately supplied.

JP 2009-000435 A

  By the way, the gaming machine as described above has the following problems. That is, the CPU is separately supplied with power (5 V) and backup power (5 V) used during normal operation, and the current values and wiring of the power (5 V) and backup power (5 V) used during normal operation. The length is also different. Therefore, there is a problem in that the voltages of both power sources vary greatly, which causes a malfunction of the CPU.

  In view of the above problems, an object of the present invention is to provide a gaming machine that can reduce malfunction of a CPU.

  The object of the present invention is achieved by the following means. In addition, although the code | symbol in a parenthesis attaches the referential mark of embodiment mentioned later, this invention is not limited to this.

According to the first aspect of the present invention, the main control unit (main control board 60) that comprehensively controls gaming operations and the power supply unit (power supply board 50) that receives the AC voltage (AC24V) and generates a plurality of types of DC voltages. A gaming machine (1) having
The main control unit (main control board 60) is provided with a one-chip microcomputer including a CPU (main control CPU 600), a ROM (main control ROM 601), and a RAM (main control RAM 602).
The power supply unit (power supply board 50) generates a main power supply (DC12V, VCC5V) used for the operation of the one-chip microcomputer provided in the main control part (main control board 60), and A backup power supply (VBB) for maintaining the storage contents of the RAM (main control RAM 602) even when the main power supply (DC12V, VCC5V) supplied to the control unit (main control board 60) is shut off is generated.
The main power supply (DC12V, VCC5V) and backup power supply (VBB) generated by the power supply section (power supply board 50) are supplied to the main control section (main control board 60),
The main power supply (VCC5V) generated by converting the supplied main power supply (VCC5V) or the supplied main power supply (DC12V) into a different voltage and the supplied backup power supply (VBB) are the one chip. Supplied to the microcomputer,
The main power supply (VCC5V) power line supplied to the one-chip microcomputer or the main conversion power supply (VCC5V) power line supplied to the one-chip microcomputer and the backup power supply (VBB) supplied to the one-chip microcomputer. ) Is connected to the power line of the diode (D30),
The diode (D30) varies between the voltage of the main power supply (VCC5V) or main conversion power supply (VCC5V) supplied to the one-chip microcomputer and the voltage of the backup power supply (VBB) supplied to the one-chip microcomputer. In order to reduce the power consumption, the power line of the main power supply (VCC5V) supplied to the one-chip microcomputer or the power supply line of the main conversion power supply (VCC5V) supplied to the one-chip microcomputer so as to satisfy the following formula 1 It is characterized in that it is connected to a power supply line of a backup power supply (VBB) supplied to a one-chip microcomputer.
(Equation 1)
L1> L2
In Formula 1, L1 is the value of the backup power supply (VBB) from the input terminal of the backup power supply (VBB) supplied from the power supply section (power supply board 50) provided in the main control section (main control board 60). Indicates the distance to the connection point (P) of the diode (D30) connected to the power supply line. L2 is the input of the backup power supply (VBB) from the connection point (P) of the diode (D30). It shows the distance to the input terminal of the chip microcomputer.

  According to the present invention, CPU malfunction can be reduced.

It is a perspective view which shows the external appearance of the game machine which concerns on one Embodiment of this invention. It is a front view of the game board of the gaming machine according to the embodiment. It is a block diagram which shows the control apparatus of the game machine which concerns on the same embodiment. FIG. 4 is a circuit diagram illustrating a circuit configuration of a part (mainly a voltage generation unit and a voltage protection unit) of the power supply substrate illustrated in FIG. 3. FIG. 4 is a circuit diagram showing a circuit configuration of a part (mainly a voltage monitoring unit and a system reset generation unit) of the power supply board shown in FIG. 3. It is a circuit diagram which shows the circuit structure of the main control board shown in FIG. FIG. 4 is a partial longitudinal sectional view of a main control board and a payout control board shown in FIG. 3. FIG. 4 is a circuit diagram showing a circuit configuration of a payout control board shown in FIG. 3. It is a flowchart figure explaining the main process of the main control which concerns on one Embodiment of this invention. It is a flowchart explaining the timer interruption process of the main control which concerns on the same embodiment. It is a flowchart figure explaining the processing content of the voltage monitoring process of the timer interruption process shown in FIG.

  Hereinafter, an embodiment of a gaming machine according to the present invention will be specifically described with reference to FIGS. 1 to 11, taking a pachinko gaming machine as an example. First, the external configuration of the pachinko gaming machine according to the present embodiment will be described with reference to FIGS.

  As shown in FIG. 1, a pachinko gaming machine 1 has a rectangular front frame 3 attached to the front surface of a wooden outer frame 2 so that it can be opened and closed, and a game board storage frame (see FIG. 1) attached to the back surface of the front frame 3. (Not shown) in which the game board 4 is mounted. The game board 4 is mounted with the game area 40 shown in FIG. 2 facing the front, and a glass door frame 5 supporting transparent glass is provided on the front side of the game area 40 as shown in FIG. . The game area 40 is an area surrounded by a ball guide rail 6 (see FIG. 2) disposed on the surface of the game board 4.

  On the other hand, as shown in FIG. 1, the pachinko gaming machine 1 is provided with a front operation panel 7 below the glass door frame 5, and the front operation panel 7 is provided with an upper tray unit 8. The unit 8 is integrally formed with an upper tray 9 for storing discharged game balls. Further, the front operation panel 7 is provided with a ball lending button 11 and a prepaid card discharge button 12 (card return button 12). A push button type effect button device 13 that can change the effect by pressing when a built-in lamp (not shown) is lit is provided on the upper plate surface portion of the upper tray 9. Further, the upper tray 9 is provided with a ball removal button 14 for pulling downward the game balls stored in the upper tray 9.

  On the other hand, as shown in FIG. 1, a launch handle 15 for operating the launch unit is provided on the right end side of the front operation panel 7, and BGM (Background music) is provided on both upper side surfaces of the front frame 3. ) Or a speaker 16 that emits sound effects. An electric lamp such as an LED lamp is disposed on the peripheral frame of the front frame 3.

  On the other hand, in the game area 40 of the game board 4, as shown in FIG. 2, a liquid crystal display device 41 made up of an LCD (Liquid Crystal Display) or the like is disposed at a substantially central portion. The liquid crystal display device 41 divides a display area into three areas, left, middle, and right, and can independently display a variable number, character, or design (decorative design).

  On the other hand, a special symbol start port 42 is disposed directly below the liquid crystal display device 41, and a special symbol start port switch (see FIG. 3) for detecting a winning ball is provided therein. A special winning opening 43 is provided on the right side of the special symbol starting opening 42, and a large winning opening switch (see FIG. 3) for detecting a winning ball is provided therein.

  On the other hand, a normal symbol start port 44 composed of a gate is disposed in the upper right part of the liquid crystal display device 41, and a normal symbol start port switch (see FIG. 3) for detecting the passage of a game ball is provided therein. It has been. Further, on the right side of the special winning opening 43 and the left side of the special symbol starting opening 42, general winning openings 45 are respectively arranged (in the drawing, one on the right side and three on the left side). Each is provided with a general winning opening switch (see FIG. 3) for detecting the passage of the game ball.

  Further, a special symbol display device 46 configured by arranging seven segments in three digits and a normal symbol display device 47 composed of two LEDs are provided at the lower right peripheral edge of the game area 40 of the game board 4. Yes. Further, a plurality of game nails (not shown) are arranged in the game area 40 of the game board 4, and a windmill 48 as a game ball drop direction changing member is arranged.

  Next, a control device that performs electronic control according to the progress of the game provided in the pachinko gaming machine 1 having the above-described external configuration will be described with reference to FIG. As shown in FIG. 3, the control device includes a power supply board 50 that receives an AC voltage AC24V, which is an external power supply supplied from a transformer (not shown) installed in a game store, and generates a plurality of types of DC voltages, A main control board 60 that controls the overall operation, a payout control board 70 that pays out a game ball based on a control command from the main control board 60, and an effect process in response to the control command from the main control board 60 This is mainly composed of an effect control board 80 to be performed. The production control board 80 receives the control command from the main control board 60 via the production I / F board 90.

  As shown in FIG. 3, the power supply board 50 includes a voltage generation unit 500, a voltage monitoring unit 510, and a system reset generation unit 520. The voltage generation unit 500 generates an AC voltage AC24V, which is an external power source supplied from a transformer (not shown) installed in a game store, and generates a plurality of types of DC voltages. Of the generated DC voltage, DC12V and backup power supply VBB are supplied to the payout control board 70, and DC12V, DC32V and backup power supply VBB are supplied to the main control board 60. Further, DC5V, DC12V, DC15V and DC32V are supplied to the effect I / F board 90. Note that the external power supply AC24V is supplied to the payout control board 70 via the power supply board 50.

  On the other hand, the voltage monitoring unit 510 monitors the voltage of the AC voltage AC24V and the DC voltage DC12V. When these voltages are cut off or a power failure occurs, a voltage abnormality signal ALARM ( 5) is output to the payout control board 70 and the main control board 60. The voltage abnormality signal ALARM outputs an “L” level signal when the voltage is abnormal, and outputs an “H” level signal when it is normal.

  On the other hand, the system reset generation unit 520 generates a reset signal, and outputs the generated reset signal to the payout control board 70, the main control board 60, and the effect I / F board 90.

  On the other hand, the main control board 60 is connected to each game component of the game board 4 via the game board relay board 100, whereby each start port 42, 44 and each prize-winning port 43, 45 on the game board 4 are connected. While receiving a switch signal provided in the game machine, a solenoid drive signal for driving solenoids such as the big prize opening 43 is transmitted to the game board relay board 100.

  When the main control board 60 receives a switch signal from each of the winning ports 43 and 45, the main control board 60 determines how many game balls are to be paid out to the player, and uses the determined information as the payout control command PAY_CMD (FIG. 6). On the other hand, from the payout control board 70, a prize ball count signal indicating a payout operation of the game ball and a status signal STAY_SIGNAL (see FIG. 6) relating to an abnormality in the payout operation are received. Note that the status signal STAY_SIGNAL includes, for example, an out-of-supply signal, an insufficient payout error signal, and a lower plate full signal.

  Further, when the main control board 60 receives the switch signal from each of the start ports 42 and 44, the main control board 60 generates a special gaming state advantageous to the player (so-called “winning”) or special advantageous to the player. A lottery of whether or not to generate a gaming state (so-called “losing”) is performed, and the variation pattern of the special symbol, the display pattern of the stop symbol or the normal symbol is determined according to the success / failure information which is the lottery result, and the determined information is It is transmitted to the special symbol display device 46 or the normal symbol display device 47. As a result, the lottery result is displayed on the special symbol display device 46 or the normal symbol display device 47. Further, the main control board 60 generates an effect control command DI_CMD (see FIG. 6) including the determined information, and transmits it to the effect I / F board 90. The main control board 60 supplies the game board relay board 100 with the DC voltage DC32V supplied from the power supply board 50.

  On the other hand, the payout control board 70 receives the payout control command PAY_CMD (see FIG. 8) from the main control board 60, and based on the received payout control command PAY_CMD (see FIG. 8), the payout motor signal MOT_SIGNAL (FIG. 8). The payout motor M is controlled by the generated payout motor signal MOT_SIGNAL to pay out the game ball to the player. Further, the payout control board 70 transmits a prize ball counting signal indicating the payout operation of the game ball and a status signal STAY_SIGNAL (see FIG. 8) relating to the abnormality of the payout operation, and plays the game ball in response to the player's operation. A firing control signal FI_SIGNAL (see FIG. 8) for starting or stopping the operation of the firing control board 110 to be fired is transmitted. The payout control board 70 supplies the AC voltage AC24V supplied from the power supply board 50 to the launch control board 110.

  The effect control board 80 is mounted with a one-chip microcomputer (not shown) including ROM, RAM, and CPU, and the effect control transmitted from the main control board 60 via the effect I / F board 90. Based on the command DI_CMD (see FIG. 6), a signal for realizing the effect by the light by driving and controlling the electric lamp such as the LED lamp disposed in the peripheral frame of the front frame 3 is the effect I / F. A process of transmitting to the electric lamp substrate 120 through the substrate 90 is performed. Further, the effect control board 80 sends a signal for realizing a sound effect by driving the speaker 16 based on the effect control command DI_CMD (see FIG. 6) via the effect I / F board 90. The process which transmits to 16 is performed. In addition, the effect control board 80 controls the liquid crystal control board 130 based on the effect control command DI_CMD (see FIG. 6) and outputs a signal for realizing the image effect by the liquid crystal display device 41. The process which transmits to the liquid crystal control board 130 via this is performed. The liquid crystal control board 130 stores various image data for displaying an image according to the contents of the effect, and further includes a VDP (Video Display Processor) that controls the overall effect output. Although not shown, each DC voltage supplied to the production I / F board 90 is supplied to each of the boards 80, 120, and 130.

  Here, the power supply board 50, the main control board 60, and the payout control board 70, which are the features of the present invention, will be described in more detail with reference to FIGS. First, the power supply substrate 50 will be described with reference to FIGS. 4 and 5.

<Power supply board 50>
4 and 5 are circuit diagrams showing the circuit configuration of the power supply board 50. FIG. 4 mainly shows the voltage generation unit 500, and FIG. 5 mainly shows the voltage monitoring unit 510 and the system reset generation unit 520. ing.

  As shown in FIG. 4, the voltage generator 500 outputs an AC voltage AC24V to the payout control board 70 via the fuse FU1, and includes a full-wave rectifier circuit including diodes D1 to D4 and smoothing capacitors C1 to C2. A DC voltage DC32V is generated from the AC voltage AC24V, and the generated DC voltage DC32V is output to the main control board 60 and the effect I / F board 90 via the fuse FU2. Further, the voltage generator 500 includes a main control CPU 600 (described later with reference to FIG. 6) from an AC voltage AC24V by a full-wave rectifier circuit including diodes D1, D2, D5, and D6, smoothing capacitors C3 to C5, and a DC-DC converter 500a. ) And the payout control CPU 700 (see FIG. 8), a DC voltage DC12V, which is a main power source used for the operation, is generated, and the generated DC voltage DC12V (main power supply) is generated as the payout control board 70, the main control board 60, and the effect I. / F substrate 90, while the full-wave rectifier circuit using diodes D1, D2, D5, and D6, smoothing capacitors C3 to C5, and reference voltage generator 500b and reference voltage used by voltage monitor 510 Vref (5 V) is generated. Note that the reference voltage generation unit 500b can continue to supply a constant voltage even if the supply of the AC voltage AC24V is interrupted for some reason.

  Furthermore, the voltage generator 500 generates the DC voltage DC15V from the AC voltage AC24V by the full-wave rectifier circuit using the diodes D1, D2, D7, and D8, the smoothing capacitors C6 to C7, and the DC-DC converter 500c. While outputting to the I / F board 90, the DC voltage DC5V is generated from the AC voltage AC24V by the full-wave rectifier circuit using the diodes D1, D2, D7, and D8, the smoothing capacitors C6 to C7, and the DC-DC converter 500d. And output to the production I / F board 90. Further, a parallel circuit of a diode D9 and storage capacitors C8 and C9 is connected to the generated DC voltage DC5V, and is output to the payout control board 70 and the main control board 60 as a backup power supply VBB (DC5V). As a result, even if the AC voltage AC24V is not supplied due to some abnormality and the DC voltage DC5V is not generated, the voltage stored in the storage capacitors C8 and C9 is discharged, so that the backup power supply VBB (DC5V) for a predetermined time is discharged. Can be supplied to the payout control board 70 and the main control board 60.

  On the other hand, as shown in FIG. 4, the power supply substrate 50 has a voltage protection unit 501, which cuts off the ground line when receiving an excessive AC voltage (for example, AC 100 V). is there. Specifically, the voltage protection unit 501 includes a rectifying unit 501a that generates a DC voltage of a predetermined level from the AC voltage AC24V, an AC monitoring unit 501b that is turned on when the AC power supply lines LN1 and LN2 are overvoltage, and an AC monitoring unit 501b. And a switch circuit 501c that performs an OFF operation corresponding to the ON operation.

  The rectifying unit 501a is configured by connecting in parallel a diode D10 that receives an AC voltage from the AC power supply line LN2, a current limiting resistor R1, a capacitor C10, and a Zener diode ZD1. As a result, during normal operation, the voltage across the capacitor C10 is made constant by the Zener diode ZD1.

  The AC monitoring unit 501b includes two diodes D11 and D12 connected to the AC power supply lines LN1 and LN2, a Zener diode ZD2 connected to a connection point of the diodes D11 and D12, bias resistors R2 and R3, and a capacitor. A parallel circuit of C11, a transistor Q1 that is turned on when the voltage across the bias resistor R3 increases, and a current limiting resistor R4 of the transistor Q1 are configured.

  The switch circuit 501c includes a MOS transistor Q2 corresponding to a large current capacity and a bias resistor R5 connected in parallel to the capacitor C10. The transistor Q2 is in an ON state as long as the voltage across the capacitor C10 is at a predetermined level, and connects the ground lines of all the circuits of the gaming machine and the frame ground FG.

  Thus, the Zener diode ZD2 of the voltage protection unit 501 configured as described above is normally in an OFF state, but is in a breakdown state when an excessive AC voltage (for example, AC100V) is applied to the AC power supply lines LN1 and LN2. . In this breakdown state, the voltage across the bias resistor R3 increases, the transistor Q1 is turned on, and the voltage across the capacitor C10 drops. As a result, the MOS transistor Q2 transitions from the ON state to the OFF state, the circuit ground and the frame ground FG are disconnected, and all the power supply voltages of the gaming machine 1 are cut off.

  On the other hand, FIG. 5 shows a voltage monitoring unit 510, which has comparators A1 to A3. In the comparator A1, the input voltage Vin1 is supplied to the plus terminal, the input voltage Vin2 is supplied to the minus terminal, and the capacitor Cs is connected between the input terminals. The input voltage Vin1 is supplied with a low voltage of the voltage Vs and the output voltage Vo2 of the comparator A2. The input voltage Vin2 is supplied with the reference voltage Vref (5V) generated by the voltage generator 500. Is divided and supplied by resistors R10 and R11. The voltage Vs is generated by a parallel circuit of a resistor R12, a capacitor C20, a resistor R13, and a Zener diode ZD10 at the connection point of the two diodes D20, D21 connected to the AC power supply lines LN1, LN2, and the diodes D20, D21. It is generated by being connected. The output voltage Vo1 is output from the comparator A1 supplied with such an input voltage.

  On the other hand, in the comparator A2, the DC voltage DC12V (main power source) generated by the voltage generator 500 is supplied to the plus terminal, and the input voltage Vin2 is supplied to the minus terminal. The output voltage Vo2 is output from the comparator A2 supplied with such an input voltage, and this output voltage Vo2 is fed back to the positive terminal side of the comparator A1 via the diode D22. Thus, by providing the diode D22 at the output terminal of the comparator A2, it is possible to prevent a voltage higher than a predetermined voltage (5V) from being fed back to the positive terminal side of the comparator A1.

  On the other hand, in the comparator A3, the input voltage Vin2 is supplied to the plus terminal, and the output voltage Vo1 is supplied to the minus terminal. The output voltage Vo3 is output from the comparator A3 supplied with such an input voltage, and this output voltage Vo3 is supplied to the base side of the transistor Q10 via the pull-up resistor R14. A parallel circuit composed of a capacitor C21 and a resistor R15 is connected to the output voltage Vo3. Thus, by connecting the parallel circuit composed of the capacitor C21 and the resistor R15, the parallel circuit serves as a low-pass filter, and it is possible to prevent the transistor Q10 from malfunctioning due to noise or the like.

  The operation of the voltage monitoring unit 510 configured as described above will be described as follows. That is, when the AC voltage AC24V is stably supplied (normal time), the DC voltage DC12V (main power) generated from the AC voltage AC24V by the voltage generator 500 is supplied to the positive terminal of the comparator A2. The divided voltage (about 2.5 V) of the reference voltage Vref (5 V) generated by the voltage generator 500 is supplied to the minus terminal as the input voltage Vin2. Therefore, since the voltage supplied to the plus terminal is higher than the voltage supplied to the minus terminal, the output voltage Vo2 (about 5 V) of “H” level is output from the comparator A2. The positive voltage of the comparator A2 is supplied with the output voltage Vo2 (about 5V), which is the lower of the voltage Vs (about 32V) generated from the AC voltage AC24V and the output voltage Vo2 (about 5V), as the input voltage Vin1. Then, the input voltage Vin2 of about 2.5V is supplied to the minus terminal. Therefore, since the voltage supplied to the plus terminal is higher than the voltage supplied to the minus terminal, the comparator A1 outputs the output voltage Vo1 (about 5 V) at the “H” level. Then, the “H” level output voltage Vo1 (about 5 V) is output to the main control board 60 and the payout control board 70 as the voltage abnormality signal ALARM via the pull-up resistor R16.

  Further, the input voltage Vin2 of about 2.5V is supplied to the plus terminal of the comparator A3, and the output voltage Vo1 (about 5V) of “H” level is supplied to the minus terminal. Therefore, since the voltage supplied to the minus terminal is higher than the voltage supplied to the plus terminal, the output voltage Vo3 of “L” level is output from the comparator A3. As a result, the transistor Q10 is turned off, and the output voltage Vo2 fed back never becomes 0V.

  On the other hand, when the supply of the AC voltage AC24V is interrupted for some reason (when abnormal), the voltage Vs gradually decreases and becomes a voltage lower than the output voltage Vo2 after a predetermined period, so that the voltage Vs becomes the input voltage. This is supplied as Vin1 to the plus terminal of the comparator A1. An input voltage Vin2 of about 2.5V is supplied to the negative terminal of the comparator A1. Therefore, since the voltage supplied to the minus terminal is higher than the voltage supplied to the plus terminal, the output voltage Vo1 of “L” level is output from the comparator A1, and the output voltage Vo1 of “L” level is pulled up. The voltage abnormality signal ALARM is output to the main control board 60 and the payout control board 70 via the resistor R16. As described above, the reference voltage Vref (5V) is supplied with a constant voltage (5V) by the reference voltage generator 500b even if the supply of the AC voltage AC24V is interrupted.

  Further, the DC voltage DC12V (main power supply) is supplied to the positive terminal of the comparator A2 if the AC voltage AC24V is stably supplied. However, if the supply of the AC voltage AC24V is interrupted for some reason, Since the DC voltage DC12V (main power supply) is not generated in the voltage generation unit 500, the voltage generation unit 500 eventually becomes 0V, and the voltage of 0V is supplied. An input voltage Vin2 of about 2.5V is supplied to the negative terminal of the comparator A2. Therefore, since the voltage supplied to the minus terminal is higher than the voltage supplied to the plus terminal, the output voltage Vo2 of “L” level is output from the comparator A2, and is fed back to the plus terminal of the comparator A1. . Furthermore, the input voltage Vin2 of about 2.5V is supplied to the plus terminal of the comparator A3, and the “L” level output voltage Vo1 is inputted to the minus terminal. Therefore, since the voltage supplied to the minus terminal is lower than the voltage supplied to the plus terminal, the output voltage Vo3 (5 V) of “H” level is output from the comparator A3. As a result, the transistor Q10 is turned on, and the output voltage Vo2 to be fed back becomes 0V. Therefore, 0V can be reliably supplied to the plus terminal of the comparator A1, and therefore the voltage abnormality signal ALARM can be reliably set to the “L” level signal.

  On the other hand, even if the AC voltage AC24V is stably supplied, if the DC voltage DC12V (main power supply) is interrupted for some reason (when abnormal), a voltage of 0V is supplied to the positive terminal of the comparator A2. Then, the input voltage Vin2 of about 2.5V is supplied to the minus terminal. Therefore, since the voltage supplied to the minus terminal is higher than the voltage supplied to the plus terminal, the output voltage Vo2 of “L” level is output from the comparator A2. Thus, the output voltage Vo2 that is lower than the voltage Vs is supplied to the plus terminal of the comparator A1 as the input voltage Vin1 to the plus terminal of the comparator A1. Further, an input voltage Vin2 of about 2.5V is supplied to the plus terminal of the comparator A1. Therefore, since the voltage supplied to the minus terminal is higher than the voltage supplied to the plus terminal, the output voltage Vo1 of “L” level is output from the comparator A1. Then, the “L” level output voltage Vo1 is output to the main control board 60 and the payout control board 70 as the voltage abnormality signal ALARM via the pull-up resistor R16.

  Further, an input voltage Vin2 of about 2.5 V is supplied to the plus terminal of the comparator A3, and an output voltage Vo1 of “L” level is supplied to the minus terminal. Therefore, since the voltage supplied to the minus terminal is lower than the voltage supplied to the plus terminal, the output voltage Vo3 (5 V) of “H” level is output from the comparator A3. As a result, the transistor Q10 is turned on, and the output voltage Vo2 to be fed back becomes 0V. Therefore, 0V can be reliably supplied to the plus terminal of the comparator A1, and therefore the voltage abnormality signal ALARM can be reliably set to the “L” level signal.

  Therefore, as described above, the voltage monitoring unit 510 normally outputs an “H” level signal as the voltage abnormality signal ALARM from the output of the comparator A1, but at the time of abnormality (the AC voltage AC24V and / or When the DC voltage DC12V (main power supply is interrupted), an “L” level signal is output as the voltage abnormality signal ALARM from the output of the comparator A1.

  On the other hand, FIG. 5 further shows a system reset generation unit 520, and this system reset generation unit 520 includes a comparator A4. In the comparator A4, the input voltage Vin3 is supplied to the plus terminal, and the input voltage Vin2 is supplied to the minus terminal. The input voltage Vin3 is connected to the output voltage Vo1 in a series circuit of a diode D23 and a resistor R18. A diode D24 is connected in parallel to both ends of the resistor R18. The resistor R18, the resistor R17, the storage capacitor C22, It is generated by connecting the closed circuit formed by Then, the output voltage Vo4 is output from the comparator A4 supplied with such an input voltage, and this output voltage Vo4 is used as the system reset signal SYS_RST as the main control board 60, the payout control board 70, and the effect I / F board 90. Will be output. The output voltage Vo3 is connected to the output voltage Vo3 of the comparator A3 via the diode D24, and further to the reference voltage Vref (5V).

  The operation of the system reset generation unit 520 configured as described above will be described as follows. That is, during normal time (a state where the AC voltage AC24 and the DC voltage DC12V (main power supply) are stably supplied), the comparator A1 of the voltage monitoring unit 510 outputs the output voltage Vo1 (5V) of “H” level. The output voltage Vin3 of about 5V is supplied to the plus terminal of the comparator A4. An input voltage Vin2 of about 2.5V is supplied to the negative terminal of the comparator A4. Therefore, since the voltage supplied to the minus terminal is lower than the voltage supplied to the plus terminal, the output voltage Vo4 (5 V) of “H” level is output from the comparator A4. As a result, an “H” level signal is output as the system reset signal SYS_RST.

  On the other hand, at the time of abnormality (the AC voltage AC24 and / or the DC voltage DC12V (main power supply) is cut off), the comparator A1 of the voltage monitoring unit 510 outputs the “L” level output voltage Vo1. The “L” level voltage is supplied to the positive terminal of the comparator A4 as the input voltage Vin3. An input voltage Vin2 of about 2.5V is supplied to the negative terminal of the comparator A4. Therefore, since the voltage supplied to the minus terminal is higher than the voltage supplied to the plus terminal, the output voltage Vo4 of “L” level is output from the comparator A4. As a result, an “L” level signal is output as the system reset signal SYS_RST.

  Thus, as described above, the system reset generation unit 520 normally outputs an “H” level signal from the output of the comparator A4 as the system reset signal SYS_RST, but at an abnormal time (the AC voltage AC24V and / or Or, when the DC voltage DC12V (main power supply is interrupted), an “L” level signal is output as the system reset signal SYS_RST from the output of the comparator A4. The timing at which the system reset signal SYS_RST transitions from the “H” level to the “L” level is the time when the voltage abnormality signal ALARM is changed from the “H” level because the storage capacitor C22 is connected to the plus terminal of the comparator A4. The transition is made later than the timing of transition to the “L” level. That is, when the “L” level output voltage Vo1 is output from the comparator A1 of the voltage monitoring unit 510 described above, the voltage stored in the storage capacitor C22 is discharged, so that the voltage of the input voltage Vin3 gradually decreases to “L”. ”Level voltage. Therefore, the timing at which the system reset signal SYS_RST transitions from the “H” level to the “L” level transitions later than the timing at which the voltage abnormality signal ALARM transitions from the “H” level to the “L” level. Thus, the timing at which the system reset signal SYS_RST transitions from the “H” level to the “L” level is delayed from the timing at which the voltage abnormality signal ALARM transitions from the “H” level to the “L” level. This is to provide a period for performing backup processing of data stored in a main control RAM 602 (see FIG. 6) and a payout control RAM 702 (see FIG. 8) which will be described later.

  On the other hand, in FIG. 5, a switch SW operated by an attendant is provided, and a value corresponding to the ON / OFF state of the switch SW is output to the main control board 60 and the payout control board 70 as a RAM clear signal RAM_CLR. ing. The RAM clear signal RAM_CLR is a signal that determines whether or not to initialize all areas of a main control RAM 602 (see FIG. 6) and a payout control RAM 702 (see FIG. 8), which will be described later. In the present embodiment, the switch SW is provided on the power supply board 50. However, the switch SW may be provided on the main control board 60 and / or the payout control board 70.

<Main control board 60>
Next, the main control board 60 will be described with reference to FIGS.

  FIG. 6 is a circuit diagram showing a circuit configuration of the main control board 60. As shown in FIG. 6, the main control board 60 stores a main control CPU 600, a control program describing a series of game control procedures, and the like. A one-chip microcomputer including a main control ROM 601 and a main control RAM 602 that functions as a work area, a buffer memory, and the like is mounted. The DC voltage DC12V (main power supply) generated by the power supply board 50 is converted from the DC voltage DC12V (main power supply) to the DC voltage VCC5V as the main conversion power supply by the regulator 611 through the noise filter 610 that removes noise. The converted DC voltage VCC5V (main conversion power supply) is supplied to the VDD terminal built in the main control CPU 600.

  Further, the backup power supply VBB (DC5V) generated by the power supply board 50 is supplied to the VBB terminal built in the main control CPU 600 via a noise filter 612 for removing noise and a resistor R20. Yes. A diode D30 is connected between the power line of the DC voltage VCC5V (main conversion power supply) converted from the DC voltage DC12V (main power supply) and the power supply line of the backup power supply VBB (DC5V).

  As described above, the diode D30 is connected between the power supply line of the DC voltage VCC5V (main conversion power supply) converted from the DC voltage DC12V (main power supply) and the power supply line of the backup power supply VBB (DC5V). This is because of the reason. That is, as shown in FIG. 6, the DC voltage VCC5V (main conversion power supply) and the backup power supply VBB (DC5V) are supplied separately, and therefore the wiring lengths are different. Further, the current consumption of the DC voltage VCC5V (main conversion power supply) in the main control CPU 600 in the normal state (a state where the AC voltage AC24 and the DC voltage DC12V (main power supply) are stably supplied) is 140 mA at maximum. The current consumption of the backup power supply VBB (DC5V) is 3 mA at the maximum, and the DC voltage VCC5V (main conversion power supply) in the main control CPU 600 at the time of abnormality (the AC voltage AC24 and / or DC voltage DC12V (main power supply) is cut off). ) Is 0 mA, and the current consumption of the backup power supply VBB (DC5V) is 20 μA at the maximum, so the current values are different. Therefore, since the wiring length is different and the current value is different, both voltages may vary greatly. Therefore, if the diode D30 is connected between the power supply line of the DC voltage VCC5V (main conversion power supply) and the power supply line of the backup power supply VBB (DC5V), the DC voltage VCC5V (main conversion power supply) varies and the backup power supply VBB ( DC5V) also fluctuates, and therefore, both voltages do not vary greatly. Therefore, the diode D30 is connected between the power supply line of the DC voltage VCC5V (main conversion power supply) and the power supply line of the backup power supply VBB (DC5V).

  As shown in FIG. 6, the diode D30 has an anode terminal connected to a power supply line of a DC voltage VCC5V (main conversion power supply) and a cathode terminal connected to a power supply line of a backup power supply VBB (DC5V). By connecting in this way, the current of the backup power supply VBB (DC5V) does not flow back to the DC voltage VCC5V (main conversion power supply), so that it is possible to prevent a situation that affects the normal operation of the main control CPU 600.

  Furthermore, as shown in FIG. 6, the diode D30 is connected between the power supply line of the DC voltage VCC5V (main conversion power supply) and the power supply line of the backup power supply VBB (DC5V) so as to satisfy L1> L2. L1 indicates the distance from the input terminal of the backup power supply VBB (DC5V) supplied from the power supply board 50 to the connection point P of the diode D30 connected to the power supply line of the backup power supply VBB (DC5V), and L2 is The distance from the connection point P to the VBB terminal built in the main control CPU 600 is shown. Thus, if the diode D30 is connected between the power supply line of the DC voltage VCC5V (main conversion power supply) and the power supply line of the backup power supply VBB (DC5V) so as to satisfy L1> L2, variations in both voltages are further reduced. Can be made.

  Furthermore, the diode D30 is disposed on the main control board 60 as shown in FIG. That is, as shown in FIG. 7, the main control board 60 includes an insulating layer 60a made of resin or the like, a component surface 60b formed on the upper surface of the insulating layer 60a, and a solder formed on the lower surface of the insulating layer 60a. It is comprised by the surface 60c. A plurality of through holes 60d are formed in the main control board 60, and an inner wall surface of the through holes 60d is plated with copper or the like 60e. The power supply line of the backup power supply VBB (DC5V) is wired to the component surface 60b of the main control board 60 formed in this way, and the power supply line of the DC voltage VCC5V (main conversion power supply) is connected to the solder surface 60c of the main control board 60. Is wired. When connecting the diode D30 between the power supply line of the backup power supply VBB (DC5V) and the power supply line of the DC voltage VCC5V (main conversion power supply) thus wired, a pair of the diode D30 is inserted into the through hole 60d. Leg portions D30a and D30a are respectively inserted, and the leg portions D30a and D30a are soldered 61 to the solder surface 60c, whereby a power supply line for the backup power supply VBB (DC5V) and a power supply line for the DC voltage VCC5V (main conversion power supply) A diode D30 is connected between the two. Thus, if the diode D30 is connected between the power supply line of the backup power supply VBB (DC5V) and the power supply line of the DC voltage VCC5V (main conversion power supply), the impedance is reduced. Can be reduced.

  On the other hand, as shown in FIG. 6, the system reset signal SYS_RST output from the power supply board 50 includes a pull-up resistor R21, an RC circuit including a resistor R22 and a capacitor C30, two Schmitt triggers ST1 and ST2, An up resistor R23 is connected to the SYS_RST terminal built in the main control CPU 600. The voltage abnormality signal ALARM output from the power supply board 50 is connected to the RC circuit of the pull-up resistor R24, the resistor R25 and the capacitor C31, and the Schmitt trigger ST3, and is built in the main control CPU 600. Connected to ALARM terminal. When this voltage abnormality signal ALARM transitions from the “H” level to the “L” level, a backup process of data stored in the main control RAM 602 is performed as described later. When the data stored in the main control RAM 602 is backed up, the stored contents in the main control RAM 602 must be maintained. As a power source for maintaining the stored contents, a backup power supply VBB (DC5V ) Is supplied.

  The RAM clear signal RAM_CLR output from the power supply substrate 50 is connected to the pull-up resistor R26, the RC circuit of the resistor R27 and the capacitor C32, and the Schmitt trigger ST4, and is built in the main control CPU 600. It is connected to the RAM_CLR terminal.

  On the other hand, the main control CPU 600 has a built-in CLK terminal, and a crystal oscillator 613 for generating a clock is connected to the CLK terminal. As shown in FIG. 6, the crystal oscillator 613 is arranged on the main control board 60 at a position separated from the diode D30. As described above, if the crystal oscillator 613 and the diode D30 are arranged at a distance from each other, it is possible to reduce the mixing of noise into the backup power supply VBB (DC5V) and the DC voltage VCC5V (main conversion power supply). The separation distance is preferably about 15 mm. In addition, although there are data buses and address buses (not shown) that are likely to generate noise, it is preferable that they are separated from the data buses and address buses that are such noise sources.

  Further, although not shown in the figure, the power supply line of the backup power supply VBB (DC5V) and the DC voltage VCC5V (main conversion power supply) disposed on the main control board 60 and the clock line of the crystal oscillator 613 are generated from the clock lines. In order to reduce the situation where noise is mixed into the power supply line, it is preferable that at least a part of the power supply line and the clock line are not arranged in parallel. In addition, it is preferable to form a ground pattern around the power supply line in order to reduce noise contamination.

  On the other hand, as shown in FIG. 6, the main control board 60 receives the switch signals of the winning ports 43 and 45 and the start ports 42 and 44 (see FIG. 2) from the game board relay board 100 (see FIG. 3). To do. This switch signal is input to the switch monitoring unit 614 via the pull-up resistor R28 of the DC voltage DC12V (main power supply), and the switch monitoring unit 614 receiving the input receives the switch signal from the DC voltage DC12V (main power supply). The switch signal is input to the main control CPU 600 via the pull-up resistor R29 of the DC voltage VCC5V (main conversion power supply) after being converted to the DC voltage DC5V and confirming whether or not the switch signal is disconnected.

  On the other hand, the main control CPU 600 receives the switch signal and transmits a solenoid drive signal for driving solenoids such as the big prize opening 43 to the game board relay board 100, and the switch signal from each of the winning openings 43 and 45. Is received, it is determined how many game balls are to be paid out to the player, and the determined information is transmitted to the payout control board 70 as a payout control command PAY_CMD. Further, when the main control CPU 600 receives the switch signal from each of the start ports 42 and 44, the main control CPU 600 generates a special game state advantageous to the player (so-called “winning”) or special game advantageous to the player. A lottery of whether or not to generate a state (so-called “losing”) is performed, and the fluctuation pattern of special symbols, display contents of stop symbols or normal symbols are determined according to the success / failure information as the lottery results, and the lottery results are displayed as special symbols. The data is transmitted to the display device 46 or the normal symbol display device 47. Further, main control CPU 600 generates an effect control command DI_CMD including the determined information and transmits it to effect I / F board 90. Meanwhile, the main control CPU 600 receives a prize ball counting signal indicating a game ball payout operation and a status signal STAY_SIGNAL related to an abnormality in the payout operation from the payout control board 70.

  On the other hand, as shown in FIG. 6, the DC voltage DC32V generated by the power supply board 50 is supplied to the main control board 60, and the DC voltage DC32V is passed through a parallel circuit including a capacitor C33 and a resistor R30. It is output to the game board relay board 100. The output voltage is used as a voltage when driving solenoids such as the big prize opening 43.

<Discharge control board 70>
Next, the payout control board 70 will be described with reference to FIG. FIG. 8 is a circuit diagram showing the circuit configuration of the payout control board 70, and there is an overlap with the circuit configuration of the main control board 60. Therefore, the same reference numerals are given to the same configurations as those of the main control board 60. A description will be omitted.

  As shown in FIG. 8, the payout control board 70 includes a payout control CPU 700, a payout control ROM 701 that stores a control program and the like, and a payout control RAM 702 that functions as a work area, a buffer memory, and the like. It is equipped with a chip microcomputer. As with the main control CPU 600 described above, the payout control CPU 700 includes a DC voltage VCC5V (main conversion power supply) converted from a DC voltage DC12V (main power supply) generated by the power supply board 50, a backup power supply VBB ( The system reset signal SYS_RST, the voltage abnormality signal ALARM, and the RAM clear signal RAM_CLR output from the power supply substrate 50 are connected. Further, the payout control CPU 700 is connected to a crystal oscillator 613 for generating a clock, similarly to the main control CPU 600 described above, and the payout control board 70 is also connected to the main control board 60 shown in FIG. A diode D30 is disposed in the same manner as in FIG.

  Further, the payout control CPU 700 receives the payout control command PAY_CMD transmitted from the main control board 60, generates a payout motor signal MOT_SIGNAL based on the payout control command PAY_CMD, and uses the payout motor signal MOT_SIGNAL generated as the payout motor M. Send to. As a result, the payout motor M operates to pay out the game ball to the player. Further, the payout control CPU 700 transmits a prize ball count signal indicating a payout operation of the game ball and a status signal STAY_SIGNAL relating to an abnormality in the payout operation to the main control board 60, and fires the game ball in response to the player's operation. A launch control signal FI_SIGNAL for starting or stopping the operation of the launch control board 110 is transmitted to the launch control board 110.

  On the other hand, as shown in FIG. 8, the payout control board 70 supplies the AC 24V supplied from the power supply board 50 to the launch control board 110 as it is.

  Next, in order to describe the details of the backup processing described above in detail, an outline of a program stored in the main control ROM 601 of the main control board 60 will be described with reference to FIGS. Note that, since the operation contents of the program stored in the payout control ROM 701 of the payout control board 70 are also common in the basic configuration, only the outline of the program stored in the main control ROM 601 of the main control board 60 is shown. I will explain.

  First, the system reset processing program (main processing) will be described with reference to FIG. The main control CPU 600 first sets itself to an interrupt disabled state (step S1), and initializes register values and the like in the main control CPU 600 (step S2).

  Subsequently, the main control CPU 600 acquires a RAM clear signal RAM_CLR signal and stores it in an internal register (not shown) (step S3). Next, the main control CPU 600 acquires the voltage abnormality signal ALARM twice, checks whether or not the levels of the voltage abnormality signal ALARM acquired twice match, and stores them in an internal register (not shown) ( In step S4), the level of the voltage abnormality signal ALARM is confirmed. If the level of the voltage abnormality signal ALARM is “L” level (step S5: YES), the process returns to step S4, and if the level of the voltage abnormality signal ALARM is “H” level (step S5: NO). The process proceeds to step S6. That is, main control CPU 600 repeats the same processing until voltage abnormality signal ALARM changes to a normal level (ie, “H” level) (steps S5 to S6). This takes into account that the DC voltage VCC5V (main conversion power supply) may not drop even after the process of step S312 shown in FIG. That is, even if the watchdog timer function (not shown) is performed and the main control CPU 600 is reset at the timing when the voltage monitoring process of FIG. It is something that keeps you from going on. If the process proceeds to step S6 and subsequent steps, the data in the main control RAM 602 (the basic data of the checksum calculation and the backup flag BFL updated in step S302) is rewritten, and the data is saved even after power interruption. This is because backup processing (steps S306 to S309) described later is wasted.

  Next, the main control CPU 600 permits data writing to the main control RAM 602 (step S6), and transmits a processing command for causing the liquid crystal display device 41 to display a standby screen on the effect I / F board 90 (step S7). . Then, the main control CPU 600 confirms whether or not a power-on signal (not shown) is transmitted from the payout control board 70. If it is transmitted (step S8: YES), the main control CPU 600 proceeds to the next processing step S9 and transmits. If not (step S8: NO), the process of step S8 is repeated.

  Next, the main control CPU 600 confirms the level of the RAM clear signal RAM_CLR acquired in the process of step S3, and when the RAM clear signal RAM_CLR is in the ON state (step S9: ON), all areas in the main control RAM 602 A process for clearing all of them is performed (step S14).

  On the other hand, when the RAM clear signal RAM_CLR is in the OFF state (step S9: OFF), the main control CPU 600 determines the contents of the backup flag BFL (step S10). The backup flag BFL is data indicating whether or not a voltage monitoring process operation of FIG.

  If this backup flag BFL is in the OFF state (step S10: OFF), the operation of the voltage monitoring process of FIG. 11 described later is not executed, and the main control CPU 600 clears all the areas in the main control RAM 602. Is performed (step S14). On the other hand, if the backup flag BFL is in the ON state (step S10: ON), the operation of the voltage monitoring process of FIG. 11 described later is being executed, so the main control CPU 600 calculates the checksum value. The checksum calculation is performed (step S11). The checksum operation is an 8-bit addition operation for the work area of the main control RAM 602.

  Then, when the checksum value is calculated, the main control CPU 600 compares the calculation result with the stored value at the SUM address in the main control RAM 602 (step S12). Note that the SUM address stores a checksum value by a checksum operation processed in the same manner in the voltage monitoring process (see FIG. 11) executed when the voltage drops (step S309). The stored calculation result is maintained by the backup power supply VBB (DC5V) together with other data stored in the main control RAM 602.

  If the stored value at this SUM address does not match the checksum value calculated in step S11 (step S12: NO), the main control CPU 600 clears all the areas in the main control RAM 602. Perform (step S14). If they match (step S12: YES), the main control CPU 600 performs a process of returning to the gaming operation at the time of power interruption based on the data stored in the main control RAM 602 (step S13).

  Next, after the processing of step S13 and step S14, the main control CPU 600 performs setting of a CTC (Counter Timer Circuit) having a function of creating a pulse output with a constant period and a function of measuring time provided therein. . That is, the main control CPU 600 sets the CTC time constant register so that a timer interrupt is periodically generated every 4 ms (step S15). Then, the main control CPU 600 performs an update process in various random number counters (step S16) in a state where the interrupt to itself is set to the prohibited state (step S16), and then returns to the interrupt enabled state (step S17). S18), processing to return to step S16.

  Next, with reference to FIG. 10, a timer interrupt program started every 4 ms by interrupting the main process described above will be described. When this timer interruption occurs, the voltage monitoring process is immediately executed without saving the register in the main control CPU 600 (step S30). This is because the timing at which the timer interrupt process is started is fixed immediately after step S16. The voltage monitoring process is to determine the level of the voltage abnormality signal ALARM output from the power supply substrate 50. The specific processing contents will be described later.

  Next, when the voltage monitoring process (step S30) ends, the main control CPU 600 performs a timer subtraction process for a timer that manages the time of each gaming operation (step S31). The timer subtracted here is used for managing the opening time of the special winning opening 43 (see FIG. 2) and other game effect times.

  Then, the main control CPU 600 receives ON / OFF signals of various switches including the switches of the winning ports 43 and 45 and the starting ports 42 and 44 (see FIG. 2), and the ON / OFF signal is input to the work area. The level and its rising state are stored (step S32). Thereafter, the main control CPU 600 performs error management processing (step S33). Note that the error management process includes a determination as to whether or not an abnormality has occurred inside the device, such as supply of game balls being stopped or game balls being clogged.

  Next, the main control CPU 600 performs management processing based on the detection signals at the winning ports 43 and 45 and the start ports 42 and 44 (see FIG. 2) (step S34), and then performs normal symbol processing (step S35). . The normal symbol process is a process for determining whether or not to operate an ordinary electric accessory such as an electric tulip.

  Next, the main control CPU 600 performs special symbol processing (step S36). The special symbol process is a process for determining whether or not to operate a special electric accessory such as the special prize opening 43 (see FIG. 2). After such a special symbol process (step S36), a process for turning on the LED managed by the main control board 60 is performed (step S37), and the solenoid for realizing the opening / closing operation of the big prize opening 43 (see FIG. 2) or the like. The driving process is executed (step S38). Thereafter, the main control CPU 600 returns to the interrupt enabled state and finishes the timer interrupt (step S39). As a result, the process returns from the interrupt process routine to the main process (see FIG. 9).

  Next, the voltage monitoring process (see step S30 in FIG. 10) will be described with reference to FIG. In the voltage monitoring process, first, an abnormal voltage signal ALARM output from the power supply board 50 is acquired twice, and it is confirmed whether or not the level of the abnormal voltage signal ALARM acquired twice coincides with the internal register (not shown). (Step S300), and the level of the voltage abnormality signal ALARM is confirmed. If the level of the voltage abnormality signal ALARM is “H” level (step S301: NO), the process proceeds to step S302, and if the level of the voltage abnormality signal ALARM is “L” level (step S301: YES). The process proceeds to step S303.

  If the level of voltage abnormality signal ALARM is “H” level (step S301: NO), main control CPU 600 turns off backup flag BFL (step S302), clears the voltage abnormality confirmation counter to zero, and performs processing. Finish (step S304).

  On the other hand, if the level of voltage abnormality signal ALARM is “H” level (step S301: NO), main control CPU 600 increments (+1) the voltage abnormality confirmation counter (step S303), and the count value of the voltage abnormality confirmation counter It is confirmed whether or not is 2 or more (step S305). If the count value of the voltage abnormality confirmation counter is smaller than 2 (step S305: NO), the process is terminated. If the count value of the voltage abnormality confirmation counter is 2 or more (step S305: YES), the voltage abnormality confirmation counter is set to zero. The backup process is started by performing the clearing process (step S306).

  Next, the main control CPU 600 sets the backup flag BFL to the ON state (step S307), and transmits a power-off command notifying the effect I / F board 90 that the power supply is cut off (step S308). Then, main control CPU 600 performs the same calculation as step S11 of the main process shown in FIG. 9 on the same work area, and ends the backup process by performing a process of storing the calculation result (step S309). ).

  After that, the main control CPU 600 sets data writing to the main control RAM 602 in a prohibited state (step S310) and clears output data of all output ports (step S311). The main control CPU 600 prohibits the timer interruption by the setting process for the CTC and repeats the infinite loop process to wait for the DC voltage to drop (step S312).

  According to the present embodiment described above, malfunctions of the main control CPU 600 mounted on the main control board 60 and the payout control CPU 700 mounted on the payout control board 70 can be reduced.

  In the present embodiment, the power supply board 50 generates the current voltage DC12V as the main power supply, and the main control board 60 and the payout control board 70 use the current voltage DC12V as the main power supply as the main conversion power supply. In the above example, the DC voltage VCC5V is converted into the DC voltage VCC5V and the converted DC voltage VCC5V is supplied to the main control CPU 600 and the payout control CPU 700. The power supply board 50 generates the DC voltage VCC5V as the main power supply, and the power supply board. The DC voltage VCC5V, which is the main power source generated at 50, may be supplied to the main control CPU 600 and the payout control CPU 700. In this embodiment, the backup power supply VBB is supplied to the payout control board 70 and the data in the payout control RAM 702 is backed up. However, the backup power supply VBB is supplied only to the main control board 60 and the payout is made. A configuration in which the backup power supply VBB is not supplied to the control board 70 may be adopted.

1 Pachinko machine 50 Power supply board (Power supply part)
60 Main control board (main control unit)
60d through hole 70 payout control board (payout control unit)
600 Main control CPU (CPU)
602 Main control RAM (RAM)
613 Crystal Oscillator 700 Discharge Control CPU (CPU)
702 Payout control RAM (RAM)
D30 Diode D30a Leg VBB Backup power supply AC24V AC voltage DC12V DC voltage (main power supply)
VCC5V DC voltage (Main power supply, Main conversion power supply)
P Connection point

Claims (1)

A gaming machine having a main control unit that comprehensively controls gaming operations and a power supply unit that receives an AC voltage and generates a plurality of types of DC voltages,
The main control unit is provided with a one-chip microcomputer composed of a CPU, ROM and RAM,
The power supply unit generates a main power supply used for the operation of the one-chip microcomputer provided in the main control unit, and the RAM even when the main power supply supplied to the main control unit is shut off Generate a backup power supply to maintain the memory content of
The main power source and the backup power source generated by the power source unit are supplied to the main control unit,
The supplied main power supply or the main conversion power generated by converting the supplied main power into a different voltage and the supplied backup power are supplied to the one-chip microcomputer.
A diode between a main power supply line supplied to the one-chip microcomputer or a main conversion power supply line supplied to the one-chip microcomputer and a backup power supply line supplied to the one-chip microcomputer. Is connected,
The diode satisfies the following formula 1 in order to reduce the variation between the voltage of the main power supply or main conversion power supply supplied to the one-chip microcomputer and the voltage of the backup power supply supplied to the one-chip microcomputer. Connected between a main power supply line supplied to the one-chip microcomputer or a main conversion power supply line supplied to the one-chip microcomputer and a backup power supply line supplied to the one-chip microcomputer. A gaming machine characterized by being made.
(Equation 1)
L1> L2
(In Formula 1, L1 indicates the distance from the input terminal of the backup power source supplied from the power source unit provided in the main control unit to the connection point of the diode connected to the power source line of the backup power source. , L2 indicates the distance from the connection point of the diode to the input terminal of the one-chip microcomputer to which the backup power supply is input.)

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