JP2013164783A - Load balance circuit, power supply device and load balance control method - Google Patents

Load balance circuit, power supply device and load balance control method Download PDF

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JP2013164783A
JP2013164783A JP2012028306A JP2012028306A JP2013164783A JP 2013164783 A JP2013164783 A JP 2013164783A JP 2012028306 A JP2012028306 A JP 2012028306A JP 2012028306 A JP2012028306 A JP 2012028306A JP 2013164783 A JP2013164783 A JP 2013164783A
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mosfet
power supply
supply circuit
load balance
zener diode
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JP5565883B2 (en
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Satoru Hosaka
悟 保坂
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NEC Computertechno Ltd
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Abstract

PROBLEM TO BE SOLVED: To solve a problem resulting from a variation in electric characteristics of a MOSFET included in a load balance circuit to be connected to a power supply device operating in parallel.SOLUTION: A load balance circuit 1 comprises: a first switching part 3 that includes a first MOSFET to be connected to a power circuit 2 and switches between a conduction state and a non-conduction state of current from the power circuit 2 in accordance with driving voltage; a second switching part 4 that includes a second MOSFET to be connected to the power circuit 2 in parallel with the first MOSFET and switches the non-conduction state to the conduction state when gate voltage increases in excess of Zener voltage of a Zener diode due to transition of the first MOSFET to the conduction state and increase in a current volume to be supplied from the power circuit; and a control part 5 for applying the driving voltage to the first MOSFET and the second MOSFET, and controlling the conduction state of the first switching part 3 and the second switching part 4.

Description

本発明は、並列して動作する電源の負荷バランスを制御する技術に関する。   The present invention relates to a technique for controlling load balance of power supplies operating in parallel.

並列動作する電源では、複数の電源にかかる負荷がバランスよく均等になるよう制御しており、電源を保護するために必須となるＯＲｉｎｇ回路を介して電力供給している。Ｏｒｉｎｇ回路は、活線挿抜時と故障した電源が発生した場合に、正常に動作している電源に対して悪影響を及ぼすような逆流電流の発生を防止する。
並列する電源の制御については、例えば、特許文献１から３に関連する技術が開示されている。特許文献１には、簡易な構造のトランスを用いた電源装置および電源装置の制御情報が開示されている。特許文献２には、並列接続の相手電源装置列が電圧上昇した時に本電源装置側に流れ込む電流によるＦＥＴの破損あるいは電力損失の発生に対して、より簡単な方法で防止する並列運転スイッチング電源装置が開示されている。さらに、特許文献３には、電源電圧の変動によらず、モータの駆動時間を一定にすることができるミラー装置用モータ制御回路が開示されている。 In a power supply that operates in parallel, the load applied to a plurality of power supplies is controlled to be even and balanced, and power is supplied through an ORing circuit that is essential for protecting the power supplies. The ORING circuit prevents the generation of a backflow current that adversely affects the power supply that is operating normally when a hot power supply occurs and when a faulty power supply occurs.
For controlling power supplies in parallel, for example, techniques related to Patent Documents 1 to 3 are disclosed. Patent Document 1 discloses a power supply device using a transformer having a simple structure and control information of the power supply device. Patent Document 2 discloses a parallel operation switching power supply apparatus that prevents an FET from being damaged or a power loss due to a current flowing into the power supply apparatus side when a voltage of a parallel-connected counterpart power supply apparatus rises in a simpler manner. Is disclosed. Further, Patent Document 3 discloses a mirror device motor control circuit capable of making the motor drive time constant regardless of fluctuations in the power supply voltage.

このＯＲｉｎｇ回路において、電力供給のスイッチの役割を担う半導体素子には、一般に、ダイオードよりも電力損失が少ないＭＯＳＦＥＴを用いている。ＯＲｉｎｇ回路で複数のＭＯＳＦＥＴを使用した場合、電源の大電流化に伴い、電力損失を減少させるために導通時の電圧が低く維持される。そのため、電気的特性のばらつきにより、負荷条件によっては導通しないＭＯＳＦＥＴが発生してしまい、電源の並列動作時に負荷バランスを悪化させる要因となっていた。   In this ORing circuit, a MOSFET having a power loss smaller than that of a diode is generally used as a semiconductor element serving as a power supply switch. When a plurality of MOSFETs are used in the ORing circuit, the voltage at the time of conduction is kept low in order to reduce power loss as the power source increases in current. Therefore, due to variations in electrical characteristics, MOSFETs that do not conduct depending on the load conditions are generated, which is a factor that deteriorates load balance during parallel operation of power supplies.

特開２０１０−１１００７７号公報JP 2010-110077 A 特開平１１−８９７４号公報Japanese Patent Laid-Open No. 11-8974 特開２００５−１９３８８９号公報Japanese Patent Laid-Open No. 2005-193889

ＯＲｉｎｇ回路の制御は、負荷の増加に伴いＭＯＳＦＥＴのゲート電圧を上下させ、ＭＯＳＦＥＴの導通電圧を一定に保つように制御する。上述したように、複数個のＭＯＳＦＥＴを並列接続して使用した場合、電力損失を抑えるために導通時の電圧が低い値で保つことになる。このため、ＭＯＳＦＥＴの特性バラつきにより導通されないＭＯＳＦＥＴが存在してしまい、導通電圧が一定に保たれる負荷値までは電力供給を行わない電源が発生してしまっていた。
上述した特許文献１は、電源装置およびその制御方法を簡易な手段で提供し、特許文献２，３では、電圧が上昇した場合や大電流が流れた場合に着目し、そこで生じる不具合を解決する。しかしながら、特許文献１から３では、複数のＭＯＳＦＥＴを並列接続して使用する場合に生じる、ＭＯＳＦＥＴの電気的特性のバラつきに着目するものではなく、このような特性バラつきに起因する不具合を解決する手段を提供するものではない。 The ORing circuit is controlled so as to increase or decrease the gate voltage of the MOSFET as the load increases, and to keep the conduction voltage of the MOSFET constant. As described above, when a plurality of MOSFETs are connected in parallel, the voltage during conduction is kept at a low value in order to suppress power loss. For this reason, there is a MOSFET that is not conductive due to variations in the characteristics of the MOSFET, and a power source that does not supply power is generated up to a load value at which the conduction voltage is kept constant.
Patent Document 1 described above provides a power supply device and its control method with simple means, and Patent Documents 2 and 3 focus on cases where the voltage rises or a large current flows, and solve the problems that occur there. . However, Patent Documents 1 to 3 do not focus on variations in the electrical characteristics of MOSFETs that occur when a plurality of MOSFETs are connected in parallel, and are means for solving the problems caused by such variations in characteristics. Does not provide.

本発明は、このような事情に鑑みてなされたものであり、並列して動作する電源装置に接続する負荷バランス回路が備える、ＭＯＳＦＥＴの電気的特性のバラつきに起因する不具合を回避する負荷バランス回路、電源装置、及び負荷バランス制御方法を提供することを目的とする。   The present invention has been made in view of such circumstances, and is provided with a load balance circuit connected to a power supply device that operates in parallel, and a load balance circuit that avoids problems caused by variations in electrical characteristics of MOSFETs An object of the present invention is to provide a power supply device and a load balance control method.

本発明に係る負荷バランス回路の一態様は、電源回路に接続される負荷バランス回路であって、第１のスイッチング部、第２のスイッチング部、及び制御部を備える。第１のスイッチング部は、前記電源回路へ接続される第１のＭＯＳＦＥＴを有し、駆動電圧に応じて、前記電源回路からの電流の導通状態と非導通状態とを切り替える。第２のスイッチング部は、前記第１のＭＯＳＦＥＴと並列に前記電源回路へ接続される第２のＭＯＳＦＥＴ、第１のツェナーダイオードと、抵抗とを有し、前記第１のＭＯＳＦＥＴが導通状態に移行して前記電源回路から供給される電流量が増加していくことで、前記第１のツェナーダイオードのツェナー電圧を上回ってゲート電圧が上昇していき、非導通状態から導通状態へ切り替える。制御部は、前記第１のＭＯＳＦＥＴ及び前記第２のＭＯＳＦＥＴへ前記駆動電圧を印加し、前記第１のスイッチング部及び前記第２のスイッチング部の導通状態を制御する。   One aspect of the load balance circuit according to the present invention is a load balance circuit connected to a power supply circuit, and includes a first switching unit, a second switching unit, and a control unit. The first switching unit includes a first MOSFET connected to the power supply circuit, and switches between a conduction state and a non-conduction state of a current from the power supply circuit according to a driving voltage. The second switching unit includes a second MOSFET connected to the power supply circuit in parallel with the first MOSFET, a first Zener diode, and a resistor, and the first MOSFET shifts to a conductive state. As the amount of current supplied from the power supply circuit increases, the gate voltage rises above the Zener voltage of the first Zener diode, and switches from the non-conductive state to the conductive state. The control unit applies the driving voltage to the first MOSFET and the second MOSFET, and controls the conduction state of the first switching unit and the second switching unit.

本発明に係る電源装置の一態様は、他の電源と並列動作する電源回路と、前記電源回路に接続する、上述した負荷バランス回路と、を備える。   One aspect of a power supply device according to the present invention includes a power supply circuit that operates in parallel with another power supply and the load balance circuit that is connected to the power supply circuit.

本発明に係る負荷バランス制御方法の一態様は、並列して動作する電源回路に接続される第１のＭＯＳＦＥＴと、前記第１のＭＯＳＦＥＴと並列に前記電源回路へ接続される第２のＭＯＳＦＥＴとを備える負荷バランス回路を制御する負荷バランス制御方法であって、次の工程を備える。前記第１のＭＯＳＦＥＴを駆動電圧に応じて、前記電源回路からの電流の導通状態と非導通状態とを切り替える工程。前記第２のＭＯＳＦＥＴを、前記第１のＭＯＳＦＥＴが導通状態に移行して前記電源回路から供給される電流量が増加していくことで、ツェナーダイオードのツェナー電圧を上回ってゲート電圧が上昇していき、非導通状態から導通状態へ切り替える工程。   One aspect of the load balance control method according to the present invention includes: a first MOSFET connected to a power supply circuit operating in parallel; a second MOSFET connected to the power supply circuit in parallel with the first MOSFET; A load balance control method for controlling a load balance circuit comprising: A step of switching between a conductive state and a non-conductive state of a current from the power supply circuit in accordance with a driving voltage of the first MOSFET. As the first MOSFET shifts to the conductive state and the amount of current supplied from the power supply circuit increases, the gate voltage rises above the Zener voltage of the Zener diode. A step of switching from the non-conducting state to the conducting state.

本発明によれば、並列して動作する電源装置に接続する負荷バランス回路が備える、ＭＯＳＦＥＴの電気的特性のバラつきに起因する不具合を回避する負荷バランス回路、電源装置、及び負荷バランス制御方法を提供することが可能となる。   According to the present invention, there are provided a load balance circuit, a power supply device, and a load balance control method, which are included in a load balance circuit connected to a power supply device operating in parallel, and which avoid problems caused by variations in electrical characteristics of MOSFETs. It becomes possible to do.

本発明に係る実施形態の負荷バランス回路の構成例を示すブロック図である。It is a block diagram which shows the structural example of the load balance circuit of embodiment which concerns on this invention. 実施形態１の負荷バランス回路の構成例を示すブロック図である。FIG. 3 is a block diagram illustrating a configuration example of a load balance circuit according to the first embodiment. 実施形態１の負荷バランス回路の電圧の推移の一例を示す図である。It is a figure which shows an example of transition of the voltage of the load balance circuit of Embodiment 1. 実施形態２の負荷バランス回路の構成例を示すブロック図である。FIG. 6 is a block diagram illustrating a configuration example of a load balance circuit according to a second embodiment.

以下、本発明の実施形態について、図面を参照しながら説明する。説明の明確化のため、以下の記載及び図面は、適宜、省略、及び簡略化がなされている。各図面において同一の構成または機能を有する構成要素および相当部分には、同一の符号を付し、その説明は省略する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

本発明の実施形態の一態様では、電源を並列動作させたときに、一方の電源からのみ電力供給してしまうＯＲｉｎｇ制御とならないようにバランスをとらせるものである。実施形態の一態様の負荷バランス回路は、複数個の並列接続した各ＭＯＳＦＥＴが導通する動作を負荷量にあわせて傾斜を持たせることにより実現する。   In one aspect of the embodiment of the present invention, when power supplies are operated in parallel, a balance is established so as not to be ORing control in which power is supplied from only one power supply. The load balance circuit according to one aspect of the embodiment is realized by providing an operation in which a plurality of MOSFETs connected in parallel to each other are provided with a slope in accordance with a load amount.

図１は、発明に係る実施形態の一態様の負荷バランス回路の構成例を示すブロック図である。負荷バランス回路１は、並列して動作する電源回路２に接続され、電源の導通状態を制御する。負荷バランス回路１は、第１のスイッチング部３、第２のスイッチング部４、及び制御部（Ｏｒｉｎｇ回路）５を備える。なお、図１では、負荷バランス回路１の構成の説明を容易するため、電源回路２も示している。
第１のスイッチング部３は、電源回路２へ接続されるＱ１のＭＯＳＦＥＴ（第１のＭＯＳＦＥＴ）を有し、駆動電圧に応じて、電源回路からの電流の導通状態と非導通状態とを切り替える。
第２のスイッチング部は、Ｑ２のＭＯＳＦＥＴ、ツェナーダイオードＺＤ１、及び、抵抗Ｒ１から構成される。第２のスイッチング部４は、Ｑ１のＭＯＳＦＥＴと並列に電源回路２へ接続されるＱ２のＭＯＳＦＥＴ（第２のＭＯＳＦＥＴ）を有し、Ｑ１のＭＯＳＦＥＴが導通状態に移行して前記電源回路から供給される電流量が増加していくことで、ツェナーダイオードのツェナー電圧を上回ってゲート電圧が上昇していき、非導通状態から導通状態へ切り替える。具体的には、第２のスイッチング部は、Ｑ１のＭＯＳＦＥＴが導通状態に移行して電源回路から供給される電流量が増加していくことで、ツェナーダイオードＺＤ１のツェナー電圧を上回ってゲート電圧が上昇していき、非導通状態から導通状態へ切り替える。
制御部５は、Ｑ１のＭＯＳＦＥＴ及びＱ２のＭＯＳＦＥＴへ駆動電圧を印加し、第１のスイッチング部３及び第２のスイッチング部４の導通状態を制御する。 FIG. 1 is a block diagram illustrating a configuration example of a load balance circuit according to an aspect of an embodiment of the invention. The load balance circuit 1 is connected to a power supply circuit 2 that operates in parallel, and controls the conduction state of the power supply. The load balance circuit 1 includes a first switching unit 3, a second switching unit 4, and a control unit (Oring circuit) 5. In FIG. 1, the power supply circuit 2 is also shown to facilitate the description of the configuration of the load balance circuit 1.
The first switching unit 3 includes a Q1 MOSFET (first MOSFET) connected to the power supply circuit 2 and switches between a conduction state and a non-conduction state of a current from the power supply circuit in accordance with the drive voltage.
The second switching unit includes a MOSFET of Q2, a Zener diode ZD1, and a resistor R1. The second switching unit 4 includes a Q2 MOSFET (second MOSFET) connected to the power supply circuit 2 in parallel to the Q1 MOSFET, and the Q1 MOSFET shifts to a conductive state and is supplied from the power supply circuit. As the amount of current increases, the gate voltage rises above the Zener voltage of the Zener diode and switches from the non-conductive state to the conductive state. Specifically, the second switching unit has a gate voltage that exceeds the Zener voltage of the Zener diode ZD1 by increasing the amount of current supplied from the power supply circuit when the MOSFET of Q1 shifts to a conductive state. It rises and switches from the non-conductive state to the conductive state.
The control unit 5 applies a driving voltage to the MOSFET of Q1 and the MOSFET of Q2, and controls the conduction state of the first switching unit 3 and the second switching unit 4.

図１に示す構成により、負荷バランス回路１は、制御部５によって、Ｑ１のＭＯＳＦＥＴを駆動電圧に応じて、電源回路からの電流の導通状態と非導通状態とを切り替える。加えて、Ｑ２のＭＯＳＦＥＴを、Ｑ１のＭＯＳＦＥＴが導通状態に移行して電源回路から供給される電流量が増加していくことで、ツェナーダイオードのツェナー電圧を上回ってゲート電圧が上昇していき、非導通状態から導通状態へ切り替える。以下、図面を参照して各実施形態について詳述する。   With the configuration shown in FIG. 1, the load balance circuit 1 switches the conduction state and the non-conduction state of the current from the power supply circuit according to the drive voltage of the MOSFET of Q1 by the control unit 5. In addition, the amount of current supplied from the power supply circuit increases as the Q2 MOSFET shifts to the conducting state of the Q2 MOSFET, so that the gate voltage rises above the Zener voltage of the Zener diode, Switch from non-conducting state to conducting state. Hereinafter, each embodiment will be described in detail with reference to the drawings.

実施形態１．
実施形態１の構成の説明
図２は、実施形態１の負荷バランス回路１１の構成例を示すブロック図である。図２では、３つのスイッチング部を備える構成例を示す。負荷バランス回路１１は、Ｑ１〜Ｑ３で示すＭＯＳＦＥＴ、抵抗Ｒ１、Ｒ２、ツェナーダイオードＺＤ１、ＺＤ２、及びＯｒｉｎｇ制御部５１を備える。ここで、図１に示す第１のスイッチング部３は、Ｑ１のＭＯＳＦＥＴに相当する。第２のスイッチング部３は、Ｑ２のＭＯＳＦＥＴ、抵抗Ｒ１、及びツェナーダイオードＺＤ１に相当する。加えて、Ｑ３のＭＯＳＦＥＴ、抵抗Ｒ２、及びツェナーダイオードＺＤ２からなる第３のスイッチング部を備える。
符号Ｑ１〜Ｑ３の各ＭＯＳＦＥＴに関して、ソース端子ＳはＤＣ−ＤＣコンバータ部２１の出力端Ｖｏ ＩＮとＯＲｉｎｇ制御部５１と接続され、ドレイン端子ＤはＯＲｉｎｇ制御部５１と電源の負荷端Ｖｏ ＯＵＴと接続される。加えて、ゲート端子ＧはＱ１のＭＯＳＦＥＴのみＯＲｉｎｇ制御部３と接続し、Ｑ２のＭＯＳＦＥＴはツェナーダイオードＺＤ１のカソード端子Ｃ、Ｑ３のＭＯＳＦＥＴはツェナーダイオードＺＤ２のカソード端子Ｃとそれぞれ接続される。各ツェナーダイオードＺ１、Ｚ２に関して、アノード端子ＡはＯＲｉｎｇ制御部５１に接続される。また、ツェナーダイオードＺ１，Ｚ２の種類についてはＺ２のツェナー電圧ＶｚがＺ１より大きく（ＺＤ１＜ＺＤ２）になるよう選択される。そして、ツェナー電流Ｉｚを決定する抵抗である抵抗Ｒ１、Ｒ２が必要であり、Ｑ２のＭＯＳＦＥＴには抵抗Ｒ１、Ｑ３のＭＯＳＦＥＴには抵抗Ｒ２がゲート端子Ｇとソース端子Ｓ間にそれぞれ接続される。 Embodiment 1. FIG.
Description of Configuration of First Embodiment FIG. 2 is a block diagram illustrating a configuration example of the load balance circuit 11 of the first embodiment. FIG. 2 shows a configuration example including three switching units. The load balance circuit 11 includes MOSFETs indicated by Q1 to Q3, resistors R1 and R2, Zener diodes ZD1 and ZD2, and an Oring control unit 51. Here, the first switching unit 3 shown in FIG. 1 corresponds to a MOSFET of Q1. The second switching unit 3 corresponds to the MOSFET Q2, the resistor R1, and the Zener diode ZD1. In addition, a third switching unit including a MOSFET of Q3, a resistor R2, and a Zener diode ZD2 is provided.
With respect to the MOSFETs Q1 to Q3, the source terminal S is connected to the output terminal Vo IN of the DC-DC converter unit 21 and the ORing control unit 51, and the drain terminal D is connected to the ORing control unit 51 and the load terminal Vo OUT of the power source. Is done. In addition, the gate terminal G is connected to the ORing control unit 3 only for the MOSFET Q1, the MOSFET Q2 is connected to the cathode terminal C of the Zener diode ZD1, and the MOSFET Q3 is connected to the cathode terminal C of the Zener diode ZD2. For each Zener diode Z1, Z2, the anode terminal A is connected to the ORing controller 51. Further, the types of the Zener diodes Z1 and Z2 are selected so that the Zener voltage Vz of Z2 is larger than Z1 (ZD1 <ZD2). The resistors R1 and R2 which are resistors for determining the Zener current Iz are required. The resistor R1 is connected between the MOSFET Q2 and the resistor R2 is connected between the gate terminal G and the source terminal S of the MOSFET Q3.

実施形態１の動作の説明
まず、ＯＲｉｎｇ制御部５１は、ＤＣ−ＤＣコンバータ部２１の出力端Ｖｏ ＩＮから各ＭＯＳＦＥＴを介して電源の負荷端Ｖｏ ＯＵＴに負荷電流Ｉｏが流れる際に、各ＭＯＳＦＥＴを駆動するゲート電圧Ｖｇｓを制御する。具体的には、ＯＲｉｎｇ制御部５１は、各ＭＯＳＦＥＴの導通電圧Ｖｄｓを常に監視することによって、一定の導通電圧Ｖｄｓ＿Ｓに保つようにするため、各ＭＯＳＦＥＴのゲート電圧Ｖｇｓを増減させることを繰り返す制御をしている。 Description of Operation of Embodiment 1 First, the ORing control unit 51 causes each MOSFET to flow when the load current Io flows from the output terminal Vo IN of the DC-DC converter unit 21 to the load terminal Vo OUT of the power supply via each MOSFET. The gate voltage Vgs to be driven is controlled. Specifically, the ORing control unit 51 repeatedly controls to increase or decrease the gate voltage Vgs of each MOSFET in order to keep the constant conduction voltage Vds_S by constantly monitoring the conduction voltage Vds of each MOSFET. doing.

図３を用いて説明する。タイミングＴ０〜Ｔ１の期間にＯＲｉｎｇ制御部５１はＤＣ−ＤＣコンバータ部２１の出両端よりＶｏ ＩＮが出力され、ＯＲｉｎｇ制御部５１よりゲート電圧Ｖｇｓが印加されると、Ｑ２のＭＯＳＦＥＴのゲート電圧Ｖｇｓ２とＱ３のＭＯＳＦＥＴのゲート電圧Ｖｇｓ３についてはそれぞれ接続されているツェナーダイオードＺＤ１、ＺＤ２のツェナー電圧Ｖｚ分が減算されるため、Ｑ１のＭＯＳＦＥＴのゲート電圧Ｖｇｓ１が駆動するゲート電圧Ｖｇｓ＿Ｓに一番先に達し、Ｑ１のＭＯＳＦＥＴが導通状態となる。   This will be described with reference to FIG. During the period of timing T0 to T1, the ORing control unit 51 outputs Vo IN from both ends of the DC-DC converter unit 21, and when the gate voltage Vgs is applied from the ORing control unit 51, the gate voltage Vgs2 of the MOSFET of Q2 The gate voltage Vgs3 of the MOSFET of Q3 is subtracted from the Zener voltage Vz of the respectively connected Zener diodes ZD1 and ZD2, so that the gate voltage Vgs1 of the MOSFET of Q1 reaches the gate voltage Vgs_S that is driven first, The MOSFET of Q1 becomes conductive.

タイミングＴ１〜Ｔ２期間では、負荷電流Ｉｏを増加させていくと、一定の導通電圧Ｖｄｓ＿Ｓを超えてしまう。このため、一定の導通電圧Ｖｄｓ＿Ｓを維持するために、ゲート電圧Ｖｇｓを増加させる動作がＯＲｉｎｇ制御部５１より行われる。結果、ツェナーダイオードＺＤ２より低いツェナー電圧ＶｚであるツェナーダイオードＺＤ１と接続しているＱ２のＭＯＳＦＥＴのゲート電圧Ｖｇｓ２が駆動するゲート電圧Ｖｇｓ＿Ｓに達するため、Ｑ２のＭＯＳＦＥＴが２番目に導通状態となる。   In the period from timing T1 to T2, when the load current Io is increased, the constant conduction voltage Vds_S is exceeded. For this reason, the ORing control unit 51 performs an operation of increasing the gate voltage Vgs in order to maintain a constant conduction voltage Vds_S. As a result, the gate voltage Vgs_S of the MOSFET of Q2 connected to the Zener diode ZD1, which is a Zener voltage Vz lower than the Zener diode ZD2, reaches the gate voltage Vgs_S to be driven, so that the MOSFET of Q2 is in the second conductive state.

タイミングＴ２〜Ｔ３の期間ではさらに負荷電流Ｉｏを増加させていき、タイミングＴ１〜Ｔ２期間と同様に、ＯＲｉｎｇ制御部５１が一定の導通電圧Ｖｄｓ＿Ｓに維持しようとして、ゲート電圧Ｖｇｓを増加させていく。すると、Ｑ３のＭＯＳＦＥＴのゲート電圧Ｖｇｓ３が駆動するゲート電圧Ｖｇｓ＿Ｓに達するため、Ｑ３のＭＯＳＦＥＴが最後に導通状態となる。よって、負荷電流Ｉｏが全てのＭＯＳＦＥＴを介して流れるようになる。   The load current Io is further increased in the period from the timing T2 to T3, and the ORing control unit 51 increases the gate voltage Vgs in an attempt to maintain the constant conduction voltage Vds_S as in the period from the timing T1 to T2. Then, since the gate voltage Vgs3 of the MOSFET of Q3 reaches the gate voltage Vgs_S to be driven, the MOSFET of Q3 is finally turned on. Therefore, the load current Io flows through all the MOSFETs.

以上説明したように、本実施形態の負荷バランス回路１１によれば、複数のＭＯＳＦＥＴを電源回路に並列して接続させ、各ＭＯＳＦＥＴの駆動電圧に傾斜を持たせることによって、ＭＯＳＦＥＴの電気的特性のバラつきに起因する不具合を解消する。具体的には並列動作している電源の負荷電流が少ない場合にもＭＯＳＦＥＴが機能するように、複数のＭＯＳＦＥＴのゲート電圧の大きさを一つ一つ変化させ、ＭＯＳＦＥＴの駆動する順番を制御する。これにより、電源に接続する複数のＭＯＳＦＥＴの電気的特性のバラつきによって導通されない素子の存在が生じることを回避する。その結果、並列接続された電源の負荷バランスを安定させる。   As described above, according to the load balance circuit 11 of the present embodiment, a plurality of MOSFETs are connected in parallel to the power supply circuit, and the drive voltage of each MOSFET is given a slope, thereby improving the electrical characteristics of the MOSFETs. Eliminate problems caused by variations. Specifically, the gate voltage of multiple MOSFETs is changed one by one to control the order of driving the MOSFETs so that the MOSFETs function even when the load current of the power supply operating in parallel is small. . This avoids the presence of an element that is not conductive due to variations in the electrical characteristics of the plurality of MOSFETs connected to the power supply. As a result, the load balance of the power supplies connected in parallel is stabilized.

実施形態２．
図４は、実施形態２の負荷バランス回路の構成例を示すブロック図である。図４に示す負荷バランス回路１２では、図２に示す負荷バランス回路１１の構成に加えて、Ｑ１のＭＯＳＦＥＴには抵抗Ｒ３、Ｑ２のＭＯＳＦＥＴには抵抗Ｒ４、Ｑ３のＭＯＳＦＥＴには抵抗Ｒ５をドレイン端子Ｄと電源の負荷端Ｖｏ ＯＵＴに接続する。
それぞれ接続した抵抗が各ＭＯＳＦＥＴの導通時抵抗成分に加算され、先と同様の動作が行われるが、負荷電流Ｉｏがより低い状態から導通電圧Ｖｄｓが一定に保たれる導通電圧Ｖｄｓ＿Ｓを超えようとするため、ゲート電圧Ｖｇｓが増加して、各ＭＯＳＦＥＴが導通していく。結果、並列動作する各電源で負荷バランスが図れるようになる。
なお、図４の負荷バランス回路１２では、図１に示す第１のスイッチング部３は、Ｑ１のＭＯＳＦＥＴと抵抗Ｒ３に相当する。第２のスイッチング部３は、Ｑ２のＭＯＳＦＥＴ、抵抗Ｒ１、Ｒ４、及びツェナーダイオードＺＤ１に相当する。加えて、Ｑ３のＭＯＳＦＥＴ、抵抗Ｒ２、Ｒ５、及びツェナーダイオードＺＤ２からなる第３のスイッチング部を備える。 Embodiment 2. FIG.
FIG. 4 is a block diagram illustrating a configuration example of the load balance circuit according to the second embodiment. In addition to the configuration of the load balance circuit 11 shown in FIG. 2, the load balance circuit 12 shown in FIG. 4 includes a resistor R3 for the MOSFET Q1, a resistor R4 for the Q2 MOSFET, and a resistor R5 for the Q3 MOSFET. D is connected to the load terminal Vo OUT of the power source.
Each connected resistance is added to the resistance component when each MOSFET is conducting, and the same operation as described above is performed. However, from the state where the load current Io is lower, the conduction voltage Vds_S tries to exceed the conduction voltage Vds_S which is kept constant. Therefore, the gate voltage Vgs increases and each MOSFET becomes conductive. As a result, load balance can be achieved with each power supply operating in parallel.
In the load balance circuit 12 of FIG. 4, the first switching unit 3 shown in FIG. 1 corresponds to the MOSFET Q1 and the resistor R3. The second switching unit 3 corresponds to a MOSFET of Q2, resistors R1 and R4, and a Zener diode ZD1. In addition, a third switching unit including a MOSFET of Q3, resistors R2 and R5, and a Zener diode ZD2 is provided.

その他の実施形態
実施形態１，２では、スイッチング部を３つ備える構成例を説明したが、３つ以上であってもよい。加えて、実施形態１，２の構成例から第３のスイッチング部となる構成要素を除いた負荷バランス回路であってもよい。 Other Embodiments In the first and second embodiments, the configuration example including the three switching units has been described. However, the number may be three or more. In addition, the load balance circuit may be a configuration in which the third switching unit is excluded from the configuration examples of the first and second embodiments.

上記各実施形態で説明したように、本発明に係る実施形態の一態様によれば、並列動作する電源に接続する、複数のＭＯＳＦＥＴの電気的促成のバラつきを考慮してＭＯＳＦＥＴの
並列動作している複数の電源の内で電力供給しない電源が発生して、負荷が偏るようなアンバランスな状態にならないため、ＯＲｉｎｇ回路でＭＯＳＦＥＴの電気的特性のバラつきによる違いに左右されることなく、負荷バランスが図れ、信頼性確保に繋がる。 As described in each of the above embodiments, according to one aspect of the embodiment of the present invention, the MOSFETs are operated in parallel in consideration of variations in electrical promotion of the plurality of MOSFETs connected to the power supply operating in parallel. Since there is a power supply that does not supply power among a plurality of power supplies, and the load is not unbalanced, load balancing is not affected by differences in the electrical characteristics of MOSFETs in the ORing circuit. Can lead to ensuring reliability.

なお、本発明は上記に示す実施形態に限定されるものではない。本発明の範囲において、上記実施形態の各要素を、当業者であれば容易に考えうる内容に変更、追加、変換することが可能である。   In addition, this invention is not limited to embodiment shown above. Within the scope of the present invention, it is possible to change, add, or convert each element of the above-described embodiment to a content that can be easily considered by those skilled in the art.

１、１１、２１ 負荷バランス回路
２ 電源回路
３ 第１のスイッチング部
４ 第２のスイッチング部
５ 制御部
６ 第３のスイッチング部
２１ ＤＣ−ＤＣコンバータ部
５１ Ｏｒｉｎｇ制御部
Ｑ１〜Ｑ３ ＭＯＳＦＥＴ、
Ｒ１〜Ｒ５ 抵抗
Ｖｏ ＩＮ 出力端
Ｖｏ ＯＵＴ 負荷端
ＺＤ１、ＺＤ２ ツェナーダイオード DESCRIPTION OF SYMBOLS 1, 11, 21 Load balance circuit 2 Power supply circuit 3 1st switching part 4 2nd switching part 5 Control part 6 3rd switching part 21 DC-DC converter part 51 Oring control part Q1-Q3 MOSFET,
R1 to R5 Resistance Vo IN Output terminal Vo OUT Load terminal ZD1, ZD2 Zener diode

Claims (8)

電源回路に接続される負荷バランス回路であって、
前記電源回路へ接続される第１のＭＯＳＦＥＴを有し、駆動電圧に応じて、前記電源回路からの電流の導通状態と非導通状態とを切り替える第１のスイッチング手段と、
前記第１のＭＯＳＦＥＴと並列に前記電源回路へ接続される第２のＭＯＳＦＥＴと、第１のツェナーダイオードと、抵抗とを有し、前記第１のＭＯＳＦＥＴが導通状態に移行して前記電源回路から供給される電流量が増加していくことで、前記第１のツェナーダイオードのツェナー電圧を上回ってゲート電圧が上昇していき、非導通状態から導通状態へ切り替える第２のスイッチング手段と、
前記第１のＭＯＳＦＥＴ及び前記第２のＭＯＳＦＥＴへ前記駆動電圧を印加し、前記第１のスイッチング手段及び前記第２のスイッチング手段の導通状態を制御する制御手段と、を備える負荷バランス回路。 A load balance circuit connected to the power supply circuit,
A first switching unit that includes a first MOSFET connected to the power supply circuit, and switches between a conductive state and a non-conductive state of a current from the power supply circuit according to a drive voltage;
A second MOSFET connected to the power supply circuit in parallel with the first MOSFET; a first Zener diode; and a resistor, wherein the first MOSFET shifts to a conductive state from the power supply circuit. A second switching means for switching from a non-conducting state to a conducting state by increasing the amount of current supplied so that the gate voltage rises above the Zener voltage of the first Zener diode;
A load balance circuit comprising: a control unit that applies the drive voltage to the first MOSFET and the second MOSFET and controls a conduction state of the first switching unit and the second switching unit. 前記第１のＭＯＳＦＥＴは、ソース端子が前記電源回路の出力端および前記制御手段と接続され、ドレイン端子が前記電源回路の負荷端と接続され、ゲート端子が前記制御手段と接続され、
前記第１のツェナーダイオードは、アノード端子が前記制御手段と接続され、
前記第２のＭＯＳＦＥＴは、ソース端子が前記電源回路の出力端と前記制御手段とに接続され、ドレイン端子が前記電源回路の負荷端と接続され、ゲート端子が前記第１のツェナーダイオードのカソード端子と接続され、
前記制御手段は、前記第１のＭＯＳＦＥＴのゲート端子へ前記駆動電圧を印加し、前記第１のツェナーダイオードを介して前記第２のＭＯＳＦＥＴのゲート端子へ前記駆動電圧を印加することを特徴とする請求項１記載の負荷バランス回路。 The first MOSFET has a source terminal connected to the output end of the power supply circuit and the control means, a drain terminal connected to the load end of the power supply circuit, and a gate terminal connected to the control means.
The first Zener diode has an anode terminal connected to the control means,
The second MOSFET has a source terminal connected to the output end of the power supply circuit and the control means, a drain terminal connected to the load end of the power supply circuit, and a gate terminal connected to the cathode terminal of the first Zener diode. Connected with
The control means applies the drive voltage to the gate terminal of the first MOSFET, and applies the drive voltage to the gate terminal of the second MOSFET via the first Zener diode. The load balance circuit according to claim 1. 前記第１のＭＯＳＦＥＴ及び前記第２のＭＯＳＦＥＴと並列に前記電源回路へ接続される第３のＭＯＳＦＥＴを有し、前記第２のＭＯＳＦＥＴが導通状態に移行して前記電源回路から供給される電流量が増加していくことで、前記第１のツェナーダイオードのツェナー電圧を上回ってゲート電圧が上昇していき、非導通状態から導通状態へ切り替える第３のスイッチング手段を、さらに備え、
前記制御手段は、前記第３のＭＯＳＦＥＴへ前記駆動電圧を印加し、前記第３のスイッチング手段の導通状態を制御することを特徴とする請求項１または２記載の負荷バランス回路。 A third MOSFET connected to the power supply circuit in parallel with the first MOSFET and the second MOSFET, and a current amount supplied from the power supply circuit when the second MOSFET shifts to a conductive state; Further increases, the gate voltage rises above the Zener voltage of the first Zener diode, further comprising a third switching means for switching from the non-conductive state to the conductive state,
3. The load balance circuit according to claim 1, wherein the control means applies the drive voltage to the third MOSFET to control a conduction state of the third switching means. 前記第３のスイッチング手段は、アノード端子が前記制御手段と接続された第２のツェナーダイオードを、さらに有し、
前記第３のＭＯＳＦＥＴは、ソース端子が前記電源回路の出力端と前記制御手段とに接続され、ドレイン端子が前記電源回路の負荷端と接続され、ゲート端子が前記第２のツェナーダイオードのカソード端子と接続され、
前記制御手段は、前記第２のツェナーダイオードを介して前記第３のＭＯＳＦＥＴのゲート端子へ前記駆動電圧を印加することを特徴とする請求項３記載の負荷バランス回路。 The third switching means further includes a second Zener diode having an anode terminal connected to the control means,
The third MOSFET has a source terminal connected to the output end of the power supply circuit and the control means, a drain terminal connected to the load end of the power supply circuit, and a gate terminal connected to the cathode terminal of the second Zener diode. Connected with
4. The load balance circuit according to claim 3, wherein the control means applies the drive voltage to a gate terminal of the third MOSFET via the second Zener diode. 前記第１のスイッチング手段は、前記第１のＭＯＳＦＥＴと前記電源回路の出力端との間に接続される第１の抵抗を、さらに有し、
前記第２のスイッチング手段は、前記第２のＭＯＳＦＥＴと前記電源回路の出力端との間に接続される第２の抵抗を、さらに備えることを特徴とする請求項１または２記載の負荷バランス回路。 The first switching means further includes a first resistor connected between the first MOSFET and an output terminal of the power supply circuit,
3. The load balance circuit according to claim 1, wherein the second switching unit further includes a second resistor connected between the second MOSFET and an output terminal of the power supply circuit. . 前記第１のスイッチング手段は、前記第１のＭＯＳＦＥＴと前記電源回路の出力端との間に接続される第１の抵抗を、さらに有し、
前記第２のスイッチング手段は、前記第２のＭＯＳＦＥＴと前記電源回路の出力端との間に接続される第２の抵抗を、さらに有し、
前記第３のスイッチング手段は、前記第３のＭＯＳＦＥＴと前記電源回路の出力端との間に接続される第３の抵抗を、さらに有することを特徴とする請求項３または４記載の負荷バランス回路。 The first switching means further includes a first resistor connected between the first MOSFET and an output terminal of the power supply circuit,
The second switching means further includes a second resistor connected between the second MOSFET and an output terminal of the power supply circuit,
5. The load balance circuit according to claim 3, wherein the third switching unit further includes a third resistor connected between the third MOSFET and an output terminal of the power supply circuit. . 他の電源と並列動作する電源回路と、
前記電源回路に接続する、請求項１乃至６のいずれか一項に記載の、負荷バランス回路と、を備える電源装置。 A power supply circuit operating in parallel with other power supplies;
A power supply apparatus comprising: a load balance circuit according to any one of claims 1 to 6 connected to the power supply circuit. 並列して動作する電源回路に接続される第１のＭＯＳＦＥＴと、前記第１のＭＯＳＦＥＴと並列に前記電源回路へ接続される第２のＭＯＳＦＥＴとを備える負荷バランス回路を制御する負荷バランス制御方法であって、
前記第１のＭＯＳＦＥＴを駆動電圧に応じて、前記電源回路からの電流の導通状態と非導通状態とを切り替え、
前記第２のＭＯＳＦＥＴを、前記第１のＭＯＳＦＥＴが導通状態に移行して前記電源回路から供給される電流量が増加していくことで、ツェナーダイオードのツェナー電圧を上回ってゲート電圧が上昇していき、非導通状態から導通状態へ切り替える負荷バランス制御方法。 A load balance control method for controlling a load balance circuit comprising: a first MOSFET connected to a power supply circuit operating in parallel; and a second MOSFET connected to the power supply circuit in parallel with the first MOSFET. There,
The first MOSFET is switched between a conduction state and a non-conduction state of a current from the power supply circuit according to a driving voltage,
As the first MOSFET shifts to the conductive state and the amount of current supplied from the power supply circuit increases, the gate voltage rises above the Zener voltage of the Zener diode. A load balance control method for switching from a non-conductive state to a conductive state.
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