JP2013162538A - Power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power conversion device that reduces a voltage unbalance between two smoothing capacitors connected in series while minimizing a loss.SOLUTION: IGBTs 20, 21 are connected in series between positive and negative phases of a three-wire direct current having a positive phase, a negative phase and a neutral phase. Smoothing capacitors 26, 27 are connected in series between the positive and negative phases. A reactor 24 is connected between the neutral phase and a junction of the IGBTs 20, 21. A controller 25 switches the IGBT 20 and turns off the IGBT 21 when a voltage Vis higher than a voltage V, and switches the IGBT 21 and turns off the IGBT 20 when the voltage Vis higher than the voltage V.

Description

  The present invention relates to a power conversion device, and more particularly, to a power conversion device including a DC circuit constituted by two smoothing capacitors connected in series.

  For example, some power converters such as a rectifier circuit or an inverter circuit include a DC circuit constituted by two smoothing capacitors connected in series.

  In the power conversion device having such a configuration, current is input to and output from the connection point (DC neutral point) of the two smoothing capacitors. A chopper circuit is further provided to compensate for the voltage imbalance between the two smoothing capacitors. A chopper circuit used for such an application generally includes two semiconductor switch elements connected in parallel to two smoothing capacitors and two diodes connected in reverse parallel to the two semiconductor switch elements, respectively. The connection point of the two semiconductor switch elements is connected to a DC neutral point via a reactor.

  For example, Japanese Patent Laying-Open No. 20007-1221903 (Patent Document 1) discloses a method for compensating for voltage imbalance between two smoothing capacitors in a power conversion device including the above-described chopper. Specifically, the current command value of the chopper circuit and the current detection value of the chopper circuit are compared at a certain sampling interval. A difference between the current command value and the current detection value is calculated as an error current. A PWM (pulse width modulation) signal for controlling the chopper circuit is generated so as to invert the polarity based on the positive / negative polarity of the error current.

JP 2007-221903 A

  When the chopper circuit is controlled as described above, a charging current and a discharging current flow for exchanging energy between the two capacitors. This energy is not only used to eliminate voltage imbalance, but is also consumed by reactors, semiconductor switches, and the like. The energy consumed by the reactor, semiconductor switch, etc. is lost. Therefore, in order to compensate for the voltage imbalance between the two smoothing capacitors, it is desirable to minimize the loss in the reactor, the semiconductor switch, and the like.

  The objective of this invention is providing the power converter device which can make voltage imbalance between two smoothing capacitors connected in series small, making loss as small as possible.

  A power conversion device according to an aspect of the present invention includes first and second semiconductor switch elements connected in series between a positive phase and a negative phase of a three-wire DC having a positive phase, a negative phase, and a neutral phase, First and second diodes connected in reverse parallel to the first and second semiconductor switch elements, respectively, a first capacitor connected between the positive phase and the neutral phase, and a neutral phase and a negative phase Connected to the second capacitor connected between the first phase and the second phase, the neutral phase, the reactor connected between the connection points of the first and second semiconductor switch elements, and the positive phase and the negative phase. A power conversion circuit that performs power conversion between alternating current and direct current, a voltage detector that detects a first voltage of the first capacitor and a second voltage of the second capacitor, and the detected first and Control first and second semiconductor switch elements based on second voltage And a that controller. When the first voltage is greater than the second voltage, the controller switches the first semiconductor switch element to turn off the second semiconductor switch element, and the second voltage is greater than the first voltage. In this case, the second semiconductor switch element is switched to turn off the first semiconductor switch element.

  According to the present invention, it is possible to reduce voltage imbalance between two smoothing capacitors connected in series while minimizing loss.

It is the circuit diagram which showed the power converter device by embodiment of this invention. It is a figure for demonstrating the balance control method corresponding to the comparative example of this invention. FIG. 3 is a diagram illustrating a configuration of a controller according to Embodiment 1. It is the figure which showed the structural example of the PWM signal generators 55 and 56 shown in FIG. It is the 1st figure for explaining balance control concerning a 1st embodiment. It is a 2nd figure for demonstrating the balance control which concerns on 1st Embodiment. 6 is a diagram illustrating a configuration of a controller according to Embodiment 2. FIG. FIG. 10 is a diagram illustrating a configuration of a controller according to a third embodiment. It is a figure explaining the structure of the controller which concerns on Embodiment 4. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 1 is a circuit diagram showing a power converter according to an embodiment of the present invention. Referring to FIG. 1, power converter 101 includes rectifier circuit A, chopper circuit B, inverter circuit C, and smoothing capacitors 26 and 27.

  The rectifier circuit A converts the alternating current of the three-phase alternating current power source 1 into direct current. The three-phase AC power source 1 is connected to the rectifier circuit A via the reactors 5, 6, and 7. The chopper circuit B suppresses voltage imbalance between the positive and negative smoothing capacitors 26 and 27. The inverter circuit C converts the direct current from the chopper circuit B into alternating current.

  The smoothing capacitor 26 is a positive-side smoothing capacitor, and the positive terminal thereof corresponds to the positive phase of three-wire DC. The smoothing capacitor 27 is a negative-side smoothing capacitor, and its negative terminal corresponds to the negative phase of three-wire DC. The connection point between the smoothing capacitors 26 and 27 corresponds to the neutral phase of the three-wire DC. That is, the smoothing capacitor 26 is connected between the positive phase and the neutral phase of the three-wire DC, and the smoothing capacitor 27 is connected between the neutral phase and the negative phase of the three-wire DC.

  The rectifier circuit A has three phases. The first phase includes IGBTs 10 and 11 connected in series between a positive phase and a negative phase of a three-wire DC, and diodes 8 and 9 connected in reverse parallel to the IGBTs 10 and 11, respectively. The second phase includes IGBTs 14 and 15 connected in series between the positive phase and the negative phase of the three-wire DC, and diodes 12 and 13 connected in reverse parallel to the IGBTs 14 and 15, respectively. The third phase includes IGBTs 18 and 19 connected in series between the positive phase and the negative phase of the three-wire DC, and diodes 16 and 17 connected in reverse parallel to the IGBTs 18 and 19, respectively.

  One phase of the three-phase AC power supply 1 is connected to a connection point of the IGBTs 10 and 11 via the reactor 5. The other one phase of the three-phase AC power source 1 is connected to the connection point of the IGBTs 14 and 15 via the reactor 6. The remaining one phase of the three-phase AC power source 1 is connected to the connection point of the IGBTs 18 and 19 via the reactor 7. Further, capacitors 2, 3 and 4 are connected between each phase of the three-phase AC power supply 1 and the neutral wire N, respectively.

  The chopper circuit B includes IGBTs 20 and 21 connected in series between the positive and negative phases of the three-wire DC, diodes 22 and 23 connected in reverse parallel to the IGBTs 20 and 21, respectively, and a reactor 24. Reactor 24 is connected between the connection point of IGBTs 20 and 21 and neutral line N. The neutral line N is connected to a connection point between the smoothing capacitors 26 and 27. Therefore, reactor 24 is connected between the connection point of IGBTs 20 and 21 and the connection point of smoothing capacitors 26 and 27.

  The inverter circuit C has the same configuration as the rectifier circuit A. That is, the inverter circuit C has three phases. The first phase includes IGBTs 28 and 29 connected in series between the positive and negative phases of the three-wire DC, and diodes 30 and 31 connected in reverse parallel to the IGBTs 28 and 29, respectively. The second phase includes IGBTs 32 and 33 connected in series between a positive phase and a negative phase of a three-wire DC, and diodes 34 and 35 connected in reverse parallel to the IGBTs 32 and 33, respectively. The third phase includes IGBTs 36 and 37 connected in series between the positive phase and the negative phase of the three-wire DC, and diodes 38 and 39 connected in reverse parallel to the IGBTs 36 and 37, respectively.

  The connection points of IGBTs 28 and 29, the connection points of IGBTs 32 and 33, and the connection points of IGBTs 36 and 37 are connected to a three-phase four-wire load 46 via reactors 42, 41, and 40, respectively. Further, capacitors 43, 44, 45 are connected between each phase of the load 46 and the neutral wire N, respectively.

The power conversion device 101 further includes voltage detectors 47 and 48 and a controller 25. The voltage detector 47 detects the voltage V _P of the smoothing capacitor 26. The voltage detector 48 detects the voltage V _N of the smoothing capacitor 27. The controller 25 generates gate control signals G _P and G _N based on the voltages V _P and V _N detected by the voltage detectors 47 and 48, respectively. The controller 25 sends the generated gate control signals G _P and G _N to the IGBTs 20 and 21 of the chopper circuit B, respectively.

  Controller 25 further generates a gate control signal for controlling the IGBT included in each of rectifier circuit A and inverter circuit C. However, in order to avoid complication of the figure, FIG. 1 does not show a gate control signal for controlling the IGBT included in each of the rectifier circuit A and the inverter circuit C. As a method for controlling rectifier circuit A and inverter circuit C, a well-known method such as PWM control can be applied. Therefore, detailed description thereof will not be repeated.

  FIG. 2 is a diagram for explaining a balance control method corresponding to a comparative example of the present invention. (A) is a figure for demonstrating operation | movement of IGBT. (B) is a wave form diagram for demonstrating the temporal change of the electric current which flows into a reactor.

Referring to FIG. 2, controller 25A detects a voltage difference between voltage V _P and voltage V _N from voltage V _P detected by voltage detector 47 and voltage V _N detected by voltage detector 48. To do. The controller 25A generates gate control signals G _P and G _N by PWM control based on this voltage difference. The IGBTs 20 and 21 are switched by the gate control signals G _P and G _N so that when one of the IGBTs 20 and 21 is on, the other is off.

  When the positive-side IGBT (IGBT 20) is on, current flows from the positive terminal of the smoothing capacitor 26 and flows into the negative terminal of the smoothing capacitor 26 via the IGBT 20 and the reactor 24. On the other hand, when the negative-side IGBT (IGBT 21) is turned on, current flows from the positive terminal of the smoothing capacitor 27 and flows into the negative terminal of the smoothing capacitor 27 via the reactor 24 and the IGBT 21.

Current I _L represents the current flowing through reactor 24. Current I _L to the positive polarity of the current I _L when flowing to the connection point of the smoothing capacitor 26, 27 from the connection point of IGBT20,21. When on the positive side of the IGBT (IGBT 20), it flows current I _L in the positive direction. On the other hand, at the time on the negative side of the IGBT (IGBT 21), a current I _L flows in the negative direction. For this reason, as shown in FIG. 2B, the polarity of the current I _L changes with time. I _LDC is the time average of the current I _L, which corresponds to the effective value of the current I _L. In FIG. 2B, I _LDC is shown as a negative value, but I _LDC may be a positive value.

In the embodiment of the present invention, controller 25, by switching the IGBT corresponding to the larger of the voltage V _P and the voltage V _N, turn off the other of the IGBT. That is, when V _P > V _N , the controller 25 switches the IGBT 20 to turn off the IGBT 21. Conversely, when V _P <V _N , the controller 25 turns off the IGBT 20 and switches the IGBT 21. Thereby, the current generated when the voltages of the smoothing capacitors 26 and 27 are unbalanced can be reduced. Therefore, loss can be reduced. Below, the concrete structure of the controller 25 which concerns on each embodiment of this invention is demonstrated.

[Embodiment 1]
FIG. 3 is a diagram illustrating the configuration of the controller according to the first embodiment. Referring to FIG. 3, the controller 25 includes a subtracter 50, a duty controller 51, a multiplier 52, duty limiters 53 and 54, and PWM signal generators 55 and 56. The subtractor 50, the duty controller 51, the multiplier 52, and the duty limiters 53 and 54 constitute a duty determining unit.

The subtractor 50 generates a difference (V _P −V _N ) between the voltage V _P and the voltage V _N. The duty controller 51 determines a value V proportional to (V _P −V _N ). The duty controller 51 may output the value of (V _P −V _N ) itself.

The multiplier 52 multiplies the output value V of the duty controller 51 by (−1). When (V _P −V _N )> 0, since the output value V of the duty controller 51 is also a positive value, the output value (= −V) of the multiplier 52 is a negative value. Conversely, when (V _P −V _N ) <0, the output value V of the duty controller 51 is a negative value, so the output value of the multiplier 52 is a positive value.

  The duty limiter 53 determines a duty ratio according to the output value V of the duty controller 51. However, the duty ratio is limited so as not to exceed a certain value. Similarly, the duty limiter 54 determines a duty ratio according to the output value (= −V) of the multiplier 52. The duty ratio is limited so as not to exceed a certain value. In the duty limiters 53 and 54, “D” indicates a duty ratio.

When the input value of each of the duty limiters 53 and 54 is 0 or a negative value, each of the duty limiters 53 and 54 outputs 0 as the duty ratio. As a result, the duty ratio P _bref output from the duty limiter 53 and the duty ratio N _bref output from the duty limiter 54 are both positive values (but do not exceed a certain value).

The PWM signal generator 55 generates the gate control signal _GP based on the duty ratio P _bref . PWM signal generator 56 generates a gate control signal G _N based on the duty ratio N _bref.

  FIG. 4 is a diagram showing a configuration example of the PWM signal generators 55 and 56 shown in FIG. Referring to FIG. 4, PWM signal generator 55 includes a pulse source 57 and modulators 58 and 59. Since the configuration of PWM signal generator 56 is the same as that shown in FIG. 4, the following description will not be repeated.

  The pulse source 57 generates a pulse (for example, a rectangular pulse). The frequency of the pulse is not particularly limited. Further, the duty ratio of the pulse generated from the pulse source 57 is not particularly limited.

The modulator 58 changes the duty ratio of the pulse generated from the pulse source 57 in accordance with the duty ratio P _bref . As a result, the modulation unit 58 generates the gate control signal _GP . Modulator 59 changes the duty ratio of the pulse generated from pulse source 57 in accordance with duty ratio N _bref . Thus the modulation unit 59 generates a gate control signal G _N.

  FIG. 5 is a first diagram for explaining the balance control according to the first embodiment. (A) is a figure for demonstrating operation | movement of IGBT. (B) is a wave form diagram for demonstrating the temporal change of the electric current which flows into a reactor.

3 and 5, when (V _P −V _N )> 0, that is, when V _P > V _N , duty ratio P _bref is a positive value, and duty ratio N _bref is 0. It is. Gate control signal G _P whereas for off according duty ratio P _bref, the gate control signal G _N is always off. Therefore, the IGBT 20 switches and the IGBT 21 remains off. As a result, the smoothing capacitor 26 is discharged, and the smoothing capacitor 27 is charged via the reactor 24.

When the IGBT 20 is turned on, current flows from the positive terminal of the smoothing capacitor 26 and flows into the negative terminal of the smoothing capacitor 26 via the IGBT 20 and the reactor 24. The current I _L flowing through the reactor 24 increases from zero.

When the IGBT 20 is turned off, the IGBT 21 is also turned off. For this reason, the current flows out from the negative terminal of the smoothing capacitor 27 and flows into the positive terminal of the smoothing capacitor 27 via the diode 23 and the reactor 24. In this case, the current I _L decreases to zero. Thus, while only IGBT20 is switched, the polarity of the current I _L is positive.

  FIG. 6 is a second diagram for explaining the balance control according to the first embodiment. (A) is a figure for demonstrating operation | movement of IGBT. (B) is a wave form diagram for demonstrating the temporal change of the electric current which flows into a reactor.

Referring to FIGS. 3 and 6, when (V _P −V _N ) <0, that is, when V _P <V _N , duty ratio P _bref is 0 and duty ratio N _bref is a positive value. It is. Gate control signal G _P whereas always turned off, the gate control signal G _N is off according to the duty ratio N _bref. Therefore, the IGBT 20 remains off and the IGBT 21 is switched. As a result, the smoothing capacitor 27 is discharged, and the smoothing capacitor 26 is charged via the reactor 24.

When the IGBT 21 is on, current flows from the positive terminal of the smoothing capacitor 27 and flows into the negative terminal of the smoothing capacitor 27 via the reactor 24 and the IGBT 21. The absolute value of the current I _L flowing through the reactor 24 increases, and the current I _L changes from 0 to the negative direction.

When the IGBT 21 is turned off, the IGBT 20 is also turned off. Therefore, the current flows out from the negative terminal of the smoothing capacitor 26 and flows into the positive terminal of the smoothing capacitor 26 via the reactor 24 and the diode 22. In this case, the absolute value decreases the current I _L, the current I _L is changed to 0 from a negative value. Thus, while only IGBT21 is switched, the polarity of the current I _L is negative.

  As shown in FIGS. 5 and 6, when the voltage of the smoothing capacitor 26 is larger than the voltage of the smoothing capacitor 27, the controller 25 switches the IGBT 20. Conversely, when the voltage of the smoothing capacitor 27 is higher than the voltage of the smoothing capacitor 26, the controller 25 switches the IGBT 21. Thereby, the voltage imbalance of the smoothing capacitors 26 and 27 can be suppressed.

Further control shown in FIG. 2, regardless of the magnitude relationship between the voltage V _P and the voltage V _N, thereby switching both IGBT20,21. As a result, the current I _L flows through the reactor 24 in the positive direction and the negative direction.

On the other hand, according to the first embodiment, when V _P > V _N , the current I _L flows through the reactor 24 only in the positive direction, and when V _P <V _N , Current I _L flows only in the negative direction. For this reason, the loss in the reactor 24 can be reduced.

Further, in the case shown in FIG. 2, the current I _L changes from positive to negative (or from negative to positive) while one of the IGBTs 20 and 21 is on. For this reason, the amount of change in the current flowing through the IGBT that is turned on increases. Therefore, the loss of the IGBT increases. On the other hand, according to the first embodiment, the current I _L changes between 0 and a positive value, or between 0 and a negative value. Variation of this for the current I _L is smaller than the variation shown in FIG. Therefore, the amount of change in the current flowing through the IGBT that is turned on is also reduced, so that the loss of the IGBT can be reduced.

  Thus, according to 1st Embodiment, the loss of a reactor and IGBT can be reduced. Thereby, since a reactor and IGBT can be reduced in size, a power converter can be reduced in size and weight.

[Embodiment 2]
FIG. 7 is a diagram illustrating the configuration of the controller according to the second embodiment. Referring to FIG. 7, controller 25 includes voltage comparators 61 and 62 and PWM signal generators 55 and 56. The voltage comparators 61 and 62 constitute a duty determining unit.

The voltage comparator 61 compares the voltage V _P with the voltage V _N. When V _P > V _N , the voltage comparator 61 sets the duty ratio (duty) to a constant value D. When V _P ≦ V _N , the voltage comparator 61 sets the duty ratio to zero. The duty ratio determined by the voltage comparator 61 is output from the voltage comparator 61 as the duty ratio P _bref .

Similarly, the voltage comparator 62 compares the voltage V _P with the voltage V _N. When V _N > V _P , the voltage comparator 62 sets the duty ratio (duty) to a constant value D. When V _N ≦ V _P , the voltage comparator 62 sets the duty ratio to zero. The duty ratio determined by the voltage comparator 62 is output from the voltage comparator 62 as the duty ratio N _bref .

The configuration of the PWM signal generators 55 and 56 is the same as that shown in FIGS. When V _P > V _N , P _bref = D and N _bref = 0. Therefore, the gate control signal G _P whereas for off according duty ratio P _bref, the gate control signal G _N is always off. That is, the IGBT 20 switches and the IGBT 21 remains off. Conversely, when V _P <V _N , P _bref = 0 and N _bref = D. Thus the gate control signal G _P whereas always turned off, the gate control signal G _N is off according to the duty ratio N _bref. That is, the IGBT 20 remains off and the IGBT 21 switches.

  Thus, according to the second embodiment, the same control as the control according to the first embodiment can be realized. Therefore, according to the second embodiment, the same effect as in the first embodiment can be obtained.

[Embodiment 3]
FIG. 8 is a diagram illustrating the configuration of the controller according to the third embodiment. 3 and 8, in the third embodiment, controller 25 includes duty limiters 53A and 54A instead of duty limiters 53 and 54. In this respect, the controller according to the third embodiment is different from the controller according to the first embodiment. Other parts of the configuration shown in FIG. 8 are the same as the corresponding parts in FIG. The subtractor 50, the duty controller 51, the multiplier 52, and the duty limiters 53A and 54A constitute a duty determining unit.

The duty limiter 53A differs from the duty limiter 53 in that it has a dead band for the output value V of the duty controller 51, in other words, (V _P −V _N ). That is, when the output value V of the duty controller 51 is greater than 0 and equal to or less than a certain positive predetermined value, the duty ratio P _bref output from the duty limiter 53A is 0. The other points of the duty limiter 53A are the same as those of the duty limiter 53. Therefore, even when the output value V of the duty controller 51 is negative, the duty ratio P _bref is 0.

The duty limiter 54A is different from the duty limiter 54 in that it has a dead band for the output value (−V) of the multiplier 52. That is, when the output value (−V) of the multiplier 52 is greater than 0 and equal to or less than a certain positive predetermined value, the duty ratio N _bref output from the duty limiter 54A is 0. The other points of the duty limiter 54A are the same as those of the duty limiter 54. Therefore, even when the output value (−V) of the multiplier 52 is negative (when V is positive), the duty ratio N _bref is 0.

In the first embodiment, either of the IGBTs 20 and 21 is switched while the voltage V _P and the voltage V _N are not equal. However, according to the third embodiment, when the absolute value of (V _P −V _N ) is equal to or less than a predetermined value, both gate control signals G _P and G _N are turned off. Therefore, even if the voltage V _P is not equal to the voltage V _N , both the IGBTs 20 and 21 are turned off if the absolute value of (V _P −V _N ) is equal to or less than a predetermined value. As a result, in the third embodiment, the time during which both IGBTs 20 and 21 are turned off can be lengthened, so that the loss of chopper circuit B (for example, the loss of the reactor, the loss of the IGBT, etc.) is reduced as compared with the first embodiment. be able to.

[Embodiment 4]
FIG. 9 is a diagram illustrating the configuration of the controller according to the fourth embodiment. 7 and 9, in the fourth embodiment, controller 25 includes voltage comparators 61A and 62A in place of voltage comparators 61 and 62. In this respect, the controller according to the fourth embodiment is different from the controller according to the second embodiment. Other parts of the configuration shown in FIG. 9 are the same as the corresponding parts in FIG. The voltage comparators 61A and 62A constitute a duty determining unit.

The voltage comparator 61A differs from the voltage comparator 61 in that it has a dead band for (V _P −V _N ). When V _P > V _N + ΔV, the voltage comparator 61A sets the duty ratio (duty) to a constant value D. When V _P ≦ V _N + ΔV, the voltage comparator 61A sets the duty ratio to zero. The duty ratio determined by the voltage comparator 61A is output from the voltage comparator 61A as the duty ratio P _bref .

The voltage comparator 62A differs from the voltage comparator 62 in that it has a dead band for (V _P −V _N ). When V _N > V _P + ΔV, the voltage comparator 62A sets the duty ratio (duty) to a constant value D. When V _N ≦ V _P + ΔV, the voltage comparator 62A sets the duty ratio to zero. The duty ratio determined by the voltage comparator 62A is output from the voltage comparator 62A as the duty ratio N _bref .

According to the fourth embodiment, when −ΔV ≦ (V _P −V _N ) ≦ ΔV, the duty ratios P _bref and N _bref are 0. For this reason, since the gate control signals G _P and G _N are turned off, the IGBTs 20 and 21 are turned off. Therefore, in the fourth embodiment, the time during which both IGBTs 20 and 21 are turned off can be lengthened. Therefore, the loss of chopper circuit B (for example, the loss of the reactor, the loss of the IGBT, etc.) can be reduced as compared with the second embodiment. Can do.

  In each of the above embodiments, an IGBT is shown as the semiconductor switch element. However, the semiconductor switch element is not limited to the IGBT, and may be a MOSFET, for example.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 AC power source, 2 to 4, 43 to 45 capacitor, 5 to 7, 24, 40 to 42 reactor, 8, 9, 12, 13, 16, 17, 22, 23, 30, 31, 31, 34, 35, 38, 39 diode, 10, 11, 14, 15, 18 to 21, 28, 29, 32, 33, 36, 37 IGBT, 25, 25A controller, 26, 27 smoothing capacitor, 46 load, 47, 48 voltage detector, 50 Subtractor, 51 Duty controller, 52 Multiplier, 53, 54, 53A, 54A Duty limiter, 55, 56 PWM signal generator, 57 Pulse source, 58, 59 Modulator, 61, 62, 61A, 62A Voltage comparison , 101 power converter, A rectifier circuit, B chopper circuit, C inverter circuit, N neutral wire.

Claims (5)

A power converter,
First and second semiconductor switching elements connected in series between the positive phase and the negative phase of a three-wire direct current having a positive phase, a negative phase and a neutral phase;
First and second diodes connected in antiparallel to the first and second semiconductor switch elements, respectively;
A first capacitor connected between the positive phase and the neutral phase;
A second capacitor connected between the neutral phase and the negative phase;
A reactor connected between the neutral phase and a connection point of the first and second semiconductor switch elements;
A power conversion circuit connected to the positive phase and the negative phase to perform power conversion between alternating current and direct current;
A voltage detector for detecting a first voltage of the first capacitor and a second voltage of the second capacitor;
A controller for controlling the first and second semiconductor switch elements based on the detected first and second voltages,
The controller switches the first semiconductor switch element to turn off the second semiconductor switch element when the first voltage is greater than the second voltage, and the second voltage is A power conversion device that switches the second semiconductor switch element to turn off the first semiconductor switch element when the voltage is higher than the first voltage. The controller is
A first duty ratio of a first control signal for controlling the first semiconductor switch element and a second duty ratio of a second control signal for controlling the second semiconductor switch element Including a duty determining unit for determining,
When the first voltage is greater than the second voltage, the duty determination unit sets the first duty ratio according to a voltage difference between the first voltage and the second voltage. And setting the second duty ratio to 0,
When the second voltage is greater than the first voltage, the duty determination unit sets the second duty ratio according to a voltage difference between the first voltage and the second voltage. The power conversion device according to claim 1, wherein the first duty ratio is set to 0 while being set. The controller is
A first duty ratio of a first control signal for controlling the first semiconductor switch element and a second duty ratio of a second control signal for controlling the second semiconductor switch element Including a duty determining unit for determining,
The duty determination unit sets the first duty ratio to a predetermined value different from 0 and sets the second duty ratio to 0 when the first voltage is greater than the second voltage. ,
The duty determination unit sets the second duty ratio to a value different from 0 and sets the first duty ratio to 0 when the second voltage is larger than the first voltage. The power conversion device according to claim 1. The controller is
A first duty ratio of a first control signal for controlling the first semiconductor switch element and a second duty ratio of a second control signal for controlling the second semiconductor switch element Including a duty determining unit for determining,
When the voltage difference between the first voltage and the second voltage is within a predetermined range across 0, the duty determination unit sets both the first and second duty ratios to 0. Set to
When the first voltage is larger than the second voltage and the voltage difference between the first voltage and the second voltage is outside the predetermined range, the duty determination unit Setting the first duty ratio according to a voltage difference between the first voltage and the second voltage and setting the second duty ratio to 0;
When the second voltage is larger than the first voltage and the voltage difference between the first voltage and the second voltage is outside the predetermined range, the duty determination unit 2. The power conversion according to claim 1, wherein the second duty ratio is set according to a voltage difference between the first voltage and the second voltage, and the first duty ratio is set to 0. 3. apparatus. The controller is
A first duty ratio of a first control signal for controlling the first semiconductor switch element and a second duty ratio of a second control signal for controlling the second semiconductor switch element Including a duty determining unit for determining,
When the voltage difference between the first voltage and the second voltage is within a predetermined range across 0, the duty determination unit sets both the first and second duty ratios to 0. Set to
When the first voltage is larger than the second voltage and the voltage difference between the first voltage and the second voltage is outside the predetermined range, the duty determination unit Setting the first duty ratio to a predetermined value different from 0 and setting the second duty ratio to 0;
When the second voltage is larger than the first voltage and the voltage difference between the first voltage and the second voltage is outside the predetermined range, the duty determination unit The power converter according to claim 1, wherein the second duty ratio is set to a value different from 0 and the first duty ratio is set to 0.

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