JP2013162018A - Resistance change type memory element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance change type memory element capable of restraining deterioration of reliability.SOLUTION: A resistance change type memory element according to the present embodiment comprises: a first electrode; a second electrode having a metal element; and a resistance change layer having a first layer provided between the first electrode and the second electrode and including amorphous silicon, and a second layer provided between the first layer and the first electrode and including polypyrrole or its derivative.

Description

  Embodiments described herein relate generally to a resistance change memory element.

  Currently, the flash memory, which is the mainstream of the nonvolatile memory technology, has the disadvantage that the device structure is complex and high integration is not easy compared to other memory devices. In order to solve such a problem, ReRAM (Resistive Random Access Memory) having a resistance change type memory element having a simple metal / resistance change layer / metal structure as a memory cell has been actively studied recently. In particular, ReRAM using a layer containing amorphized silicon (a-Si) of a semiconductor as a resistance change layer of a resistance change type memory element is manufactured using a conventional silicon as a main material since the main material is silicon. Since the method can be diverted, there is an advantage that an increase in manufacturing cost due to introduction of a new material can be suppressed.

  As will be described later, the resistance change type memory element has a problem that the reliability of the ReRAM is lowered.

US Patent Application Publication No. 2009/0014707

  The present embodiment provides a resistance change type memory element that can suppress a decrease in reliability.

  The variable resistance element according to the present embodiment includes a first electrode, a second electrode having a metal element, a first layer including amorphous silicon provided between the first electrode and the second electrode, And a resistance change layer having a second layer containing polypyrrole or a derivative thereof provided between the first layer and the first electrode.

1 is a cross-sectional view showing a resistance change type memory element according to a first embodiment; Sectional drawing which shows the resistance change type memory element by the 1st modification of 1st Embodiment. Sectional drawing which shows the resistance change type memory element by the 2nd modification of 1st Embodiment. Sectional drawing which shows the resistance change type memory element by a comparative example. FIG. 5A and FIG. 5B are schematic views showing cross sections of the resistance change layer in the resistance change type memory element of the first embodiment and the comparative example, respectively. FIG. 6A and FIG. 6B are schematic views showing energy bands and state density distributions of the resistance change layers of the first embodiment and the comparative example, respectively. FIGS. 7A to 7D are views showing chemical structural formulas showing examples of molecules of materials used for the hole injection suppressing layer. The schematic diagram which shows a resistance change layer at the time of using the material shown to Fig.7 (a) as a hole injection suppression layer. FIG. 9A and FIG. 9B are a plan view and a cross-sectional view, respectively, showing the resistance change type memory according to the second embodiment. The figure explaining the write-in method of the resistance change type memory of 2nd Embodiment. The figure explaining the read-out method of the resistance change memory of 2nd Embodiment. The figure explaining the erasing method of the resistance change memory of 2nd Embodiment. Sectional drawing which shows the resistance change type memory of 3rd Embodiment.

  Before explaining the embodiment, the background to the embodiment will be described.

  The present inventors have examined the case where a layer containing amorphous silicon (a-Si) of a semiconductor is used as a resistance change layer of a resistance change memory element having a metal / insulator layer / metal (MIM) structure. As a result, the metal filament formed in the a-Si layer is oxidized by holes injected from a layer adjacent to the a-Si layer even when no bias is applied to the resistance change type memory element. The inventors have discovered. Furthermore, the present inventors have found that oxidation of the metal filament raises the resistance of the resistance change type memory element, causing a problem that the memory effect is lost and the reliability of the ReRAM is lowered. Accordingly, the present inventors have sought hard research and invented a resistance change memory element that makes it possible to suppress a decrease in the reliability of the ReRAM. This will be described in the following embodiment.

  Embodiments will be described below with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and detailed description is abbreviate | omitted suitably.

(First embodiment)
A resistance change type memory element (hereinafter also referred to as a memory element) according to the first embodiment is shown in FIG. FIG. 1 is a cross-sectional view of the memory element of the first embodiment. The memory element 1 according to the first embodiment includes a first electrode 2, a second electrode 8, and a resistance change layer 4 provided between the first electrode 2 and the second electrode 8. The resistance change layer 4 is provided on the first electrode 2 side, a polysilicon layer 4a doped with a high concentration of p-type impurities, an a-Si layer 4b provided on the second electrode 8 side, and a polysilicon layer 4a. And a hole injection suppression layer 4c provided between the a-Si layer 4b. The second electrode 8 is partially in contact with the a-Si layer 4b, and the other part is provided with the insulating layer 6 between the a-Si layer 4b. That is, a through hole is provided in the insulating layer 6, and a part of the second electrode 8 is in contact with the a-Si layer 4b through the through hole. Note that, as in the first modification of the first embodiment shown in FIG. 2, the insulating layer 6 is not provided, and all the opposing surfaces of the second electrode 8 are in contact with the a-Si layer 4b. Also good.

  The memory device 1 of the first embodiment shown in FIG. 1 includes a first electrode 2, a polysilicon layer 4a, a hole injection suppression layer 4c, an a-Si layer 4b, an insulating layer 6, and a second electrode 8 stacked in this order. However, the second electrode 8, the insulating layer 6, the a-Si layer 4b, the hole injection suppressing layer 4c, the polysilicon layer 4a, and the first electrode 2 are stacked in the reverse order. The structure laminated | stacked in this order may be sufficient.

  As the first electrode 2, a metal other than that used for the second electrode 8, for example, a metal containing at least one element of Au (gold), W (tungsten), Al (aluminum), or Au (gold), A silicide, nitride, boride, carbide, or the like containing at least one element of W (tungsten), Ti (titanium), Ag (silver), Al (aluminum), and Ni (nickel) can be used. However, it is not limited to these.

  The second electrode 8 is preferably a metal having a large diffusion coefficient, for example, a metal containing at least one element of Ag, Ni, and Ti, but is not limited thereto.

  In addition to the three-layer structure shown in FIG. 1, the resistance change layer 4 may have a two-layer structure obtained by removing the polysilicon layer 4a from the three-layer structure shown in FIG. 1, but is not limited thereto. The polysilicon layer 4a is preferably a p-type impurity doped at a high concentration. However, a polysilicon layer doped with a low concentration of p-type impurities or a polysilicon layer doped with n-type impurities can be used. A memory element 1 in which the resistance change layer 4 has a two-layer structure excluding the polysilicon layer 4a is shown in FIG. 3 as a second modification of the first embodiment.

  The a-Si layer 4b is preferably undoped a-Si. However, those containing an impurity element other than silicon, those doped with p-type impurities or n-type impurities, those containing single crystal Si or polycrystalline Si in a part of each form, and parts or the whole of each form Those obtained by oxidizing, nitriding, and carbonizing can also be used. The material of the hole injection suppression layer 4c will be described later in detail.

  The insulator layer 6 can use silicon oxide or silicon nitride, but is not limited thereto.

  The effect of this embodiment will be described with reference to FIGS. 4 to 6B. FIG. 4 is a cross-sectional view showing a comparative example of the memory element of this embodiment. The memory element 100 of this comparative example uses a resistance change layer 104 having a two-layer structure in which the hole injection suppression layer 4c is deleted instead of the resistance change layer 4 in the memory element 1 of the first embodiment shown in FIG. It has a configuration.

  Sectional views of the resistance change layer 4 of the first embodiment and the resistance change layer 104 of the comparative example are shown in FIGS. 5A and 5B, respectively. As shown in FIG. 5A, the forward bias voltage (also referred to as write voltage), that is, the potential applied to the second electrode 8 is high in the memory element 1 of the first embodiment, and the potential applied to the first electrode 2. By applying a voltage Vset that lowers the value, the metal filament 5 that penetrates the a-Si layer 4b from the second electrode 8 and reaches the hole injection suppression layer 4c is formed. Further, when the write voltage Vset is applied to the memory element 100 of the comparative example, the metal filament 5 that penetrates the a-Si layer 4b from the second electrode 8 and reaches the polysilicon layer 4a is formed.

  The electrical resistance of the memory element 1 of the first embodiment is that of the first and second electrodes 2 and 8, the electrical resistance of the metal filament 5, the electrical resistance of the hole injection suppression layer 4c, and the polysilicon layer 4a. It is the sum of electrical resistance. The electric resistance of the memory element 100 of the comparative example is the sum of the electric resistance of the first and second electrodes 2 and 8, the electric resistance of the metal filament 5, and the electric resistance of the polysilicon layer 4a. For this reason, the metal filament 5 functions to lower the resistance of the memory element. The states shown in FIGS. 5A and 5B are the write state (low resistance state) in the first embodiment and the comparative example, respectively. From this writing state, the low resistance (writing) state is maintained even after the bias voltage Vset is set to 0V.

  By applying a reverse bias voltage (also referred to as erase voltage) Vreset to the memory element in the written state, holes are injected from the first electrode into the a-Si layer 4b. Then, the metal filament 5 is oxidized and the resistance of the memory element is increased. This is the erased state (high resistance state). Even after the erase voltage Vreset is set to 0V, the high resistance state is maintained.

  Reading is performed by applying a read voltage Vread in the forward direction and determining whether the memory element is in the low resistance state or the high resistance state based on the value of the read current Iread.

Specifically, in the first embodiment shown in FIG. 1, a silver silicide is used for the first electrode 2 and p ⁺ poly having a thickness of 20 nm doped with 10 ²¹ atoms cm ⁻² of boron as the polysilicon layer 4a. Silicon is used, and an a-Si layer having a thickness of 20 nm is used as the a-Si layer 4b. A self-assembled monolayer (Self-Assembled Monolayer (hereinafter also referred to as SAM layer)) having a thickness of 3.0 nm is used as the hole injection suppressing layer 4c, and an oxide having a through hole with a diameter of 100 nm as the insulating layer 6 is used. Silicon was used as the second electrode 8. Then, when the write voltage Vset = 6.0V is applied, the state transits to the write state. Thereafter, when the erase voltage Vreset = -4.0 V is applied, the state transits to the erase state. When reading is performed with the read voltage Vread = 2.0 V, the read current Iread is about 10 nA when the memory element is in the write state, and the read current Iread is about 0.1 nA when the memory element is in the erase state.

In the comparative example shown in FIG. 4, when left after the written state, a transition from the written state to the erased state occurs. However, in the first embodiment, the transition from the write state to the erase state can be prevented. This will be described with reference to FIGS. 6 (a) and 6 (b). FIGS. 6A and 6B are diagrams showing energy bands and state density distributions when no bias is applied in the first embodiment and the comparative example, respectively. In the comparative example, as shown in FIG. 6B, holes h ⁺ are injected into the metal filament 5 from the upper end of the valence band of the polysilicon layer 4a. In contrast, in the first embodiment, as shown in FIG. 6A, holes h ⁺ are injected from the upper end of the valence band of the polysilicon layer 4a into the hole injection suppressing layer 4c. Since there is an appropriate energy difference between the hole injection suppression layer 4c and the a-Si layer 4b and the metal filament 5 in the a-Si layer 4b, the amount of hole injection into the metal filament 5 in the first embodiment Is suppressed as compared with the comparative example. As a result, in the first embodiment, it is possible to suppress an increase in the resistance of the memory element and prevent the memory effect from being lost when left unattended.

  The property of the hole injection suppression layer 4c having an appropriate energy difference between the a-Si layer 4b and the metal filament 5 in the a-Si layer 4b is the ionization potential of the substance constituting the hole injection suppression layer 4c ( IP). The energy at the lower end of the conduction electron band and the upper end of the valence band of the a-Si layer 4b is approximately 4.0 eV and 5.2 eV, respectively, in accordance with crystalline silicon. When the a-Si layer 4b is undoped, The Fermi level of the metal filament 5 in the Si layer 4b is located at about 4.5 eV. When the IP value of the hole injection suppressing layer 4c is smaller than the Fermi level of the metal filament 5 and larger than the lower end of the conduction electron band of the a-Si layer 4b, holes injected from the first electrode 2 into the polysilicon layer 4a. Is trapped by the hole injection suppressing layer 4c, so that hole injection into the a-Si layer 4b or the metal filament 5 is suppressed. That is, the IP value of the hole injection suppression layer is preferably 4.0 eV to 4.5 eV.

  Generally, the IP value of a substance corresponds to the highest occupied level (Highest Occupied Molecular Orbital) measured from the vacuum level, and in the case of a molecular substance, it has a unique value that reflects the molecular structure. The value of IP in the thin film can be easily measured by, for example, photo-electron spectroscopy in air. For example, Non-Patent Document 1 describes IP values of substances centering on various organic molecules used in organic electronic devices (for example, “Chiyado Adachi, Takato Koyamada, Yoshiyuki Nakajima,“ Organic Organic thin-film work function data collection for electronic device researchers [2nd edition] ”, see CMC Publishing March 2006). The IP value can also be obtained with high accuracy by theoretical calculation. For example, Non-Patent Document 2 describes a value obtained by calculating the IP value of a conductive polymer by a VEH (Valence Effective Hamiltonian) method, which is a kind of Huckle method, which is a typical molecular orbital calculation method (for example, J. Pat. -See L. Bredas, “Handbook of Conducting Polymers”, p881, Marcel Dekker, New York (1986)).

  Next, the material of the hole injection suppression layer 4c will be described. Examples of chemical structural formulas of molecules of materials used for the hole injection suppressing layer 4c are shown in FIGS. 7 (a) to 7 (d). One type of molecule is selected from the molecules shown in FIGS. 7A to 7D, and the monomolecular layer is formed. That is, the hole injection suppression layer 4c is formed by arranging these molecules two-dimensionally and having substantially only a single molecule in the thickness direction. The a-Si layer 4b can be formed from the outside on the first electrode 2 side, that is, on the surface of the polysilicon layer 4a in the first embodiment shown in FIG. In particular, when the monomolecular layer is composed of organic molecules, a self-assembled monolayer (hereinafter also referred to as a SAM layer) is used because it has excellent coverage and forms a uniform interface. be able to. The SAM layer is thermally stable and can also prevent molecular diffusion. Furthermore, when the organic molecule is linear and has an appropriate length, the arrangement tends to be more regular. In order to form an aligned SAM layer, it is desirable to use molecules having a carbon number in the range of 10 to 20 in the linear direction. 7A to 7D, it is desirable that the polymerization degree n is 3 to 5. As a result, the thickness of the hole injection suppression layer 4c formed of the SAM layer is about 3.0 nm to 5.0 nm. Although the IP value of the conjugated molecule greatly varies depending on the number of benzene rings, if it is a linear type, the number is 4 or more and approaches the value of the polymer, so that n> 2 in FIGS. 7 (a) to 7 (d). In that case, polymer values can be used.

  In general, many organic molecules have an IP value of 5.0 eV to 6.0 eV. Examples of organic molecules having an IP value in the range of 4.0 eV <IP <4.5 eV include polypyrrole and derivatives thereof. The polypyrrole shown in FIG. 7 (a) has an IP value of about 4.0 eV, and the substitution products shown in FIGS. 7 (b) and 7 (c) are poly-1-methylpyrrole, poly-3-methylpyrrole, poly-4- Polythionylpyrrole, a copolymer of methylpyrrole and thiophene having different heterocycles shown in FIG. 7 (d), changes the electronic structure and exhibits an IP value that is about 0.1 eV to 0.5 eV higher than polypyrrole. For example, the IP value of the molecule shown in FIG. 7D is about 4.5 eV which is an intermediate value between the IP value of polypyrrole and the IP value of polythiophene of about 5.0 eV. Note that polypyrrole derivatives are not limited to those shown in FIGS. 7A to 7D, and other derivatives may be used.

  The hole injection suppression layer 4c using polypyrrole and its derivatives is an insulator having an energy gap of about 3.0 eV, but is a π-electron conjugated system, so that it can be easily formed by doping with halogen molecules such as iodine and bromine. The conductivity can be controlled. Polypyrrole is a conductive polymer having high thermal stability, and its thermal decomposition temperature is about 300 ° C.

Note that examples of molecules that form SAM on a metal or compound semiconductor include organic sulfur molecules and organic selenium / tellurium molecules. Examples of organic sulfur molecules include
Alkylthiol; R-SH, R = C2n + 1Hn,
Dialkyldisulfide; RS-SR ′
Thioisocyanide; R-SCN
Etc.

Examples of organic selenium and tellurium molecules include
Alkylselenolate, tellurolate; R-SeH, R-TeH
Dialkyldiselenide; R-Se-SeR '
Etc.

  FIG. 8 shows a schematic diagram of the resistance change layer 4 when the material shown in FIG. 7A is used as the hole injection suppression layer 4c. FIG. 8 shows a case where the polymerization degree n is 3.

  As described above, according to the first embodiment, by providing the hole injection suppression layer, it is possible to prevent the metal filament from being oxidized, and it is possible to suppress the decrease in the reliability of the ReRAM. .

(Second Embodiment)
Next, a resistance change type memory according to the second embodiment will be described with reference to FIGS. A resistance change type memory (hereinafter also referred to as a memory) according to the second embodiment is a cross-point type memory, and the resistance change type memory element 1 according to the first embodiment and the first and second modifications thereof are used as memory cells. The resistance change type memory element 1 is used. FIG. 9A is a plan view showing a schematic configuration of the memory cell array 30 of the memory according to the second embodiment, and FIG. 9B is a cross-point portion (intersection region) of the memory cell array 30 shown in FIG. It is sectional drawing which shows schematic structure of these.

9A and 9B, the memory cell array 30 includes a lower wiring 31.
Are formed in the column direction, and the upper wiring 34 is formed in the row direction. A memory element 1 according to the first modification of the first embodiment is disposed at a cross point portion between the lower wiring 31 and the upper wiring 34. That is, a memory element in which the first electrode 2, the polysilicon layer 4a, the hole injection suppression layer 4c, the a-Si layer 4b, and the second electrode 8 are stacked in this order in the intersection region of the lower wiring 31 and the upper wiring 34. 1 is arranged.

  FIG. 10 is a plan view for explaining a voltage setting method when writing a selected cell in the memory cell array 30 shown in FIG. In FIG. 10, a control unit 35 that performs row selection and a control unit 36 that performs column selection are provided around the memory cell array 30. When writing to the selected cell, a set voltage (write voltage) Vset is applied to the lower wiring 31 in the selected column, and a voltage ½ of the set voltage Vset is applied to the lower wiring 31 in the non-selected column. Further, 0 V is applied to the upper wiring 34 in the selected row, and a voltage that is ½ of the set voltage Vset is applied to the upper wiring 34 in the non-selected row.

  As a result, the set voltage Vset is applied to the selected cell designated by the selected column and the selected row, and writing is performed. On the other hand, a half voltage of the set voltage Vset is applied to the half-selected cell specified by the non-selected column and the selected row, and writing is prohibited. Further, a half voltage of the set voltage Vset is applied to the half-selected cell designated by the selected column and the non-selected row, and writing is prohibited. Further, 0 V is applied to unselected cells designated by unselected columns and unselected rows, and writing is prohibited.

  FIG. 11 is a plan view for explaining a voltage setting method at the time of reading a selected cell in the memory cell array 30 shown in FIG. In FIG. 11, when reading the selected cell, a voltage that is ½ of the read voltage Vread is applied to the lower wiring 31 of the selected column, and 0 V is applied to the lower wiring 31 of the non-selected column. Further, a voltage that is −1/2 of the read voltage Vread is applied to the upper wiring 34 of the selected row, and 0 V is applied to the upper wiring 34 of the non-selected row.

  As a result, the read voltage Vread is applied to the selected cell designated by the selected column and the selected row, and reading is performed. On the other hand, a voltage that is -1/2 of the read voltage Vread is applied to the half-selected cells specified by the non-selected columns and the selected rows, and reading is prohibited. Further, a half voltage of the read voltage Vread is applied to the half-selected cells designated by the selected column and the non-selected row, and reading is prohibited. Further, 0 V is applied to unselected cells designated by unselected columns and unselected rows, and reading is prohibited.

  FIG. 12 is a plan view for explaining a voltage setting method at the time of erasing a selected cell in the memory cell array 30 shown in FIG. In FIG. 12, when erasing a selected cell, a reset voltage (erase voltage) Vreset is applied to the lower wiring 31 of the selected column, and a voltage ½ of the reset voltage Vreset is applied to the lower wiring 31 of the non-selected column. . Further, 0 V is applied to the upper wiring 34 in the selected row, and a voltage ½ of the reset voltage Vreset is applied to the upper wiring 34 in the non-selected row.

  As a result, the reset voltage Vreset is applied to the selected cell designated by the selected column and the selected row, and erasing is performed. On the other hand, a half voltage of the reset voltage Vreset is applied to the half-selected cell specified by the non-selected column and the selected row, and erasure is prohibited. Further, a half voltage of the reset voltage Vreset is applied to the half-selected cells designated by the selected column and the non-selected row, and erasing is prohibited. Further, 0 V is applied to unselected cells designated by unselected columns and unselected rows, and erasure is prohibited.

  Since the resistance change type memory according to the second embodiment includes the memory elements according to the first embodiment and the first and second modifications, it is possible to suppress a decrease in reliability.

(Third embodiment)
Next, a resistance change type memory (hereinafter also referred to as a memory) according to a third embodiment will be described with reference to FIG. The memory according to the third embodiment has at least one memory cell, and FIG. 13 shows a cross-sectional view of the memory cell. The memory cell 40 includes the memory element 1 according to the first embodiment and any of the first and second modifications as a memory element, and one transistor Tr connected to the memory element 1. .

  The transistor Tr includes a source / drain region 202 formed apart from the semiconductor region 200, and a gate electrode WL provided via a gate insulating film on a semiconductor region serving as a channel region between the source region and the drain region. And. The gate electrode WL also serves as a word line WL for selecting the memory cell 40.

  One end of a contact plug P1 is connected to one of the source / drain regions 202. A lead electrode LE is connected to the other end of the contact plug P1. The memory element 1 according to the first modification of the first embodiment is provided on the extraction electrode LE. That is, the memory element 1 in which the first electrode 2, the polysilicon layer 4a, the hole injection suppression layer 4c, the a-Si layer 4b, and the second electrode 8 are stacked in this order is provided on the extraction electrode LE. . A bit line BL is connected to the second electrode 8. The bit line BL and the word line WL are arranged so as to intersect. Note that an interlayer insulating film is formed around the transistor Tr and the memory element 1.

  In this memory, in order to perform write, read, and erase operations, a voltage is applied to the word line WL, the transistor Tr is turned on, and the method described in the first embodiment is performed.

  Since the resistance change type memory according to the third embodiment includes the memory elements according to the first embodiment and the first and second modifications, it is possible to suppress a decrease in reliability.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the invention described in the claims and equivalents thereof as well as included in the scope and gist of the invention.

DESCRIPTION OF SYMBOLS 1 Resistance change type memory element 2 1st electrode 4 Resistance change layer 4a Polysilicon layer 4b Amorphous silicon layer (a-Si layer)
4c Hole injection suppression layer 5 Metal filament 6 Insulating layer 8 Second electrode

Claims (5)

A first electrode;
A second electrode having a metal element;
A first layer containing amorphous silicon provided between the first electrode and the second electrode; a second layer containing polypyrrole or a derivative thereof provided between the first layer and the first electrode; A resistance change layer having:
A resistance change type memory element comprising: A first electrode;
A second electrode having a metal element;
A first layer including amorphous silicon provided between the first electrode and the second electrode; a second layer including a hole injection suppression material provided between the first layer and the first electrode; A resistance change layer having:
A resistance change type memory element comprising:   The resistance change type memory device according to claim 2, wherein the second layer is a self-assembled monolayer.   4. The resistance change type memory element according to claim 2, wherein the second layer contains an organic molecular compound having an ionization potential IP in a range of 4.0 eV <IP <4.5 eV. .   The resistance change type memory element according to claim 1, further comprising a polysilicon layer provided between the first electrode and the second layer.

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