JP2013161487A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of narrowing the threshold distribution of memory cells.SOLUTION: According to an embodiment, a nonvolatile semiconductor storage device includes: a plurality of memory cells; a plurality of word lines and a plurality of bit lines that are used for controlling the memory cells. Furthermore, the device includes a control unit that applies a write voltage to a first word line out of the plurality of word line one or more times to write data to within the memory cells on the first word line; and after writing data to within the memory cells on the first word line, applies an additional voltage to the first word line one or more times. In writing to a second word line after writing to the first word line, the control unit writes data within the memory cells on the second word lines, sets the plurality of bit lines to a non-selected state or selected state, and then applies the additional voltage to the second word line.

Description

  Embodiments described herein relate generally to a nonvolatile semiconductor memory device.

  In recent years, with the miniaturization of non-volatile memories, the inter-cell interference effect has increased and the threshold distribution of memory cells has become wider. Further, since the withstand voltage of the memory cell is reduced due to the miniaturization of the nonvolatile memory, the upper limit of the write voltage is lowered, and it is difficult to obtain a high voltage threshold distribution. In particular, in the multi-value method, since it is necessary to create a plurality of threshold distributions that tend to increase within the narrowed threshold range, the difficulty of writing increases. Therefore, it is a problem to narrow the threshold distribution.

JP 2007-207333 A

  A nonvolatile semiconductor memory device capable of narrowing the threshold distribution of memory cells is provided.

  According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of memory cells, and a plurality of word lines and a plurality of bit lines for controlling the memory cells. Furthermore, the device applies a write voltage to the first word line of the plurality of word lines one or more times to write data in the memory cells on the first word line, and And a controller that applies an additional voltage to the first word line one or more times after the data is written into the memory cell on the word line. Further, when writing to the second word line after writing to the first word line, the control unit writes the data in the memory cell on the second word line, and then The additional voltage is applied to the second word line with the bit line in a non-selected state or a selected state.

1 is a circuit diagram illustrating a structure of a nonvolatile semiconductor memory device according to a first embodiment. 1 is a schematic cross-sectional view showing a structure of a NAND cell unit according to a first embodiment. FIG. 3 is a flowchart illustrating a method for controlling the nonvolatile semiconductor memory device according to the first embodiment. 4 is a graph showing a write voltage and an additional voltage in the first embodiment. It is the graph which showed the threshold value distribution of the memory cell in 1st Embodiment. It is the graph which showed the relationship between the additional voltage application frequency in 1st Embodiment, and threshold value distribution width | variety. It is a flowchart figure which shows the control method of the non-volatile semiconductor memory device of 2nd Embodiment. It is the graph which showed the write-in voltage and additional voltage in 2nd Embodiment. It is the graph which showed the threshold value distribution of the memory cell in 2nd Embodiment. It is the graph which showed the relationship between the frequency | count of additional voltage application in 2nd Embodiment, and threshold value distribution width | variety. It is the graph which showed the write-in voltage and additional voltage in 3rd Embodiment. It is the graph which showed the write-in voltage and additional voltage in the modification of 1st Embodiment. It is the graph which showed the write voltage and additional voltage in the modification of 2nd Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing the structure of the nonvolatile semiconductor memory device according to the first embodiment. The nonvolatile semiconductor memory device in FIG. 1 is a NAND flash memory.

  The nonvolatile semiconductor memory device of FIG. 1 includes a memory cell array 1, a sense amplifier (SA) circuit 2, a row decoder 3, an input / output (I / O) buffer 4, a controller 5, a voltage generation circuit 6, A ROM fuse 7 and a data storage circuit 8 are provided.

  The memory cell array 1 has a plurality of memory blocks BLK0 to BLKi (i is an integer of 2 or more) formed on the same well. As shown in FIG. 1, each memory block BLK is configured by arranging a plurality of NAND cell units 11 extending in the Y direction in the X direction. Furthermore, each NAND cell unit 11 includes a plurality of memory cells MC0 to MC63 connected in series, and select transistors S1 and S2 connected to both ends thereof.

  FIG. 1 shows word lines WL0 to WL63 and select gate lines SGS and SGD for the memory block BLK0. The word lines WL0 to WL63 are connected to the control gates of the memory cells MC0 to MC63, respectively, and all extend in the X direction. The selection gate lines SGS and SGD are connected to the gates of the selection transistors S1 and S2, respectively, and both extend in the X direction. These word lines WL0 to WL63 and select gate lines SGS and SGD are common to a plurality of NAND cell units 11 adjacent in the X direction.

  Further, the source of each selection transistor S1 in the memory block BLK0 is connected to the same source line SL. Further, the drain of each selection transistor S2 in the memory block BLK0 is connected to the corresponding bit lines BL0 to BLj (j is an integer of 2 or more). As shown in FIG. 1, the source line SL extends in the X direction, and the bit lines BL0 to BLj extend in the Y direction.

  The sense amplifier circuit 2 is a circuit that reads data from the memory cell MC through the bit lines BL0 to BLj, and includes a plurality of sense amplifiers 12. The row decoder 3 is a circuit that selects and drives either a word line or a selection gate line. The input / output buffer 4 is a circuit that exchanges data between the sense amplifier circuit 2 and the external input / output terminals and receives command data and address data from the controller 5.

  The controller 5 is a control unit that performs various controls on the memory cell array 1. For example, the controller 5 receives external control signals such as a write enable signal WEn, a read enable signal REn, an address latch enable signal ALE, and a command latch enable signal CLE from a host or a memory controller (MH), and performs operations such as writing and reading. Control.

  The voltage generation circuit 6 includes a plurality of booster circuits 21 and a pulse generation circuit 22. The voltage generation circuit 6 switches the number of boosting circuits 21 to be driven based on a control signal from the controller 5. The voltage generation circuit 6 controls the pulse generation circuit 22 to adjust the pulse width and pulse height of the pulse voltage.

  The ROM fuse 7 is a storage unit for storing set values of the pulse width and pulse height of the pulse voltage at the time of writing and erasing. The data storage circuit 8 is a rewritable nonvolatile storage circuit for storing various data for control of the memory cell array 1.

  FIG. 2 is a schematic cross-sectional view showing the structure of the NAND cell unit 11 of FIG.

  Memory cells MC <b> 0 to MC <b> 63 and select transistors S <b> 1 and S <b> 2 are formed on well 102 in semiconductor substrate 101, and are connected in series by diffusion layer 103 in well 102. These transistors are covered with an interlayer insulating film 121.

  Each memory cell MC includes a charge storage layer (for example, a floating gate) 112 formed on the semiconductor substrate 101 via a gate insulating film 111 and a control formed on the charge storage layer 112 via an inter-gate insulating film 113. And an electrode (for example, a control gate) 114. Each of the select transistors S1 and S2 has a gate electrode 116 formed on the semiconductor substrate 101 with a gate insulating film 115 interposed therebetween.

  Note that the charge storage layer 112 may be an insulating film (for example, a silicon nitride film) having a charge storage function.

(1) Control Method of Nonvolatile Semiconductor Memory Device Hereinafter, a control method of the nonvolatile semiconductor memory device of the first embodiment will be described with reference to FIGS.

  FIG. 3 is a flowchart illustrating the method for controlling the nonvolatile semiconductor memory device according to the first embodiment.

  FIG. 3 shows a control method when data is written in each memory cell MC on the word line WLn (n is an integer of 0 or more). The control in FIG. 3 is performed by the controller 5, the sense amplifier 2, and the row decoder 3. The controller 5, the sense amplifier 2, and the row decoder 3 are examples of control units. The controller 5, the sense amplifier 2, and the row decoder 3 may include the voltage generation circuit 6 as a control unit.

  The word line WLn is an example of the second word line, and the word line to which writing is performed before the word line WLn is an example of the first word line. Normally, writing can be performed in the order of the word lines WL0, WL1,... WL62, WL63. In this case, the word line WLn−1 to be written before the word line WLn is the first word line. It is an example.

  FIG. 4 is a graph showing the write voltage and the additional voltage in the first embodiment.

  At the time of writing, a write voltage (Vpgm) or an additional voltage (Vadd) is applied to the word line WLn. As shown in FIG. 4, the value of the write voltage increases according to the number of times of application of the write voltage. Similarly, the value of the additional voltage increases according to the number of times of application of the additional voltage. The operation in which the write voltage and the additional voltage increase may be referred to as “step-up operation”.

  Hereinafter, the flowchart of FIG. 3 will be described. In the description of FIG. 3, the graph of FIG. 4 is also referred to as appropriate.

  First, among all the bit lines BL in the memory cell array 1, all the bit lines BL to be written are set to a selected state, and the other bit lines BL are set to a non-selected state (step S101). Here, the selected state is a state in which data is written to the memory cell MC (the threshold voltage of the memory cell MC is increased), and the non-selected state is a state in which data is not written to the memory cell MC (the threshold value of the memory cell MC). The voltage is hardly increased. For example, in the selected state, the control unit applies 0 V to the bit line BL, and in the non-selected state, the control unit applies a power supply voltage to the bit line BL. Next, the write voltage Vpgm is applied to the word line WLn (step S102). In the first write, the write voltage value is set to Vpgm1 (see FIG. 4).

Next, write verify is performed to check whether data has been written in the memory cell MC on the word line WLn (step S103). Next, it is determined whether or not the number of uncompleted memory cells MC is N ₁ (N ₁ is an integer of 0 or more) (step S104). Incidentally, it can be determined whether or not the number of bit lines BL connected to the memory cell MC that has not been written is equal to or less than the condition value N ₁ .

If the number of incomplete memory cells is N ₁ or less, it is determined that writing has been completed, and the process proceeds to step S111. On the other hand, when the incomplete memory cell number is greater than _one N, after increasing the write voltage Vpgm by .DELTA.Vpgm (step S105), it repeats the processing of steps S101-S104. FIG. 4 shows an example in which writing is completed by five times of processing. In the second to fifth processing, the write voltage values are set to Vpgm2 to Vpgm5 (Vpgm1 <Vpgm2 <Vpgm3 <Vpgm4 <Vpgm5), respectively (see FIG. 4). The number N ₁ may be the number of memory cells MC to be written, or may be a number in consideration of the number of memory cells MC to be written that can be relieved by ECC (Error-Correcting Code).

  Subsequently, when the writing to the word line WLn is completed, the initial value of the additional voltage Vadd is set to a value obtained by adding ΔVadd to the final value of the write voltage Vpgm (step S111). That is, the value of Vadd1 is set to Vpgm5 + ΔVadd.

  Next, all the bit lines BL in the memory cell array 1 are set to a non-selected state (step S112). Next, an additional voltage Vadd is applied to the word line WLn (step S113). In the first application of the additional voltage, the value of the additional voltage is set to Vadd1 (see FIG. 4).

  Next, it is confirmed whether or not the additional voltage has been applied a specified number of times (step S114). If the number of times of application of the additional voltage is less than the designated number, the additional voltage Vadd is increased by ΔVadd (step S115), and then the processes of steps S112 to S114 are repeated. FIG. 4 shows an example in which the designated number of times is three. In the second and third processing, the value of the additional voltage is set to Vadd2 and Vadd3, respectively (see FIG. 4).

  On the other hand, when the number of times of application of the additional voltage reaches the designated number, application of the additional voltage to the word line WLn is completed. Thereafter, the processing of steps S101 to S115 can be performed on the next word line WLn + 1. In this processing, the word line WLn + 1 is an example of the second word line, and the word line WLn to which writing has already been performed is an example of the first word line.

  Note that the value of ΔVadd may be the same as or different from ΔVpgm. In this embodiment, the values of ΔVpgm and ΔVadd and the above-mentioned designated times are set in the ROM fuse 7, for example. These numerical values may be sent from the host or the memory controller (MH).

  The initial value Vadd1 of the additional voltage may be set to a value other than Vpgm5 + ΔVadd. For example, the initial value Vadd1 of the additional voltage may be set to a value higher than the final value Vpgm5 of the write voltage, or may be set to a value lower than the final value Vpgm5 of the write voltage (or write) It may be set equal to the final voltage value Vpgm5). However, from the viewpoint of reducing the number of times of application of the additional voltage, it is desirable to set the initial value Vadd1 of the additional voltage higher than the final value Vpgm5 of the write voltage. In this embodiment, by setting Vadd1> Vpgm5, the values of the additional voltages Vadd1 to Vadd3 are all set higher than the final value Vpgm5.

(2) Operational Effect of Write Control in FIG. 3 Next, the operational effect of the write control in FIG. 3 will be described with reference to FIGS.

  FIG. 5 is a graph showing the threshold distribution of the memory cells MC in the first embodiment. FIG. 5 shows an example of simulation by an in-house simulator for an 8-level NAND flash memory. 5A to 5D, the horizontal axis indicates the threshold voltage of the memory cell MC, and the vertical axis indicates the number of bits (the number of memory cells MC) on a log scale. In FIG. 5, simulation is performed using an 8-value method (3 bits of data are stored in one memory cell MC. The number of threshold distributions of the memory cells MC is 8) as an example.

  FIG. 5A shows a threshold distribution on the word line WLn immediately after writing (that is, immediately after S104-Yes). FIG. 5B shows a threshold distribution on the word line WLn immediately after application of the additional voltage (that is, immediately after S114-Yes).

  The arrows A and B in FIGS. 5A and 5B indicate the threshold level distribution of the erase level. According to FIGS. 5A and 5B, it can be seen that the threshold level distribution of the erasure level is shifted to the high voltage side due to the application of the additional voltage. As described above, when all the bit lines BL are deselected and an additional voltage is applied to the word line WLn, the memory cells MC at the erase level on the word line WLn are selectively additionally written, and the erase level on the word line WLn is selectively written. The threshold distribution moves to the high voltage side.

  Next, the influence (inter-cell interference effect) that the word line WLn has on the word line WLn−1 will be described.

  FIG. 5C shows a threshold distribution on the word line WLn−1 immediately after writing to the word line WLn. FIG. 5D shows a threshold distribution on the word line WLn−1 immediately after application of the additional voltage to the word line WLn.

  Writing to the word line WLn affects the threshold distribution on the adjacent written word line WLn-1. At this time, the influence of the memory cell MC on the word line WLn−1 differs depending on the threshold voltage of the adjacent memory cell MC on the word line WLn. As a result, the threshold value distribution on the word line WLn−1 is expanded by writing to the word line WLn, as shown in FIG. A range C in FIG. 5C shows a threshold distribution of the write level of the memory cell MC having a write level higher than the erase level thus expanded.

  In general, on the high voltage side in the spread threshold distribution, there are many memory cells MC that have received many inter-cell interference effects, that is, memory cells MC having a high threshold voltage of adjacent cells. On the other hand, on the low voltage side in the spread threshold distribution, the memory cell MC that has not received much inter-cell interference effect, that is, the memory cell MC having a low threshold voltage of the adjacent cell (for example, the threshold voltage of the adjacent cell is at the erase level) There are many memory cells MC).

  The range D in FIG. 5D shows the threshold distribution of the memory cells MC at the write level higher than the erase level, like the range C. According to FIG. 5D, the lower skirt of the threshold distribution of the write level on the word line WLn−1 is shifted to the high voltage side, and the threshold distribution on the word line WLn−1 is narrowed. I understand. This corresponds to the additional writing being performed on the memory cell MC at the erase level on the word line WLn. As a result of the additional writing, it is considered that the threshold voltage of the memory cell MC in the lower skirt has increased due to the inter-cell interference effect.

  On the other hand, the memory cell MC having a write level higher than the erase level has little effect of additional writing. This is because since the write level is high, the threshold voltage of the memory cell MC hardly moves even if an additional voltage is applied to the word line WLn in the non-selected state. As a result, it is considered that the threshold voltage of the memory cell MC in the upper skirt of the threshold distribution hardly receives an inter-cell interference effect and does not increase. That is, it can be said that the application of the additional voltage in this embodiment corresponds to selectively performing additional writing on the memory cell MC at the erase level on the word line WLn.

  Thus, according to the present embodiment, the threshold voltage distribution of the memory cells MC on the word line WLn−1 is narrowed by applying all the bit lines BL to the unselected state and applying the additional voltage to the word line WLn. Can do. Note that the write control of this embodiment can be applied to a binary method or a multi-value method other than the 8-value method.

  FIG. 6 is a graph showing the relationship between the number of times of additional voltage application and the threshold distribution width in the first embodiment.

  The horizontal axis in FIG. 6 represents the number of times of application of the additional voltage to the word line WLn. A state where the number of times of application is 0 corresponds to a state immediately after writing. Also, the vertical axis in FIG. 6 represents the threshold distribution width of the write level on the word line WLn−1 that has been normalized so that the width immediately after writing is 1. FIG. 6 shows a simulation example of an 8-level NAND flash memory, as in FIG.

  As can be seen from FIG. 6, when the number of times of application of the additional voltage is increased from 0, the threshold distribution width becomes narrower and the threshold distribution width becomes minimum after a certain number of times of application. In the example of FIG. 6, the number of times of application is eight. Then, it can be seen that as the number of times of application is further increased, the threshold distribution width is increased. This is considered because the inter-cell interference effect additionally received by the memory cell MC on the word line WLn becomes too large.

  Thus, there is an optimum value for the number of times of application of the additional voltage. Therefore, in the present embodiment, the optimum value or a value close to the optimum value is determined by experiment or simulation, and the determined value is set in the ROM fuse 7 as the designated time described above. Therefore, according to the present embodiment, an optimized threshold distribution width can be realized. The designated number of times may be determined by trimming at the time of testing the nonvolatile semiconductor memory device.

(3) Effects of First Embodiment Finally, effects of the first embodiment will be described.

  As described above, in the present embodiment, when the writing to the word line WLn is completed, all the bit lines BL are set to a non-selected state and an additional voltage is applied to the word line WLn. The application of the additional voltage to the word line WLn can be performed before the start of writing to the word line WLn + 1. Therefore, according to the present embodiment, the threshold distribution of the memory cells MC on the adjacent written word line WLn−1 can be narrowed.

  In this embodiment, the process of applying the write voltage and the additional voltage includes the application of the write voltage to the word line WLn, the application of the additional voltage to the word line WLn, the application of the write voltage to the word line WLn + 1, and the word line. Like the application of the additional voltage to WLn + 1, the writing voltage and the additional voltage are applied to the same word line in succession. Therefore, according to the present embodiment, it is possible to apply these voltages at high speed.

  In addition, according to the present embodiment, since the multi-level nonvolatile semiconductor memory device can be operated with a write voltage having a low upper limit, the withstand voltage condition is relaxed, and the memory cell MC can be further miniaturized. .

(Second Embodiment)
In the second embodiment, when an additional voltage is applied, all the bit lines BL in the memory cell array 1 are set to a selected state. In the second embodiment, the values of the additional voltages Vadd1 to Vadd3 are all set to values lower than the initial value Vpgm1 of the write voltage.

(1) Control Method of Nonvolatile Semiconductor Memory Device Hereinafter, a control method of the nonvolatile semiconductor memory device of the second embodiment will be described with reference to FIGS.

  FIG. 7 is a flowchart illustrating a method for controlling the nonvolatile semiconductor memory device according to the second embodiment. FIG. 8 is a graph showing the write voltage and the additional voltage in the second embodiment. Hereinafter, the flowchart of FIG. 7 will be described with reference to FIG. 8 as appropriate.

  First, among all the bit lines BL in the memory cell array 1, all the bit lines BL to be written are set to a selected state, and the other bit lines BL are set to a non-selected state (step S201). Next, the write voltage Vpgm is applied to the word line WLn (step S202).

Next, write verify is performed to check whether data has been written in the memory cell MC on the word line WLn (step S203). Next, it is determined whether or not the number of unwritten memory cells MC is N ₁ (N ₁ is an integer of 0 or more) (step S204).

If the number of incomplete memory cells is N ₁ or less, it is determined that writing has been completed, and the process proceeds to step S211. On the other hand, if the number of incomplete memory cells is greater than N ₁ , the write voltage Vpgm is increased by ΔVpgm (step S205), and then the processes of steps S201 to S204 are repeated. FIG. 8 shows an example in which writing has been completed by five times of processing.

  Subsequently, when the writing to the word line WLn is completed, the initial value of the additional voltage Vadd is set to a value lower than the initial value of the write voltage Vpgm (step S211). That is, the value of Vadd1 is set to Vpgm1−Δ (Δ> 0) and Vadd1> 0.

  Next, all the bit lines BL in the memory cell array 1 are set to a selected state (step S212). Next, an additional voltage Vadd is applied to the word line WLn (step S213). In the first application of the additional voltage, the value of the additional voltage is set to Vadd1 (see FIG. 8).

  Next, it is confirmed whether or not an additional voltage has been applied a specified number of times (step S214). If the number of times of application of the additional voltage is less than the specified number, the additional voltage Vadd is increased by ΔVadd (step S215), and then the processes of steps S212 to S214 are repeated. FIG. 8 shows an example in which the designated number of times is three. In the second and third processing, the value of the additional voltage is set to Vadd2 and Vadd3, respectively (see FIG. 8).

  On the other hand, when the number of times of application of the additional voltage reaches the designated number, application of the additional voltage to the word line WLn is completed. Thereafter, in the present embodiment, the processes of steps S201 to S215 are performed on the next word line WLn + 1.

(2) Effects of Write Control in FIG. 7 Next, the effects of the write control in FIG. 7 will be described with reference to FIGS. 9 and 10.

  FIG. 9 is a graph showing the threshold distribution of the memory cells MC in the second embodiment. FIG. 9 shows a simulation example of an 8-value NAND flash memory.

  As in the case of the first embodiment, the application of the additional voltage in the second embodiment has an effect of moving the threshold level distribution of the erase level to the high voltage side. That is, by applying an additional voltage to the word line WLn with all the bit lines BL in a selected state, an effect equivalent to that of performing additional writing to the memory cell MC at the erase level on the word line WLn can be obtained. The threshold level distribution of the erase level on the line WLn moves to the high voltage side. This is the same as in FIGS. 5 (a) and 5 (b).

  Next, the influence (inter-cell interference effect) that the word line WLn has on the word line WLn−1 will be described.

  FIG. 9A shows a threshold distribution on the word line WLn−1 immediately after writing to the word line WLn. FIG. 9B shows a threshold distribution on the word line WLn−1 immediately after application of the additional voltage to the word line WLn.

  In the second embodiment, for the same reason as in the first embodiment, the threshold distribution on the word line WLn−1 is widened by writing to the word line WLn (FIG. 9A). The range E in FIG. 9A shows the threshold distribution of the write level of the memory cell MC having a write level higher than the erase level thus expanded.

  The range F in FIG. 9B shows the threshold distribution of the memory cells MC at the write level higher than the erase level, like the range E. According to FIG. 9B, the lower tail of the threshold distribution of the write level on the word line WLn−1 has moved to the high voltage side, and the threshold distribution on the word line WLn−1 is narrowed. I understand. As in the case of the first embodiment, this is because selective write is selectively performed on the memory cell MC at the erase level on the word line WLn, so that the threshold voltage of the memory cell MC in the lower skirt causes inter-cell interference. This is thought to be due to the effect.

  On the other hand, the memory cell MC having a write level higher than the erase level has little effect of additional writing. This is because since the write level is high, the threshold voltage of the memory cell MC hardly moves even if an additional voltage is applied to the word line WLn in the selected state. As a result, it is considered that the threshold voltage of the memory cell MC in the upper skirt of the threshold distribution hardly receives an inter-cell interference effect and does not increase. That is, it can be said that the application of the additional voltage in this embodiment corresponds to selectively performing additional writing on the memory cell MC at the erase level on the word line WLn.

  Thus, according to the present embodiment, the threshold voltage distribution of the memory cells MC on the word line WLn−1 can be narrowed by applying all the bit lines BL to the selected state and applying the additional voltage to the word line WLn. it can. In this embodiment, since the bit line is set to the selected state, the values of all the additional voltages Vadd1 to Vadd3 are set to values lower than the initial value Vpgm1 of the write voltage in order to prevent excessive additional writing.

  FIG. 10 is a graph showing the relationship between the number of additional voltage applications and the threshold distribution width in the second embodiment. FIG. 10 shows an example of a simulation by an in-house simulator for an 8-level NAND flash memory, as in FIG.

  As shown in FIG. 10, there is an optimum value for the number of times of application of the additional voltage. In the example of FIG. 10, the optimum value is about 15 times. Therefore, in the present embodiment, the optimum value or a value close to the optimum value is determined by experiment or simulation, and the determined value is set in the ROM fuse 7 as the designated time described above. Therefore, according to the present embodiment, an optimized threshold distribution width can be realized.

(3) Effects of Second Embodiment Finally, effects of the second embodiment will be described.

  As described above, in this embodiment, when writing to the word line WLn is completed, all the bit lines BL are set to a selected state and an additional voltage is applied to the word line WLn. The application of the additional voltage to the word line WLn can be performed before the start of writing to the word line WLn + 1. Therefore, according to the present embodiment, as in the first embodiment, the threshold distribution of the memory cells MC on the adjacent written word line WLn−1 can be narrowed.

(Third embodiment)
FIG. 11 is a graph showing the write voltage and the additional voltage in the third embodiment.

  In the first embodiment, when applying an additional voltage, all the bit lines BL in the memory cell array 1 are set to a non-selected state. In the second embodiment, when an additional voltage is applied, all the bit lines BL in the memory cell array 1 are set to a selected state. In contrast, in the third embodiment, when an additional voltage is applied, all the bit lines BL in the memory cell array 1 are set to a selected state or a non-selected state according to the value of the additional voltage.

  Specifically, when the value of the additional voltage Vadd is set to a value lower than the initial value Vpgm1 of the write voltage, all the bit lines BL are set to the selected state. In FIG. 11, Vadd1 and Vadd2 correspond to this example.

  On the other hand, when the value of the additional voltage Vadd is set to a value higher than the initial value Vpgm1 of the write voltage, all the bit lines BL are set to a non-selected state. In FIG. 11, Vadd3 to Vadd5 correspond to this example.

  According to the present embodiment, unlike the first and second embodiments, where the value of the additional voltage is limited, the value of the additional voltage can be set to an arbitrary value.

  Note that applying the additional voltage with all the bit lines BL selected is preferable from the viewpoint of the stability of the potential of the bit line BL than applying the additional voltage with all the bit lines BL not selected. . On the other hand, when all the bits BL are set to the selected state, excessive additional writing may occur as described above. However, in this embodiment, since all the bit lines BL can be switched between a selected state and a non-selected state, excessive additional writing can be prevented while enjoying the advantages of the selected state. .

  The first to third embodiments have been described above. However, these embodiments are presented as examples, and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms. Moreover, various modifications can be obtained by making various omissions, substitutions, and changes to these embodiments without departing from the scope of the invention.

  For example, the method of applying the additional voltage Vadd can be changed from applying a plurality of independent pulses to applying a single pulse whose voltage continuously changes (see FIGS. 12 and 13). 12 and 13 are graphs showing the write voltage and the additional voltage in the modified examples of the first and second embodiments, respectively. Thus, by continuously changing a single voltage, the stress applied to the gate insulating film 111 of the memory cell MC can be reduced. In addition, the writing time can be reduced because there is no time for the voltage to fall, compared to when an independent pulse is applied. In addition, “continuous change of a single voltage” includes not only the case where the voltage changes linearly as shown in FIGS. 12 and 13, but also the case where the voltage changes in a curvilinear or stepwise manner. . This is because even with such a voltage change, the effect of reducing the stress applied to the gate insulating film 111 of the memory cell MC and the effect of reducing the writing time can be obtained.

  These forms and modifications are included in the scope and gist of the invention, and these forms and modifications are included in the claims and the scope equivalent thereto.

1: memory cell array, 2: sense amplifier circuit, 3: row decoder,
4: input / output buffer, 5: controller, 6: voltage generation circuit,
7: ROM fuse, 8: Data storage circuit,
11: NAND cell unit, 12: sense amplifier,
21: Booster circuit, 22: Pulse generation circuit,
101: Semiconductor substrate, 102: Well, 103: Diffusion layer,
111: Gate insulating film, 112: Charge storage layer,
113: Inter-gate insulating film, 114: Control electrode,
115: Gate insulating film, 116: Gate electrode, 121: Interlayer insulating film

Claims (6)

A plurality of memory cells;
A plurality of word lines and a plurality of bit lines for controlling the memory cells;
A write voltage is applied to the first word line of the plurality of word lines at least once to write data into the memory cells on the first word line, and the memory cells on the first word line A controller for applying an additional voltage to the first word line one or more times after the data is written in,
When writing to the second word line after writing to the first word line, the control unit writes the data into the memory cell on the second word line, and then writes the plurality of bit lines. A non-volatile semiconductor memory device in which the additional voltage is applied to the second word line in a non-selected state or a selected state.   The nonvolatile semiconductor memory device according to claim 1, wherein the control unit sets the value of the additional voltage to a value higher than a final value of the write voltage.   The nonvolatile semiconductor memory device according to claim 1, wherein the control unit sets an initial value of the additional voltage to a value lower than a final value of the write voltage.   The nonvolatile semiconductor memory device according to claim 1, wherein the control unit sets the value of the additional voltage to a value lower than an initial value of the write voltage.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the control unit sets the plurality of bit lines to a selected state or a non-selected state according to a value of the additional voltage. The controller is
When setting the value of the additional voltage to a value lower than the initial value of the write voltage, set the plurality of bit lines in a selected state,
In the case where the value of the additional voltage is set to a value higher than the initial value of the write voltage, the plurality of bit lines are set to a non-selected state.
The nonvolatile semiconductor memory device according to claim 5.

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