JP2013157612A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily ensure electrical insulation between a first circuit and a second circuit even when signal voltages of the first circuit and the second circuit are different from each other.SOLUTION: A semiconductor chip 10 has a first circuit 100 and a first inductor 302. The semiconductor chip 20 has a second circuit 200 and a chip side connection terminal 545. A wiring board 60 is attached to an area ranging from the semiconductor chip 10 to the semiconductor chip 20. The wiring board 60 has a second inductor 304 and a substrate side connection terminal 610. The second inductor 304 is positioned above the first inductor 302. The chip side connection terminal 545 and the two substrate side connection terminals 610 are connected with each other through first solder balls 700.

Description

  The present invention relates to a semiconductor device capable of transmitting an electric signal between two circuits having different electric signal potentials.

  When an electric signal is transmitted between two circuits having different electric signal potentials, a photocoupler is often used. The photocoupler has a light emitting element such as a light emitting diode and a light receiving element such as a phototransistor, and converts an inputted electric signal into light by the light emitting element, and returns this light to an electric signal by the light receiving element. An electrical signal is transmitted.

  However, since the photocoupler has a light emitting element and a light receiving element, it is difficult to reduce the size. Further, when the frequency of the electrical signal is high, it becomes impossible to follow the electrical signal. As a technique for solving these problems, a technique for transmitting an electric signal by inductively coupling two inductors has been developed as described in, for example, Patent Document 1.

  Patent Document 2 describes that an inductor pair is used when a first semiconductor chip on a transmission side and a second semiconductor chip on a reception side are connected to each other via a transmission path. Specifically, the transmission line and the first semiconductor chip are connected in a non-contact manner by electromagnetic coupling of the transmission-side inductor pair. The transmission line and the second semiconductor chip are connected in a non-contact manner by electromagnetic coupling of the receiving-side inductor pair.

JP-T-2001-513276 JP 2008-113093 A

  When the signal voltage of the transmission side circuit and the reception side circuit are different, when the transmission side circuit and the reception side circuit are connected by an inductor pair, if the mutual interval between two inductors constituting the inductor pair is narrowed, the transmission side It becomes impossible to ensure insulation between the circuit and the receiving circuit.

According to the present invention, comprising one or two semiconductor chips having a wiring layer, and a wiring board attached to the wiring layer side of the one or two semiconductor chips,
The one or two semiconductor chips are:
A first circuit for generating a signal;
A second circuit for processing the signal;
A first inductor formed in the wiring layer and connected to one of the first circuit and the second circuit;
A chip-side connection terminal formed on the uppermost layer of the wiring layer and connected to the other of the first circuit and the second circuit;
Have
The wiring board is
A second inductor located above the first inductor;
A substrate-side connection terminal connected to the second inductor and located above the chip-side connection terminal;
Have
A semiconductor device is provided in which the chip-side connection terminal and the substrate-side connection terminal are connected via a first solder ball or a first bump.

  According to the present invention, the first solder ball or the first bump is located between the semiconductor chip and the wiring board. For this reason, the space | interval of a semiconductor chip and a wiring board, ie, the space | interval of a 1st inductor, and a 2nd inductor, can be ensured easily. Therefore, even when the signal voltages of the first circuit and the second circuit are different, insulation between the first circuit and the second circuit can be easily ensured.

  According to the present invention, insulation between the first circuit and the second circuit can be easily ensured even when the signal voltages of the first circuit and the second circuit are different.

1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment. FIG. 2 is an equivalent circuit diagram of the semiconductor device shown in FIG. 1. FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1. It is sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 4th Embodiment. It is a top view which shows the structure of the semiconductor device which concerns on 5th Embodiment. It is a top view which shows the structure of the semiconductor device which concerns on 6th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 7th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. This semiconductor device includes two semiconductor chips 10 and 20 and a wiring board 60. The semiconductor chip 10 has a multilayer wiring layer 400, and the semiconductor chip 20 has a multilayer wiring layer 500.

  The semiconductor chip 10 includes a first substrate 102, a first circuit 100, and a first inductor 302. The first substrate 102 is a semiconductor substrate such as a silicon substrate. The first circuit 100 generates a signal to be transmitted. The signal to be transmitted is, for example, a digital signal, but may be an analog signal. The first inductor 302 is formed in the multilayer wiring layer 400. The first inductor 302 is connected to the first circuit 100 and receives a signal generated by the first circuit 100.

  The semiconductor chip 20 includes a second substrate 202, a second circuit 200, and chip-side connection terminals 545. The second substrate 202 is a semiconductor substrate such as a silicon substrate. The second circuit 200 receives and processes the signal generated by the first circuit 100. The chip-side connection terminal 545 is formed in the uppermost layer of the multilayer wiring layer 500 and is connected to the second circuit 200 through wiring, vias, and contacts in the multilayer wiring layer 500.

  Note that the functions of the first circuit 100 and the second circuit 200 may be reversed. In this case, the first circuit 100 receives and processes the signal generated by the second circuit 200.

  The wiring board 60 is attached from the semiconductor chip 10 to the semiconductor chip 20. The wiring board 60 includes a second inductor 304 and two board-side connection terminals 610 (only one is shown in FIG. 1). The second inductor 304 is located above the first inductor 302. The two substrate side connection terminals 610 are respectively connected to the center side end portion and the outer end portion of the second inductor 304, and are located above the two chip side connection terminals 545.

  The two chip side connection terminals 545 and the two substrate side connection terminals 610 are connected via the first solder balls 700. The diameter of the first solder ball 700 is, for example, about 20 μm.

  In the present embodiment, the semiconductor chip 10 is provided with a first dummy connection terminal 445, and the wiring substrate 60 is provided with a second dummy connection terminal 612. The first dummy connection terminal 445 is provided in the uppermost layer of the multilayer wiring layer 400. The second dummy connection terminal 612 is located above the first dummy connection terminal 445. The first dummy connection terminal 445 is not connected to any active element formed on the semiconductor chip 10. Further, the second dummy connection terminal 612 is not connected to a signal transmission line among the wirings of the wiring board 60. The first dummy connection terminal 445 and the second dummy connection terminal 612 are connected via the second solder ball 702. The diameter of the second solder ball 702 is substantially the same as the diameter of the first solder ball 700.

  A space between the wiring substrate 60 and the semiconductor chip 20 is sealed with a sealing resin 720. Therefore, the first solder balls 700, the chip side connection terminals 545, and the substrate side connection terminals 610 are protected by the sealing resin 720. The space between the wiring substrate 60 and the semiconductor chip 10 is sealed with a sealing resin 722. Therefore, the second solder ball 702, the first dummy connection terminal 445, and the second dummy connection terminal 612 are protected by the sealing resin 722.

  In the example shown in FIG. 1, the wiring substrate 60 is an interposer formed using a resin substrate 602. A protective layer 604 such as a solder resist layer is formed on both surfaces of the substrate 602. However, the wiring board 60 may be a silicon interposer. When the wiring substrate 60 is a silicon interposer and the first substrate 102 and the second substrate 202 are silicon substrates, the substrate 602 of the wiring substrate 60 is formed of three layers of an insulating film, a silicon substrate, and an insulating film. The impurity concentration of the silicon substrate of the substrate 602 is preferably lower than the substrate impurity concentration of the first substrate 102 and the substrate impurity concentration of the second substrate 202. In this way, generation of eddy current in the substrate 602 can be suppressed.

  In the present embodiment, the second inductor 304 is formed on the surface of the wiring substrate 60 that faces the semiconductor chips 10 and 20. The center-side end portion of the second inductor 304 is connected to one substrate-side connection terminal 610 via a through-wiring 622 that penetrates the substrate 602, a wiring 624, and a through-wiring 626 that penetrates the substrate 602. . The wiring 624 is formed on the surface of the substrate 602 that does not face the semiconductor chips 10 and 20. Further, the outer end portion of the second inductor 304 is connected to the other board side connection terminal 610 (not shown) via a wiring (not shown in FIG. 1) formed in the same layer as the second inductor 304. Connected.

  The first inductor 302 and the second inductor 304 constitute a signal transmission element 300. The signal transmission element 300 transmits a signal by inductive coupling of the first inductor 302 and the second inductor 304. In the present embodiment, the first circuit 100 is a transmission circuit, and the second circuit 200 is a reception circuit. Therefore, the first inductor 302 functions as a transmission-side inductor, and the second inductor 304 functions as a reception-side inductor.

  In the present embodiment, the multilayer wiring layer 400 has a configuration in which an insulating layer 410, a wiring layer 412, an insulating layer 420, a wiring layer 422, an insulating layer 430, a wiring layer 432, an insulating layer 440, and a wiring layer 442 are stacked in this order. Have. In the example shown in the drawing, the first inductor 302 is provided in the wiring layer 412 that is the first wiring layer of the multilayer wiring layer 400. However, the first inductor 302 may be provided in another wiring layer, for example, the uppermost wiring layer 442.

  The multilayer wiring layer 500 has a configuration in which an insulating layer 510, a wiring layer 512, an insulating layer 520, a wiring layer 522, an insulating layer 530, a wiring layer 532, an insulating layer 540, and a wiring layer 542 are stacked in this order.

  Each insulating layer constituting the multilayer wiring layers 400 and 500 may have a structure in which a plurality of insulating films are stacked, or may be a single insulating film. The multilayer wiring layers 400 and 500 are covered with a protective film (not shown). The number of layers of the multilayer wiring layers 400 and 500 may be the same or different.

  The wiring in each wiring layer is a Cu wiring formed by a damascene method, and is embedded in a groove formed in each wiring layer. A connection terminal such as a pad, for example, a chip-side connection terminal 545 of the semiconductor chip 20 is formed in the uppermost layer wiring. In the multilayer wiring layers 400 and 500, at least one of the wiring layers may be an Al alloy wiring. Note that the wirings formed in each wiring layer are connected to each other through plugs embedded in the insulating layer.

Each insulating film constituting the insulating layer and the wiring layer may be a SiO ₂ film or a low dielectric constant film. The low dielectric constant film can be an insulating film having a relative dielectric constant of 3.3 or less, preferably 2.9 or less, for example. As the low dielectric constant film, in addition to SiOC, polyhydrogensiloxane such as HSQ (hydrogensilsesquioxane), MSQ (methylsilsesquioxane), or MHSQ (methylated hydrogensilsesquioxane), Aromatic-containing organic materials such as polyaryl ether (PAE), divinylsiloxane-bis-benzocyclobutene (BCB), or Silk (registered trademark), SOG, FOX (flowable oxide) (registered trademark), Cytop (registered trademark) ) Or BCB (Bencyclocyclene) or the like can also be used. Moreover, these porous films can also be used as the low dielectric constant film.

  In addition, when the thickness of the multilayer wiring layer 400 and the multilayer wiring layer 500 is different, the wiring board 60 may be inclined. In this case, the thicknesses of the semiconductor chip 10 and the semiconductor chip 20 may be made the same by changing the back surface grinding amounts of the first substrate 102 and the second substrate 202.

  The first circuit 100 is, for example, a transmission side driver circuit (for example, a gate driver), and amplifies a transmission signal obtained by modulating a digital signal and outputs the amplified signal to the first inductor 302. The second circuit 200 is, for example, a receiving side driver circuit (for example, a gate driver), and amplifies and outputs a digital signal generated by modulating the signal received by the second inductor 304.

  The first circuit 100 and the second circuit 200 have different electric signal potentials. However, since the signal transmission element 300 transmits the electric signal using inductive coupling, the first circuit 100 and the second circuit 200 are transmitted to the first circuit 100 and the second circuit 200. There is no problem. In the configuration of FIG. 1, as the case where “the electric potentials of the input electric signals are different from each other”, when the electric signals have different amplitudes (the difference between the electric potential indicating 0 and the electric potential indicating 1), the reference electric potential ( (Potentials indicating 0) are different, and the amplitudes of the electric signals are different from each other and the reference potentials of the electric signals are different.

  The first circuit 100 of the semiconductor chip 10 has a first transistor. The first transistor includes an N-type transistor and a P-type transistor. The N-type first transistor 121 is formed in a P-type well 120 and has two N-type impurity regions 124 and a gate electrode 126 that serve as a source and a drain. The P-type first transistor 141 is formed in the N-type well 140 and has two P-type impurity regions 144 and a gate electrode 146 that serve as a source and a drain. A gate insulating film is located under each of the gate electrodes 126 and 146. These two gate insulating films have substantially the same thickness. The first transistors 121 and 141 constitute the above-described transmission side driver circuit, for example, an inverter.

  A P-type impurity region 122 is formed in the well 120, and an N-type impurity region 142 is formed in the well 140. A wiring for supplying a reference potential (ground potential) of the N-type first transistor 121 is connected to the impurity region 122, and a wiring for supplying a power supply potential of the P-type first transistor 141 is connected to the impurity region 142. Yes.

  The second circuit 200 of the semiconductor chip 20 has a second transistor. The second transistor includes an N-type transistor and a P-type transistor. The N-type second transistor 221 is formed in the P-type well 220 and has two N-type impurity regions 224 and a gate electrode 226 that serve as a source and a drain. The P-type second transistor 241 is formed in the N-type well 240 and has two P-type impurity regions 244 and a gate electrode 246 that serve as a source and a drain. A gate insulating film is located under each of the gate electrodes 226 and 246. The second transistors 221 and 241 constitute the receiving driver circuit described above, for example, an inverter.

  A P-type impurity region 222 is formed in the well 220, and an N-type impurity region 242 is formed in the well 240. A wiring for supplying a reference potential of the N-type second transistor 221 is connected to the impurity region 222, and a wiring for supplying a power supply potential of the P-type second transistor 241 is connected to the impurity region 242.

  In the example shown in the figure, the first transistors 121 and 141 and the second transistors 221 and 241 have different gate insulating film thicknesses, but may be the same.

  The area of the wiring board 60 is smaller than the sum of the area of the semiconductor chip 10 and the area of the semiconductor chip 20.

  FIG. 2 is an equivalent circuit diagram of the semiconductor device shown in FIG. The signal generated by the first circuit 100 is received by the second circuit 200 via the signal transmission element 300. The signal transmission element 300 transmits a signal by inductive coupling of the first inductor 302 and the second inductor 304.

  FIG. 3 is a schematic plan view of the semiconductor device shown in FIG. As described above, the wiring substrate 60 has the two substrate-side connection terminals 610, and the semiconductor chip 20 has the two chip-side connection terminals 545. One substrate-side connection terminal 610 is connected to the center-side end of the second inductor 304 via the through-wire 622, the wire 624, and the through-wire 626, and the other substrate-side connection terminal 610 is connected to the second substrate-side connection terminal 610. It is connected to the outer end of the second inductor 304 through a wiring formed in the same layer as the inductor 304. The two substrate-side connection terminals 610 are connected to the chip-side connection terminals 545 via the first solder balls 700, respectively.

  The semiconductor chip 10 has a first dummy connection terminal 445, and the wiring board 60 has a second dummy connection terminal 612. The first dummy connection terminal 445 is connected to the second dummy connection terminal 612 via the second solder ball 702. Note that the semiconductor device may include a plurality of first dummy connection terminals 445, second solder balls 702, and second dummy connection terminals 612.

  Next, the operation and effect of this embodiment will be described. The first circuit 100 and the second circuit 200 have different electric signal potentials. The withstand voltage between the first circuit 100 and the second circuit 200 is determined by the distance between the first inductor 302 of the semiconductor chip 10 and the second inductor 304 of the wiring board 60. In the present embodiment, the semiconductor chip 20 and the wiring board 60 are connected using the first solder ball 700. For this reason, the distance between the semiconductor chip 10 and the wiring board 60, that is, the distance between the first inductor 302 and the second inductor 304 can be easily secured. Therefore, the breakdown voltage, that is, insulation between the first circuit 100 and the second circuit 200 can be easily ensured.

  Further, the first dummy connection terminal 445 is provided on the semiconductor chip 10, and the second dummy connection terminal 612 is provided on the wiring substrate 60. The first dummy connection terminal 445 and the second dummy connection terminal 612 are connected using a second solder ball 702. For this reason, the number of solder balls supporting the wiring substrate 60 on the semiconductor chips 10 and 20 is increased from two to three or more, for example. Therefore, the wiring board 60 is suppressed from being inclined.

  Further, the end portion on the center side of the second inductor 304 is connected to the substrate-side connection terminal 610 via the through wiring 622, the wiring 624, and the through wiring 626. The wiring 624 is formed on the surface of the wiring board 60 opposite to the second inductor 304. Therefore, the end portion on the center side of the second inductor 304 can be pulled out to the substrate side connection terminal 610 without interfering with the second inductor 304.

(Second Embodiment)
FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. In this semiconductor device, the sealing resin 722 is not formed in a region 724 that overlaps the second inductor 304 in a plan view in the space between the semiconductor chip 20 and the wiring substrate 60, according to the first embodiment. It is the same. Note that the region 724 is a space closed by the sealing resin 722, the wiring substrate 60, and the semiconductor chip 20. For this reason, when the atmosphere when forming the sealing resin 722 is a vacuum, the region 724 is in a vacuum.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. Further, since the sealing resin 722 is not formed in a region overlapping with the second inductor 304 in plan view, the withstand voltage between the first inductor 302 and the second inductor 304 can be further increased.

(Third embodiment)
FIG. 5 is a cross-sectional view illustrating a configuration of a semiconductor device according to the third embodiment. This semiconductor device is the same as that of the first embodiment except for the points described below. First, the surface of the wiring board 60 where the wiring 624 is formed faces the semiconductor chips 10 and 20. The second dummy connection terminal 612 is formed on the surface where the wiring 624 is formed.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. In this embodiment, the sealing resin 722 may be the same as that in the third embodiment.

(Fourth embodiment)
FIG. 6 is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment. This semiconductor device has the same configuration as that of the first embodiment, except for the connection structure between the end portion on the center side of the second inductor and the board-side connection terminal 610 in the wiring board 60.

  In the present embodiment, the wiring board 60 has a multilayer wiring layer 650. A second inductor 304 is formed in one layer of the multilayer wiring layer 650. The center-side end of the second inductor 304 is connected to the substrate-side connection terminal 610 via a wiring 644 formed on a layer different from the second inductor 304 in the multilayer wiring layer 650 and plugs 642 and 646. Yes. The plug 642 connects the wiring 644 and the end of the second inductor 304 on the center side, and the plug 646 connects the wiring 644 and the board side connection terminal 610.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. In the second or third embodiment, the connection structure between the end portion on the center side of the second inductor and the board side connection terminal 610 may be as in this embodiment.

(Fifth embodiment)
FIG. 7 is a plan view showing the configuration of the semiconductor device according to the fifth embodiment. This figure corresponds to FIG. 3 in the first embodiment. In the semiconductor device according to the present embodiment, the semiconductor chip 10 and the semiconductor chip 20 communicate bidirectionally. This semiconductor device has the same configuration as that of any of the first to third embodiments except for the points described below.

  This semiconductor device has two sets of a first circuit 100, a first inductor 302, a second circuit 200, two chip-side connection terminals 545, a second inductor 304, and two substrate-side connection terminals 610. The two sets of two chip-side connection terminals 545 and the two sets of two substrate-side connection terminals 610 are connected via the first solder balls 700, respectively.

  Specifically, the semiconductor chip 10 includes a first circuit 100, a second circuit 200, and two first inductors 302. The semiconductor chip 20 includes the first circuit 100, the second circuit 200, and two Two sets of chip side connection terminals 545 are provided. The wiring board 60 has a second inductor 304 above each of the two first inductors 302, and a board-side connection terminal 610 above each of the four chip-side connection terminals 545. .

  The first circuit 100 of the semiconductor chip 10 and the second circuit 200 of the semiconductor chip 20 transmit and receive signals via the signal transmission element 300 including one of the first inductor 302 and the second inductor 304. The second circuit 200 of the semiconductor chip 10 and the first circuit 100 of the semiconductor chip 20 transmit and receive signals via the signal transmission element 300 including the other first inductor 302 and second inductor 304.

  In the present embodiment, a plurality of sets (for example, two sets) of the first dummy connection terminals 445, the second dummy connection terminals 612, and the second solder balls 702 are provided on the semiconductor chip 10.

  Also according to the present embodiment, the same effects as those of the first to third embodiments can be obtained. In this embodiment, when the four chip-side connection terminals 545 are not arranged in the same straight line, the wiring can be performed even if the first dummy connection terminal 445, the second dummy connection terminal 612, and the second solder ball 702 are omitted. Inclination of the substrate 60 can be suppressed.

(Sixth embodiment)
FIG. 8 is a plan view showing the configuration of the semiconductor device according to the sixth embodiment. This figure corresponds to FIG. 7 in the fifth embodiment. As in the fifth embodiment, the semiconductor device according to this embodiment includes the first circuit 100, the first inductor 302, the second circuit 200, the two chip-side connection terminals 545, the second inductor 304, and the two substrates. Two sets of side connection terminals 610 are provided. The semiconductor device has the same configuration as that of the semiconductor device according to the fifth embodiment except for the points described below.

  First, the first set of the first circuit 100 and the first inductor 302, the second set of the second circuit 200 and the two chip-side connection terminals 545 are formed in the semiconductor chip 10. The second set of the first circuit 100 and the first inductor 302, the first set of the second circuit 200, and the two chip-side connection terminals 545 are formed in the second semiconductor chip 20.

  That is, the first circuit 100 of the semiconductor chip 10 and the second circuit 200 of the semiconductor chip 20 are connected via the signal transmission element 300 including the first inductor 302 provided in the semiconductor chip 10 and the second inductor 304 positioned above the first inductor 302. , Send and receive signals. The second circuit 200 of the semiconductor chip 10 and the first circuit 100 of the semiconductor chip 20 are connected via a signal transmission element 300 including a first inductor 302 provided on the semiconductor chip 20 and a second inductor 304 positioned above the first inductor 302. , Send and receive signals.

  The semiconductor device does not have the first dummy connection terminal 445, the second dummy connection terminal 612, and the second solder ball 702.

  Also in this embodiment, the same effect as that of the fifth embodiment can be obtained. Further, since the chip-side connection terminal 545, the first solder ball 700, and the substrate-side connection terminal 610 are provided corresponding to the semiconductor chip 10 and the semiconductor chip 20, respectively, the first dummy connection terminal 445, the second dummy connection terminal 445 are provided. Even if the connection terminal 612 and the second solder ball 702 are not provided, the wiring board 60 can be prevented from being inclined.

(Seventh embodiment)
FIG. 9 is a cross-sectional view showing the configuration of the semiconductor device according to the seventh embodiment. This semiconductor device has the same configuration as that of any of the first to sixth embodiments except that the first substrate 102 of the semiconductor chip 10 is an SOI substrate and the semiconductor chip 20 is integrated with the semiconductor chip 10. is there. FIG. 9 shows a case where the configuration is the same as that of the first embodiment.

  The first circuit 100, the second circuit 200, the first inductor 302, and the second inductor 304 are formed in the semiconductor chip 10 and do not have the semiconductor chip 20. The first circuit 100 and the first inductor 302 are formed in the first region 12 of the semiconductor chip 10, and the second circuit 200 and the second inductor 304 are formed in the second region 14 of the semiconductor chip 10.

  The first substrate 102 is an SOI (Silicon On Insulator) substrate and has a configuration in which an insulating layer 106 and a silicon layer 108 are stacked in this order on a silicon substrate 104. An insulating isolation layer 109 that insulates the first region 12 and the second region 14 is embedded in the silicon layer 108. The lower end of the insulating separation layer 109 reaches the insulating layer 106.

  Also according to the present embodiment, the same effects as those of the first to third embodiments can be obtained. In addition, a first circuit 100 as a transmission circuit and a second circuit 200 as a reception circuit can be formed on the semiconductor chip 10.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable. For example, in each of the above-described embodiments, a bump such as a gold bump may be used instead of the first solder ball 700 and the second solder ball 702.

10 semiconductor chip 12 first region 14 second region 20 semiconductor chip 60 wiring substrate 100 first circuit 102 first substrate 104 silicon substrate 106 insulating layer 108 silicon layer 109 insulating isolation layer 120 well 121 first transistor 122 impurity region 124 impurity region 126 Gate electrode 140 Well 141 First transistor 142 Impurity region 144 Impurity region 146 Gate electrode 200 Second circuit 202 Second substrate 220 Well 221 Second transistor 222 Impurity region 224 Impurity region 226 Gate electrode 240 Well 241 Second transistor 242 Impurity region 244 Impurity region 246 Gate electrode 300 Signal transmission element 302 First inductor 304 Second inductor 400 Multilayer wiring layer 410 Insulating layer 412 Wiring layer 420 Insulating layer 422 Wiring layer 4 0 insulating layer 432 wiring layer 440 insulating layer 442 wiring layer 445 first dummy connection terminal 500 multilayer wiring layer 510 insulating layer 512 wiring layer 520 insulating layer 522 wiring layer 530 insulating layer 532 wiring layer 540 insulating layer 542 wiring layer 545 chip side connection Terminal 602 Substrate 604 Protective layer 610 Substrate side connection terminal 612 Second dummy connection terminal 622 Through wiring 624 Wiring 626 Through wiring 642 Plug 644 Wiring 646 Plug 650 Multilayer wiring layer 700 First solder ball 702 Second solder ball 720 Sealing resin 722 Sealing resin 724 region

Claims (9)

One or two semiconductor chips having a wiring layer, and a wiring board attached to the wiring layer side of the one or two semiconductor chips,
The one or two semiconductor chips are:
A first circuit for generating a signal;
A second circuit for processing the signal;
A first inductor formed in the wiring layer and connected to one of the first circuit and the second circuit;
A chip-side connection terminal formed on the uppermost layer of the wiring layer and connected to the other of the first circuit and the second circuit;
Have
The wiring board is
A second inductor located above the first inductor;
A substrate-side connection terminal connected to the second inductor and located above the chip-side connection terminal;
Have
The semiconductor device in which the chip side connection terminal and the substrate side connection terminal are connected via a first solder ball or a first bump. The semiconductor device according to claim 1,
A first dummy connection terminal provided on the uppermost layer of the wiring layer of the one or two semiconductor chips;
A second dummy connection terminal provided on the wiring board and positioned above the first dummy connection terminal;
The semiconductor device in which the first dummy connection terminal and the second dummy connection terminal are connected via a second solder ball or a second bump. The semiconductor device according to claim 1 or 2,
A sealing resin for sealing a space between the one or two semiconductor chips and the wiring board;
A semiconductor device in which the sealing resin is not formed in a region overlapping the second inductor in plan view. In the semiconductor device as described in any one of Claims 1-3,
The second inductor is formed on one side of the wiring board,
A semiconductor device in which an end on the center side of the second inductor is connected to the substrate-side connection terminal via a through wiring that penetrates the wiring substrate and a wiring provided on the other surface side of the wiring substrate. In the semiconductor device as described in any one of Claims 1-3,
The wiring board has a multilayer wiring layer,
The second inductor is formed in the multilayer wiring layer;
The end of the second inductor on the center side is connected to the substrate side connection terminal via a wiring formed in a layer different from the second inductor in the multilayer wiring layer and vias. In the semiconductor device according to any one of claims 1 to 5,
The first circuit, the first inductor, the second circuit, and the two chip-side connection terminals provided on the one or two semiconductor chips, the second inductor provided on the wiring board, and the It has two sets of board side connection terminals,
The two sets of the two chip-side connection terminals and the two sets of the substrate-side connection terminals are respectively connected via the first solder balls or the first bumps. The semiconductor device according to claim 6.
The one or two semiconductor chips include a first semiconductor chip and a second semiconductor chip,
The wiring board is attached over the second semiconductor chip from the first semiconductor chip,
The first set of the first circuit and the first inductor, and the second set of the second circuit and the two chip side connection terminals are formed on the first semiconductor chip,
The semiconductor device in which the second set of the first circuit and the first inductor, and the first set of the second circuit and the two chip-side connection terminals are formed on the second semiconductor chip. In the semiconductor device according to any one of claims 1 to 5,
The one or two semiconductor chips include a first semiconductor chip and a second semiconductor chip,
The first circuit and the first inductor are formed in the first semiconductor chip;
The second circuit is formed in the second semiconductor chip;
The semiconductor device, wherein the wiring board is attached from the first semiconductor chip to the second semiconductor chip. In the semiconductor device according to claim 1,
The first circuit, the second circuit, the first inductor, and the chip-side connection terminal are formed on one semiconductor chip,
The first circuit and the first inductor are formed in a first region of the semiconductor chip;
The second circuit and the chip-side connection terminal are formed in a second region of the semiconductor chip;
A semiconductor device in which the first region and the second region are insulated.

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