JP2013157522A - Semiconductor device, method of manufacturing semiconductor device, testing instrument for semiconductor device, method of testing semiconductor device, and method of connecting semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a defect of contact with a testing jig can be prevented while improving a property of welding with external circuit wiring by exposing a member of a solid copper by breaking a thick natural oxide film formed in an external derivation terminal comprised of the member of the solid copper without using inert gas, a method of manufacturing the semiconductor device, a testing instrument for the semiconductor device, a method of testing the semiconductor device and a method of connecting the semiconductor device, at low cost.SOLUTION: In an external derivation terminal 2 comprised of a member 11 of a solid copper, a recess 8 and a protrusion 9 are formed using pressurizing jigs 14, 17 (or testing jigs 32, 34) and a thick natural oxide film 10 formed by a heat history during manufacturing steps is destroyed, thereby exposing the member 11 of the solid copper.

Description

  The present invention relates to a semiconductor device, a semiconductor device manufacturing method, a semiconductor device test instrument, a semiconductor device test method, and a semiconductor device connection method.

  In a power semiconductor device such as IGBT (Insulated Gate Bipolar Transistor) or MOSFET, or a semiconductor device incorporating an electronic circuit, a measurement test of electrical characteristics may be performed by sandwiching an external lead terminal with a measurement probe. In some cases, the external lead-out terminal of the semiconductor device and the external circuit wiring are connected by welding.

  7A and 7B are configuration diagrams of a conventional semiconductor device, in which FIG. 7A is a plan view of the main part, and FIG. 7B is a cross-sectional view of the main part taken along line YY in FIG. . In this semiconductor device 500, an IGBT is taken as an example. However, in addition to this IGBT, an electronic circuit may be built in a chip. In the figure, the inside of the resin case 57 is indicated by a dotted line.

  The semiconductor device 500 includes a die 51, an IGBT chip 53 fixed on the die 51 with solder 72 or the like, an external lead-out terminal 52, and a resin case 57 that covers them. The die 51 and the external lead-out terminal 52 are resin-sealed and then cut out from the lead frame. The external lead-out terminal 52 connected to the die 51 is connected to the collector electrode on the back surface of the IGBT chip 53 via the die 51 and becomes the collector terminal of the semiconductor device 500. The external lead-out terminal 52 connected to the IGBT emitter electrode 54 with the bonding wire 56 becomes the emitter terminal of the semiconductor device 500. The external lead-out terminal 52 connected to the gate electrode pad 55 with the bonding wire 56 is a gate terminal of the semiconductor device 500. Since the base material of the die 51 and the external lead-out terminal 52 is a solid copper member 61, in order to prevent a thick natural oxide film from being formed due to the thermal history during the manufacturing process, A nickel plating layer 60 is formed.

  Further, Patent Document 1 includes a non-oxidizing gas supply means for supplying an inert gas or a reducing gas and a nozzle for making the atmosphere of the portion where the electrode pad and the probe needle are in contact with each other into a non-oxidizing atmosphere. It is disclosed that by using the inspection device provided, the electrical characteristics of the semiconductor device can be tested with high accuracy without damaging the semiconductor device.

  Patent Document 2 discloses a more compact apparatus and measurement method that is an electrical characteristic measurement apparatus that can perform a stable measurement in an inert gas atmosphere speedily and inexpensively.

JP-A-7-273157 JP 2000-164648 A

  When welding an external circuit wiring (not shown) to the external lead-out terminal 52 on which the nickel plating layer 60 is formed, as in the semiconductor device 500 of FIG. 7, the weldability is reduced by the nickel plating layer 60, resulting in poor bonding. There is. Therefore, a case where a nickel plating layer is not formed on the external lead-out terminal 52 can be considered.

  FIGS. 8A and 8B are configuration diagrams of a semiconductor device 600 having an external lead-out terminal 52 made of a solid copper member 61. FIG. 8A is a plan view of the main part, and FIG. 8B is a plan view of FIG. It is principal part sectional drawing cut | disconnected by the YY line. The difference between the semiconductor device 600 and the semiconductor device 500 of FIG. 7 is that a solid copper member 61 that does not form the nickel plating layer 60 on the die 51 and the external lead-out terminal 52 is used.

  FIG. 9 is a diagram showing a state in which a measurement test of electrical characteristics of the semiconductor device 600 of FIG. 8 is performed. FIG. 9A is a diagram before the external lead-out terminal 52 is sandwiched between the measurement probes 80. FIG. b) is a view after the external lead-out terminal 52 is sandwiched.

  In this semiconductor device 600, the solid copper member 61 is oxidized by the thermal history during the manufacturing process, and a thick natural oxide film 70 is formed on the surface of the external lead-out terminal 52. As shown in FIG. In the test process, the measurement probe 80 may not be in contact with the copper base (solid copper member 61) due to the thick natural oxide film 70, and contact failure may occur. Reference numeral 81 in the figure denotes a tester.

  Therefore, conventionally, in order to suppress oxidation, the thermal history process is performed in a nitrogen atmosphere that is an inert gas, and the test is also performed in an inert gas atmosphere as disclosed in Patent Documents 1 and 2, or As described above, the external lead-out terminal 52 is covered with the nickel plating layer 60 so as not to be oxidized, and the electrical characteristics are measured.

  Further, in the subsequent welding process for connection to the external circuit wiring, when nickel plating is applied, the nickel plating layer 60 is peeled off before the welding to expose the solid copper member 61 for welding. It is done.

However, any of these methods has a problem of cost increase due to introduction of equipment and increase in man-hours.
Further, Patent Document 1 and Patent Document 2 do not describe performing a characteristic test or welding of a semiconductor device provided with an external lead terminal formed of a solid copper member without using an inert gas.

  The object of the present invention is to solve the above-described problems and break at least a part of a natural oxide film formed on an external lead-out terminal made of a solid copper member without using an inert gas to expose the solid copper member. Semiconductor device capable of improving weldability with external circuit wiring and preventing contact failure with test jig, semiconductor device manufacturing method, semiconductor device test instrument, semiconductor device test method, and semiconductor device connection method Is to be provided at a low cost.

  In order to achieve the above object, according to the invention described in claim 1 of the claims, a semiconductor chip, a die to which the back surface of the semiconductor chip is fixed, an external lead terminal connected to the die, In the semiconductor device having the semiconductor chip and the case for housing the die, the external lead-out terminal is formed of a member that is easily oxidized by a thermal history during the manufacturing process of the semiconductor device, and an external circuit of the external lead-out terminal A concave portion is provided on one surface of the connection portion with the wiring, and a convex portion corresponding to the concave portion is provided on the other surface, and a natural oxide film formed by a thermal history before the convex portion on the surface of the convex portion is provided. At least a part is destroyed.

According to the invention described in claim 2 of the claims, in the invention described in claim 1, the member is preferably made of pure copper.
According to the invention described in claim 3 of the claims, in the invention described in claim 1, the case may be a resin case.

According to the invention of claim 4, the step of fixing a semiconductor chip to a portion corresponding to a die of a solid copper lead frame, a portion corresponding to the die of the lead frame, and the semiconductor A step of housing the chip and a portion of the lead frame corresponding to the external lead-out terminal in a resin case, a step of cutting a predetermined portion of the lead frame,
The convex portion and concave portion of the pressurizing jig are brought into contact with both sides of the connection portion of the external lead terminal with the external circuit wiring, and the concave portion and convex portion are formed on the external lead terminal by pressurizing the pressurizing jig. And forming and destroying at least a part of the natural oxide film formed on the surface of each of the concave and convex portions to expose the pure copper.

  According to the invention described in claim 5 of the claims, it is a test instrument used for a measurement test of a semiconductor device, and has a convex portion and a concave portion having the same shape as the pressure jig according to claim 4. A test instrument having the formed measurement probe and connected to the tester is provided.

  According to the invention of claim 6, a portion corresponding to a die of a solid copper lead frame, a semiconductor chip fixed to the die, and a portion corresponding to an external lead terminal of the lead frame A test method for a semiconductor device in which a part of the test probe is housed in a resin case, wherein the convex portion of the measurement probe according to claim 5 is connected to an external circuit wiring of an external lead-out terminal separated from the lead frame. And the concave portion corresponding to the concave portion and the convex portion are formed on the external lead-out terminal, and formed on the respective surfaces of the concave portion and the convex portion formed on the external lead-out terminal. A step of bringing the measurement probe and the external lead-out terminal into contact with each other in a state in which at least a part of the formed natural oxide film is broken to expose the solid copper, and a tester connected to the measurement probe. And measuring testing electrical characteristics of a semiconductor device, the test method comprising.

  According to a seventh aspect of the present invention, after the test method for the semiconductor device according to the sixth aspect is completed, the external circuit wiring is welded to the convex portion of the external lead-out terminal to complete the test. A semiconductor device connection method for connecting an external lead-out terminal to the external circuit wiring.

  According to this invention, a natural oxide film is formed by forming a recess and a protrusion on an external lead-out terminal made of a solid copper member using a pressure jig (or a test jig), and a thermal history during the manufacturing process. At least a part of the material is destroyed to expose a solid copper member. The weldability is improved by welding the external circuit wiring to the convex portion of the external lead-out terminal from which the solid copper member is exposed or the thin natural oxide film is formed on the solid copper member. Reliability can be increased.

  In addition, at least a part of the natural oxide film of the external lead terminal is broken by the convex part and the concave part of the test jig to form a concave part and / or convex part in which the solid copper member is exposed, and the concave part of the external lead terminal and / or Alternatively, a contact failure between the test tool and the external lead-out terminal can be prevented by bringing the test jig into contact with the convex portion.

  Further, it is possible to reduce the cost by not applying, for example, nickel plating for preventing oxidation to the external lead terminal made of a solid copper member.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device which is 1st Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the YY line of (a). It is a manufacturing method of the semiconductor device which is 2nd Example of this invention, (a)-(d) is the principal part manufacturing process top view shown to process order. FIG. 3D is a detailed explanatory diagram of the process of FIG. 2D, where FIG. 2A is a diagram before forming the concave portion and the convex portion on the external lead-out terminal, and FIG. FIG. It is a principal part block diagram of the test device of the semiconductor device which is 3rd Example of this invention. FIG. 6 shows a test method of a semiconductor device according to a fourth embodiment of the present invention, wherein FIGS. FIG. 10 shows a semiconductor device connection method according to a fifth embodiment of the present invention, and FIGS. It is a block diagram of the conventional semiconductor device, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the YY line of (a). 4A and 4B are configuration diagrams of a semiconductor device having an external lead terminal made of a solid copper member, where FIG. 4A is a plan view of the main part, and FIG. 4B is a cross-sectional view of the main part taken along line YY in FIG. . It is a figure which shows a mode that the measurement test of the electrical property of the semiconductor device of FIG. 8 is performed, (a) is a figure before pinching an external lead-out terminal with a measurement probe, (b) is after pinching an external lead-out terminal. FIG.

Embodiments will be described in the following examples.
<Example 1>
FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a plan view of an essential part, and FIG. 1 (b) is a YY line of FIG. 1 (a). It is the principal part sectional drawing cut | disconnected. The semiconductor device 100 has been described here as an example of an IGBT (insulated gate bipolar transistor). However, the semiconductor device 100 is not limited to this, and may be a semiconductor device incorporating a MOSFET, an electronic circuit, or the like. In addition, when incorporating an electronic circuit etc., it is necessary to further increase the number of the external lead-out terminals 2.

  The semiconductor device 100 includes a die 1 that is a support base, an IGBT chip 3 that is fixed onto the die 1 with solder 22 or the like, an external lead-out terminal 2, and a resin case 7 that covers them. The die 1 and the external lead-out terminal 2 are resin-sealed and then cut out from the lead frame 20 in FIG. The external lead-out terminal 2 connected to the die 1 is connected to the collector electrode on the back surface of the IGBT chip 3 through the die 1 and becomes a collector terminal of the semiconductor device 100. The external lead-out terminal 2 connected to the IGBT emitter electrode 4 by the bonding wire 6 becomes the emitter terminal of the semiconductor device 100. The external lead-out terminal 2 connected to the gate electrode pad 5 by the bonding wire 6 is a gate terminal of the semiconductor device 100. A concave portion 8 and a convex portion 9 corresponding to the concave portion 8 are formed on both surfaces of the external lead-out terminal 2 at a portion 41 exposed from the resin case 7 and connected to the external circuit wiring of the external lead-out terminal 2. The die 1 and the external lead-out terminal 2 are cut out from a lead frame 20 made of a solid copper member 11 shown in FIG. In the concave portion 8 and the convex portion 9, at least a part of the thick natural oxide film 10 of about several hundred nm formed by the thermal history during the manufacturing process of the semiconductor device 100 is broken, and the solid copper member 11 is exposed. . Further, during storage other than the thermal history during the manufacturing process, for example, during storage, an extremely thin natural oxide film of about several tens of nm (not shown) may be formed on the solid copper member 11. The convex portion 9 may be referred to as a dowel.

  The convex portion 9 and the external circuit wiring 42 are connected by welding. However, since the solid copper member 11 is exposed, it can be easily welded even when the welding power is small to improve the weldability. . Further, even if an extremely thin natural oxide film is formed, it is easily broken during welding and the pure copper member 11 is exposed, so that the weldability can be improved.

  Further, since nickel plating for preventing oxidation is not applied to the surfaces of the die 1 and the external lead-out terminal 2, the number of manufacturing steps can be reduced and the manufacturing cost can be reduced. Also, no plating equipment is required.

A plurality of the concave portions 8 and the convex portions 9 may be formed in the same plane.
The convex portion 9 is formed to protrude from the back surface by forming the concave portion 8. The planar shape of the concave portion 8 and the convex portion 9 formed on the front and back sides of the external lead-out terminal 2 is a triangle, a quadrangle, a polygon, etc. in addition to the circle shown in FIG. About 0.5 mm. The thickness of the external lead-out terminal is, for example, about 1 mm.

In some cases, a nickel plating layer is formed except for the convex portion 9 of the external lead-out terminal 2. Also in this case, since there is no nickel plating layer in the convex part 9, weldability improves.
<Example 2>
FIG. 2 shows a method of manufacturing a semiconductor device according to a second embodiment of the present invention. FIGS. 2A to 2D are plan views of the main part manufacturing process shown in the order of steps.

  In FIG. 2A, a lead frame 20 made of a solid copper member to be used as the die 1 and the external lead-out terminal 2 is prepared. The lead frame 20 is not subjected to nickel plating for preventing oxidation.

  In FIG. 2B, the IGBT chip 3 is fixed on the die 1 via solder 22 (not shown). Subsequently, the emitter electrode 4, the gate electrode pad 5 and the external lead-out terminal 2 are connected by the bonding wire 6. Further, the die 1, the IGBT chip 3, and a part of the external lead-out terminal 2 are covered with a mold resin. This mold resin becomes the resin case 7. At this stage, a thick natural oxide film 10 of about several hundred nm is formed on the die 1 and the external lead-out terminal 2.

In FIG. 2C, the lead frame 20 is cut at a predetermined portion 21 indicated by a dotted line in FIG.
In FIG. 4D, the concave portion 8 and the convex portion 9 are formed in the portion 41 connected to the external circuit wiring (not shown) of the external lead-out terminal 2 exposed from the resin case 7, and formed by the thermal history during the manufacturing process. Then, at least a part of the natural oxide film 10 having a thickness of about several hundred nm is destroyed. Due to this destruction, an IGBT which is the semiconductor device 100 of the resin case 7 having the external lead-out terminal 2 from which the part 11 made of pure copper is exposed is completed. A thin natural oxide film (for example, a thickness of about several tens of nanometers) (not shown) is formed on the solid copper member 11 where the concave portions 8 and the convex portions 9 are exposed by storing the IGBT other than the thermal history during the manufacturing process. Sometimes.

  Further, when the nickel plating layer is formed except for the convex portion 9 described at the end of the description related to FIG. 1, the location where the lead frame is to be welded in the process between FIG. 2A and FIG. 41 is masked to form a nickel plating layer on the lead frame 20. The subsequent steps are the same as in FIG.

  3A and 3B are detailed explanatory views of the process of FIG. 2D. FIG. 3A is a view before forming the concave portion 8 and the convex portion 9 in the external lead-out terminal 2, and FIG. FIG. 6 is a view after forming a concave portion 8 and a convex portion 9 on the lead-out terminal 2.

An upper pressurizing jig 14 having a convex portion 13 is attached to the tip of the expansion / contraction part 12 a of the cylinder / piston mechanism 12, and a lower pressurization jig 17 having a concave part 16 at the tip of the expansion / contraction part 15 a of the cylinder / piston mechanism 15. Installing. The cylinder / piston mechanisms 12 and 15 are moved to extend the telescopic portions 12 a and 15 a, so that both surfaces of the external lead-out terminal 2 are sandwiched between the pressurizing jigs 14 and 17. By applying pressure by the cylinder / piston mechanisms 12 and 15, the front surface 2a of the external lead-out terminal 2 is dented to form a concave portion 8, and at the same time, the rear surface 2b is projected to project the convex portion 9 Form. At this time, the thick natural oxide film 10 is broken and the pure copper member 11 is exposed.
<Example 3>
FIG. 4 is a block diagram showing the principal part of a test apparatus for a semiconductor device according to a third embodiment of the present invention. The tester 37 is also shown in the figure.

  The test jig 200 shown in FIG. 4 includes an upper measurement probe 32 having a convex portion 31 and a lower measurement probe 34 having a concave portion 33, and the upper and lower measurement probes 32 and 34 have a pressure measurement function. The shapes of the convex portions 31 and the concave portions 33 are the same as the shapes of the convex portions 13 and the concave portions 16 of the pressing jigs 14 and 17 in FIG. 3, but they may be different. Further, the upper measurement probe 32 constituting the measurement probe is connected to the tester 37 via the main wiring 35 through which the main current flows, and the lower measurement probe 34 is connected to the tester 37 via the measurement line 36. The connection relationship between the upper measurement probe 32 and the lower measurement probe 34, the main wiring 35, and the measurement line 36 may be reversed. Alternatively, the main wiring 35 and the measurement line 36 may be connected to one of the upper measurement probe 32 and the lower measurement probe 34 so that the main current is supplied and measured with the one wiring.

As shown in FIG. 5 described later, the vertical measurement probes 32 and 34 are attached to the tips of the expansion / contraction portions 12a and 15a of the cylinder / piston mechanisms 12 and 15 before entering the step of FIG. 14 and 17 are attached instead. Then, the process of FIG. 2D is entered, and an electrical measurement test of the semiconductor device is performed by the tester 37 with the recesses 8 and the protrusions 9 formed in the external lead-out terminals 2 shown in FIG. In this way, the concave and convex portions 8 and the convex portions 9 are formed in the external lead-out terminal 2 by the vertical measurement probes 32 and 34, and the thick natural oxide film 10 is broken, thereby causing poor contact between the external lead-out terminal 2 and the vertical measurement probes 32 and 33. Is prevented.
<Example 4>
FIG. 5 shows a test method for a semiconductor device according to a fourth embodiment of the present invention. FIG. 5A and FIG. 5B are principal part process diagrams shown in the order of processes. This test method may be incorporated as part of the manufacturing method.

In FIG. 2A, the convex portions 31 and the concave portions 33 of the vertical measurement probes 32 and 34 are respectively disposed above and below the portion 41 to be welded with the external circuit wiring of the external lead-out terminal 2 of the semiconductor device.
In FIG. 2B, the cylinder / piston mechanisms 12 and 15 are driven to sandwich the external lead-out terminal 2 with the vertical measurement probes 32 and 34. Subsequently, a pressure F (for example, about 10000 N: about 1 ton) is applied to the external lead-out terminal 2 by the cylinder / piston mechanisms 12 and 15 to form the concave portion 8 and the convex portion 9 in the external lead-out terminal 2. At this time, at least part of the thick natural oxide film 10 covering the concave portion 8 and the convex portion 9 is broken to expose the solid copper member 11, and the convex portions 31 and the concave portions 33 of the upper and lower measurement probes 32 and 34 are externally provided. Contact is made between the concave portion 8 and the convex portion 9 where the solid copper member 11 of the lead-out terminal 2 is exposed. Since the convex portions 31 and the concave portions 33 of the vertical measurement probes 32 and 34 are in contact with the concave portions 8 and the convex portions 9 where the solid copper member 11 of the external lead-out terminal 2 is exposed, poor contact can be prevented.

  In this way, even when the inert gas atmosphere is not used, the electrical measurement test of the semiconductor device can be performed by the tester 37 in a state where contact failure does not occur. After this test, the IGBT of the semiconductor device 100 of FIG. 1 is completed.

Since this electrical measurement test also serves as the process of FIG. 2D, the test cost can be reduced as compared with the case where the electrical measurement test is performed again after the process of FIG.
In addition, in this test, since the inert gas atmosphere is not used as described above, the test cost can be reduced.

Furthermore, since an apparatus for making an inert gas atmosphere is unnecessary, an inexpensive tester can be used.
<Example 5>
FIG. 6 shows a method for connecting a semiconductor device according to a fifth embodiment of the present invention, and FIGS. 6A to 6B are principal part process diagrams shown in the order of processes. Connection is made using welding.

  In FIG. 2A, after the process of FIG. 2D or FIG. 4B is completed, the thick natural oxide film 10 is removed and the solid copper member 11 is exposed (or a thin natural oxide film not shown). The external circuit wiring 42 is placed in contact with the convex portion 9 of the external lead-out terminal 2 of the semiconductor device 500 that is covered.

  In FIG. 4B, the convex portion 9 and the external circuit wiring 42 are welded, and the external lead-out terminal 2 and the external circuit wiring 42 are connected at a welding location 43. Even when the convex portion is covered with a thin natural oxide film (not shown), the natural oxide film is easily broken with a small welding energy, so that the weldability is improved as compared with the case of nickel plating.

  Thus, weldability can be improved by welding with the convex part 9 where the solid copper member 11 is exposed or the convex part 9 covered with a thin natural oxide film (not shown).

Reference Signs List 1 die 2 external lead-out terminal 3 IGBT chip 4 emitter electrode 5 gate electrode pad 6 bonding wire 7 resin case 8 recess (external lead-out terminal 2)
9 Convex (external lead-out terminal 2)
10 Thick natural oxide film 11 Solid copper member 12, 15 Cylinder / piston mechanism 13 Convex part (pressure jig 14)
14 Pressure jig 16 Recess (Pressure jig 17)
17 Pressurizing jig 20 Lead frame 21 locations 22 Solder 31 Convex part (upper measurement probe 32)
32 Upper measurement probe 33 Recess (lower measurement probe 34)
34 Lower measurement probe 35 Main wiring 36 Measurement line 37 Tester 41 location 42 External circuit wiring 43 Welding location 100 Semiconductor device 200 Test jig 500 Semiconductor device

Claims (7)

  A semiconductor device having a semiconductor chip, a die to which a back surface of the semiconductor chip is fixed, an external lead terminal connected to the die, and a case for housing the semiconductor chip and the die, wherein the external lead terminal is the semiconductor device. Formed of a member that is easily oxidized by a thermal history during the manufacturing process, and provided with a concave portion on one surface of the connection portion with the external circuit wiring of the external lead-out terminal and a convex portion corresponding to the concave portion on the other surface The semiconductor device is characterized in that at least a part of a natural oxide film formed by a thermal history before the projections are provided on the surface of the projections is destroyed.   The semiconductor device according to claim 1, wherein the member is made of pure copper.   The semiconductor device according to claim 1, wherein the case is a resin case. A process of fixing a semiconductor chip to a portion corresponding to a die of a solid copper lead frame;
Storing a portion corresponding to a die of the lead frame, the semiconductor chip, and a part of a portion corresponding to an external lead-out terminal of the lead frame in a resin case;
Cutting a predetermined portion of the lead frame;
The convex portion and concave portion of the pressurizing jig are brought into contact with both sides of the connection portion of the external lead terminal with the external circuit wiring, and the concave portion and convex portion are formed on the external lead terminal by pressurizing the pressurizing jig. Forming and destroying at least a part of the natural oxide film formed on the surface of each of the concave and convex portions and exposing the solid copper,
A method for manufacturing a semiconductor device, comprising:   A test instrument for use in a measurement test of a semiconductor device, comprising a measurement probe having a convex part and a concave part having the same shape as the pressure jig according to claim 4, wherein the measurement probe is connected to a tester. A test apparatus for semiconductor devices. A test method for a semiconductor device in which a part corresponding to a die of a solid copper lead frame, a semiconductor chip fixed to the die, and a part of a part corresponding to an external lead-out terminal of the lead frame are accommodated in a resin case. The convex portion and concave portion of the measurement probe according to claim 5 are brought into contact with a connection portion of the external lead terminal separated from the lead frame with the external circuit wiring to correspond to the convex portion and concave portion of the measurement probe. Forming concave portions and convex portions on the external lead-out terminals, and exposing at least a part of the natural oxide film formed on the respective surfaces of the concave and convex portions formed on the external lead-out terminals to expose the solid copper. Contacting the measurement probe and the external lead-out terminal in a state in which
A step of measuring and testing electrical characteristics of the semiconductor device by a tester connected to the measurement probe;
A method for testing a semiconductor device, comprising:   7. The semiconductor device connection method according to claim 6, wherein after the test method for the semiconductor device according to claim 6 is completed, an external circuit wire is welded to a convex portion of the external lead-out terminal, and the external lead-out terminal is connected to the external circuit wire.