JP2013157410A - Semiconductor element manufacturing method and semiconductor element - Google Patents

Semiconductor element manufacturing method and semiconductor element Download PDF

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JP2013157410A
JP2013157410A JP2012016007A JP2012016007A JP2013157410A JP 2013157410 A JP2013157410 A JP 2013157410A JP 2012016007 A JP2012016007 A JP 2012016007A JP 2012016007 A JP2012016007 A JP 2012016007A JP 2013157410 A JP2013157410 A JP 2013157410A
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rewiring
chip
semiconductor element
substrate
high heat
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JP5921219B2 (en
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Shinya Matsuo
伸也 松尾
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New Japan Radio Co Ltd
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New Japan Radio Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To enable easy manufacturing of a compact semiconductor element having high heat radiation property, and provide a compact semiconductor element having high heat radiation property.SOLUTION: A semiconductor element manufacturing method comprises: bonding a plurality of IC chips 8 to predetermined positions of a single high heat dissipation material 10; and subsequently mounting 1-chip substrate 13 for rewiring on the IC chips 8. That is, by connecting the substrates 13 for rewiring to stand bumps 9 provided on a logic circuit surface of the IC chips 8 via ACF (Anisotropic Conductive Film) 16 disposed on each of the substrates 13 for rewiring, chip-on-chip mounting is performed. The method further comprises: subsequently, performing resin encapsulation by resin 18 on all of the IC chips 8 on which the substrate 13 for rewiring are mounted, respectively; and performing singulation by a dicing saw and the like to manufacture individual semiconductor elements.

Description

本発明は半導体素子の製造方法及び半導体素子、特に高放熱性を有するモールドアレイパッケージや小型パッケージ等の半導体素子に関する。   The present invention relates to a method for manufacturing a semiconductor element and a semiconductor element, and more particularly to a semiconductor element such as a mold array package or a small package having high heat dissipation.

近年、小型化、薄型化の要請に対応したCSP(Chip Size Package)等の半導体素子が製作されており、このCSP等では、生産性の向上、コストダウン等の目的のため、例えばモールドアレイパッケージ(MAP:Mold Array Package)工法による製造が行われる。このモールドアレイパッケージ工法は、多数の半導体回路を1つの基板(MAP基板)上にアレイ状に集合・配置し、このMAP基板上に形成した半導体回路をダイシングにて個片化することで、多数の半導体素子が製作される。   In recent years, a semiconductor element such as a CSP (Chip Size Package) corresponding to the demand for miniaturization and thinning has been manufactured. For example, a mold array package is used for the purpose of improving productivity and reducing cost. Manufacture by the (MAP: Mold Array Package) method is performed. In this mold array package construction method, a large number of semiconductor circuits are assembled and arranged in an array on one substrate (MAP substrate), and the semiconductor circuits formed on the MAP substrate are separated into individual pieces by dicing. The semiconductor device is manufactured.

上記のようなモールドアレイパッケージ形態を採用する半導体素子(パッケージ)の製造方法では、有機基板やリードフレームにICチップを半導体素子用接着剤により搭載し、ワイヤボンディング技術等を用いて再配線が行なわれる。そして、この再配線材料とICチップは、樹脂にて封止され、耐環境性を確保した上で、ダイシングソー等を用いて個片化することにより、半導体素子のパッケージングを完了することが一般的である。   In the method of manufacturing a semiconductor element (package) adopting the mold array package form as described above, an IC chip is mounted on an organic substrate or a lead frame with an adhesive for a semiconductor element, and rewiring is performed using a wire bonding technique or the like. It is. Then, the rewiring material and the IC chip are sealed with a resin, and after ensuring the environment resistance, the packaging of the semiconductor element can be completed by dividing into pieces using a dicing saw or the like. It is common.

図4には、従来のICチップのMAP工法等による再配線の工程が示されており、この再配線では、図4(A)のように、複数の半導体素子分の配線と電極が形成された再配線用集合基板(リードフレーム等)1にICチップ2がワイヤ(金線等)3によりワイヤボンディングされた後、全体に封止用樹脂4によりモールドされる。そして、モールド後の集合基板1を個片化することで、図4(B)の半導体素子が複数製作される。   FIG. 4 shows a rewiring process by a conventional IC chip MAP method or the like. In this rewiring, wiring and electrodes for a plurality of semiconductor elements are formed as shown in FIG. After the IC chip 2 is wire-bonded to the rewiring collective substrate (lead frame or the like) 1 with a wire (gold wire or the like) 3, the whole is molded with a sealing resin 4. Then, a plurality of semiconductor elements shown in FIG. 4B are manufactured by dividing the assembled substrate 1 after molding into individual pieces.

特開2004−179507号公報JP 2004-179507 A

ところで、再配線が実施される各種の半導体素子(パッケージ)においては、高放熱特性が必要となるものがあるが、複数の半導体素子を効率よく製造するMAP工法等では、高放熱特性を容易に得ることが困難であった。   By the way, in various semiconductor elements (packages) to which rewiring is performed, there are those that require high heat dissipation characteristics. However, in the MAP method for efficiently manufacturing a plurality of semiconductor elements, high heat dissipation characteristics are easily achieved. It was difficult to get.

即ち、図4(B)で示した半導体素子に対し高放熱特性を付与する場合、樹脂4によって封止される前に、ICチップ2に対し、高放熱特性を持つ高放熱性塗料の塗布や放熱板の取付け等を行う必要があるが、この段階でこれらを実施することは困難で、図5(A)のように、封止用樹脂4の上に、高放熱性塗料5を塗布したり、図5(B)のように、封止用樹脂4の上に、放熱板6を配置したりすることになる。   That is, when high heat dissipation characteristics are imparted to the semiconductor element shown in FIG. 4B, before the resin chip 4 is sealed, application of a high heat dissipation paint having high heat dissipation characteristics to the IC chip 2 is possible. Although it is necessary to attach a heat sink, etc., it is difficult to carry out these steps at this stage. As shown in FIG. 5 (A), a high heat dissipating paint 5 is applied on the sealing resin 4. Alternatively, as shown in FIG. 5B, the heat radiating plate 6 is disposed on the sealing resin 4.

しかし、このような図5(A),(B)の高放熱特性の付与では、ICチップ2の近くに高放熱性塗料や放熱板等を配置することができず、高放熱化が図り難いという問題があり、図5(B)の場合は、MAP工法で製作される半導体素子が極めて小さいため、個々の半導体素子に対し放熱板6を搭載することも困難である。   However, with the provision of the high heat dissipation characteristics shown in FIGS. 5A and 5B, it is difficult to achieve high heat dissipation because it is not possible to dispose a high heat dissipating paint or heat dissipating plate near the IC chip 2. In the case of FIG. 5B, since the semiconductor element manufactured by the MAP method is extremely small, it is difficult to mount the heat sink 6 on each semiconductor element.

本発明は上記問題点に鑑みてなされたものであり、その目的は、高放熱特性を有する小型の半導体素子を容易に製造することができる半導体素子の製造方法及び高放熱特性を有する小型の半導体素子を提供することにある。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor element capable of easily manufacturing a small semiconductor element having high heat dissipation characteristics and a small semiconductor having high heat dissipation characteristics. It is to provide an element.

上記目的を達成するために、請求項1の発明に係る半導体素子(パッケージ)の製造方法は、複数のICチップを高放熱基材の所定の位置へボンディングする工程と、再配線のための配線及び電極が形成され、個片化された再配線用基板を、ICチップ上に搭載する工程と、上記再配線用基板を搭載した複数のICチップに対し樹脂封止する工程と、個々の半導体素子に個片化する工程と、を有することを特徴とする。
請求項2の発明に係る半導体素子は、バンプ電極が形成されたICチップと、再配線のための配線及び電極が形成されかつ個片化された再配線用基板とを設け、上記ICチップのバンプ電極とは反対側の面に、高放熱材料をボンディングし、上記ICチップのバンプ電極に対し、個片化された再配線用基板を異方性導電フィルムを介して接続してなることを特徴とする。
In order to achieve the above object, a method of manufacturing a semiconductor device (package) according to the invention of claim 1 includes a step of bonding a plurality of IC chips to a predetermined position of a high heat dissipation base material, and wiring for rewiring. And a step of mounting the separated redistribution substrate on which the electrodes are formed, on the IC chip, a step of resin-sealing a plurality of IC chips on which the redistribution substrate is mounted, and individual semiconductors And a step of dividing the device into pieces.
According to a second aspect of the present invention, there is provided a semiconductor device comprising: an IC chip on which bump electrodes are formed; and a rewiring substrate on which wirings and electrodes for rewiring are formed and separated into pieces. A high heat dissipation material is bonded to the surface opposite to the bump electrode, and the separated rewiring substrate is connected to the bump electrode of the IC chip through an anisotropic conductive film. Features.

上記請求項1の構成によれば、複数のICチップが1枚の高放熱材料の所定の位置へボンディングされた後、個片化(1チップ化)されている再配線用基板がICチップ上にフリップチップボンディング技術等の接続技術を用いて搭載される。例えば、ICチップの論理回路面に設けられたスタンドバンプ電極に、再配線用基板に設けられた異方性導電フィルムを介して再配線用基板をチップオンチップ(チップオンチップに準ずる手法)で接続することにより行われる。その後、この再配線用基板を搭載した全てのICチップに対し樹脂封止が行われ、ダイシングソー等で個片化されることで、個々の半導体素子が製作される。   According to the configuration of the first aspect, after the plurality of IC chips are bonded to a predetermined position of one high heat dissipation material, the rewiring substrate separated into one piece (one chip) is mounted on the IC chip. It is mounted using connection technology such as flip chip bonding technology. For example, a rewiring board is mounted on a stand bump electrode provided on a logic circuit surface of an IC chip via an anisotropic conductive film provided on the rewiring board in a chip-on-chip (a technique similar to a chip-on-chip). This is done by connecting. Thereafter, resin sealing is performed on all the IC chips on which the rewiring substrate is mounted, and individual semiconductor elements are manufactured by being separated into pieces by a dicing saw or the like.

本発明の半導体素子の製造方法によれば、高放熱特性が必要となる半導体素子において、ICチップに対し高放熱を目的とした材料を確実に配置することが可能となり、容易に高放熱特性を得ることができる。即ち、従来ICチップを搭載するために用いられる再配線用基板は、電気的接続を行う再配線材料の役割を担うため、高放熱性塗料を塗布することが容易ではないが、本発明によれば、個片化(1チップ化)した再配線用基板をチップオンチップで搭載することにより再配線を行う構成であるから、一層の高放熱特性を得るための高放熱性塗料等を塗布した放熱用材料を使用することが可能になるという利点がある。   According to the method for manufacturing a semiconductor device of the present invention, in a semiconductor device that requires high heat dissipation characteristics, it is possible to reliably dispose a material for high heat dissipation on the IC chip, and easily provide high heat dissipation characteristics. Can be obtained. That is, since the rewiring substrate conventionally used for mounting the IC chip plays a role of a rewiring material for electrical connection, it is not easy to apply a high heat dissipation paint. For example, since the rewiring substrate is mounted by chip-on-chip, the rewiring board that has been singulated (single chip) is applied, so that a high heat dissipating paint or the like is applied to obtain higher heat dissipation characteristics. There is an advantage that a heat dissipating material can be used.

また、本発明の半導体素子の製造方法では、製造時の反りも発生せず、平面度の高い半導体素子が得られるという効果がある。即ち、上記ICチップに対し個片化した再配線用基板ではなく、集合基板としての再配線用基板を配置することも可能であるが、この場合には、再配線用の集合基板と高放熱基材の熱膨張係数の差により反りが発生し易い。これは、工場内を一定の温度に管理することがコスト面で困難であり、水平分業のため、高放熱基材と再配線用の集合基板を接合した半製品を移動させる場合等があるからである。しかし、本発明は、個片化した再配線用基板をチップオンチップで搭載するから、高放熱基材等の反りもなく、この反りによる影響をなくすことができる。更には、既存の生産設備において実施できるという利点もある。   In addition, the semiconductor element manufacturing method of the present invention has an effect that a semiconductor element having high flatness can be obtained without causing warpage during manufacturing. That is, it is possible to arrange a rewiring board as a collective board instead of a separate rewiring board with respect to the IC chip. In this case, the rewiring collective board and the high heat dissipation board are arranged. Warpage is likely to occur due to the difference in thermal expansion coefficient of the substrate. This is because it is difficult in terms of cost to manage the inside of the factory at a constant temperature, and because of the horizontal division of labor, there is a case where a semi-finished product joined with a high heat dissipation base material and a rewiring aggregate board may be moved. It is. However, according to the present invention, since the separated rewiring substrate is mounted on a chip-on-chip basis, there is no warp of the high heat dissipation base material and the influence of this warp can be eliminated. Furthermore, there is an advantage that it can be carried out in an existing production facility.

本発明の半導体素子によれば、高放熱特性を有する小型の半導体素子が得られるという効果がある。   According to the semiconductor element of the present invention, there is an effect that a small semiconductor element having high heat dissipation characteristics can be obtained.

本発明の実施例に係る半導体素子の製造方法で製造された半導体素子の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor element manufactured with the manufacturing method of the semiconductor element which concerns on the Example of this invention. 実施例の半導体素子の製造方法の各工程を説明するための図である。It is a figure for demonstrating each process of the manufacturing method of the semiconductor element of an Example. 実施例の搬送用ウェハーリング上の再配線用基板が搭載された集合基板を示す図である。It is a figure which shows the assembly board | substrate with which the board | substrate for rewiring on the wafer ring for conveyance of an Example was mounted. 従来のICチップのMAP工法等による再配線工程を示す図である。It is a figure which shows the rewiring process by the MAP construction method etc. of the conventional IC chip. 従来の半導体素子において考えられる放熱対策の例を示し、図(A)は高放熱性塗料を塗布する場合の図、図(B)は放熱板を配置する場合の図である。The example of the heat dissipation countermeasure considered in the conventional semiconductor element is shown, A figure (A) is a figure in the case of apply | coating a high heat dissipation paint, A figure (B) is a figure in the case of arrange | positioning a heat sink.

図1には、本発明の実施例に係る半導体素子の製造方法で得られた半導体素子(半導体パッケージ)の構成が示されており、この図1において、8はICチップ、10は高放熱材料、11はICチップ8と高放熱材料10を接続する半導体用接着剤、13は再配線用基板(15は有機基板)、9はICチップ8と再配線用基板13の再配線に用いられるスタッドバンプ(バンプ接続用電極)、16はICチップ8と再配線用基板13の再配線に用いられる異方性導電フィルム(ACF)、18は封止用樹脂である。   FIG. 1 shows a configuration of a semiconductor element (semiconductor package) obtained by a method of manufacturing a semiconductor element according to an embodiment of the present invention. In FIG. 1, 8 is an IC chip, 10 is a high heat dissipation material. , 11 is an adhesive for a semiconductor connecting the IC chip 8 and the high heat dissipation material 10, 13 is a rewiring substrate (15 is an organic substrate), and 9 is a stud used for rewiring the IC chip 8 and the rewiring substrate 13. Bumps (bump connection electrodes), 16 is an anisotropic conductive film (ACF) used for rewiring between the IC chip 8 and the rewiring substrate 13, and 18 is a sealing resin.

図2には、実施例の半導体製造方法が示されており、図2(A)に示されるように、ICチップ8には、その論理回路面にバンプ接続用電極であるスタッドバンプ9が形成され、また金属薄板10aに熱伝導率の高い塗料(例えば窒化アルミニウムが配合された塗料)10bが塗布された1枚の高放熱材料(シート)10が設けられ、この高放熱材料10は複数のICチップ8を搭載できる大きさからなる。この高放熱材料10としては、ガラスクロスやポリイミドのベースに熱伝導率の高い塗料を塗布し、フレキシブルにしたもの等、各種のものが適用できる。まず、図2(A)の工程では、上記高放熱材料10の上の所定位置にICチップ8(スタッドバンプ9が設けられていない面)が、半導体用接着剤11を用いてダイボンディングされる。そして、このICチップ8の全てについてダイボンディングが終了した後、接着剤11を硬化させる。   FIG. 2 shows a semiconductor manufacturing method according to the embodiment. As shown in FIG. 2A, the IC chip 8 has stud bumps 9 as bump connection electrodes formed on the logic circuit surface thereof. In addition, a single high heat dissipation material (sheet) 10 in which a coating material 10b having a high thermal conductivity (for example, a coating material containing aluminum nitride) 10b is applied to the metal thin plate 10a is provided. The size is such that the IC chip 8 can be mounted. As the high heat dissipation material 10, various materials such as a glass cloth or a polyimide base coated with a high thermal conductivity paint and made flexible can be used. First, in the step of FIG. 2A, the IC chip 8 (the surface on which the stud bump 9 is not provided) is die-bonded at a predetermined position on the high heat dissipation material 10 using the semiconductor adhesive 11. . Then, after die bonding is completed for all of the IC chips 8, the adhesive 11 is cured.

次に、図2(B)に示されるように、個片化された再配線用基板13が上記ICチップ8にフリップチップボンディング等によるチップオンチップにて接続される。この再配線用基板13は、有機基板15に対し再配線処理のための配線14aと電極14bが形成され、この再配線用基板13の電極14b側に異方性導電フィルム(ACF)16が仮接着されたもので、事前に製作される。即ち、図3に示されるように、搬送用ウェハーリング20には、その上のUVテープ21上に、上記再配線用基板13を複数形成した集合基板22がその二次実装面を上方にして(ACF16の支持テープと共に)搭載されており、この集合基板22をダイシング技術により切断することで、1チップ化された再配線用基板13が製作される。   Next, as shown in FIG. 2B, the separated rewiring substrate 13 is connected to the IC chip 8 by chip-on-chip by flip-chip bonding or the like. In this rewiring substrate 13, wirings 14 a and electrodes 14 b for rewiring processing are formed on the organic substrate 15, and an anisotropic conductive film (ACF) 16 is temporarily provided on the electrode 14 b side of the rewiring substrate 13. Glued and made in advance. That is, as shown in FIG. 3, the transfer wafer ring 20 includes a collective substrate 22 in which a plurality of the rewiring substrates 13 are formed on the UV tape 21 on the transfer wafer ring 20 with the secondary mounting surface facing upward. It is mounted (with the supporting tape of the ACF 16), and the collective substrate 22 is cut by a dicing technique, whereby the rewiring substrate 13 made into one chip is manufactured.

そして、この図2(B)の工程では、再配線用基板13のACF16側の面をICチップ8のスタッドバンプ9側の面に当てて加圧・加熱し、接着することで(ダイボンディング技術により)、再配線用基板13が1チップ毎にICチップ8に対して(チップオンチップで)搭載される。この際、上記ACF16の支持テープが図3のUVテープ21の接着力により剥がれるよう、UVテープ21の材料を選定し、かつダイシング条件の設定を行うことになる。   2B, the surface on the ACF 16 side of the rewiring substrate 13 is applied to the surface on the stud bump 9 side of the IC chip 8 to apply pressure, heat, and bond (die bonding technology). Thus, the rewiring substrate 13 is mounted on the IC chip 8 on a chip-by-chip basis (chip-on-chip). At this time, the material of the UV tape 21 is selected and the dicing conditions are set so that the support tape of the ACF 16 is peeled off by the adhesive force of the UV tape 21 shown in FIG.

次に、ICチップ8の全てに対して再配線用基板13の搭載が完了すると、図2(C)に示されるように、集合基板(MAP基板)に対しモールド装置にて封止用樹脂(エポキシ樹脂等)18を用いた樹脂封止が行われる。この樹脂封止が完了すると、集合基板を再度ウェハーリング20上に貼り付けられたUVテープ21へ二次実装面を上方にした状態で搭載し、ダイシング技術にて最終製品形態(半導体素子)になるよう個片化が行われる。最終製品形態へと個片化された半導体素子は、電気特性試験が実施された後、出荷用包装材へ収納されることで完成品となる。   Next, when the mounting of the rewiring substrate 13 on all of the IC chips 8 is completed, as shown in FIG. 2C, a sealing resin (MAP) is formed on the collective substrate (MAP substrate) by a molding apparatus. Resin sealing using an epoxy resin or the like) 18 is performed. When this resin sealing is completed, the assembly substrate is mounted again on the UV tape 21 affixed on the wafer ring 20 with the secondary mounting surface facing upward, and the final product form (semiconductor element) is obtained by dicing technology. Individualization is performed so that A semiconductor element separated into a final product form is subjected to an electrical characteristic test and then housed in a shipping packaging material to be a finished product.

このような実施例によれば、従来の半導体製造ラインを用いて、小型で高放熱特性を有する半導体素子の製造が可能である。また、図2(B)の工程で、IC基板8に対し再配線用の集合基板を配置することも可能で、この場合は再配線用の集合基板と高放熱基材10の熱膨張係数の差により反りが生じるが、本発明は、ICチップ8に個片化した再配線用基板13を接合するので、各部材(10,13)の熱膨張係数の差によって製造物に反りが発生することもない。仮に、樹脂(18)封止において、フィラーが混入していない液状樹脂をポッティングモールドした場合でも、高放熱基材10等に永久歪が生じることはなく、平面度の高い半導体素子(パッケージ)が得られるという利点がある。   According to such an embodiment, it is possible to manufacture a small semiconductor device having high heat dissipation characteristics using a conventional semiconductor manufacturing line. In the step of FIG. 2B, it is also possible to arrange a rewiring collective substrate with respect to the IC substrate 8. In this case, the thermal expansion coefficient of the rewiring collective substrate and the high heat dissipation base material 10 Although warpage occurs due to the difference, in the present invention, since the rewiring substrate 13 separated into the IC chip 8 is joined, warpage occurs in the product due to the difference in thermal expansion coefficient of each member (10, 13). There is nothing. Even if the resin (18) is sealed by potting a liquid resin in which no filler is mixed, permanent deformation does not occur in the high heat dissipation base material 10 and the like, and a semiconductor element (package) with high flatness is obtained. There is an advantage that it can be obtained.

更に、ACF16を含む個片化された再配線用基板13をICチップ8へその都度位置補正を行いながら搭載し、再配線を行うことが可能であるため、集合基板の状態の再配線用基板との再配線を行う工法に比べ、より小型の半導体素子を製造するために優位である。なお、再配線用基板13の形状をウェハーと同様の円形とすることもでき、半導体素子の製造コスト削減への対応も可能となる。   Further, the rewiring substrate 13 including the ACF 16 can be mounted on the IC chip 8 while correcting the position each time, and rewiring can be performed. Compared with the method of performing rewiring, it is advantageous for manufacturing a smaller semiconductor device. Note that the rewiring substrate 13 can have a circular shape similar to that of the wafer, and the manufacturing cost of the semiconductor element can be reduced.

また、実施例の半導体素子は、ICチップ8のスタッドバンプ9とは反対側の面に、高放熱材料10が接着剤で接着され、ICチップ8のバンプ電極に対しては、個片化された再配線用基板13が異方性導電フィルム16を介して接続された構成となり、高放熱特性を有する小型の半導体素子が得られるという利点がある。   Further, in the semiconductor element of the example, the high heat dissipation material 10 is bonded to the surface of the IC chip 8 opposite to the stud bump 9 with an adhesive, and the bump electrode of the IC chip 8 is separated into pieces. Further, the rewiring substrate 13 is connected via the anisotropic conductive film 16, and there is an advantage that a small semiconductor element having high heat dissipation characteristics can be obtained.

2,8…ICチップ、 4,18…封止用樹脂、
9…スタッドバンプ、 10…高放熱材料、
10a…金属薄板、 10b…塗料、
11…半導体用接着剤、 13…再配線用基板、
14a…配線、 14b…電極、
15…有機基板、 16…ACF(異方性導電フィルム)。
2, 8 ... IC chip, 4, 18 ... Resin for sealing,
9 ... Stud bump, 10 ... High heat dissipation material,
10a ... thin metal plate, 10b ... paint,
11 ... Adhesive for semiconductor, 13 ... Substrate for rewiring,
14a ... wiring, 14b ... electrode,
15 ... Organic substrate, 16 ... ACF (anisotropic conductive film).

Claims (2)

複数のICチップを高放熱基材の所定の位置へボンディングする工程と、
再配線のための配線及び電極が形成され、個片化された再配線用基板を、ICチップ上に搭載する工程と、
上記再配線用基板を搭載した複数のICチップに対し樹脂封止する工程と、
個々の半導体素子に個片化する工程と、を有する半導体素子の製造方法。
Bonding a plurality of IC chips to a predetermined position of the high heat dissipation substrate;
A step of mounting a wiring board and electrodes for rewiring and mounting the separated rewiring substrate on an IC chip;
A step of resin-sealing a plurality of IC chips mounted with the rewiring substrate;
A method of manufacturing a semiconductor element, comprising the step of dividing into individual semiconductor elements.
バンプ電極が形成されたICチップと、
再配線のための配線及び電極が形成され、かつ個片化された再配線用基板とを設け、
上記ICチップのバンプ電極とは反対側の面に、高放熱材料をボンディングし、上記ICチップのバンプ電極に対し、個片化された再配線用基板を異方性導電フィルムを介して接続してなる半導体素子。
An IC chip on which bump electrodes are formed;
Provided are wiring and electrodes for rewiring, and a rewiring substrate separated into pieces,
A high heat dissipation material is bonded to the surface opposite to the bump electrode of the IC chip, and the separated rewiring substrate is connected to the bump electrode of the IC chip through an anisotropic conductive film. A semiconductor element.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001358172A (en) * 2000-06-15 2001-12-26 Seiko Epson Corp Semiconductor package
JP2003031737A (en) * 2002-06-03 2003-01-31 Fujitsu Ltd Semiconductor device and its manufacturing method
US20070092996A1 (en) * 2005-10-21 2007-04-26 Freescale Semiconductor, Inc. Method of making semiconductor package with reduced moisture sensitivity

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001358172A (en) * 2000-06-15 2001-12-26 Seiko Epson Corp Semiconductor package
JP2003031737A (en) * 2002-06-03 2003-01-31 Fujitsu Ltd Semiconductor device and its manufacturing method
US20070092996A1 (en) * 2005-10-21 2007-04-26 Freescale Semiconductor, Inc. Method of making semiconductor package with reduced moisture sensitivity

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