JP2013157396A - Compound semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor device and a manufacturing method of the same, which can effectively reduce leakage current between source-drain.SOLUTION: A compound semiconductor device comprises: a two-dimensional electron gas suppression layer 5 formed on an electron supply layer 4; a source electrode 12s and a drain electrode 12d which are formed at positions that sandwich the two-dimensional electron gas suppression layer 5; and a gate electrode 21 formed on the two-dimensional electron gas suppression layer 5. The compound semiconductor device further comprises an insulation layer 22 including at least a first part 22a which is positioned between the two-dimensional electron gas suppression layer 5 and the gate electrode 21 and which functions as a gate insulation film, and a second part 22b which is positioned on the electron supply layer 4 and between the first part 22a and the drain electrode 12d. The second part 22b includes a tapered, inclined plane 22c at an end on the first part 22a side. The gate electrode 21 is formed so as to follow the inclined plane 22c.

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  In recent years, a compound semiconductor device having a high withstand voltage and a high output has been actively developed using characteristics of a nitride compound semiconductor such as a high saturation electron velocity and a wide band gap. For example, field effect transistors such as a high electron mobility transistor (HEMT) have been developed. Among them, GaN-based HEMTs that include a GaN layer as an electron transit layer (channel layer) and an AlGaN layer as an electron supply layer have attracted attention. In such a GaN-based HEMT, a strain caused by the difference in lattice constant between AlGaN and GaN is generated in the AlGaN layer, piezo-polarization occurs along with this strain, and a high-concentration two-dimensional electron gas is formed in the GaN under the AlGaN layer. Occurs near the top surface of the layer. For this reason, a high output can be obtained.

  However, since a two-dimensional electron gas is present at a high concentration, it is difficult to realize a normally-off transistor. In order to solve this problem, various techniques have been studied. For example, a technique has been proposed in which a p-type GaN layer is formed between a gate electrode and an electron supply layer to cancel two-dimensional electron gas.

  In order to suppress the gate leakage current, it is preferable to adopt a MIS (metal insulator semiconductor) structure using a gate insulating film.

  However, in a conventional MIS HEMT having a p-type GaN layer and having a MIS structure, it is difficult to reduce the source-drain leakage current.

JP 2005-244072 A JP 2006-32552 A

  An object of the present invention is to provide a compound semiconductor device capable of effectively reducing a leakage current between a source and a drain and a method for manufacturing the same.

  An aspect of the compound semiconductor device includes an electron transit layer, an electron supply layer formed above the electron transit layer, and a two-dimensional electron gas suppression layer formed above the electron supply layer. ing. Provided are a source electrode and a drain electrode formed at a position sandwiching the two-dimensional electron gas suppression layer between the electron supply layer and a gate electrode formed above the two-dimensional electron gas suppression layer. It has been. Furthermore, at least a first part that functions as a gate insulating film located between the two-dimensional electron gas suppression layer and the gate electrode, and the first part and the drain above the electron supply layer An insulating layer having a second portion located between the electrodes is provided. A tapered inclined surface is formed at an end portion of the second portion located on the first portion side, and the gate electrode is formed so as to follow the inclined surface.

  In one aspect of the method for manufacturing a compound semiconductor device, an electron supply layer is formed above the electron transit layer, and a two-dimensional electron gas suppression layer is formed above the electron supply layer. A source electrode and a drain electrode are formed above the electron supply layer at a position sandwiching the two-dimensional electron gas suppression layer, and a gate electrode is formed above the two-dimensional electron gas suppression layer. At least a first part that functions as a gate insulating film located between the two-dimensional electron gas suppression layer and the gate electrode, and the first part and the drain electrode above the electron supply layer An insulating layer having a second portion located between the two is formed. When forming the insulating layer, a tapered inclined surface is formed at an end portion of the second portion located on the first portion side, and the gate electrode is formed so as to follow the inclined surface. .

  According to the above compound semiconductor device or the like, the second portion appropriate for the insulating layer is formed, and the gate electrode is formed so as to follow the inclined surface of the second portion. Thus, the leakage current between the source and the drain can be effectively reduced.

It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 2nd Embodiment. It is sectional drawing about the manufacturing method of the compound semiconductor device which concerns on 2nd Embodiment. FIG. 3B is a cross-sectional view of the method for manufacturing the compound semiconductor device, following FIG. 3A. FIG. 3B is a cross-sectional view of the method for manufacturing the compound semiconductor device, following FIG. 3B. 3C is a cross-sectional view of the method for manufacturing the compound semiconductor device, following FIG. 3C. 3D is a cross-sectional view of the method for manufacturing the compound semiconductor device, following FIG. 3D. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 3rd Embodiment. It is sectional drawing about the manufacturing method of the compound semiconductor device which concerns on 3rd Embodiment. FIG. 5B is a cross-sectional view of the method for manufacturing the compound semiconductor device, following FIG. 5A. FIG. 5B is a cross-sectional view of the method for manufacturing the compound semiconductor device, following FIG. 5B. It is a figure which shows the discrete package which concerns on 4th Embodiment. It is a connection diagram which shows the PFC circuit which concerns on 5th Embodiment. It is a connection diagram which shows the power supply device which concerns on 6th Embodiment. It is a connection diagram which shows the high frequency amplifier which concerns on 7th Embodiment.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a cross-sectional view showing the structure of the compound semiconductor device according to the first embodiment.

  In the compound semiconductor device (GaN-based HEMT) according to the first embodiment, as shown in FIG. 1, an electron supply layer 4 is formed above the electron transit layer (channel layer) 3, and above the electron supply layer 4. A two-dimensional electron gas (2DEG) suppression layer 5 such as a p-type GaN layer is formed. The band gap of the material of the electron supply layer 4 is larger than that of the material of the electron transit layer 3. A source electrode 12s and a drain electrode 12d are formed above the electron supply layer 4 at a position sandwiching the 2DEG suppression layer 5 therebetween in plan view. A gate electrode 21 is formed above the 2DEG suppression layer 5. An insulating layer 22 is formed above the electron supply layer 4. The insulating layer 22 includes at least a first portion 22a that functions as a gate insulating film located between the 2DEG suppression layer 5 and the gate electrode 21, and a first portion in plan view above the electron supply layer 4. A second portion 22b located between the portion 22a and the drain electrode 12d is included. A tapered inclined surface 22c is formed at the end of the second portion 22b located on the first portion 22a side in plan view, and the gate electrode 21 is formed so as to follow the inclined surface 22c. ing.

  In the compound semiconductor device according to the first embodiment configured as described above, since the band gap of the electron supply layer 4 is larger than the band gap of the electron transit layer 3, a quantum well is generated, and electrons are accumulated in the quantum well. Is done. As a result, a two-dimensional electron gas (2DEG 13) is generated in the vicinity of the interface between the electron transit layer 3 and the electron supply layer 4. However, since the 2DEG suppression layer 5 and the first portion 22 a are provided, the 2DEG 13 is canceled below the 2DEG suppression layer 5. For this reason, an appropriate normally-off operation can be realized. In addition, since the gate electrode 21 is formed so as to follow the inclined surface 22c formed at the end of the second portion 22b, the electric field concentration below the gate electrode 21 extends from directly below the 2DEG suppression layer 5 to the drain electrode 12d. It is gradually eased as it goes. For this reason, the leak current between the source and the drain due to the electric field concentration as occurs in the conventional GaN-based HEMT can be effectively suppressed.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 2 is a cross-sectional view showing the structure of the compound semiconductor device according to the second embodiment.

  In the compound semiconductor device (GaN-based HEMT) according to the second embodiment, as shown in FIG. 2, a buffer layer 102, an electron transit layer (channel layer) 103, and an electron supply layer 104 are formed on a substrate 101. . The band gap of the material of the electron supply layer 104 is larger than that of the material of the electron transit layer 103. In the buffer layer 102, the electron transit layer 103, and the electron supply layer 104, an element isolation region 106 that partitions an element region is formed. A protective film 107 is formed on the electron supply layer 104 and the element isolation region 106. An opening 107 a located in the element region is formed in the protective film 107, and the 2DEG suppression layer 105 is formed on the electron supply layer 104 in the opening 107 a. The opening 107a is formed in a tapered shape, and its inner side surface is, for example, a flat inclined surface 107b. An insulating film 108 covering the 2DEG suppression layer 105 is formed on the protective film 107 so as to extend to the outside of the inclined surface 107b with the 2DEG suppression layer 105 as a reference. A gate electrode 121 is formed on the insulating film 108. Further, an insulating film 110 covering the gate electrode 121 is formed on the protective film 107. An opening 111s and an opening 111d are formed at a position sandwiching the 2DEG suppression layer 105 between the insulating film 110 and the protective film 107, and the source electrode 112s and the drain are formed in the opening 111s and the opening 111d, respectively. An electrode 112d is formed.

  In this embodiment, the insulating layer 122 including the stacked body of the protective film 107 and the insulating film 108 includes a first portion 122a that functions as a gate insulating film, and the first portion 122a and the drain electrode 112d in plan view. The 2nd site | part 122b located between these is provided. A tapered inclined surface 122c exists at an end portion of the second portion 122b located on the first portion 122a side in plan view, and the gate electrode 121 is formed so as to follow the inclined surface 122c. Yes.

  In the second embodiment, since the band gap of the electron supply layer 104 is larger than the band gap of the electron transit layer 103, a quantum well is generated and electrons are accumulated in the quantum well. As a result, a two-dimensional electron gas (2DEG 113) is generated near the interface between the electron transit layer 103 and the electron supply layer 104. However, the 2DEG 113 is canceled by the action of the 2DEG suppression layer 105 below the 2DEG suppression layer 105. For this reason, a normally-off operation is possible.

  Furthermore, in this embodiment, since the gate electrode 121 is formed so as to follow the inclined surface 122c formed at the end of the second portion 122b, the electric field concentration below the gate electrode 121 starts from directly below the 2DEG suppression layer 105. It gradually relaxes toward the drain electrode 112d. For this reason, the leak current between the source and the drain due to the electric field concentration as occurs in the conventional GaN-based HEMT can be effectively suppressed. In particular, in a region between the 2DEG suppression layer 105 and the drain electrode 112d in plan view, only the thin insulating film 108 exists between the lower end of the gate electrode 121 and the electron supply layer 104. For this reason, the electric field concentration in this region can be more effectively mitigated. And the leak current between the source and the drain can be reduced more effectively.

  Next, a method for manufacturing a compound semiconductor device according to the second embodiment will be described. 3A to 3E are cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the second embodiment in the order of steps.

First, as shown in FIG. 3A (a), a buffer layer 102 is formed on a substrate 101 such as a Si substrate or a SiC substrate. As the buffer layer 102, for example, an AlN layer having a thickness of about 0.5 μm to 5.0 μm is formed. As the buffer layer 102, a stacked body in which a plurality of AlN layers and GaN layers are alternately stacked may be formed, and Al _x Ga _(1-x) N (0 _{) in which the} Al composition decreases as the distance from the interface with the substrate 101 increases. <X ≦ 1) layer (AlN at the interface with the substrate 101) may be formed. Thereafter, an electron transit layer (channel layer) 103 is formed on the buffer layer 102. As the electron transit layer 103, for example, a GaN layer having a thickness of about 1 μm to 3 μm is formed. Subsequently, the electron supply layer 104 is formed on the electron transit layer 103. As the electron supply layer 104, for example, an AlGaN layer having a thickness of about 5 nm to 40 nm and an Al composition of 10% to 30% is formed. Since the AlGaN band gap of the electron supply layer 104 is larger than the GaN band gap of the electron transit layer 103, a quantum well is generated, and electrons are accumulated in the quantum well. As a result, a two-dimensional electron gas (2DEG) as a carrier is generated in the vicinity of the interface between the electron transit layer 103 and the electron supply layer 104. Next, a 2DEG suppression layer 105 that reduces 2DEG is formed on the electron supply layer 104. As a result, 2DEG generated near the interface between the electron transit layer 103 and the electron supply layer 104 disappears. As the 2DEG suppression layer 105, for example, a p-type GaN layer having a thickness of about 10 nm to 150 nm and containing Mg as a p-type impurity at a concentration of about 4 × 10 ¹⁹ cm ⁻³ is formed.

Next, as shown in FIG. 3A (b), the other part of the 2DEG suppression layer 105 is removed by dry etching using an etching mask or the like covering the portion of the 2DEG suppression layer 105 where the GaN-based HEMT gate is to be formed. To do. As a result, 2DEG is generated again in the vicinity of the interface between the electron transit layer 103 and the electron supply layer 104 in the region where the 2DEG suppression layer 105 is removed. In this dry etching, for example, chlorine gas or SF _x gas is used as an etching gas. Thereafter, at least the crystals of the electron supply layer 104 and the electron transit layer 103 are damaged by ion implantation to form an element isolation region 106 that partitions the element region. In this ion implantation, for example, Ar ions or B ions are implanted.

  Subsequently, as shown in FIG. 3B (c), a protective film 107 is formed on the entire surface. As the protective film 107, for example, a silicon nitride film having a thickness of about 100 nm to 500 nm is formed by a plasma chemical vapor deposition (CVD) method, a thermal CVD method, or an atomic layer deposition (ALD) method. To do. When forming by plasma CVD method, film-forming temperature shall be about 400 degreeC, for example. Next, a resist pattern 131 is formed on the protective film 107 so as to expose a region where an opening is to be formed and cover other portions.

  Thereafter, as shown in FIG. 3B (d), the protective film 107 is wet etched using the resist pattern 131 as an etching mask. In this wet etching, for example, a chemical solution containing hydrofluoric acid is used as an etching solution. As a result of this wet etching, an opening 107a having an inclined inner surface is formed. That is, the inclined surface 107 b is formed on the protective film 107. The inclined surface 107 b is a flat surface and is inclined about 45 ° with respect to the surface of the electron supply layer 104.

  Subsequently, as shown in FIG. 3C (e), the resist pattern 131 is removed. Then, an insulating film 108 functioning as a gate insulating film is formed over the entire surface. As the insulating film 108, for example, an aluminum nitride film, a silicon nitride film, an aluminum oxynitride film, a hafnium oxide film, an aluminum oxide film, or the like having a thickness of about 5 nm to 100 nm is formed by an ALD method or the like. Moreover, you may form these laminated bodies. That is, for example, a laminated body of an aluminum nitride film and a silicon nitride film thereon may be formed. After forming the insulating film 108, annealing at about 400 ° C. to 1000 ° C. may be performed.

  Next, as illustrated in FIG. 3C (f), a conductive film 109 is formed over the insulating film 108. As the conductive film 109, for example, a titanium film, a titanium nitride film, a tantalum nitride film, an aluminum film or the like having a thickness of about 10 nm to 500 nm is formed by a physical vapor deposition (PVD) method. Thereafter, a resist pattern 132 is formed on the conductive film 109 so as to cover a region where the gate electrode 121 is to be formed and expose other portions.

  Subsequently, as shown in FIG. 3D (g), the conductive film 109 and the insulating film 108 are dry-etched using the resist pattern 132 as an etching mask. Then, the resist pattern 132 is removed. The conductive film 109 after dry etching becomes the gate electrode 121.

  Next, as shown in FIG. 3D (h), an insulating film 110 is formed on the entire surface. For example, a silicon oxide film is formed as the insulating film 110. The surface of the insulating film 110 is preferably flat, and for this purpose, a silicon oxide film using spin on glass (SOG) may be formed as the insulating film 110. Further, after a silicon oxide film or the like is formed by a deposition method or the like, the surface thereof may be planarized by a chemical mechanical polishing (CMP) method or the like. Thereafter, a resist pattern 133 is formed on the insulating film 110 so as to expose a region where a source electrode is to be formed and a region where a drain electrode is to be formed.

Subsequently, as shown in FIG. 3E (i), the insulating film 110 and the protective film 107 are dry-etched using the resist pattern 133 as an etching mask. As a result, an opening 111 s for the source electrode and an opening 111 d for the drain electrode are formed in the insulating film 110 and the protective film 107. In this dry etching, for example, using a parallel plate type etching apparatus, the substrate temperature is set to 25 ° C. to 200 ° C. and the pressure is set to 10 mT to 2 Torr in a gas atmosphere containing CF ₄ , SF ₆ , CHF ₃ or fluorine. The RF power is 10 W to 400 W.

  Next, as illustrated in FIG. 3E (j), the source electrode 112s is formed in the opening 111s, and the drain electrode 112d is formed in the opening 111d. As the source electrode 112s and the drain electrode 112d, for example, a stacked body of a tantalum film having a thickness of 10 nm and an aluminum film having a thickness of 300 nm thereon is formed by a PVD method. Thereafter, annealing is performed to change the tantalum film included in the source electrode 112s and the drain electrode 112d into a film having a lower contact resistance. For example, the annealing atmosphere is one or more of rare gas, nitrogen, oxygen, ammonia and hydrogen, the time is 180 seconds or less, and the temperature is 550 ° C. to 650 ° C. By this annealing treatment, the tantalum film and the aluminum film react to generate a minute Al spike on the semiconductor portion (electron supply layer 104). As a result, the contact resistance decreases. At this time, the low work function of Al also contributes to the reduction in resistance.

  Thereafter, a wiring, a passivation film, and the like are formed to complete the compound semiconductor device.

  Note that when 2DEG is generated again, the 2DEG suppression layer 105 may be thinned instead of removing the entire 2DEG suppression layer 105 in a region other than the region where the gate is to be formed in plan view. In this case, the thickness after thinning is preferably 10 nm or less. This is to generate a sufficient amount of 2DEG.

(Third embodiment)
Next, a third embodiment will be described. FIG. 4 is a sectional view showing the structure of the compound semiconductor device according to the third embodiment.

  In the compound semiconductor device (GaN-based HEMT) according to the third embodiment, as shown in FIG. 4, a stacked body of an insulating film 108a and an insulating film 108b is provided in place of the insulating film 108 in the second embodiment. ing. At least the insulating film 108b is thinner than the insulating film 108. The insulating film 108 b is formed on the entire lower part of the gate electrode 121, whereas the insulating film 108 a is formed only on a part of the lower part of the gate electrode 121. That is, in a region between the 2DEG suppression layer 105 and the drain electrode 112d in plan view, the insulating film 108a is formed so that a gap 115 exists between the protective film 107 and the insulating film 108a. The insulating film 108 b enters the gap 115. Other configurations are the same as those of the second embodiment.

  Also in the third embodiment, a normally-off operation is possible as in the second embodiment. In addition, the stacked body of the protective film 107, the insulating film 108a, and the insulating film 108b functions as the insulating layer 122 including the first portion 122a and the second portion 122b. A region where only the insulating film 108b thinner than the insulating film 108 is interposed between the lower end of the gate electrode 121 and the electron supply layer 104 exists between the 2DEG suppression layer 105 and the drain electrode 112d in plan view. That is, a region where only the insulating film 108b thinner than the first portion 122a exists is present between the 2DEG suppression layer 105 and the drain electrode 112d in plan view. For this reason, the electric field concentration can be further reduced as compared with the second embodiment, and the leakage current between the source and the drain can be suppressed.

  Next, a method for manufacturing a compound semiconductor device according to the third embodiment will be described. 5A to 5C are cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the third embodiment in the order of steps.

  First, as shown in FIG. 5A (a), the processes from the formation of the opening 107a to the protective film 107 and the removal of the resist pattern 131 are performed as in the second embodiment. Then, an insulating film 108a functioning as a gate insulating film is formed over the entire surface. As the insulating film 108a, for example, an aluminum nitride film, a silicon nitride film, an aluminum oxynitride film, a hafnium oxide film, an aluminum oxide film, or the like is formed by an ALD method or the like. Moreover, you may form these laminated bodies. That is, for example, a laminated body of an aluminum nitride film and a silicon nitride film thereon may be formed. The insulating film 108a is thinner than the insulating film 108 in the second embodiment, and is formed to have a thickness of about half, for example.

  Next, as shown in FIG. 5A (b), in order to process the insulating film 108a so that the gap 115 described above exists, a resist pattern 134 that covers a region where the insulating film 108a remains and exposes other portions is formed. It is formed on the insulating film 108a.

  Thereafter, as shown in FIG. 5B (c), the insulating film 108a is etched using the resist pattern 134 as an etching mask. As a result, a gap 115 is formed between the insulating film 108a and the protective film 107. As this etching, for example, wet etching using a chemical solution containing hydrofluoric acid is performed.

  Subsequently, as shown in FIG. 5B (d), the resist pattern 134 is removed. Then, an insulating film 108b functioning as a gate insulating film is formed on the entire surface. As the insulating film 108b, for example, an aluminum nitride film, a silicon nitride film, an aluminum oxynitride film, a hafnium oxide film, an aluminum oxide film, or the like having a thickness of about 5 nm to 100 nm is formed by an ALD method or the like. Moreover, you may form these laminated bodies. That is, for example, a laminated body of an aluminum nitride film and a silicon nitride film thereon may be formed. After forming the insulating film 108b, annealing may be performed at about 400 ° C. to 1000 ° C. for about 60 seconds.

  Next, as shown in FIG. 5C (e), a conductive film 109 is formed on the insulating film 108b and a resist pattern 132 is formed on the conductive film 109, as in the second embodiment. Thereafter, dry etching of the conductive film 109, the insulating film 108b, and the insulating film 108a is performed using the resist pattern 132 as an etching mask.

  Subsequently, as shown in FIG. 5D (g), the resist pattern 132 is removed. Then, similarly to the second embodiment, the processing after the formation of the insulating film 110 is performed.

  In this way, the compound semiconductor device is completed.

  In the second and third embodiments, a part of the upper surface of the insulating layer 122 supplies electrons more than the upper surface of the 2DEG suppression layer 105 between the 2DEG suppression layer 105 and the drain electrode 112d in plan view. Located on the layer 104 side. That is, a part of the lower end of the gate electrode 121 is located closer to the electron supply layer 104 than the upper surface of the 2DEG suppression layer 105. The entire lower end of the gate electrode 121 may be located in the same plane as the upper surface of the 2DEG suppression layer 105 or on the side away from the electron supply layer 104.

  In the second embodiment and the third embodiment, GaN is used for the electron transit layer 103, AlGaN is used for the electron supply layer 104, and a quantum well structure of GaN and AlGaN is adopted. The materials for the electron transit layer 103 and the electron supply layer 104 are not particularly limited as long as they can be generated.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment relates to a discrete package of a compound semiconductor device including a GaN-based HEMT. FIG. 6 is a diagram illustrating a discrete package according to the fourth embodiment.

  In the fourth embodiment, as shown in FIG. 6, the back surface of the HEMT chip 210 of the compound semiconductor device according to any one of the first to third embodiments is land (die pad) using a die attach agent 234 such as solder. 233 is fixed. Further, a wire 235d such as an Al wire is connected to the drain pad 226d to which the drain electrode 12d or 112d is connected, and the other end of the wire 235d is connected to a drain lead 232d integrated with the land 233. A wire 235s such as an Al wire is connected to a source pad 226s connected to the source electrode 12s or 112s, and the other end of the wire 235s is connected to a source lead 232s independent of the land 233. A wire 235g such as an Al wire is connected to the gate pad 226g connected to the gate electrode 21 or 121, and the other end of the wire 235g is connected to a gate lead 232g independent of the land 233. The land 233, the HEMT chip 210, and the like are packaged with the mold resin 231 so that a part of the gate lead 232g, a part of the drain lead 232d, and a part of the source lead 232s protrude.

  Such a discrete package can be manufactured as follows, for example. First, the HEMT chip 210 is fixed to the land 233 of the lead frame using a die attach agent 234 such as solder. Next, by bonding using wires 235g, 235d and 235s, the gate pad 226g is connected to the gate lead 232g of the lead frame, the drain pad 226d is connected to the drain lead 232d of the lead frame, and the source pad 226s is connected to the source of the lead frame. Connect to lead 232s. Thereafter, sealing using a molding resin 231 is performed by a transfer molding method. Subsequently, the lead frame is separated.

(Fifth embodiment)
Next, a fifth embodiment will be described. The fifth embodiment relates to a PFC (Power Factor Correction) circuit including a compound semiconductor device including a GaN-based HEMT. FIG. 7 is a connection diagram showing a PFC circuit according to the fifth embodiment.

  The PFC circuit 250 is provided with a switch element (transistor) 251, a diode 252, a choke coil 253, capacitors 254 and 255, a diode bridge 256, and an AC power supply (AC) 257. The drain electrode of the switch element 251 is connected to the anode terminal of the diode 252 and one terminal of the choke coil 253. The source electrode of the switch element 251 is connected to one terminal of the capacitor 254 and one terminal of the capacitor 255. The other terminal of the capacitor 254 and the other terminal of the choke coil 253 are connected. The other terminal of the capacitor 255 and the cathode terminal of the diode 252 are connected. A gate driver is connected to the gate electrode of the switch element 251. An AC 257 is connected between both terminals of the capacitor 254 via a diode bridge 256. A direct current power supply (DC) is connected between both terminals of the capacitor 255. In this embodiment, the compound semiconductor device according to any one of the first to third embodiments is used for the switch element 251.

  When manufacturing the PFC circuit 250, the switch element 251 is connected to the diode 252, the choke coil 253, and the like using, for example, solder.

(Sixth embodiment)
Next, a sixth embodiment will be described. The sixth embodiment relates to a power supply device including a compound semiconductor device including a GaN-based HEMT. FIG. 8 is a connection diagram illustrating the power supply device according to the sixth embodiment.

  The power supply device includes a high-voltage primary circuit 261 and a low-voltage secondary circuit 262, and a transformer 263 disposed between the primary circuit 261 and the secondary circuit 262.

  The primary circuit 261 is provided with an inverter circuit connected between both terminals of the PFC circuit 250 according to the sixth embodiment and the capacitor 255 of the PFC circuit 250, for example, a full bridge inverter circuit 260. The full bridge inverter circuit 260 is provided with a plurality (here, four) of switch elements 264a, 264b, 264c, and 264d.

  The secondary side circuit 262 is provided with a plurality (three in this case) of switch elements 265a, 265b, and 265c.

  In the present embodiment, the switch element 251 of the PFC circuit 250 and the switch elements 264a, 264b, 264c, and 264d of the full bridge inverter circuit 260 that constitute the primary circuit 261 are either one of the first to third embodiments. A compound semiconductor device is used. On the other hand, normal MIS type FETs (field effect transistors) using silicon are used for the switch elements 265a, 265b and 265c of the secondary side circuit 262.

(Seventh embodiment)
Next, a seventh embodiment will be described. The seventh embodiment relates to a high-frequency amplifier including a compound semiconductor device including a GaN-based HEMT. FIG. 9 is a connection diagram illustrating the high-frequency amplifier according to the seventh embodiment.

  The high frequency amplifier is provided with a digital predistortion circuit 271, mixers 272 a and 272 b, and a power amplifier 273.

  The digital predistortion circuit 271 compensates for nonlinear distortion of the input signal. The mixer 272a mixes the input signal compensated for nonlinear distortion and the AC signal. The power amplifier 273 includes the compound semiconductor device according to any one of the first to third embodiments, and amplifies the input signal mixed with the AC signal. In this embodiment, for example, by switching the switch, the output-side signal can be mixed with the AC signal by the mixer 272b and sent to the digital predistortion circuit 271.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
An electronic travel layer,
An electron supply layer formed above the electron transit layer;
A two-dimensional electron gas suppression layer formed above the electron supply layer;
A source electrode and a drain electrode formed at positions above the electron supply layer and sandwiching the two-dimensional electron gas suppression layer;
A gate electrode formed above the two-dimensional electron gas suppression layer;
At least a first part that functions as a gate insulating film located between the two-dimensional electron gas suppression layer and the gate electrode, and the first part and the drain electrode above the electron supply layer An insulating layer having a second portion located between
Have
A tapered inclined surface is formed at an end portion of the second part located on the first part side,
The compound semiconductor device, wherein the gate electrode is formed so as to follow the inclined surface.

(Appendix 2)
The electron transit layer is a GaN layer;
The electron supply layer is an AlGaN layer;
The compound semiconductor device according to appendix 1, wherein the two-dimensional electron gas suppression layer is a p-type GaN layer.

(Appendix 3)
A part of the lower end of the gate electrode is located between the two-dimensional electron gas suppression layer and the drain electrode on the electron supply layer side from the upper surface of the two-dimensional electron gas suppression layer. The compound semiconductor device according to Supplementary Note 1 or 2,

(Appendix 4)
4. The compound semiconductor device according to any one of appendices 1 to 3, wherein a portion thinner than the first portion exists in the second portion.

(Appendix 5)
5. The compound semiconductor device according to claim 1, wherein the inclined surface is inclined by 45 ° with respect to the upper surface of the electron supply layer.

(Appendix 6)
Forming an electron supply layer above the electron transit layer;
Forming a two-dimensional electron gas suppression layer above the electron supply layer;
Forming a source electrode and a drain electrode at a position sandwiching the two-dimensional electron gas suppression layer above the electron supply layer;
Forming a gate electrode above the two-dimensional electron gas suppression layer;
At least a first part that functions as a gate insulating film located between the two-dimensional electron gas suppression layer and the gate electrode, and the first part and the drain electrode above the electron supply layer Forming an insulating layer having a second portion located between the two,
Have
The step of forming the insulating layer includes a step of forming a tapered inclined surface at an end portion of the second portion located on the first portion side,
A method of manufacturing a compound semiconductor device, wherein the gate electrode is formed so as to follow the inclined surface.

(Appendix 7)
The electron transit layer is a GaN layer;
The electron supply layer is an AlGaN layer;
The method of manufacturing a compound semiconductor device according to appendix 6, wherein the two-dimensional electron gas suppression layer is a p-type GaN layer.

(Appendix 8)
A part of the upper surface of the insulating layer is positioned closer to the electron supply layer than the upper surface of the two-dimensional electron gas suppression layer between the two-dimensional electron gas suppression layer and the drain electrode. The method for manufacturing a compound semiconductor device according to appendix 6 or 7.

(Appendix 9)
The compound semiconductor device according to any one of appendices 6 to 8, wherein the step of forming the insulating layer includes a step of forming a portion thinner than the first portion in the second portion. Manufacturing method.

(Appendix 10)
10. The method of manufacturing a compound semiconductor device according to any one of appendices 6 to 9, wherein the inclined surface is inclined by 45 ° with respect to the upper surface of the electron supply layer.

3: Electron transit layer 4: Electron supply layer 5: Two-dimensional electron gas (2DEG) suppression layer 12g: Gate electrode 12s: Source electrode 12d: Drain electrode 22: Insulating layer 22a: First part 22b: Second part 22c : Inclined surface

Claims (6)

An electronic travel layer,
An electron supply layer formed above the electron transit layer;
A two-dimensional electron gas suppression layer formed above the electron supply layer;
A source electrode and a drain electrode formed at positions above the electron supply layer and sandwiching the two-dimensional electron gas suppression layer;
A gate electrode formed above the two-dimensional electron gas suppression layer;
At least a first part that functions as a gate insulating film located between the two-dimensional electron gas suppression layer and the gate electrode, and the first part and the drain electrode above the electron supply layer An insulating layer having a second portion located between
Have
A tapered inclined surface is formed at an end portion of the second part located on the first part side,
The compound semiconductor device, wherein the gate electrode is formed so as to follow the inclined surface. The electron transit layer is a GaN layer;
The electron supply layer is an AlGaN layer;
The compound semiconductor device according to claim 1, wherein the two-dimensional electron gas suppression layer is a p-type GaN layer.   A part of the lower end of the gate electrode is located between the two-dimensional electron gas suppression layer and the drain electrode on the electron supply layer side from the upper surface of the two-dimensional electron gas suppression layer. The compound semiconductor device according to claim 1 or 2.   4. The compound semiconductor device according to claim 1, wherein a portion thinner than the first portion exists in the second portion. 5. Forming an electron supply layer above the electron transit layer;
Forming a two-dimensional electron gas suppression layer above the electron supply layer;
Forming a source electrode and a drain electrode at a position sandwiching the two-dimensional electron gas suppression layer above the electron supply layer;
Forming a gate electrode above the two-dimensional electron gas suppression layer;
At least a first part that functions as a gate insulating film located between the two-dimensional electron gas suppression layer and the gate electrode, and the first part and the drain electrode above the electron supply layer Forming an insulating layer having a second portion located between the two,
Have
The step of forming the insulating layer includes a step of forming a tapered inclined surface at an end portion of the second portion located on the first portion side,
A method of manufacturing a compound semiconductor device, wherein the gate electrode is formed so as to follow the inclined surface. The electron transit layer is a GaN layer;
The electron supply layer is an AlGaN layer;
6. The method of manufacturing a compound semiconductor device according to claim 5, wherein the two-dimensional electron gas suppression layer is a p-type GaN layer.

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