JP2013150453A - Controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller capable of preventing overshoot or undershoot of an output voltage generated when the number of operated PWM control switching regulators is changed.SOLUTION: An SVID interface 14 receives from exterior a change command for changing the number of voltage regulators to be operated among a plurality of voltage regulators 30-1 to 30-4. In the case that the number of voltage regulators to be operated is increased from 1 to k (2≤k≤n), a hard logic power supply control circuit 13A sequentially starts outputting of pulses of second to k-th phase clocks for controlling second to k-th regulators after a pulse of a first phase clock for controlling the first regulator is outputted. The i-th phase clock delays by (i×T)/n compared with the first phase clock. T is a cycle of the first to n-th phase clocks, and i satisfies 2≤i≤n.

Description

  The present invention relates to a controller.

  Conventionally, a technique for suppressing fluctuations in the output voltage of a switching regulator is known. For example, in patent document 1 (Unexamined-Japanese-Patent No. 2007-288974), a regulator is switched according to a mode switching signal. That is, a technique is described in which voltage switching without overshoot is possible by supplying power corresponding to the output target voltage of a switching regulator by a series regulator having a high response speed only for a predetermined period.

  Patent Document 2 (Japanese Patent Laid-Open No. 2011-24305) describes a technique for switching the duty ratio in stages. That is, when the output current is smaller than the switching current value, the power supply device starts driving the first switching converter. Thereafter, when the output current increases from a value smaller than the switching current value, the power supply device starts driving the second switching converter and then stops driving the first switching converter. When the driving of the first switching converter and the second switching converter is started or stopped, the duty ratio of the MOSFET Q1 or MOSFET Q2 is not changed rapidly, but is gradually changed while changing its value over a plurality of times.

  In Patent Document 3 (Japanese Patent Application Laid-Open No. 2009-33855), when the detection voltage changes from a state higher than a target voltage to a lower state, the variable power of the hard switching regulator circuit is increased by a larger amount than usual to detect the detection voltage. A switching regulator is described that reduces the variable power of the hard switching regulator circuit by a larger amount than usual when the voltage changes from lower to higher than the target voltage.

JP 2007-288974 A JP 2011-24305 A JP 2009-33855 A

  However, in Patent Document 1, when the output voltage is changed, the output target voltage of the series regulator is used as the output target voltage of the power supply device, and the timing of PWM (Pulse Width Modulation) is not studied.

  Further, Patent Documents 1 to 3 do not consider measures for preventing output voltage overshoot or undershoot that occurs when the number of regulators to be operated is changed.

  When increasing the number of voltage regulators to be operated from one to k (2 ≦ k ≦ n), the controller according to one embodiment of the present invention provides a pulse of the first phase clock that controls the first regulator. And a controller that sequentially starts outputting pulses of the second to k-th phase clocks that control the second to k-th regulators. However, the i-th phase clock is delayed by (i × T) / n as compared to the first phase clock, T is the period of the first to n-th phase clocks, and 2 ≦ i ≦ n. .

  According to one embodiment of the present invention, it is possible to prevent overshoot or undershoot of the output voltage that occurs when the number of operating PWM control switching regulators is changed.

It is a figure showing the example from which an output voltage fluctuates at the time of the change of the power state mode in a prior art. It is a figure showing the structure of the semiconductor system of 1st Embodiment. It is a figure showing the change of a phase clock and a feedback coefficient in 1st Embodiment. It is a figure showing the change of a phase clock and a feedback coefficient in the modification of 1st Embodiment. It is a figure for demonstrating the processing time when changing the magnitude | size of the output voltage Vo. It is a figure showing the structure of the semiconductor system of 2nd Embodiment. It is a figure showing the structure of the semiconductor system of 3rd Embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
An object of the first embodiment is to solve a problem when the power state mode is changed.

First, a problem when the power state mode changes in the prior art will be described.
FIG. 1 is a diagram illustrating an example in which the output voltage fluctuates when the power state mode changes in the prior art.

  The power state mode defines the number of voltage regulators that operate. When the power state mode is State 1, one voltage regulator operates. When the power state mode is State 0, four voltage regulators operate.

  As shown in FIG. 1A, when the power state mode is State 1, one voltage regulator is operated by the phase clock CLK # 0. When the power state mode is State 0, four voltage regulators are operated by the phase clocks CLK # 1 to # 3.

  As shown in FIG. 1B, undershoot or overshoot occurs when the power state mode is switched from State 1 to State 0 and from State 0 to State 1. In order to avoid such an undershoot, a method of detecting and complementing the fluctuation waveform is also conceivable, but a delay occurs due to the complementation, which is not appropriate.

FIG. 2 is a diagram illustrating the configuration of the semiconductor system according to the first embodiment.
With reference to FIG. 2, the semiconductor system includes a controller 1, a regulator group 30, and a CPU 25.

  The regulator group 30 supplies the voltage Vo to the CPU 25 under the control of the controller 1 </ b> A and the CPU 25. The regulator group 30 includes four voltage regulators 30-1 to 30-4.

Here, the controller 1A is composed of one chip (one semiconductor chip).
The controller 1A includes a PIN control unit 6, a flash memory 7, a parameter register 8, a performance register 9, an MCU 5, a PMBUS (Power Management Bus) interface 10, an SVID (Serial VID) command determination circuit 12, a hardware A logic power supply control circuit 13A, an analog power supply control circuit 11A, and a power supply abnormality monitoring circuit 2 are provided.

  Among the components of the controller 1A, the MCU 5, the hard logic power supply control circuit 13A, the analog power supply control circuit 11A, and the power supply abnormality monitoring circuit 2 constitute a control unit 161A.

  The SVID command determination circuit 12 includes an SVID interface 14, an operation mode register 16, a voltage instruction value register 18, and a power state instruction value register 19.

  Here, the CPU 25 is composed of one chip, and receives the power supply voltage output from the voltage regulators 30-1 to 30-4 and performs various processes. Further, the CPU 25 sends an instruction to the controller 1A through the SVID interface 14. For example, the CPU 25 sends a control signal instructing to change the number of voltage regulators to be operated to the controller 1A through the SVID interface 14 in accordance with the required amount of power.

  The PIN control unit 6 outputs setting information indicating how the external terminal is set to the MCU 5 in accordance with the terminal potential fixed by the external potential fixing unit 26.

  The flash memory 7 stores a program for the MCU 5 to perform processing. By using the program, it is possible to save the trouble of redeveloping the device even if the power supply standard is changed. The flash memory 7 stores a table of a plurality of parameters that define initial values such as a maximum allowable voltage value, a maximum allowable temperature, and a maximum allowable current.

  Through the SVID interface 14, the parameter register 8 changes the voltage value change amount (step voltage) for each step in the digital step control and the instruction voltage and the discharge mode that are the final voltages to be lowered in the discharge mode before reaching the instruction voltage. The value of ΔV, which is the difference from the target voltage Vs when the discharge mode is terminated, is stored.

  The performance register 9 receives and stores data such as the maximum allowable voltage value, the maximum allowable temperature, and the maximum allowable current recorded in the flash memory 7.

  Here, the maximum allowable voltage value is the maximum power supply voltage that can be applied to the CPU. The maximum allowable temperature is the highest temperature allowed for operation at a temperature measured from a voltage regulator or the like. The maximum allowable current is the maximum current that the voltage regulator can flow. When these values are exceeded, the controller outputs an instruction signal to a voltage regulator or the like so as to decrease the values.

The MCU 5 performs arithmetic processing based on the program.
The PMBUS interface 10 receives a signal from the external system control unit 27 through the PMBUS and outputs a signal to the external system control unit 27.

  The SVID interface 14 receives a signal from the CPU 25 through a serial communication line and outputs a signal to the CPU 25.

  The operation mode register 16 stores the current operation mode. For example, the operation mode includes a normal mode and a discharge mode.

  The voltage instruction value register 18 stores a voltage value instructed by the CPU 25 during voltage control.

  The power state instruction value register 19 stores a power state mode instructed by the CPU 25 during power state control. The power state mode determines the number of voltage regulators that operate. When the power state mode is State 1, one voltage regulator 30-1 operates. When the power state mode is State 0, the four voltage regulators 30-1 to 30-4 operate.

  The hard logic power supply control circuit 13 includes a DAC digital step control unit 220 and a phase clock generation unit 21.

  The DAC digital step control unit 220 determines a voltage change value at each step so as to reach the voltage specified in a plurality of steps, and outputs the determined voltage change value as a digital voltage DV.

  The phase clock generator 121 activates the control signal SMOD to the voltage regulator to be operated. When the power state mode is State 0, the phase clock generator 121 activates the control signals SMOD # 0 to SMOD # 3 to the four voltage regulators 30-1 to 30-4. The phase clock generation unit 121 activates the control signal SMOD # 0 to one voltage regulator 30-1 when the power state mode is State1.

  Further, the phase clock generation unit 121 determines the phase of the phase clock to the voltage regulator to be operated, and outputs the phase clock having the determined phase. The phase clock generation unit 21 generates a phase clock at a PWM (Pulse Width Modulation) cycle timing according to an internal timer. The period of the phase clock of the voltage regulator is the same (PWM period), but the phases of the phase clocks of the voltage regulator are all different. The phase clock generation unit 21 deactivates the control signal SMOD to the voltage regulator to be stopped.

  The phase clocks output from the phase clock generator 121 to the voltage regulators 30-1 to 30-4 are referred to as phase clocks CLK # 0 to CLK # 3, respectively. The periods of the phase clocks CLK # 0 to CLK # 3 are the same T. The phases of the phase clocks CLK # 1 to CLK # 3 are delayed by T / 4, 2T / 4, and 3T / 4, respectively, with respect to the phase clock CLK # 0.

  The analog power supply control circuit 11A includes a DAC (Digital Analog Converter) 22A, a differential amplifier 24A, an error amplifier 23, an ADC (Analog Digital Converter) 17, and a filter unit 59. Filter unit 59 includes resistors R1 to R3, capacitors C2 and C2, and a switch SW1 controlled by control signal SW1C.

  The DAC 22A converts the digital voltage DV output from the DAC digital step control unit 20 into an analog voltage Vd. Further, the DAC 22A outputs a control signal SW1C for controlling the switch SW1 based on the phase clock CLK # 0. In the power state mode State1 (single unit operation), the DAC 22 sets the control signal SW1C to a low level and turns off the switch SW1. As a result, the resistance value in the filter unit 59 becomes RS1. When the DAC 22A is in the power state mode State0 (operation of four units), the DAC 22A sets the control signal SW1C to a high level and turns on the switch SW1. As a result, the resistance value in the filter unit 59 becomes RS2.

  When the power state mode is switched, the DAC 22A switches on / off the switch SW1 by switching the level of the control signal SW1C at the timing of the first pulse of the phase clock CLK # 0.

  The differential amplifier 24 amplifies the difference between the high-potential-side voltage VSEN1 and the low-potential-side voltage VSEN2 of the CPU 25 and outputs the voltage V2.

  The error amplifier 23 receives the voltage Vd output from the DAC 22 at the positive input terminal, and receives the voltage output from the differential amplifier 24 and the feedback current from the current control unit 41 at the negative input terminal. The error amplifier 23 amplifies the difference between the voltages at the two input terminals, and outputs the amplified voltage to the voltage regulator as a voltage representing the difference between the designated voltage and the current CPU 25 voltage.

  The current control unit 41 detects the amount of current Io supplied from the regulator group 30 based on the output voltage from the error amplifier 23. The current control unit 41 supplies a feedback current GC × Io proportional to the detected current amount Io to the negative input terminal of the error amplifier 23. GC1 is a feedback coefficient. The current control unit 41 supplies a feedback current GC × Io corresponding to the power state mode in order to prevent undershoot or overshoot of the output voltage Vo when changing in the power state mode. That is, the current control unit 41 supplies the feedback current CG0 × Io (that is, the feedback coefficient is set to GC0) in the power state mode State0 (operation of four units). The current control unit 41 supplies the feedback current GC1 × Io (that is, the feedback coefficient is GC1) in the power state mode State1 (single unit operation). Here, GC0 / GC1 = 4.

  When the power state mode is switched, the current control unit 41 switches the value of the feedback coefficient GC at the timing of the first pulse of the phase clock CLK # 0.

The ADC 17 AD converts the output voltage Vo of the regulator group 30.
The power supply abnormality monitoring circuit 2 includes a voltage comparator 4 and a power supply abnormality monitoring unit 3.

  The voltage comparator 4 receives the voltage generated by the voltage regulator and compares it with a predetermined standard voltage by analog processing.

  The power supply abnormality monitoring unit 3 monitors whether the power supply voltage of the CPU 25 is abnormal according to the output of the voltage comparator 4.

  The voltage regulators 30-1 to 30-4 supply a power supply voltage to the CPU 25. Here, each of the voltage regulators 30-1 to 30-4 is housed in one package. Further, here, the package is composed of three chips of a high-side MOS transistor 196, a low-side MOS transistor 197, and other parts (PWM unit 151 and MOS control unit 198).

  The voltage regulators 30-1 to 30-4 are PWM control switching regulators that operate according to the phase clock, and include a PWM unit 151 and a DC-DC converter 33. The voltage regulators 30-1 to 30-4 operate when the control signal SMOD is activated, and stop operating when the control signal SMOD is deactivated.

The PWM unit 151 includes a PWM comparator 31 and a latch circuit 32.
The PWM comparator 31 outputs a PWM signal based on the error signal that is the output of the error amplifier 23.

  The output of the PWM comparator 31 is input to the set terminal S of the latch circuit 32. The phase clock that is the output of the phase clock generator 21 is input to the reset terminal R of the latch circuit 32.

  The DC-DC converter 33 is connected to the output of the latch circuit 32 and supplies a power supply voltage to the CPU 25. Here, the DC-DC converter 33 is controlled by the PWM signal output from the latch circuit 32.

  When the high side MOS transistor 196 shown in FIG. 2 is turned on and the low side MOS transistor 197 is turned off, the voltage VSEN1 of the CPU voltage line on the high potential side of the CPU 25 increases. On the other hand, when the high side MOS transistor 196 is turned off and the low side MOS transistor 197 is turned on, the voltage VSEN1 of the CPU voltage line drops.

  In the normal mode, on / off of the high-side MOS transistor 196 and the low-side MOS transistor 197 is controlled so that the voltage VSEN1 of the CPU voltage line becomes a constant voltage. That is, when the voltage is low, the high side MOS transistor 196 is turned on (at this time, the low side MOS transistor 197 is turned off) to increase the voltage, or when the voltage is high, the low side MOS transistor 197 is turned on (at this time, the high side MOS transistor 197 is turned off). The MOS transistor 196 is turned off, and the voltage is lowered.

  FIG. 3 is a diagram illustrating changes in the phase clock and the feedback coefficient in the first embodiment.

  FIG. 3 shows an example in which the power state mode changes from State 1 to State 0 to State 1.

  First, in State 1, the phase clock generation unit 121 activates the control signal SMOD # 0, generates CLK # 0, and supplies it to the voltage regulator 30-1.

  In the transition from State 1 to State 0, the phase clock generation unit 121 activates the control signal SMOD # 3 and starts generating the phase clock (CLK # 3) immediately after the switching timing as shown in (1). do not do. Instead, the phase clock generator 121 generates the control signal SMOD # 1, SMOD # 2, SMOD # 2, after the first phase clock CLK # 0 pulse is generated after switching from State1 to State0 (shown in (2)). The activation is performed in the order of SMOD # 3, and generation is started in the order of phase clocks CLK # 1, CLK # 2, and CLK # 3. As a result, the first output pulse in the PWM cycle at State 0 can be made the pulse of the phase clock CLK # 0.

  Also, according to the first pulse of the phase clock CLK # 0 after switching from State1 to State0, the current control unit 41 switches the feedback coefficient to GC0, the DAC 22A sets the control signal SW1C to high level, and switches the switch SW1. turn on. As a result, the current supplied to the error amplifier 23 changes from GC1 × Io to GC0 × Io.

  In the transition from State 0 to State 1, the phase clock generator 121 deactivates the control signal SMOD # 3 and stops generating the phase clock (CLK # 3) immediately after the timing of switching as shown in (3). Do not do. Instead, after the phase clock CLK # 0 is generated (shown in (4)) after the phase clock generator 121 switches from the State 0 to the State 1, the control signals SMOD # 1, SMOD # 2, and SMOD # 3 are generated. Are deactivated in this order, and generation is stopped in the order of the phase clocks CLK # 1, CLK # 2, and CLK # 3. As a result, the number of phase clock pulses in the PWM period (that is, the number of operating voltage regulators) can be changed from four to one. As shown in (3), when the generation of the phase clock (CLK # 3) is stopped, the number of pulses of the phase clock changes as 4 → 3 → 1. Does not match the instructions.

  In addition, according to the first phase clock CLK # 0 pulse after switching from State 0 to State 1, the current control unit 41 switches the feedback coefficient to GC1, the DAC 22A sets the control signal SW1C to low level, and turns off the switch SW1. To. As a result, the supplied current changes from GC0 × Io to GC1 × Io.

  As described above, according to the present embodiment, the number of PWM control switching regulators operated by controlling the generation and stop of the other phase clocks CLK # 1 to # 3 starting from the phase clock CLK # 0. It is possible to prevent overshoot or undershoot of the output voltage that occurs when V is changed.

[Modification 1 of the first embodiment]
In the first embodiment, the feedback current amount is changed by switching the feedback coefficient GC and the level of the control signal SW1C at the timing of the first pulse of the phase clock CLK # 0 after the power state mode is switched. However, when processing delay in the filter unit 59 becomes a problem, it is desirable to change the feedback current amount at a timing preceding the timing of the first phase clock CLK # 0 after the power state mode is switched. In this modification, a method for changing the feedback current amount in advance will be described.

  FIG. 4 is a diagram illustrating changes in the phase clock and the feedback coefficient in the modification of the first embodiment.

  First, in State 1, the phase clock generation unit 121 activates the control signal SMOD # 0, generates CLK # 0, and supplies it to the voltage regulator 30-1.

  In the transition from State 1 to State 0, the phase clock generation unit 121 activates the control signal SMOD # 3 and starts generating the phase clock (CLK # 3) immediately after the switching timing as shown in (1). do not do. Instead, the phase clock generator 121 generates the control signal SMOD # 1, SMOD # 2, SMOD # 2, after the first phase clock CLK # 0 pulse is generated after switching from State1 to State0 (shown in (2)). The activation is performed in the order of SMOD # 3, and generation is started in the order of phase clocks CLK # 1, CLK # 2, and CLK # 3. As a result, the first output pulse in the PWM cycle at State 0 can be made the pulse of the phase clock CLK # 0.

  In addition, before the first phase clock CLK # 0 pulse is output after switching from State1 to State0, the current control unit 41 switches the feedback coefficient to GC0 in accordance with the pulse of the previous phase clock CLK # 0, and the DAC 22A Sets the control signal SW1C to a high level and turns on the switch SW1. As a result, the supplied current changes from GC1 × Io to GC0 × Io. Thus, by switching the magnitude of the feedback current prior to the switching of the phase clock, it is possible to prevent a delay until the increase in the feedback current amount is reflected in the output voltage Vo.

  In the transition from State 0 to State 1, the phase clock generator 121 deactivates the control signal SMOD # 3 and stops generating the phase clock (CLK # 3) immediately after the timing of switching as shown in (3). Do not do. Instead, after the phase clock CLK # 0 is generated (shown in (4)) after the phase clock generator 121 switches from the State 0 to the State 1, the control signals SMOD # 1, SMOD # 2, and SMOD # 3 are generated. And the generation is stopped in the order of the phase clocks CLK # 1, CLK # 2, and CLK # 3. As a result, the number of phase clock pulses in the PWM period (that is, the number of operating voltage regulators) can be changed from four to one.

  Before the first phase clock CLK # 0 pulse is output after switching from State0 to State1, the current control unit 41 switches the feedback coefficient to GC1 according to the previous phase clock CLK # 0 pulse, and the DAC 22A The control signal SW1C is set to a low level, and the switch SW1 is turned off. As a result, the supplied current changes from GC0 × Io to GC1 × Io. Thus, by switching the magnitude of the feedback current prior to the switching of the phase clock, it is possible to prevent a delay until the decrease in the feedback current amount is reflected in the output voltage Vo.

[Modification 2 of the first embodiment]
In the first embodiment, switching between State 1 in which one of four regulators operates and State 0 in which all four regulators operate has been described. However, the present invention is not limited to this.

  Switching between State 1 in which one of the n regulators operates and State 0 in which k of the n regulators (2 ≦ k ≦ n) operate can be switched in the same manner. When the number of voltage regulators to be operated is increased from 1 to k, after the pulse of the phase clock CLK # 0 is output, the output of the pulses of the phase clock CLK # 2 to CLK # k is sequentially started. When the number of voltage regulators to be operated is decreased from k to 1, the output of the pulses of the phase clock CLK # 2 to CLK # k is stopped after the pulse of the phase clock CLK # 0 is output. Here, the phase clock CLK # i (2 ≦ i ≦ k) is delayed by (i × T) / n from the phase clock CLK # 0.

[Second Embodiment]
The second embodiment aims to solve the problem in changing the voltage instruction value.

  FIG. 5 is a diagram for explaining the processing time when the magnitude of the output voltage Vo is changed.

  As shown in FIG. 5, when the output voltage Vo is changed from Vo1 to Vo2, the processing time Tat from when the control command is received until the completion of the operation indicating completion is obtained, and the change rate dVd of the DAC output voltage Vd. / Dt is determined so as to be within a certain period of time.

  When there is no feedback current from the current control unit 41, the target voltage Vr, which is the voltage at the negative input terminal of the error amplifier 23, matches the output voltage Vd of the DAC, but the feedback current from the current control unit 41 is In some cases, the target voltage Vr, which is the voltage at the negative input terminal of the error amplifier 23, is apparently expressed by the following equation.

Vr = Vd−GC × Io (1)
The output current Io includes a current I1 flowing through the CPU 25 and a current I2 that charges the output capacitor CX. Therefore, Formula (1) becomes as follows.

Vr = Vd−GC × (I1 + I2) (2)
When the output voltage Vo changes, the current I2 that charges the output capacitor CX increases. When the current I2 increases, the target voltage Vr temporarily decreases. As a result, as shown in FIG. 5, the rise time of the output voltage Vo becomes long, and there is a problem that the processing times Tat and dVd / dt cannot be within a certain time.

FIG. 6 is a diagram illustrating a configuration of a semiconductor system according to the second embodiment.
The semiconductor system of FIG. 6 is different from the semiconductor system of the first embodiment of FIG. 2 in a DAC digital step control unit 520, a DAC 22B, and a current control unit 41B.

  When the updated value of the voltage instruction value is stored in the voltage instruction value register 18 from the CPU 25, the DAC digital step control unit 520 instructs the current controller 41B to switch the value of the feedback coefficient GC.

  When receiving an instruction to switch the feedback coefficient GC from the DAC digital step control unit 520, the current control unit 41B decreases the value of the feedback coefficient GC for a fixed time, and returns the feedback coefficient GC to the original value after the fixed time has elapsed. Here, the fixed time is the time until the voltage control based on the updated voltage instruction value ends and the output voltage Vo does not change.

  As described above, according to the present embodiment, while the output voltage Vo is changing, by reducing the amount of feedback current, the processing time from receiving the control command until the completion of the operation indicating completion is obtained. Tat and the rate of change dVd / dt of the output voltage Vd of the DAC can be kept within a certain time.

[Modification of Second Embodiment]
In the second embodiment, when the current control unit 41B receives an instruction to switch the feedback coefficient GC from the DAC digital step control unit 520, the current control unit 41B decreases the value of the feedback coefficient GC for a certain period of time. The value may be gradually reduced.

  Further, upon receiving an instruction to switch the feedback coefficient GC from the DAC digital step control unit 520, the current control unit 41B, based on one or a combination of two or more of the following (1) to (4), The value of the feedback coefficient GC may be switched for a certain time.

(1) The value of the current output voltage Vo detected by the ADC 17,
(2) The voltage instruction value after the change from the CPU 25,
(3) The difference between the voltage instruction value before the change and the voltage instruction value after the change,
(4) Time required for changing the output voltage sent from the CPU 25 together with the changed voltage instruction value.

[Third Embodiment]
Similar to the second embodiment, the third embodiment aims to solve the problem in changing the voltage instruction value.

FIG. 7 is a diagram illustrating a configuration of a semiconductor system according to the third embodiment.
The semiconductor system of FIG. 7 is different from the semiconductor system of the first embodiment of FIG. 2 in a DAC digital step control unit 420, a DAC 22C, a switch SW2, and a current control unit 41C.

  When the updated value of the voltage instruction value is stored in the voltage instruction value register 18 from the CPU 25, the DAC digital step control unit 420 instructs the DAC 22C to turn off the switch SW2.

The DAC 22C turns off the switch SW2 by switching the level of the control signal SW2C to low level based on an instruction from the DAC digital step control unit 520.
Further, the DAC 22C turns on the switch SW2 by switching the level of the control signal SW2C to a high level after a predetermined time, that is, after a predetermined number of pulses of the phase clock CLK # 0 are output, after the switch SW2 is turned off. To do. Here, the fixed time is the time until the voltage control based on the updated voltage instruction value ends and the output voltage Vo does not change.

  The switch SW2 is turned on when the control signal SW2 is at a high level, and turned off when the control signal SW2 is at a low level.

  The current control unit 41C latches the value of the detected current amount Io and supplies the same feedback current GC × Io to the negative input terminal of the error amplifier 23 unless the current amount Io changes. Therefore, while the output voltage Vo is changing, the value of the feedback current can be prevented from changing. Therefore, the feedback current increases due to the increase in the amount of current I2 charged to the capacitor CX, and the output voltage Vo The problem of a long rise time can be avoided.

  As described above, according to the present embodiment, while the output voltage Vo is changing, by maintaining the amount of feedback current immediately before the change, the operation completion indicating completion after receiving the control command is completed. The processing time Tat until output and the rate of change dVd / dt of the output voltage Vd of the DAC can be kept within a certain time.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1A, 1B, 1C controller, 2 power supply abnormality monitoring circuit, 3 power supply abnormality monitoring part, 4 voltage comparator, 5 MCU, 6 PIN control part, 7 flash memory, 8 parameter register, 9 performance register, 10 PMBUS interface, 11, A , 11B, 11C Analog power supply control circuit, 12 SVID command determination circuit, 13A, 13B, 13C hard logic power supply control circuit, 161A, 161B, 161C control unit, 14 SVID interface, 16 operation mode register, 18 voltage instruction value register, 19 Power state instruction value register, 220, 420, 520 DAC digital step controller, 121 phase clock generator, 22A, 22B, 22C DAC, 23 error amplifier, 24 differential amplifier, 25 CP , 26 potential fixing unit, 27 system control unit, 30 regulator group, 30-1 to 30-4 voltage regulator, 31 PWM comparator, 32 latch circuit, 33 DC-DC converter, 151 PWM unit, 196 high side MOS transistor, 197 Low side MOS transistor, 198 MOS controller.

Claims (5)

A controller that controls a plurality of voltage regulators that supply a power supply voltage to the first semiconductor device, wherein the plurality of voltage regulators are PWM control switching regulators that operate according to a phase clock;
An interface for receiving a command to change the number of the voltage regulators to be operated from among the plurality of voltage regulators;
When the number of voltage regulators to be operated is increased from one to k (2 ≦ k ≦ n), after the first phase clock pulse for controlling the first regulator is output, the second to second a controller for sequentially starting output of pulses of the second to k-th phase clocks for controlling the regulator of k,
The i-th phase clock is delayed by (i × T) / n with respect to the first phase clock, where T is the period of the first to n-th phase clocks, and 2 ≦ i ≦ n.   When the number of voltage regulators to be operated is decreased from k to one, the control unit outputs the pulses of the second to k-th phase clocks after the first phase clock pulse is output. The controller according to claim 1, wherein output is stopped. The controller is
A current controller for supplying a feedback current according to the current output from the voltage regulator;
An error amplifier that amplifies a difference between voltages input to the first terminal and the second terminal and outputs the amplified difference to the voltage regulator, the first terminal receives an instruction voltage, and the second terminal is , Receiving a voltage applied to the first semiconductor device and receiving the feedback current,
The current control unit supplies, as the feedback current, a current obtained by multiplying a current output from the voltage regulator by a feedback coefficient,
3. The controller according to claim 2, wherein, when the number of voltage regulators to be operated is changed, the current control unit switches the value of the feedback coefficient in accordance with the pulse of the first clock. A controller that controls a plurality of voltage regulators that supply a power supply voltage to the first semiconductor device, wherein the plurality of voltage regulators are PWM control switching regulators that operate according to a clock;
An interface that receives an updated value of the indicated voltage from the outside,
A control unit that controls the plurality of voltage regulators according to an update value of the instruction voltage;
The controller is
A current controller for supplying a feedback current according to the current output from the voltage regulator;
An error amplifier that amplifies a difference between voltages input to the first terminal and the second terminal and outputs the amplified difference to the voltage regulator, the first terminal receives an instruction voltage, and the second terminal is , Receiving a voltage applied to the first semiconductor device and receiving the feedback current,
The current control unit supplies, as the feedback current, a current obtained by multiplying a current output from the voltage regulator by a feedback coefficient,
When the current control unit receives an updated value of the instruction voltage from the outside, the current control unit is configured to change the feedback coefficient of the first semiconductor device while the voltage applied to the first semiconductor device is changing compared to before receiving the updated value. Controller to decrease the value. A controller that controls a plurality of voltage regulators that supply a power supply voltage to the first semiconductor device, wherein the plurality of voltage regulators are PWM control switching regulators that operate according to a clock;
An interface that receives an updated value of the indicated voltage from the outside,
A control unit that controls the plurality of voltage regulators according to an update value of the instruction voltage;
The controller is
A current controller for supplying a feedback current according to the current output from the voltage regulator;
An error amplifier that amplifies a difference between voltages input to the first terminal and the second terminal and outputs the amplified difference to the voltage regulator, the first terminal receives an instruction voltage, and the second terminal is , Receiving a voltage applied to the first semiconductor device and receiving the feedback current,
The current control unit supplies, as the feedback current, a current obtained by multiplying a current output from the voltage regulator by a feedback coefficient,
When the current control unit receives the updated value of the instruction voltage from the outside, the current control unit determines the magnitude of the feedback current before receiving the updated value while the voltage applied to the first semiconductor device is changing. Maintain the controller.

Images