JP2013150102A - Peak factor reduction circuit and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a peak factor reduction circuit which can cut down power consumption.SOLUTION: In a peak factor reduction circuit, determination of whether the frequency band of a modulation signal included in an input signal is located on frequency axis symmetrically to a baseband frequency is made on the basis of carrier setting information, and the determination result is output as a carrier asymmetric arrangement flag. If the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrical to the baseband frequency, a complex filtering section stops operations executed in complex filter arithmetic between a peak correction signal and a complex filter coefficient, which include a filter arithmetic operation on the real part of the peak correction signal and the imaginary part of the complex filter coefficient and a filter arithmetic operation on the imaginary part of the peak correction signal and the imaginary part of the complex filter coefficient.

Description

  The present invention relates to a peak factor reduction circuit for reducing a peak factor of a transmission signal and a control method thereof.

  The power amplifier used in the transmission device needs to be designed in consideration of backoff (difference between the maximum output power level and the output saturation power level) in order to amplify the transmission signal with low distortion. In particular, since a digitally modulated signal has a large difference between peak power and average power, a power amplifier that amplifies the signal after digital modulation needs to have a large backoff margin. However, a power amplifier having a large back-off margin, that is, a power amplifier having a large dynamic range is generally large and consumes a large amount of power. Therefore, for example, in a transmission apparatus used in a mobile communication system, the peak factor of the transmission signal (the ratio between the instantaneous maximum power of the signal and the average power) is used in order to reduce the back-off of the power amplifier and reduce the size and power consumption. ) Is reduced.

  The peak factor reduction process generally generates a peak correction signal for suppressing the peak component of the transmission signal to a predetermined level from the transmission signal, and subtracts the peak correction signal from the original transmission signal. To do. However, since the frequency bandwidth of the transmission signal is expanded when the peak factor is reduced in the transmission signal, it is desirable to execute processing for suppressing the expansion of the frequency bandwidth.

  For example, in Patent Document 1, by using a complex filter circuit to limit the frequency band of the peak correction signal to a frequency band equivalent to that of the transmission signal, the frequency band of the transmission signal generated due to the peak factor reduction process is reduced. A method for suppressing expansion has been proposed. A specific example of the complex filter circuit is disclosed in Patent Document 2, for example.

JP 2008-47959 A JP-A-8-9200

  A peak factor reduction circuit for reducing the peak factor of a complex input signal having an in-phase component (real part) and a quadrature component (imaginary part) generates a complex signal as the input signal as the peak correction signal. The complex filter circuit included in the peak factor reduction circuit limits the frequency band of the peak correction signal to a frequency band equivalent to that of the transmission signal by complex multiplication of the peak correction signal by a required complex filter coefficient.

  Here, assuming that the peak correction signal is X + jY (j: imaginary unit) and the complex filter coefficient is A + jB, the complex filter circuit performs operations of X × A, X × B, Y × A, and Y × B, respectively. Further, the value of the real part of the peak correction signal after the band limitation is obtained by executing the calculation of X × A−Y × B, and the peak correction signal after the band limitation is calculated by performing the calculation of X × B + Y × A. What is necessary is just to obtain | require the value of the imaginary part.

  For the calculation of X × A, X × B, Y × A, and Y × B, for example, when limiting the peak correction signal to a frequency band equivalent to a transmission signal used in a mobile communication system, a filter of about several tens to several hundreds This can be realized by a well-known FIR (Finite Impulse Response) filter made up of coefficients (real numbers).

  As described above, in the peak factor reduction circuit, four FIR filters having several tens to hundreds of filter coefficients are required in order to limit the frequency band of the peak correction signal to a frequency band equivalent to the transmission signal. Therefore, there is a problem that the power consumption of the peak factor reduction circuit is large.

  The present invention has been made to solve the above-described problems of the background art, and an object of the present invention is to provide a peak factor reduction circuit capable of reducing power consumption and a control method thereof.

In order to achieve the above object, a peak factor reduction circuit of the present invention is a peak factor reduction circuit for reducing the peak factor of an input signal,
A peak correction signal generator for generating a peak correction signal for suppressing the peak component of the input signal to a predetermined level;
A complex filtering unit that performs a complex filter operation using a required complex filter coefficient for the peak correction signal, and limits a frequency band of the peak correction signal to a frequency band equivalent to the input signal;
A delay unit that delays and outputs the input signal by a time corresponding to a processing time in the peak correction signal generation unit and the complex filtering unit;
A first subtractor that subtracts a band-corrected peak correction signal output from the complex filtering unit from a delayed signal output from the delay unit, and outputs the signal as a signal after the peak factor reduction;
Included in the input signal based on carrier setting information including the number of carriers included in the input signal, the frequency bandwidth for each modulated signal that is a modulated signal corresponding to the carrier, and the frequency offset information for each modulated signal A carrier symmetrical arrangement determination unit that determines whether or not the frequency band of the modulated signal is symmetrically positioned on the frequency axis with respect to the baseband frequency, and outputs a carrier asymmetric arrangement flag indicating the determination result;
Have
The complex filtering unit includes:
When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrically located on the frequency axis with respect to the baseband frequency, the complex filter operation of the peak correction signal and the complex filter coefficient The filter operation of the real part of the peak correction signal and the imaginary part of the complex filter coefficient, and the filter operation of the imaginary part of the peak correction signal and the imaginary part of the complex filter coefficient are stopped.

On the other hand, the control method of the peak factor reduction circuit of the present invention includes a peak correction signal generation unit that generates a peak correction signal for suppressing the peak component of the input signal to a predetermined level;
A complex filtering unit that performs a complex filter operation using a required complex filter coefficient for the peak correction signal, and limits a frequency band of the peak correction signal to a frequency band equivalent to the input signal;
A delay unit that delays and outputs the input signal by a time corresponding to a processing time in the peak correction signal generation unit and the complex filtering unit;
A first subtractor that subtracts a band-corrected peak correction signal output from the complex filtering unit from a delayed signal output from the delay unit, and outputs the signal as a signal after the peak factor reduction;
Included in the input signal based on carrier setting information including the number of carriers included in the input signal, the frequency bandwidth for each modulated signal that is a modulated signal corresponding to the carrier, and the frequency offset information for each modulated signal A carrier symmetrical arrangement determination unit that determines whether or not the frequency band of the modulated signal is symmetrically positioned on the frequency axis with respect to the baseband frequency, and outputs a carrier asymmetric arrangement flag indicating the determination result;
A control method of a peak factor reduction circuit for reducing a peak factor of the input signal,
The complex filtering unit is
When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrically located on the frequency axis with respect to the baseband frequency, the complex filter operation of the peak correction signal and the complex filter coefficient In this method, the filter operation of the real part of the peak correction signal and the imaginary part of the complex filter coefficient, and the filter operation of the imaginary part of the peak correction signal and the imaginary part of the complex filter coefficient are stopped.

  According to the present invention, the power consumption of the peak factor reduction circuit can be reduced.

It is a block diagram which shows the example of 1 structure of the peak factor reduction circuit of this invention. It is a graph which shows an example in which the modulation signal is arranged symmetrically with respect to the baseband frequency. It is a graph which shows an example in which the modulation signal is arranged asymmetrically with respect to the baseband frequency.

  Next, the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of a peak factor reduction circuit according to the present invention.

  As shown in FIG. 1, the peak factor reduction circuit of the present invention includes a peak correction signal generation unit 1, a complex filtering unit 2, a delay unit 3, a subtractor 4, and a carrier symmetrical arrangement determination unit 5.

  The input signal of the peak factor reduction circuit shown in FIG. 1 is a complex signal having an in-phase component (real part) and a quadrature component (imaginary part).

  The peak correction signal generation unit 1 generates a peak correction signal for suppressing the peak component of the input signal to a predetermined level. A method of generating a peak correction signal is described in, for example, Patent Document 1 described above.

  The complex filtering unit 2 performs a complex filter operation on the peak correction signal generated by the peak correction signal generation unit 1 using a required complex filter coefficient, and sets the frequency band of the peak correction signal to a frequency band equivalent to the input signal. It is a complex filter circuit to limit.

  The delay unit 3 delays the input signal by a time corresponding to the processing time in the peak correction signal generation unit 1 and the complex filtering unit 2 and outputs the delayed signal.

  The subtracter 4 subtracts the band-limited peak correction signal output from the complex filtering unit 2 from the delayed signal output from the delay unit 3 and outputs the result as a transmission signal after the peak factor reduction.

  The carrier symmetrical arrangement determination unit 5 includes carrier setting information including information such as the number of carriers included in the input signal, the frequency bandwidth for each modulation signal that is a modulated signal corresponding to each carrier, and the frequency offset for each modulation signal. Based on this, it is determined whether or not the frequency band of each modulation signal included in the input signal is symmetrically located on the frequency axis with respect to the baseband frequency. If it is symmetrical, “0” is set as the carrier asymmetric arrangement flag. If it is asymmetric, “1” is output as the carrier asymmetric arrangement flag. The carrier setting information is supplied from, for example, a DSP (Digital Signal Processor) (not shown) included in the transmission device or a processing device (computer) including a CPU, a memory, various logic circuits, etc., which manages control information from the host device. Is done.

  FIG. 2 is a graph showing an example in which the modulation signals are arranged symmetrically with respect to the baseband frequency.

  In the example shown in FIG. 2, two modulation signals having a spectrum width of about 5 MHz have a frequency offset of ± 2.5 MHz and are symmetrically arranged on the frequency axis with a baseband frequency (0 Hz in FIG. 2) as a boundary. Yes. In this case, the carrier symmetrical arrangement determination unit 5 outputs “0” as the carrier asymmetric arrangement flag.

  FIG. 3 is a graph showing an example in which modulation signals are arranged asymmetrically with respect to the baseband frequency.

  In the example shown in FIG. 3, the frequency offset is −5 MHz, the modulation signal having a spectrum width of about 10 MHz, and the modulation signal having the frequency offset of +2.5 MHz and the spectrum width of about 5 MHz are baseband frequencies (FIG. 3). Are arranged asymmetrically on the frequency axis. In this case, the carrier symmetrical arrangement determination unit 5 outputs “1” as the carrier asymmetric arrangement flag.

  As shown in FIG. 1, the complex filtering unit 2 includes a first filter unit 21, a second filter unit 22, a third filter unit 23, a fourth filter unit 24, a subtracter 25, an adder 26, a clock gate unit 27, A first selection unit 28 and a second selection unit 29 are provided.

  When the peak correction signal is X + jY (j: imaginary unit) and the complex filter coefficient is A + jB, the complex filtering unit 2 performs complex multiplication of the peak correction signal and the complex filter coefficient, and the band-limited peak correction signal X × A−Y × B is output as the value of the real part, and X × B + Y × A is output as the value of the imaginary part of the peak correction signal after band limitation. The complex filter coefficient is supplied from, for example, a DSP (Digital Signal Processor) (not shown) included in the transmission device, or a processing device (computer) including a CPU, a memory, various logic circuits, and the like. The complex filter coefficient may be generated according to the frequency band of each carrier and the frequency offset of each carrier included in the input signal, for example, and may be generated using the carrier setting information. As the complex filter coefficients, values corresponding to the arrangement pattern, frequency band, and the like of each carrier may be obtained in advance based on the carrier setting information, and stored in a memory in a table format or the like.

  The first filter unit 21 performs an X × A filter operation, the second filter unit 22 performs an X × B filter operation, the third filter unit 23 performs a Y × A filter operation, and a fourth filter operation. The filter unit 24 performs Y × B filter calculation.

  The subtracter 25 subtracts the output value (Y × B) of the fourth filter unit 24 from the output value (X × A) of the first filter unit 21. The adder 26 adds the output value (X × B) of the second filter unit 22 and the output value (Y × A) of the third filter unit 23.

  As described above, the calculation of X × A, X × B, Y × A, and Y × B by the first filter unit 21 to the fourth filter unit 24 is, for example, a transmission signal that uses a peak correction signal in a mobile communication system. When limiting to an equivalent frequency band, it can be realized by a well-known FIR filter having filter coefficients (real numbers) of about several tens to several hundreds. The FIR filter may be realized using a known DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or the like.

  The clock gate unit 27 performs an AND operation between the operation clock supplied from the outside for operating the peak factor reduction circuit and the carrier asymmetric arrangement flag output from the carrier symmetric arrangement determination unit 5, and the operation result is obtained. The gated clock is supplied to the second filter unit 22 and the fourth filter unit 24, respectively. When the carrier asymmetric arrangement flag is “1”, the clock gate unit 27 outputs the operation clock as it is as a gated clock, and when the carrier asymmetric arrangement flag is “0”, the clock gate unit 27 always outputs “0” as the gated clock. That is, when the carrier asymmetric arrangement flag is “0”, the clock gate unit 27 stops supplying the operation clock to the second filter unit 22 and the fourth filter unit 24.

  When “1” is supplied as the carrier asymmetrical arrangement flag from the carrier symmetric arrangement determining unit 5, the first selection unit 28 selects and outputs the output value (X × A−Y × B) of the subtractor 25. Further, when “0” is supplied as the carrier asymmetric arrangement flag from the carrier symmetric arrangement determination unit 5, the first selection unit 28 selects and outputs the output value (X × A) of the first filter unit 21.

  When “1” is supplied as the carrier asymmetric arrangement flag from the carrier symmetric arrangement determination unit 5, the second selection unit 29 selects and outputs the output value (X × B + Y × A) of the adder 26. Further, when “0” is supplied as the carrier asymmetric arrangement flag from the carrier symmetric arrangement determination unit 5, the second selection unit 29 selects and outputs the output value (Y × A) of the third filter unit 21.

  In such a configuration, in the peak factor reduction circuit of the present embodiment, when each modulation signal included in the input signal is arranged asymmetrically with respect to the baseband frequency, the carrier symmetrical arrangement determination unit 5 sets the carrier asymmetric arrangement flag. “1” is output.

  At this time, the first selection unit 28 of the complex filtering unit 2 selects the output value of the subtracter 25 and outputs it as the real part of the peak correction signal after band limitation. The second selection unit 29 of the complex filtering unit 2 selects the output value of the adder 26 and outputs it as the imaginary part of the peak correction signal after band limitation.

  In this case, the complex filtering unit 2 outputs the calculation result of X × A−Y × B as the real part of the peak correction signal after band limitation, and X × B + Y × A as the imaginary part of the peak correction signal after band limitation. The result of the operation is output.

  On the other hand, when the modulation signals included in the input signal are arranged symmetrically with respect to the baseband frequency, the carrier symmetrical arrangement determination unit 5 outputs “0” as the carrier asymmetric arrangement flag.

  At this time, the value B of the imaginary part of the complex filter coefficient supplied to the complex filtering unit 2 is “0” due to the symmetry of each modulation signal included in the input signal. In this case, the peak factor reduction circuit may use the calculation result of X × A as the real part of the peak correction signal after band limitation and use the calculation result of Y × A as the imaginary part of the peak correction signal after band limitation. . That is, the complex filtering unit 2 operates only the first filter unit 21 that performs the X × A calculation and the third filter unit 23 that performs the Y × A calculation, and performs the X × B calculation. It is not necessary to operate the unit 22 and the fourth filter unit 24 that executes the calculation of Y × B.

  Since “0” is input as the carrier asymmetrical arrangement flag from the carrier symmetric arrangement determining unit 5, the clock gate unit 27 always outputs a clock that is “0”. In this case, since the supply of the operation clock to the second filter unit 22 and the fourth filter unit 24 is stopped, the operations of the second filter unit 22 and the fourth filter unit 24 are stopped.

  The first selection unit 28 selects the output value of the first filter unit 21 and outputs it as a real part of the peak correction signal after band limitation. The second selection unit 29 selects the output value of the third filter unit 23 and outputs it as the imaginary part of the peak correction signal after band limitation.

  As a result, the complex filtering unit 2 outputs the calculation result of X × A as the real part of the peak correction signal after band limitation, and outputs the calculation result of Y × A as the imaginary part of the peak correction signal after band limitation. .

  As described above, according to the present invention, when the modulated signals included in the input signal are arranged symmetrically with respect to the baseband frequency, the operations of the second filter unit 22 and the fourth filter unit 24 are stopped. Therefore, the power consumption of the peak factor reduction circuit can be reduced.

  In the above description, the clock supplied from the clock gate unit 27 to the second filter unit 22 and the fourth filter unit 24 is stopped when each modulation signal included in the input signal is symmetric with respect to the baseband frequency. Although the configuration example in which the operations of the second filter unit 22 and the fourth filter unit 24 are stopped by (gated clock) is shown, the present invention is not limited to such a configuration. For example, when the modulation signals included in the input signal are symmetric with respect to the baseband frequency, such as stopping power supply to the second filter unit 22 and the fourth filter unit 24, the second filter unit 22 and the fourth filter unit Any other configuration may be used as long as the operation of 24 can be stopped.

  Further, in FIG. 1, when each modulation signal included in the input signal is symmetric with respect to the baseband frequency, the clock supplied to the second filter unit 22 and the fourth filter unit 24 is stopped (gated clock). As shown, for example, when the subtracter 25 and the adder 26 are realized by a circuit that operates with a clock, the clock output from the clock gate unit 27 is supplied to the subtracter 25 and the adder 26, and the second filter unit 22. When the supply of the clock to the fourth filter unit 24 is stopped, the clock supplied to the subtracter 25 and the adder 26 may also be stopped. In that case, the power consumption of the peak factor reduction circuit can be further reduced.

DESCRIPTION OF SYMBOLS 1 Peak correction signal production | generation part 2 Complex filtering part 3 Delay part 4, 25 Subtractor 5 Carrier symmetrical arrangement determination part 21 1st filter part 22 2nd filter part 23 3rd filter part 24 4th filter part 26 Adder 27 Clock gate Part 28 first selection part 29 second selection part

Claims (7)

A peak factor reduction circuit for reducing a peak factor of an input signal,
A peak correction signal generator for generating a peak correction signal for suppressing the peak component of the input signal to a predetermined level;
A complex filtering unit that performs a complex filter operation using a required complex filter coefficient for the peak correction signal, and limits a frequency band of the peak correction signal to a frequency band equivalent to the input signal;
A delay unit that delays and outputs the input signal by a time corresponding to a processing time in the peak correction signal generation unit and the complex filtering unit;
A first subtractor that subtracts a band-corrected peak correction signal output from the complex filtering unit from a delayed signal output from the delay unit, and outputs the signal as a signal after the peak factor reduction;
Included in the input signal based on carrier setting information including the number of carriers included in the input signal, the frequency bandwidth for each modulated signal that is a modulated signal corresponding to the carrier, and the frequency offset information for each modulated signal A carrier symmetrical arrangement determination unit that determines whether or not the frequency band of the modulated signal is symmetrically positioned on the frequency axis with respect to the baseband frequency, and outputs a carrier asymmetric arrangement flag indicating the determination result;
Have
The complex filtering unit includes:
When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrically located on the frequency axis with respect to the baseband frequency, the complex filter operation of the peak correction signal and the complex filter coefficient A peak factor reduction circuit for stopping the filter operation of the real part of the peak correction signal and the imaginary part of the complex filter coefficient, and the filter operation of the imaginary part of the peak correction signal and the imaginary part of the complex filter coefficient. The complex filtering unit includes:
When the peak correction signal is X + jY and the complex filter coefficient is A + jB,
A first filter unit that performs an X × A filter operation;
A second filter unit that performs an X × B filter operation;
A third filter unit that performs a filter operation of Y × A;
A fourth filter unit that performs a Y × B filter operation;
A second subtracter for subtracting the output value of the fourth filter unit from the output value of the first filter unit;
An adder for adding the output value of the second filter unit and the output value of the third filter unit;
When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is not symmetrically located on the frequency axis with respect to the baseband frequency, the output value of the second subtracter is selected and output. , When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrically located on the frequency axis with respect to the baseband frequency, the output value of the first filter unit is selected and output A first selection unit to
When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is not symmetrically located on the frequency axis with respect to the baseband frequency, the output value of the adder is selected and output, When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrically located on the frequency axis with respect to the baseband frequency, the output value of the third filter unit is selected and output. 2 selection units;
When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrically located on the frequency axis with respect to the baseband frequency, the clocks for the second filter unit and the fourth filter unit A clock gate section for stopping supply;
The peak factor reduction circuit according to claim 1, comprising: The clock gate unit is
When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrically located on the frequency axis with respect to the baseband frequency, the clock is supplied to the second subtracter and the adder. The peak factor reduction circuit according to claim 2, which stops. The clock gate unit is
4. The peak factor reduction circuit according to claim 2, wherein the peak factor reduction circuit is a logical product circuit that outputs a logical product of the carrier asymmetric arrangement flag and the clock. A peak correction signal generator for generating a peak correction signal for suppressing the peak component of the input signal to a predetermined level;
A complex filtering unit that performs a complex filter operation using a required complex filter coefficient for the peak correction signal, and limits a frequency band of the peak correction signal to a frequency band equivalent to the input signal;
A delay unit that delays and outputs the input signal by a time corresponding to a processing time in the peak correction signal generation unit and the complex filtering unit;
A first subtractor that subtracts a band-corrected peak correction signal output from the complex filtering unit from a delayed signal output from the delay unit, and outputs the signal as a signal after the peak factor reduction;
Included in the input signal based on carrier setting information including the number of carriers included in the input signal, the frequency bandwidth for each modulated signal that is a modulated signal corresponding to the carrier, and the frequency offset information for each modulated signal A carrier symmetrical arrangement determination unit that determines whether or not the frequency band of the modulated signal is symmetrically positioned on the frequency axis with respect to the baseband frequency, and outputs a carrier asymmetric arrangement flag indicating the determination result;
A control method of a peak factor reduction circuit for reducing a peak factor of the input signal,
The complex filtering unit is
When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrically located on the frequency axis with respect to the baseband frequency, the complex filter operation of the peak correction signal and the complex filter coefficient A peak factor reduction circuit that stops the filter operation of the real part of the peak correction signal and the imaginary part of the complex filter coefficient, and the filter operation of the imaginary part of the peak correction signal and the imaginary part of the complex filter coefficient. Control method. In the complex filtering unit,
When the peak correction signal is X + jY and the complex filter coefficient is A + jB,
A first filter unit that performs an X × A filter operation;
A second filter unit that performs an X × B filter operation;
A third filter unit that performs a filter operation of Y × A;
A fourth filter unit that performs a Y × B filter operation;
A second subtracter for subtracting the output value of the fourth filter unit from the output value of the first filter unit;
An adder for adding the output value of the second filter unit and the output value of the third filter unit;
With
The complex filtering unit includes:
When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrically located on the frequency axis with respect to the baseband frequency, the clocks for the second filter unit and the fourth filter unit The peak factor reduction circuit control method according to claim 5, wherein the supply is stopped. The complex filtering unit includes:
When the carrier asymmetric arrangement flag indicates that the frequency band of the modulation signal is symmetrically located on the frequency axis with respect to the baseband frequency, the clock is supplied to the second subtracter and the adder. 8. The peak factor reduction circuit control method according to claim 6, wherein the peak factor reduction circuit is stopped.

Images