JP2013150047A - Information processing device and method of controlling information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress occurrence of a timing error in a circuit configured to operate in synchronism with a clock signal.SOLUTION: When a predetermined process is executed on a data signal output in synchronism with either of rise timing and fall timing of a clock signal, a holding section holds the execution result in synchronism with the other of the rise timing and fall timing. A control section controls at least either timing of the rise timing and fall timing in accordance with execution time of the predetermined process so that a period from the one timing to the other timing is longer than the execution time. A clock generation section generates the clock signal in accordance with the controlled timing.

Description

  The present technology relates to an information processing apparatus and a control method thereof. Specifically, the present invention relates to an information processing apparatus that operates in synchronization with a clock signal and a control method thereof.

  In a circuit that operates in synchronization with a clock signal, a storage element such as a register that holds and outputs a data signal in synchronization with the clock signal, and performs processing such as logical operation on the output data signal And a processing circuit based on a combinational logic circuit. In such a circuit, when the timing of output from the processing circuit is synchronized with the clock signal, a retiming circuit for adjusting the timing of output of the processing result may be further provided. For example, a retiming circuit including a flip-flop that holds and outputs an input signal in synchronization with a clock signal has been proposed (see Patent Document 1).

  In such a retiming circuit, the processing result of the data signal may be held at a timing (for example, a falling timing) different from the timing (for example, the rising timing) at which the data signal is output to the processing circuit. . By delaying the timing of holding the processing result of the data signal with respect to the timing of outputting the data signal to the processing circuit, the processing result is reliably held and the occurrence of a timing error in the retiming circuit is suppressed.

JP 2009-290775 A

  However, the above-described conventional technology may not be able to suppress the occurrence of timing errors. For example, when the voltage of a processing circuit decreases, the execution time in the processing circuit often increases. If the execution time becomes longer than expected, the retiming circuit fails to hold the processing result, and a timing error occurs.

  The present technology has been developed in view of such a situation, and an object thereof is to suppress the occurrence of a timing error in a circuit that operates in synchronization with a clock signal.

  The present technology has been made to solve the above-described problems, and a first aspect of the present technology is a data signal output in synchronization with one of rising and falling timings of a clock signal. When a predetermined process is executed, a holding unit that holds the execution result in synchronization with the other timing of the rise and the fall, and a period from the one timing to the other timing A control unit that controls the timing of at least one of the rising and falling according to the execution time so as to be longer than the execution time of the predetermined process, and generates the clock signal according to the controlled timing An information processing apparatus including a clock generation unit that performs the control, and a control method thereof. As a result, there is an effect that the timing of at least one of rising and falling is controlled according to the execution time so that the period from one timing to the other timing is longer than the execution time of the predetermined process. .

  In the first aspect, the control unit further sets the period of the clock signal so that a period from when the other timing elapses until the next one timing elapses is at least a predetermined time. And the clock generation unit may generate the clock signal having the controlled period. This brings about the effect that the cycle of the clock signal is controlled so that the period from when the other timing elapses until the next one timing elapses is at least a predetermined time.

  The first aspect further includes a processing circuit that executes the predetermined processing on the data signal at an execution time corresponding to a set voltage and outputs the execution result to the holding unit, The control unit may control the timing according to the voltage. This brings about the effect that the timing is controlled according to the voltage.

  Further, in this first aspect, the processing circuit is a circuit in which the execution time becomes longer as the set voltage is lower, and the control unit sets the one timing as the set voltage is lower. You may perform at least one of the control which makes early, and the control which makes said other timing late, so that the said set voltage is low. Thus, there is an effect that at least one of the control to advance one timing earlier as the set voltage is lower and the control to delay the other timing as the set voltage is lower is performed.

  In the first aspect, when the voltage is equal to or lower than the predetermined voltage, the processing result held in the holding unit is selected and output. When the voltage is higher than the predetermined voltage, the processing result is selected. You may further comprise the selection part which selects and outputs the said process result from a processing circuit. Thereby, when the voltage is equal to or lower than the predetermined voltage, the processing result held in the holding unit is output, and when the voltage is higher than the predetermined voltage, the processing result from the processing circuit is output.

  In the first aspect, the holding unit further operates a holding unit that operates the holding unit when the voltage is equal to or lower than the predetermined voltage, and stops the holding unit when the voltage is higher than the predetermined voltage. You may have. Accordingly, the holding unit operates when the voltage is equal to or lower than the predetermined voltage, and the holding unit is stopped when the voltage is higher than the predetermined voltage.

  According to the present technology, in a circuit that operates in synchronization with a clock signal, it is possible to achieve an excellent effect that generation of a timing error is suppressed.

It is a block diagram which shows the example of 1 structure of the information processing apparatus in 1st Embodiment. It is a table | surface which shows an example of operation | movement of the control part in 1st Embodiment. It is a block diagram which shows the example of 1 structure of the clock generation part in 1st Embodiment. 3 is a block diagram illustrating a configuration example of a clock generation circuit according to the first embodiment. FIG. It is a table | surface which shows an example of operation | movement of the elapsed time counter in 1st Embodiment. 3 is a table illustrating an example of an operation of the clock generation circuit according to the first embodiment. 3 is a timing chart illustrating an operation of a clock generation unit according to the first embodiment. It is a flowchart which shows an example of operation | movement of the control part in 1st Embodiment. 3 is a timing chart illustrating an example of an operation of the information processing apparatus at a normal voltage according to the first embodiment. 3 is a timing chart illustrating an example of an operation of the information processing apparatus at a low voltage according to the first embodiment. 3 is a timing chart illustrating an example of an operation of the information processing apparatus at an ultra-low voltage in the first embodiment. 3 is a timing chart illustrating an example of an operation of the information processing apparatus at a normal voltage according to the first embodiment. 3 is a timing chart illustrating an example of an operation of the information processing apparatus at a low voltage according to the first embodiment. It is a block diagram which shows the example of 1 structure of the information processing apparatus in 2nd Embodiment. It is a table | surface which shows an example of operation | movement of the retiming operation control part in 2nd Embodiment. It is a table | surface which shows an example of operation | movement of the selector in 2nd Embodiment. It is a block diagram which shows the example of 1 structure of the information processing apparatus in 3rd Embodiment. It is a block diagram which shows the example of 1 structure of the information processing apparatus in 4th Embodiment.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First Embodiment (Example of controlling edge timing of clock signal)
2. Second embodiment (example of stopping retiming register at normal voltage)
3. Third Embodiment (Example of controlling edge timing in a storage device)
4). Fourth Embodiment (Example of controlling edge timing in a plurality of storage devices)

<1. First Embodiment>
[Configuration example of information processing device]
FIG. 1 is a block diagram illustrating a configuration example of an information processing apparatus according to an embodiment. This information processing apparatus is an apparatus that executes various types of information processing, and includes a high-voltage operation circuit 110, a retiming register 120, and a low-voltage operation circuit 130. The information processing apparatus also includes a clock tree including buffers 210, 220, and 230, a control unit 300, and a clock generation unit 400.

  The high voltage operation circuit 110 is a circuit in which a voltage higher than that of the low voltage operation circuit 130 is set, and includes a register 111 and a logic circuit 112. The register 111 holds the input signal in synchronization with the rising edge of the clock signal CLK and outputs it to the logic circuit 112. The logic circuit 112 performs a predetermined logical operation on the signal output from the register 111 and outputs the execution result to the retiming register 120 as the data signal Q1. The logic circuit 112 is an example of a processing circuit described in the claims.

  The retiming register 120 holds the data signal Q1 from the logic circuit 112 in synchronization with the fall of the clock signal CLK and outputs it to the low voltage operation circuit 130 as the data signal rQ1. For example, the retiming register 120 is supplied with the same voltage as the voltage set in the high voltage operation circuit 120. The retiming register 130 may be supplied with the same voltage as the voltage set in the low voltage operation circuit 130 or supplied with a voltage different from the voltages of the high voltage operation circuit 120 and the low voltage operation circuit 130. May be.

  Since the retiming register 120 holds the data signal Q1 at a timing (falling) different from the timing (rising) at which the signal is output from the register 111 by the retiming register 120, the data signal Q1 is reliably received by the retiming register 120. Is taken in. The retiming register 120 is an example of a holding unit described in the claims.

  The low voltage operation circuit 130 is a circuit in which a voltage lower than that of the high voltage operation circuit 110 is set, and includes a register 131 and a logic circuit 132. The register 131 holds the data signal rQ1 from the retiming register 120 and outputs it to the logic circuit 132 as the data signal Q2 in synchronization with the rise of the clock signal CLK. The logic circuit 132 performs a predetermined logical operation on the data signal Q2 from the register 131 and outputs the execution result.

  The controller 300 controls the timing of the rising edge and falling edge in the clock signal CLK and the clock cycle. The control unit 300 includes a timing control circuit 310 and a clock cycle control circuit 320.

  The timing control circuit 310 controls the timing of at least one of the rising edge and the falling edge of the clock signal CLK. The timing control circuit 310 receives a voltage mode signal that notifies the voltage level set in the high voltage operation circuit 110.

  The timing control circuit 310 controls each timing so that the period from the rising edge timing tR to the falling edge timing tF is longer than the execution time of the processing by the logic circuit 112. Thereby, before the execution time elapses from the rising edge timing tR, the retiming register 120 does not perform the operation of holding the execution result (Q1), and the timing error in the retiming register 120 is suppressed.

  As specific control, the timing control circuit 310 performs control to make the rising edge timing tR earlier as the voltage set in the high voltage operation circuit 110 is lower, and control to delay the falling edge timing tF as the voltage is lower. Do at least one of the following. In general, the lower the voltage, the longer the processing time in the logic circuit 112. The timing control circuit 310 outputs the controlled rising edge timing tR and falling edge timing tF to the clock generator 400 via signal lines 318 and 319.

  The clock cycle control circuit 320 controls the cycle of the clock signal CLK. A voltage mode signal is also input to the clock cycle control circuit 320. The clock cycle control circuit 320 controls the clock cycle pCK so that the period from the falling edge timing tF to the next rising edge timing tR is at least a predetermined time. The predetermined time is, for example, a time longer than the hold time of the retiming register 120. Here, the hold time is a time that the retiming register 120 should keep holding the data signal from when the data signal is instructed to be taken in (for example, the falling edge timing tF).

  As described above, the timing control circuit 310 performs control so that the falling edge timing tF is delayed as the set voltage is lower. As a result, there is a possibility that the time from the timing (tF) at which the data signal Q1 is held until the time (tR) at which the data signal Q1 is next updated becomes too short. If this time is less than the hold time, a timing error of hold violation may occur. Therefore, the clock cycle control circuit 320 performs control to increase the clock cycle pCK as the set voltage is lower. This suppresses the occurrence of hold violation timing errors.

  The clock cycle control circuit 320 outputs the controlled clock cycle pCK to the clock generation unit 400 via the signal line 328. Further, the clock cycle control circuit 320 outputs the reset signal RST to the clock generation unit 400 via the signal line 329 when the high voltage operation circuit 110 has stopped operating.

The clock generator 400 generates the clock signal CLK from the reference clock signal bCLK according to the clock cycle pCK, the rising edge timing tR, and the falling edge timing tF. Specifically, the clock generation unit 400 uses the ratio (f _L / f _H ) between the frequency (f _L ) corresponding to the clock cycle pCK and the frequency (f _H ) of the reference clock signal bCLK as a division ratio. The frequency of the clock signal bCK is divided. The clock generation unit 400 adjusts the edge timing of the clock signal CLK according to the rising edge timing tR and the falling edge timing tF. The clock generation unit 400 outputs the divided signal as a clock signal CLK to the buffer 210 via the signal line 409. Further, when the reset signal RST is output from the clock cycle control circuit 320, the clock generation unit 400 stops generating and outputting the clock signal CLK.

  The clock tree including the buffers 210, 220, and 230 distributes the clock signal CLK to the high voltage operation circuit 110, the retiming register 120, and the low voltage operation circuit 130.

  FIG. 2 is a table showing an example of the operation of the control unit 300 in the first embodiment. It is assumed that values “0” to “3” are set in the voltage mode signal. For example, when the high voltage operation circuit 110 stops operating, the value “0” is set as the voltage mode signal. When a normal voltage is set in the high voltage operation circuit 110, a value of “1” is set as the voltage mode signal. When a low voltage lower than the normal voltage is set in the high voltage operation circuit 110, a value of “2” is set in the voltage mode signal. When an ultra low voltage lower than the low voltage is set in the high voltage operation circuit 110, a value of “3” is set in the voltage mode signal.

  In the clock cycle pCK, for example, a multiplication number with respect to the cycle of the reference clock signal bCLK (in other words, the reciprocal of the frequency division ratio) is set. For example, when the frequency division ratio is controlled to “1/10”, a value of “10” is set as the clock cycle pCK in decimal. The rising edge timing tR and the falling edge timing tF are set to values obtained by dividing the elapsed time from the start of the cycle of the clock signal CLK to the rise or fall timing by the cycle of the reference clock signal bCLK. . For example, when the falling timing is the time when five clocks of the reference clock signal bCLK elapse from the start of the cycle of the clock signal CLK, the falling edge timing tF has a value of “5” in decimal. Is set.

  The timing control circuit 310 performs control to delay the falling edge timing tF as the voltage set in the high voltage operation circuit 110 is lower. For example, the timing control circuit 310 controls the falling edge timing tF to “5” at the normal voltage, “7” at the low voltage, and “9” at the very low voltage. On the other hand, the timing control circuit 310 controls the rising edge timing tR to “0” regardless of the voltage.

  The clock cycle control circuit 320 controls the clock cycle pCK so that the period from the falling edge timing tF to the next rising edge timing tR is at least a predetermined time. The predetermined time is, for example, a time corresponding to three clocks of the reference clock signal bCLK. In the normal voltage and the low voltage, the clock cycle control circuit 320 controls the clock cycle pCK to “10”, for example. When the falling edge timing tF is controlled to “9” at an extremely low voltage, the period from the falling edge timing tF to the next rising edge timing tR is less than “3” while the clock cycle pCK remains “10”. It becomes. Therefore, the clock cycle control circuit 320 controls the clock cycle pCK to, for example, “14” at the time of the arbitration voltage.

  Further, the clock cycle control circuit 320 outputs a reset signal RST when the high voltage operation circuit 110 has stopped operating.

[Configuration example of clock generator]
FIG. 3 is a block diagram illustrating a configuration example of the clock generation unit 400 according to the first embodiment. The clock generation unit 400 includes a clock generation circuit 410, an elapsed time counter 420, and a register 430.

  The elapsed time counter 420 counts numerical values in synchronization with the reference clock signal bCLK. The elapsed time counter 420 outputs the counted value as the count value CNT to the clock generation circuit 410 via the signal line 429 and returns it to itself. Further, the elapsed time counter 420 resets the count value to the initial value when the counter reset signal cRST instructing the initialization of the count value is input.

  The clock generation circuit 410 generates a signal value of the clock signal CLK. The clock generation circuit 410 receives a rising edge timing tR, a falling edge timing tF, a clock cycle pCK, a reset signal RST, and a count value CNT. The clock generation circuit 410 compares the count value CNT with the rising edge timing tR, the falling edge timing tF, and the clock cycle pCK. When the count value CNT is greater than or equal to the rising edge timing tR and less than the falling edge timing tF, the clock generation circuit 410 outputs the value “1” to the register 430 via the signal line 419 as the clock signal value VAL. . In other cases, the clock generation circuit 410 outputs the value “0” to the register 430 as the clock signal value VAL.

  When the count value CNT matches the clock cycle pCK, the clock generation circuit 410 outputs the counter reset signal cRST to the elapsed time counter 420 via the signal line 418. When the reset signal RST is input, the clock generation circuit 410 outputs the value “0” as the clock signal value VAL to the register 430 and outputs the counter reset signal cRST to the elapsed time counter 420.

  Thus, since the count value counted in synchronization with the reference clock signal bCLK is initialized with the period of the clock period pCK, the clock signal CLK generated with this clock period pCK divides the reference clock signal bCLK. Signal.

  The clock generation unit 400 uses the elapsed time counter 420 to change the cycle and timing of the clock signal CLK according to the control of the control unit 300. The configuration of the clock generation unit 400 is illustrated in FIG. It is not limited to the configuration. For example, the timing may be changed using a phase comparator. Further, the period may be changed using, for example, a PLL (Phased Lock Loop) and a frequency divider.

  The register 430 holds the clock signal value VAL in synchronization with the reference clock signal bCLK and outputs the clock signal CLK to the clock tree. Even when a delay time occurs in the process of generating the clock signal value VAL by the clock generation circuit 410, the timing of transition of the value of the clock signal CLK is adjusted by the operation of the register 430.

[Configuration example of clock generation circuit]
FIG. 4 is a block diagram illustrating a configuration example of the clock generation circuit 410 according to the first embodiment. The clock generation circuit 410 includes comparison circuits 411 and 412, a coincidence determination circuit 413, an OR (logical sum) gate 414, and an AND (logical product) gate 415.

  The comparison circuits 411 and 412 compare the magnitudes of two input values and output a comparison result. The comparison circuit 411 receives the count value CNT from the elapsed time counter 420 and the rising edge timing tR from the control unit 300. When the count value CNT is less than the rising edge timing tR, the comparison circuit 411 outputs a value “1” to the AND gate 415 as a comparison result, and otherwise outputs a value “0” as a comparison result. Output to the gate 415.

  The comparison circuit 412 receives the count value CNT from the elapsed time counter 420 and the falling edge timing tF from the control unit 300. The comparison circuit 412 outputs a value “1” as a comparison result to the AND gate 415 when the count value CNT is less than the falling edge timing tF, and outputs a value “0” as the comparison result otherwise. Output to the AND gate 415.

  The coincidence determination circuit 413 determines whether or not two input values match and outputs a determination result. The coincidence determination circuit 413 receives the count value CNT from the elapsed time counter 420 and the clock cycle pCK from the control unit 300. The coincidence determination circuit 413 outputs a value of 1 as a determination result to the OR gate 414 when the count value CNT and the clock cycle pCK match, and outputs a value of 0 as the determination result to the OR gate 414 when they do not match. To do.

  The OR gate 414 outputs a logical sum of input values. The OR gate 414 receives the determination result from the coincidence determination circuit 413 and the reset signal RST from the control unit 300. The OR gate 414 outputs a logical sum of these input values to the elapsed time counter 420 as a counter reset signal cRST.

  The AND gate 415 outputs a logical product of input values. The AND gate 415 receives the inverted value of the comparison result from the comparison circuit 411, the comparison result from the comparison circuit 412, and the inverted value of the reset signal RST. The AND gate 415 outputs the logical product of these input values to the register 430 as the clock signal value VAL. Note that the configuration of the clock generation circuit 410 is not limited to the configuration illustrated in FIG. 4 as long as the clock signal value VAL can be generated based on the control amounts (tR, tF, and pCK).

  FIG. 5 is a table showing an example of the operation of the elapsed time counter 420 in the first embodiment. When the counter reset signal cRST is not input, the elapsed time counter 420 refers to the returned count value CNT and increments and outputs the count value CNT in synchronization with the rising edge of the reference clock signal bCLK. . The increment value is “1” in decimal notation, for example. On the other hand, when the counter reset signal cRST is input, the elapsed time counter 420 sets the count value CNT to an initial value (for example, “0”).

  FIG. 6 is a table showing an example of the operation of the clock generation circuit 410 according to the first embodiment. When the reset signal RST is input, the clock generation circuit 410 outputs the value “0” as the clock signal value VAL and outputs the counter reset signal cRST. When the reset signal RST is not input, the clock generation circuit 410 compares the count value CNT with the rising edge timing tR, the falling edge timing tF, and the clock cycle pCK. As a result of the comparison, when the count value CNT is less than the rising edge timing tR, the clock generation circuit 410 outputs a value of 0 as the clock signal value VAL. When the count value CNT is greater than or equal to the rising edge timing tR and less than the falling edge timing tF, the clock generation circuit 410 outputs a value “1” as the clock signal value VAL. When the count value CNT is greater than or equal to the falling edge timing tF, the clock generation circuit 410 outputs a value “0” as the clock signal value VAL. When the count value CNT coincides with the clock cycle pCK, the clock generation circuit 410 outputs a counter reset signal cRST.

[Configuration example of clock generator]
FIG. 7 is a timing chart illustrating the operation of the clock generation unit 400 according to the first embodiment. When the reset signal RST is not input, the elapsed time counter 420 increments the count value CNT in synchronization with the reference clock signal bCLK.

  The clock generation circuit 410 outputs a value of “1” as the clock signal value VAL when the count value CNT is equal to or higher than the rising edge timing tR and lower than the falling edge timing tF. For example, consider a case where “2” is set to the rising edge timing tR and “7” is set to the falling edge timing tF. In this case, when the count value CNT becomes “2”, the clock signal value VAL is set to “1”, and when the count value CNT becomes “7”, the clock signal value VAL is set to “0”. The

  The register 430 holds the value of the clock signal value VAL in synchronization with the reference clock signal bCLK and outputs it as the clock signal CLK.

  When the count value CNT is equal to the clock cycle pCK (for example, “10”), the clock generation circuit 410 outputs the counter reset signal cRST to the elapsed time counter 420. When the counter reset signal cRST is input, the elapsed time counter 420 resets the count value to an initial value (for example, “0”).

[Configuration example of control unit]
FIG. 8 is a flowchart illustrating an example of the operation of the control unit 300 according to the first embodiment. This operation starts when the high voltage operation circuit 110 and the low voltage operation circuit 130 are operated.

  Based on the voltage mode signal, the controller 300 determines whether a low voltage is set in the high voltage operation circuit 110 (step S910). When the low voltage is set (step S910: Yes), the control unit 300 performs control to delay the rising edge timing tR (step S920).

  When the low voltage is not set (step S910: No) or after step S920, the control unit 300 determines whether or not the ultra-low voltage is set in the high-voltage operation circuit 110 (step S930). . When the ultra-low voltage is set (step S930: Yes), the control unit 300 performs control to further delay the rising edge timing tR and lower the clock frequency (step S940). When the ultra-low voltage is not set (step S930: No), or after step S940, the control unit 300 returns to step S910.

[Operation example of information processing device]
FIG. 9 is a timing chart illustrating an example of the operation of the information processing apparatus at the normal voltage according to the first embodiment. In the case of the normal voltage, the control unit 300 controls the rising edge timing tR to “0”, the falling edge timing tF to “5”, and the clock cycle pCK to “10”.

  The logic circuit 112 performs predetermined processing on the signal input in synchronization with the rising edge of the clock signal CLK, and outputs a data signal Q1 as a processing result. The retiming register 120 holds the data signal Q1 in synchronization with the falling of the clock signal CLK and outputs it as the data signal rQ1.

  Here, at the normal voltage, the processing execution time of the logic circuit 112 is sufficiently shorter than the period from the rising edge timing tR to the falling edge timing tF of the clock signal. Therefore, the processing result (Q1) of the logic circuit 112 is reliably held in the retiming register 120 at the falling edge timing, and no timing error occurs.

  The register 131 in the low voltage operation circuit 130 holds the data signal rQ1 output from the retiming register 120 and outputs it as the data signal Q2 in synchronization with the rising edge of the clock signal CLK. Since the voltage set in the low voltage operation circuit 130 is lower than the voltage of the high voltage operation circuit 110, the operation speed of the low voltage operation circuit 130 is lower than that of the high voltage operation circuit 110. However, since the register 131 holds the data signal rQ1 at a timing (tR) different from the timing (tF) at which the retiming register 120 outputs the data signal rQ1, the data signal is reliably delivered.

  FIG. 10 is a timing chart illustrating an example of the operation of the information processing apparatus at a low voltage according to the first embodiment. At a low voltage, the delay time in the processing of the logic circuit 112 may be longer than that at a normal voltage. Therefore, the control unit 300 performs control to delay the falling edge timing tF in order to prevent the period from the rising edge timing tR to the falling edge timing tF from becoming less than the execution time. For example, the falling edge timing tF is changed from “5” to “7”. As a result, the processing result (Q1) of the logic circuit 112 is reliably held in the retiming register 120 at the falling edge timing, and the occurrence of a timing error is suppressed.

  FIG. 11 is a timing chart showing an example of the operation of the information processing apparatus at an ultra-low voltage according to the first embodiment. It is assumed that the execution time of the process of the logic circuit 112 may be further increased at an extremely low voltage compared to when the voltage is low. Therefore, the control unit 300 performs control to further delay the falling edge timing tF in order to prevent the period from the rising edge timing tR to the falling edge timing tF from becoming the execution time or less. For example, the falling edge timing tF is changed from “7” to “9”.

  Here, if the time point (tF) for holding the data signal Q1 is made too late, the time from the time point (tF) to the time point (tR) at which the data signal Q1 is updated next is less than the hold time of the retiming register 120. Therefore, a timing error may occur. Therefore, the control unit 300 performs control to increase the clock cycle pCK so that the period from the falling edge timing tF to the next rising edge timing tR is equal to or longer than the hold time of the retiming register 120. For example, the clock cycle pCK is changed from “10” to “14”.

  As a result, the processing result (Q1) of the logic circuit 112 is reliably held in the retiming register 120 at the falling edge timing, and the occurrence of a timing error is suppressed.

  In addition, although the control part 300 is set as the structure which performs the control which delays the falling edge timing tF according to a voltage, you may perform the control which advances the rising edge timing tR. For example, as illustrated in FIG. 12, at the normal voltage, the control unit 300 controls the clock cycle pCK to 10 and controls the rising edge timing tR and the falling edge timing tF to 3 and 7. Then, as illustrated in FIG. 13, at a low voltage, the control unit 300 changes the rising edge timing tR from “3” to “0”. Thereby, the period from the rising edge timing tR to the falling edge timing tF becomes longer than that at the normal voltage, and the occurrence of the timing error is suppressed.

  In addition, the control unit 300 may perform both control for increasing the rising edge timing tR according to the voltage and control for delaying the falling edge timing tF according to the voltage.

  Further, in the information processing apparatus, the data signal Q1 is output in synchronization with the rising edge timing of the clock signal CLK, and the signal is held in the retiming register 120 in synchronization with the falling edge timing. However, conversely, the data signal Q1 may be output in synchronization with the falling edge timing of the clock signal CLK, and the signal may be held in synchronization with the rising edge timing. In this case, the control unit 300 may execute at least one of the control for increasing the falling edge timing according to the voltage and the control for delaying the rising edge timing according to the voltage.

  As described above, in the first embodiment of the present technology, when the logic circuit 112 performs a process such as a logical operation on the data signal output in synchronization with the rising edge of the clock signal, The execution result is held in synchronization with the fall. On the other hand, the control unit 300 controls the timing according to the execution time at the voltage set in the logic circuit 112 so that the period from the rising edge timing to the falling edge timing is longer than the execution time of the process in the logic circuit 112. To do. Thereby, since the period from the rising edge timing to the falling edge timing becomes longer than the execution time, the retiming register 120 can reliably hold the processing result. Therefore, occurrence of a timing error in the retiming register 120 is suppressed.

<2. Second Embodiment>
[Configuration example of information processing device]
FIG. 14 is a block diagram illustrating a configuration example of the information processing apparatus according to the second embodiment. In the information processing apparatus, timing adjustment by the retiming register 120 may not be necessary. For example, when the difference between the normal voltage of the high voltage operation circuit 110 and the voltage of the low voltage operation circuit 130 is not so large, the difference in operation speed is not so large. In this case, as long as the voltage of the high-voltage operation circuit 110 does not decrease, the necessity for adjusting the timing by the retiming register 120 is low. The information processing apparatus according to the second embodiment is different from the first embodiment in that the retiming register 120 is stopped as necessary. Specifically, the information processing apparatus according to the second embodiment is different in that it further includes a selector 121 and a retiming operation control unit 330.

  The retiming operation control unit 330 controls the operations of the retiming register 120 and the selector 121 according to the voltage. A voltage mode signal is input to the retiming operation control unit 330. When the operation is stopped or the normal voltage is set in the high voltage mode signal, the retiming operation control unit 330 outputs a retiming instruction signal Retime for not performing retiming to the retiming register 120 and the selector 121. To do. On the other hand, when a low voltage or an ultra-low voltage is set in the high voltage mode signal, the retiming operation control unit 330 sends the retiming instruction signal Retime instructing to perform retiming to the retiming register 120 and the selector. It outputs to 121. In the retiming instruction signal Retime, for example, a high level is set when retiming is performed, and a low level is set when retiming is not performed.

  The retiming operation control unit 330 is an example of a holding operation control unit described in the claims. In addition, the retiming operation control unit 330 is configured to stop the operation of the retiming register 120 as necessary, but may be configured not to perform control to stop the retiming register 120. Specifically, the retiming operation control unit 330 outputs the retiming instruction signal Retime to only the selector 121 without outputting it to the retiming register 120.

  The retiming instruction signal Retime is input to the enable terminal EN of the retiming register 120 as an enable signal of the retiming register 120. The retiming register 120 becomes valid when it is instructed to perform retiming by the retiming instruction signal Retime, and becomes invalid when instructed not to perform retiming.

  The selector 121 selects and outputs one of the input values according to the retiming instruction signal Retime. The selector 121 receives the data signal rQ 1 from the retiming register 120 and the data signal Q 1 from the logic circuit 112. When the selector 121 is instructed to perform retiming by the retiming instruction signal Retime, the selector 121 selects the data signal rQ1 from the retiming register 120 and outputs it to the low voltage operation circuit 130. On the other hand, when it is instructed not to perform retiming, the selector 121 selects the data signal Q 1 from the logic circuit 112 and outputs it to the low voltage operation circuit 130.

  FIG. 15 is a table illustrating an example of the operation of the retiming operation control unit 330 according to the second embodiment. When the high voltage mode signal is set to 0 (operation stop) or 1 (normal voltage), the retiming operation control unit 330 outputs a retiming instruction signal Retime instructing not to perform retiming. On the other hand, when 2 (low voltage) or 3 (very low voltage) is set in the high voltage mode signal, the retiming operation control unit 330 generates a retiming instruction signal Retime that instructs retiming. Output.

  FIG. 16 is a table showing an example of the operation of the selector 121 in the second embodiment. The selector 121 selects and outputs the data signal Q1 from the logic circuit 112 when the retiming instruction signal Retime indicates that retiming is not performed. On the other hand, when the retiming instruction signal Retime instructs to perform retiming, the selector 121 selects and outputs the data signal rQ1 from the retiming register 120.

  As described above, according to the second embodiment of the present technology, when the retiming is unnecessary, the retiming operation control unit 330 can cause the selector 121 to output an unretimed data signal. it can. Thereby, unnecessary delay due to retiming can be avoided. Further, according to the second embodiment of the present technology, the retiming operation control unit 330 can stop the operation of the retiming register 120 when retiming is unnecessary. This can reduce power consumption when retiming is unnecessary.

<3. Third Embodiment>
[Configuration example of information processing device]
FIG. 17 is a block diagram illustrating a configuration example of the information processing apparatus according to the third embodiment. The information processing apparatus according to the third embodiment is different from the first embodiment in that retiming of a data signal transferred between the storage device and the processing device is performed. The information processing apparatus according to the third embodiment includes a storage device 140 and a processing device 150 instead of the high voltage operation circuit 110, the retiming register 120, and the low voltage operation circuit 130.

  The storage device 140 stores the input data signal and outputs the stored data signal. The storage device 140 includes a register 141, a reading unit 142, and a retiming register 143.

  The register 141 holds a read request in synchronization with the rise of the clock signal CLK and outputs it to the reading unit 142.

  The reading unit 142 reads the data signal Q1 from the cell array or the like in accordance with a read request from the register 141. The reading unit 142 outputs the read data signal Q1 to the retiming register 143.

  The retiming register 143 holds the data signal Q1 in synchronization with the falling edge of the clock signal CLK and outputs it to the processing device 150 as the data signal rQ1.

  The processing device 150 performs processing such as logical operation on the data signal rQ1. The processing device 150 includes a logic circuit 151 and a register 152. The logic circuit 151 performs predetermined processing on the data signal rQ1 and outputs the execution result to the register 152. The register 152 holds the processing result in synchronization with the rising edge of the clock signal CLK and outputs it as the data signal Q2.

  Note that the retiming register 143 is provided inside the storage device 140, but the retiming register 143 may be arranged inside the processing device 150. In addition to reading data from the storage device 140, retiming may be performed when writing data to the storage device 140.

  As described above, according to the third embodiment of the present technology, the clock generation unit 400 supplies the clock signal CLK whose cycle and edge timing are controlled to the storage device 140, thereby causing a timing error in the storage device 140. Can be suppressed. As a result, accurate data is transferred from the storage device 140 to the processing device 150.

<4. Fourth Embodiment>
[Configuration example of information processing device]
FIG. 18 is a block diagram illustrating a configuration example of the information processing apparatus according to the fourth embodiment. When the information processing apparatus includes a plurality of storage devices, the edge timing and cycle of the clock signal can be individually controlled for each storage device. The information processing apparatus according to the fourth embodiment is different from the third embodiment in that it further includes storage devices 160 and 180, processing devices 170 and 190, and clock generation units 401 and 402. The information processing apparatus according to the fourth embodiment is an integrated circuit such as an LSI (Large Scale Integration) including such a plurality of storage devices and a plurality of processing devices.

  The configuration of the storage devices 160 and 180 is the same as that of the storage device 140 in the third embodiment. The configuration of the processing devices 170 and 190 is the same as that of the processing device 150 in the third embodiment. The configurations of the clock generation units 401 and 402 are the same as those of the clock generation unit 400 in the third embodiment.

  Each set of the storage device and the processing device may exchange data with each other. For example, the processing device 150 may output the data signal Q2 to the storage device 160.

  Clock generators 400, 401, and 402 generate clock signals CLK1, CLK2, and CLK3, respectively. The storage device 140 and the processing device 150 operate in synchronization with the clock signal CLK1, and the storage device 160 and the processing device 170 operate in synchronization with the clock signal CLK2. The storage device 180 and the processing device 190 operate in synchronization with the clock signal CLK3.

  The periods and edge timings of these clock signals CLK1, CLK2, and CLK3 are individually controlled according to the voltages set in each of storage devices 140, 160, and 180.

  As described above, according to the fourth embodiment of the present technology, since each of the clock signals is individually controlled, even in the case where each voltage of the storage device is individually controlled, in the storage device Generation of timing errors is suppressed.

  The above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the invention-specific matters in the claims have a corresponding relationship. Similarly, the invention specific matter in the claims and the matter in the embodiment of the present technology having the same name as this have a corresponding relationship. However, the present technology is not limited to the embodiment, and can be embodied by making various modifications to the embodiment without departing from the gist thereof.

  Further, the processing procedure described in the above embodiment may be regarded as a method having a series of these procedures, and a program for causing a computer to execute these series of procedures or a recording medium storing the program. You may catch it. As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disk), a memory card, a Blu-ray Disc (registered trademark), or the like can be used.

In addition, this technique can also take the following structures.
(1) When a predetermined process is executed on the data signal output in synchronization with the timing of either one of the rising edge and the falling edge of the clock signal, the execution result is indicated as the rising edge or the falling edge. A holding unit for holding in synchronization with the other timing of
A control unit that controls the timing of at least one of the rising edge and the falling edge according to the execution time so that the period from the one timing to the other timing is longer than the execution time of the predetermined process When,
An information processing apparatus comprising: a clock generation unit that generates the clock signal according to the controlled timing.
(2) The control unit further controls the cycle of the clock signal so that a period from when the other timing elapses until the next one timing elapses is at least a predetermined time,
The information processing apparatus according to (1), wherein the clock generation unit generates the clock signal having the controlled period.
(3) further comprising a processing circuit that executes the predetermined processing on the data signal in an execution time corresponding to a set voltage and outputs the execution result to the holding unit;
The information processing apparatus according to (1) or (2), wherein the control unit controls the timing according to the voltage.
(4) The processing circuit is a circuit in which the execution time becomes longer as the set voltage is lower,
The control unit executes at least one of the control to advance the one timing earlier as the set voltage is lower and the control to delay the other timing as the set voltage is lower (3 ) The information processing apparatus described.
(5) When the voltage is equal to or lower than the predetermined voltage, the processing result held in the holding unit is selected and output, and when the voltage is higher than the predetermined voltage, the processing from the processing circuit is performed. The information processing apparatus according to (4), further including a selection unit that selects and outputs a result.
(6) The apparatus further includes a holding operation control unit that operates the holding unit when the voltage is equal to or lower than a predetermined voltage, and stops the holding unit when the voltage is higher than the predetermined voltage. The information processing apparatus described.
(7) When the holding unit executes a predetermined process on the data signal output in synchronization with any one of the rising edge and the falling edge of the clock signal, the execution result is displayed on the rising edge and the rising edge. A holding procedure for holding in synchronization with the other timing of falling;
The control unit sets the timing of at least one of the rising edge and the falling edge according to the execution time so that a period from the one timing to the other timing is longer than an execution time of the predetermined process. Control procedures to control;
A method for controlling an information processing apparatus, comprising: a clock generation procedure in which a clock generation unit generates the clock signal according to the controlled timing.

110 High Voltage Operation Circuit 111, 131, 141, 142, 152, 161, 163, 172, 430 Register 112, 132, 151, 171 Logic Circuit 120, 143 Retiming Register 121 Selector 130 Low Voltage Operation Circuit 140, 160, 180 Memory Device 142, 161 Reading unit 150, 170, 190 Processing unit 210, 220, 230 Buffer 300 Control unit 310 Timing control circuit 320 Clock cycle control circuit 330 Retiming operation control unit 400, 401, 402 Clock generation unit 410 Clock generation circuit 411 412 Comparison circuit 413 Match determination circuit 414 OR gate 415 AND gate 420 Elapsed time counter

Claims (7)

When a predetermined process is performed on the data signal output in synchronization with the timing of one of the rising edge and the falling edge of the clock signal, the execution result is transferred to the other of the rising edge and the falling edge. A holding unit for holding in synchronization with the timing;
A control unit that controls the timing of at least one of the rising edge and the falling edge according to the execution time so that the period from the one timing to the other timing is longer than the execution time of the predetermined process When,
An information processing apparatus comprising: a clock generation unit that generates the clock signal according to the controlled timing. The control unit further controls the period of the clock signal so that a period from when the other timing elapses until the next one timing elapses is at least a predetermined time,
The information processing apparatus according to claim 1, wherein the clock generation unit generates the clock signal having the controlled period. A processing circuit for executing the predetermined processing on the data signal at an execution time corresponding to a set voltage and outputting the execution result to the holding unit;
The information processing apparatus according to claim 1, wherein the control unit controls the timing according to the voltage. The processing circuit is a circuit in which the execution time becomes longer as the set voltage is lower,
The said control part performs at least one of the control which makes said one timing early, so that the said set voltage is low, and the control which makes said other timing late, so that the said set voltage is low. The information processing apparatus described. When the voltage is less than or equal to the predetermined voltage, the processing result held in the holding unit is selected and output, and when the voltage is higher than the predetermined voltage, the processing result from the processing circuit is selected. The information processing apparatus according to claim 4, further comprising a selection unit that outputs the information. The information processing according to claim 5, further comprising: a holding operation control unit that operates the holding unit when the voltage is equal to or lower than a predetermined voltage, and stops the holding unit when the voltage is higher than the predetermined voltage. apparatus. When the holding unit executes a predetermined process on the data signal output in synchronization with one of the rising edge and the falling edge of the clock signal, the execution result is displayed on the rising edge and the falling edge. Holding procedure for holding in synchronization with the other timing;
The control unit sets the timing of at least one of the rising edge and the falling edge according to the execution time so that a period from the one timing to the other timing is longer than an execution time of the predetermined process. Control procedures to control;
A method for controlling an information processing apparatus, comprising: a clock generation procedure in which a clock generation unit generates the clock signal according to the controlled timing.

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