JP2013149908A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurence of an erasure defect in a nonvolatile memory.SOLUTION: Charge storage layers 130 are located on a semiconductor substrate 100, and are formed on both sides of a select gate electrode 120 in a plan view. Each charge storage layer 130 is an ONO film in which a silicon oxide film 132, a silicon nitride film 134, and a silicon oxide film 136 are stacked in this order. Control gate electrodes 150 are formed on the two charge storage layers 130 respectively. The silicon oxide film 136 is located below an end portion 152 on the opposite side of the select gate electrode 120 of the control gate electrode 150 in a plan view. More specifically, below the end portion 152 of the control gate electrode 150, only the silicon oxide film 136 is formed. The thickness of the silicon oxide film 136 is thinner than that of the silicon nitride film 134.

Description

  The present invention relates to a semiconductor device having a nonvolatile memory and a method for manufacturing the semiconductor device.

  One type of nonvolatile memory is a split gate type nonvolatile memory. This nonvolatile memory has a configuration in which an ONO film for charge accumulation is formed between a select gate electrode and a source / drain diffusion layer, and a select gate electrode is provided on the ONO film. In the split gate type nonvolatile memory, writing is performed by injecting charges into the ONO film using channel hot electrons, and erasing is performed by using hot hole injection into the ONO film using Gate Induced Drain Leakage (GIDL). It is carried out.

  In the split gate type nonvolatile memory, the end portion of the select gate overlaps with the impurity region. In Patent Document 1, it is described that a silicon oxide film having the same thickness as the ONO film is formed in this overlapping portion instead of the ONO film.

JP 2005-536895 A

  As a result of examination by the present inventors, it has been found that the split gate type nonvolatile memory has the following problems. When the distribution of charges injected by the above-described writing operation does not match the distribution of holes injected by the erasing operation, holes may accumulate in the insulating film for charge accumulation as writing and erasing are repeated. When this hole accumulation occurs at the end of the charge accumulation layer on the impurity region side, the accumulated hole shields the electric field applied between the drain region and the select gate electrode during the erase operation, thereby Generation of the GIDL current is hindered. When the generation of the GIDL current is prevented, there is a possibility that the number of holes necessary for erasing is not injected into the charge storage layer even when a predetermined erasing voltage is applied. That is, there is a possibility that an erasure failure occurs in the nonvolatile memory.

According to the present invention, a semiconductor substrate;
A select gate insulating film formed on the semiconductor substrate;
A select gate electrode formed on the select gate insulating film;
A charge storage layer formed on the semiconductor substrate, located on both sides of the select gate electrode, and including a silicon nitride layer;
A control gate electrode formed on each of the two charge storage layers;
An impurity region formed on the semiconductor substrate and located on the opposite side of the select gate insulating film via the charge storage layer;
The control gate electrode is located below the end opposite to the select gate electrode, thinner than the charge storage layer, and an end insulating film made of silicon oxide,
A semiconductor device is provided.

  According to the present invention, the end insulating film is formed under the end of the control gate electrode opposite to the select gate electrode. The end insulating film is made of silicon oxide and is thinner than the charge storage layer. Thus, when viewed in terms of electrical film thickness (that is, film thickness converted to a silicon oxide film based on the dielectric constant), the end insulating film is thinner than the charge storage layer. For this reason, even when holes are accumulated at the end of the charge accumulation layer on the impurity region side, the electric field applied between the impurity region and the select gate electrode is prevented from being shielded due to this. . Therefore, it is possible to suppress the occurrence of erasure failure in the nonvolatile memory.

According to the present invention, a step of forming a select gate insulating film on a semiconductor substrate;
Forming a select gate electrode on the select gate insulating film;
Forming a laminated film of a first silicon oxide film and a silicon nitride film in regions located on both sides of the select gate electrode in the semiconductor substrate;
Forming a second silicon oxide film on the semiconductor substrate and the laminated film;
Forming a control gate electrode on each of a region of the second silicon oxide film that overlaps the stacked film and a region on the opposite side of the select gate insulating film in the periphery of the region;
Forming an impurity region by implanting impurities into the semiconductor substrate using the select gate electrode and the control gate electrode as a mask;
A method for manufacturing a semiconductor device is provided.

  According to the present invention, it is possible to suppress the occurrence of erasure failure in a nonvolatile memory.

It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment. This semiconductor device has a non-volatile memory having a split gate type MONOS structure. Specifically, the semiconductor device includes a semiconductor substrate 100, a select gate insulating film 110, a select gate electrode 120, a charge storage layer 130, a control gate electrode 150, and source / drain regions 160. The semiconductor substrate 100 is, for example, a silicon substrate. The select gate insulating film 110 is formed on the semiconductor substrate 100, and the select gate electrode 120 is formed on the select gate insulating film 110. The charge storage layer 130 is located on the semiconductor substrate 100 and is formed on each side of the select gate electrode 120 in plan view. The charge storage layer 130 is an ONO film in which a silicon oxide film 132, a silicon nitride film 134, and a silicon oxide film 136 are stacked in this order. The control gate electrode 150 is formed on each of the two charge storage layers 130. The source / drain region 160 (impurity region) is formed in the semiconductor substrate 100 and is located on the opposite side of the select gate insulating film 110 with the charge storage layer 130 in plan view. The select gate electrode 120 and the charge storage layer 130 are, for example, polysilicon films.

  The silicon oxide film 136 (end insulating film) is located under the end 152 on the opposite side of the control gate electrode 150 from the select gate electrode 120 in plan view. In other words, the silicon oxide film 132 and the silicon nitride film 134 in the charge storage layer 130 do not overlap the entire control gate electrode 150 in plan view. Under the end 152 of the control gate electrode 150, only the silicon oxide film 136 is formed. The thickness of the silicon oxide film 136 is smaller than the thickness of the silicon nitride film 134.

  Further, the end of the source / drain region 160 on the control gate electrode 150 side overlaps the control gate electrode 150 in plan view. In at least a part (preferably all) of the overlapping portions, only the silicon oxide film 136 of the charge storage layer 130 is located.

  2, 3, and 4 are cross-sectional views illustrating a method for manufacturing the semiconductor device illustrated in FIG. 1. This semiconductor device manufacturing method includes the following steps. First, the select gate insulating film 110 is formed on the semiconductor substrate 100. Next, a select gate electrode 120 is formed on the select gate insulating film 110. Next, a stacked film of a silicon oxide film 132 and a silicon nitride film 134 is formed in regions located on both sides of the select gate electrode 120 in the semiconductor substrate 100. Next, a silicon oxide film 136 is formed over the semiconductor substrate 100 and over the stacked film of the silicon oxide film 132 and the silicon nitride film 134. Next, in the silicon oxide film 136, the region overlapping with the stacked film of the silicon oxide film 132 and the silicon nitride film 134, and the region located on the opposite side to the select gate insulating film 110 in the periphery of this region, A control gate electrode 150 is formed. Next, impurities are implanted into the semiconductor substrate 100 using the select gate electrode 120 and the control gate electrode 150 as a mask, thereby forming source / drain regions 160. Details will be described below.

  First, as shown in FIG. 2A, a select gate insulating film 110 is formed on the semiconductor substrate 100. When the semiconductor substrate 100 is a silicon substrate, the select gate insulating film 110 is a silicon oxide film formed by, for example, a thermal oxidation method. Next, a conductive film such as a polysilicon film is formed on the select gate insulating film 110. Next, a mask pattern (for example, a resist pattern: not shown) is formed on the conductive film, and the conductive film is etched using the mask pattern as a mask. As a result, the select gate electrode 120 is formed on the select gate insulating film 110. In this etching step, most of the portion of the select gate insulating film 110 that is not covered with the select gate electrode 120 may be removed.

  Next, a silicon oxide film 132 and a silicon nitride film 134 are formed in this order on the top and side surfaces of the stacked structure of the select gate insulating film 110 and the select gate electrode 120 and on the semiconductor substrate 100. The silicon oxide film 132 and the silicon nitride film 134 are formed by a vapor phase method. The thickness of the silicon nitride film 134 is, for example, not less than 10 nm and not more than 20 nm.

  Next, as shown in FIG. 2B, the sidewall 140 is formed on the side surface of the select gate electrode 120. The sidewall 140 is formed, for example, by etching back a silicon oxide film. The sidewall 140 also covers a region of the silicon nitride film 134 located on the semiconductor substrate 100 that is located next to the select gate electrode 120 in plan view.

  Next, as shown in FIG. 3A, the silicon nitride film 134 and the silicon oxide film 132 are etched using the sidewall 140 as a mask. Thereby, the stacked film of the silicon oxide film 132 and the silicon nitride film 134 is removed except for the portion chased by the sidewall 140. That is, the stacked film of the silicon oxide film 132 and the silicon nitride film 134 is located on a portion located on the side surface of the select gate electrode 120 and on a region located next to the select gate electrode 120 in the plan view of the semiconductor substrate 100. Removed except for parts.

  Thereafter, as shown in FIG. 3B, the sidewall 140 is removed. Next, a silicon oxide film 136 is formed on the semiconductor substrate 100, the select gate electrode 120, and the silicon nitride film 134. The silicon oxide film 136 is formed by, for example, a vapor phase method. The thickness of the silicon oxide film 136 is, for example, not less than 3 nm and not more than 10 nm, and is thinner than the silicon nitride film 134.

  Next, as shown in FIG. 4, a conductive film such as a polysilicon film is formed on the silicon nitride film 134. Next, a mask pattern (for example, a resist pattern: not shown) is formed on the conductive film, and the conductive film is etched using the mask pattern as a mask. Thereby, the control gate electrode 150 is formed. At this time, the end 152 of the control gate electrode 150 is positioned on the region of the semiconductor substrate 100 where only the silicon oxide film 136 is formed.

  Thereafter, impurities are implanted into the semiconductor substrate 100 using the select gate electrode 120 and the control gate electrode 150 as a mask, thereby forming source / drain regions 160. Thereby, the semiconductor device shown in FIG. 1 is formed.

  Next, the operation and effect of this embodiment will be described. According to the present embodiment, only the silicon oxide film 136 among the silicon oxide film 132, the silicon nitride film 134, and the silicon oxide film 136 constituting the charge storage layer 130 is provided below the end portion 152 of the control gate electrode 150. Is formed. The silicon oxide film 136 is thinner than the silicon nitride film 134. For this reason, even if holes are accumulated at the end of the charge accumulation layer 130 on the source / drain region 160 side, an electric field applied between the source / drain region 160 and the select gate electrode 120 is caused by this. Shielding is suppressed. Therefore, it is possible to suppress the occurrence of erasure failure in the nonvolatile memory.

  In addition, since only the silicon oxide film 136 is formed under the end portion 152 of the control gate electrode 150, compared with the case where the entire layer of the charge storage layer 130 is formed under the end portion 152, The magnitude of the voltage applied to the control gate electrode 150 when erasing the memory can be reduced. Thereby, a circuit for generating a voltage to be applied to the control gate electrode 150 can be reduced and simplified. In addition, the power consumption of the nonvolatile memory can be reduced.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

100 Semiconductor substrate 110 Select gate insulating film 120 Select gate electrode 130 Charge storage layer 132 Silicon oxide film 134 Silicon nitride film 136 Silicon oxide film 140 Side wall 150 Control gate electrode 152 End 160 Source / drain region

Claims (4)

A semiconductor substrate;
A select gate insulating film formed on the semiconductor substrate;
A select gate electrode formed on the select gate insulating film;
A charge storage layer formed on the semiconductor substrate, located on both sides of the select gate electrode, and including a silicon nitride layer;
A control gate electrode formed on each of the two charge storage layers;
An impurity region formed on the semiconductor substrate and located on the opposite side of the select gate insulating film via the charge storage layer;
The control gate electrode is located below the end opposite to the select gate electrode, thinner than the charge storage layer, and an end insulating film made of silicon oxide,
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device, wherein the charge storage layer is an ONO film in which a first silicon oxide film, the silicon nitride layer, and a second silicon oxide film are stacked in this order. The semiconductor device according to claim 1 or 2,
A part of the impurity region overlaps a portion of the control gate electrode located on the end insulating film. Forming a select gate insulating film on the semiconductor substrate;
Forming a select gate electrode on the select gate insulating film;
Forming a laminated film of a first silicon oxide film and a silicon nitride film in regions located on both sides of the select gate electrode in the semiconductor substrate;
Forming a second silicon oxide film on the semiconductor substrate and the laminated film;
Forming a control gate electrode on each of a region of the second silicon oxide film that overlaps the stacked film and a region on the opposite side of the select gate insulating film in the periphery of the region;
Forming an impurity region by implanting impurities into the semiconductor substrate using the select gate electrode and the control gate electrode as a mask;
A method for manufacturing a semiconductor device comprising:

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