JP2013149744A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2013149744A
JP2013149744A JP2012008246A JP2012008246A JP2013149744A JP 2013149744 A JP2013149744 A JP 2013149744A JP 2012008246 A JP2012008246 A JP 2012008246A JP 2012008246 A JP2012008246 A JP 2012008246A JP 2013149744 A JP2013149744 A JP 2013149744A
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semiconductor device
semiconductor chip
wiring
external connection
pattern
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Takashi Tomohiro
任志 友廣
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Micron Memory Japan Ltd
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Elpida Memory Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing an external connection terminal located below a corner part of a semiconductor chip mounted on a wiring board from breaking due to a temperature cycle without increasing the size of the wiring board.SOLUTION: A semiconductor device 10 comprises: a first semiconductor chip 14; a wiring board 11 having a wiring pattern 22 disposed on one surface and electrically connected to the first semiconductor chip 14 and a plurality of lands disposed on the other surface and electrically connected to the wiring pattern 22; and first to third external connection terminals 12A, 12B, and 12C provided on the plurality of lands. The wiring board 11 includes a stress dispersion pattern 27 facing the first external connection terminal 12A located below a corner part 14A of the first semiconductor chip 14 and the second external connection terminal 12B disposed outside the corner part 14A.

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

従来、半導体チップが搭載された配線基板（「パッケージ基板」ともいう）と、該配線基板の裏面に配置された複数のランドのそれぞれに配置されたはんだボール（外部接続端子）と、を備えた半導体装置が用いられている。   Conventionally, a wiring board (also referred to as a “package board”) on which a semiconductor chip is mounted and solder balls (external connection terminals) arranged on each of a plurality of lands arranged on the back surface of the wiring board are provided. A semiconductor device is used.

上記半導体装置では、配線基板に設けられたはんだボールのうち、特に、半導体チップ外延の近辺に配置されたはんだボールの破断が問題となる。
一般に、半導体チップと配線基板との間には熱膨張係数の差があるため、半導体チップと配線基板との境界に加わる応力に起因して、一部のはんだボールがダメージを受けやすい。 In the semiconductor device, breakage of the solder balls arranged in the vicinity of the outer periphery of the semiconductor chip among the solder balls provided on the wiring board becomes a problem.
In general, since there is a difference in thermal expansion coefficient between the semiconductor chip and the wiring board, some solder balls are easily damaged due to stress applied to the boundary between the semiconductor chip and the wiring board.

特に、半導体装置のうち、半導体チップが存在する部分と半導体チップが存在しない部分とでは熱膨張係数の差が大きいため、半導体チップのコーナー部に近接する領域ではんだボールが受けるダメージは、他の領域に設けられたはんだボールと比較して大きくなる。
したがって、半導体装置の実装信頼性を向上させるため、半導体チップのコーナー部近辺に配置されたはんだボールのダメージを軽減する方策が望まれる。 In particular, in the semiconductor device, the difference in the thermal expansion coefficient between the portion where the semiconductor chip is present and the portion where the semiconductor chip is not present is large. It becomes larger than the solder balls provided in the region.
Therefore, in order to improve the mounting reliability of the semiconductor device, a measure for reducing the damage of the solder balls arranged in the vicinity of the corner portion of the semiconductor chip is desired.

特許文献１には、パッケージ基板と、パッケージ基板の一方の面に搭載された半導体チップと、パッケージ基板の他方の面に形成され、配線構造を介して半導体チップと電気的に接続される複数のバンプ電極（はんだボール）と、パッケージ基板の一方の面のうち、半導体チップのコーナー部に近接する所定領域に搭載されたダミーチップと、を備えた半導体装置が開示されている。   Patent Document 1 discloses a plurality of package substrates, a semiconductor chip mounted on one surface of the package substrate, and a plurality of semiconductor chips formed on the other surface of the package substrate and electrically connected to the semiconductor chip through a wiring structure. A semiconductor device is disclosed that includes a bump electrode (solder ball) and a dummy chip mounted in a predetermined region near one corner of the semiconductor chip on one surface of the package substrate.

また、特許文献１には、熱膨張係数が半導体チップと同一又は近似する材料を用いて、上記ダミーチップを構成することで、半導体チップのコーナー部の応力集中に起因するダメージが軽減され、半導体装置の接続信頼性が向上することが開示されている。   Patent Document 1 discloses that the dummy chip is configured using a material having the same or similar thermal expansion coefficient as that of the semiconductor chip, thereby reducing damage caused by stress concentration at the corner portion of the semiconductor chip. It is disclosed that the connection reliability of the device is improved.

特開２００９−２１２３１５号公報JP 2009-212315 A

ところで、近年、携帯機器等の小型化により、これらに搭載される半導体チップの小型化の要求があるが、上記特許文献１に記載の半導体装置の構成では、配線基板上に搭載された半導体チップの４つのコーナー部の近傍に複数のダミーチップを搭載するため、ダミーチップの搭載エリアを確保する必要があり、配線基板が大型化（言い換えれば、半導体装置が大型化）する恐れがあった。   By the way, in recent years, due to miniaturization of portable devices and the like, there is a demand for miniaturization of semiconductor chips mounted thereon. However, in the configuration of the semiconductor device described in Patent Document 1, the semiconductor chip mounted on a wiring board is required. Since a plurality of dummy chips are mounted in the vicinity of the four corners, it is necessary to secure a dummy chip mounting area, which may increase the size of the wiring board (in other words, increase the size of the semiconductor device).

本発明の一観点によれば、複数の第１の電極パッドを有する第１の半導体チップと、一面に配置され、前記第１の半導体チップと電気的に接続される配線パターン、及び他面に配置され、前記配線パターンと電気的に接続された複数のランドを有する配線基板と、複数の前記ランドのそれぞれに対して設けられた外部接続端子と、を有する半導体装置であって、前記配線基板は、複数の前記外部接続端子のうち、前記第１の半導体チップのコーナー部の下方に位置する第１の外部接続端子、及び該コーナー部の外側に配置された第２の外部接続端子と対向配置された応力分散用パターンを有することを特徴とする半導体装置が提供される。   According to one aspect of the present invention, a first semiconductor chip having a plurality of first electrode pads, a wiring pattern disposed on one surface and electrically connected to the first semiconductor chip, and on the other surface A semiconductor device comprising: a wiring board having a plurality of lands arranged and electrically connected to the wiring pattern; and an external connection terminal provided for each of the plurality of lands. Is opposed to the first external connection terminal located below the corner portion of the first semiconductor chip and the second external connection terminal disposed outside the corner portion among the plurality of external connection terminals. A semiconductor device having a stress distribution pattern arranged is provided.

本発明の半導体装置によれば、第１の半導体チップが実装される配線パターンに、複数の外部接続端子のうち、第１の半導体チップのコーナー部の下方に位置する第１の外部接続端子、及び該コーナー部の外側に配置された第２の外部接続端子と対向する応力分散用パターンを設けることにより、温度サイクルにより第１の外部接続端子の歪みや第１の外部接続端子への応力集中を分散させることが可能となる。   According to the semiconductor device of the present invention, the first external connection terminal located below the corner portion of the first semiconductor chip among the plurality of external connection terminals in the wiring pattern on which the first semiconductor chip is mounted, In addition, by providing a stress distribution pattern facing the second external connection terminal arranged outside the corner portion, distortion of the first external connection terminal and stress concentration on the first external connection terminal due to the temperature cycle Can be dispersed.

これにより、ダミーチップを備えた従来の半導体装置と比較して、配線基板（半導体装置）を大型化させることなく、温度サイクルに起因して、第１の半導体チップのコーナー部の下方に位置する第１の外部接続端子の破断を抑制できる。
したがって、半導体装置をマザーボード等の基板に実装する際の接続信頼性を向上させることができる。 Thereby, compared with the conventional semiconductor device provided with the dummy chip, the wiring substrate (semiconductor device) is positioned below the corner portion of the first semiconductor chip due to the temperature cycle without increasing the size. Breakage of the first external connection terminal can be suppressed.
Therefore, connection reliability when the semiconductor device is mounted on a substrate such as a mother board can be improved.

本発明の第１実施の形態に係る半導体装置の平面図である。1 is a plan view of a semiconductor device according to a first embodiment of the present invention. 図１に示す半導体装置のＡ−Ａ線方向の断面図である。It is sectional drawing of the AA line direction of the semiconductor device shown in FIG. 図１に示す半導体装置のＢ−Ｂ線方向の断面図である。FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 in the BB line direction. 本発明の第１実施の形態に係る半導体装置の製造工程を示す断面図（その３）である。It is sectional drawing (the 3) which shows the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施の形態に係る半導体装置の製造工程を示す断面図（その４）である。It is sectional drawing (the 4) which shows the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施の形態に係る半導体装置の製造工程を示す断面図（その５）である。It is sectional drawing (the 5) which shows the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施の形態に係る半導体装置の製造工程を示す断面図（その６）である。It is sectional drawing (the 6) which shows the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施の形態に係る半導体装置の製造工程を示す断面図（その７）である。It is sectional drawing (the 7) which shows the manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第２実施の形態に係る半導体装置の平面図である。It is a top view of the semiconductor device concerning a 2nd embodiment of the present invention. 図９に示す第２の実施の形態の半導体装置のＥ−Ｅ線方向の断面図である。It is sectional drawing of the EE line direction of the semiconductor device of 2nd Embodiment shown in FIG. 図９に示す第２の実施の形態の半導体装置のＦ−Ｆ線方向の断面図である。It is sectional drawing of the FF line direction of the semiconductor device of 2nd Embodiment shown in FIG. 本発明の第３実施の形態に係る半導体装置の平面図である。It is a top view of the semiconductor device concerning a 3rd embodiment of the present invention. 図１２に示す第３の実施の形態の半導体装置のＨ−Ｈ線方向の断面図である。It is sectional drawing of the HH line direction of the semiconductor device of 3rd Embodiment shown in FIG. 本発明の第４実施の形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 4th Embodiment of this invention. 本発明の第５実施の形態に係る半導体装置の断面図（その１）である。It is sectional drawing (the 1) of the semiconductor device which concerns on 5th Embodiment of this invention. 本発明の第５実施の形態に係る半導体装置の断面図（その２）である。It is sectional drawing (the 2) of the semiconductor device which concerns on 5th Embodiment of this invention.

以下、図面を参照して本発明を適用した実施の形態について詳細に説明する。なお、以下の説明で用いる図面は、本発明の実施の形態の構成を説明するためのものであり、図示される各部の大きさや厚さや寸法等は、実際の半導体装置の寸法関係とは異なる場合がある。   Embodiments to which the present invention is applied will be described below in detail with reference to the drawings. The drawings used in the following description are for explaining the configuration of the embodiment of the present invention, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the dimensional relationship of an actual semiconductor device. There is a case.

（第１の実施の形態）
図１は、本発明の第１実施の形態に係る半導体装置の平面図である。図２は、図１に示す半導体装置のＡ−Ａ線方向の断面図であり、図３は、図１に示す半導体装置のＢ−Ｂ線方向の断面図である。 (First embodiment)
FIG. 1 is a plan view of the semiconductor device according to the first embodiment of the present invention. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 in the AA line direction, and FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. 1 in the BB line direction.

図１では、説明の便宜上、図２及び図３に示す封止樹脂１８の図示を省略する。また、図１では、配線基板１１の一面１１ａ側からは見ることのできない配線基板１１の他面１１ｂ側に配置された第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃ、及び応力分散用パターン２７を点線で図示する。   In FIG. 1, the illustration of the sealing resin 18 shown in FIGS. 2 and 3 is omitted for convenience of explanation. In FIG. 1, the first to third external connection terminals 12A, 12B, 12C arranged on the other surface 11b side of the wiring board 11 that cannot be seen from the one surface 11a side of the wiring board 11, and the stress distribution The pattern 27 is illustrated by a dotted line.

図１乃至図３を参照するに、第１の実施の形態の半導体装置１０は、配線基板１１と、第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃ（複数の外部接続端子）と、第１の半導体チップ１４と、接着部材１５と、導電性ワイヤ１７と、封止樹脂１８と、を有する。   1 to 3, the semiconductor device 10 according to the first embodiment includes a wiring board 11, first to third external connection terminals 12 </ b> A, 12 </ b> B, and 12 </ b> C (a plurality of external connection terminals), The first semiconductor chip 14, the adhesive member 15, the conductive wire 17, and the sealing resin 18 are included.

配線基板１１は、絶縁基材２１と、配線パターン２２と、複数のランド２４と、貫通電極２５と、応力分散用パターン２７と、第１のソルダーレジスト２９と、第２のソルダーレジスト３１と、を有する。
絶縁基材２１は、板状とされており、平坦な面とされた一面２１ａ（配線基板１１の一面１１ａ）及び他面２１ｂ（配線基板１１の他面１１ｂ）を有する。絶縁基材２１としては、例えば、厚さが０．２ｍｍのガラスエポキシ基板を用いることができる。 The wiring substrate 11 includes an insulating base material 21, a wiring pattern 22, a plurality of lands 24, a through electrode 25, a stress distribution pattern 27, a first solder resist 29, a second solder resist 31, Have
The insulating base material 21 is plate-shaped, and has a flat surface 21a (one surface 11a of the wiring substrate 11) and another surface 21b (other surface 11b of the wiring substrate 11). As the insulating base material 21, for example, a glass epoxy substrate having a thickness of 0.2 mm can be used.

配線パターン２２は、絶縁基材２１の一面２１ａに設けられている。配線パターン２２は、導電性ワイヤ１７（例えば、Ａｕワイヤ）の一端が接続される接続パッド部２２Ａを有する。
接続パッド部２２Ａは、第１の半導体チップ１４の実装領域を囲むように、枠状に配置されている。配線パターン２２の材料としては、例えば、Ｃｕを用いることができる。 The wiring pattern 22 is provided on one surface 21 a of the insulating base material 21. The wiring pattern 22 has a connection pad portion 22A to which one end of a conductive wire 17 (for example, an Au wire) is connected.
The connection pad portion 22A is arranged in a frame shape so as to surround the mounting region of the first semiconductor chip 14. As a material of the wiring pattern 22, for example, Cu can be used.

複数のランド２４は、絶縁基材２１の他面２１ｂに所定の間隔でグリッドアレイ状に配置されている。ランド２４の材料としては、例えば、Ｃｕを用いることができる。
各ランド２４には、第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃのうち、いずれか１つの外部接続端子が配設されている。
ランド２４に設けられた第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃは、第２のソルダーレジスト３１の下面３１ａから下方側に突出している。 The plurality of lands 24 are arranged in a grid array at predetermined intervals on the other surface 21 b of the insulating base material 21. As a material of the land 24, for example, Cu can be used.
Each land 24 is provided with any one of the first to third external connection terminals 12A, 12B, and 12C.
The first to third external connection terminals 12 </ b> A, 12 </ b> B, and 12 </ b> C provided on the land 24 protrude downward from the lower surface 31 a of the second solder resist 31.

ここで、第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃについて説明する。
第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃは、同様な構成とされた外部接続端子であり、配線基板１１に実装される第１の半導体チップ１４に対してどこの位置に配置されるかが異なる。 Here, the first to third external connection terminals 12A, 12B, and 12C will be described.
The first to third external connection terminals 12 </ b> A, 12 </ b> B, and 12 </ b> C are external connection terminals having the same configuration, and are arranged at any position with respect to the first semiconductor chip 14 mounted on the wiring board 11. It is different.

具体的には、第１の外部接続端子１２Ａは、矩形とされた第１の半導体チップ１４の４つのコーナー部１４Ａの下方に配置された外部接続端子である。
また、第２の外部接続端子１２Ｂは、第１の半導体チップ１４の４つのコーナー部１４Ａの外側で、かつ第１の外部接続端子１２Ａの近傍に配置された外部接続端子である。
また、第３の外部接続端子１２Ｃは、第１及び第２の外部接続端子１２Ａ，１２Ｂの配設領域以外の領域に配置された外部接続端子である。
第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃとしては、例えば、はんだボールを用いる。 Specifically, the first external connection terminal 12 </ b> A is an external connection terminal disposed below the four corner portions 14 </ b> A of the rectangular first semiconductor chip 14.
The second external connection terminal 12B is an external connection terminal arranged outside the four corner portions 14A of the first semiconductor chip 14 and in the vicinity of the first external connection terminal 12A.
The third external connection terminal 12C is an external connection terminal disposed in a region other than the region where the first and second external connection terminals 12A and 12B are disposed.
For example, solder balls are used as the first to third external connection terminals 12A, 12B, and 12C.

貫通電極２５は、配線パターン２２とランド２４との間に位置する絶縁基材２１を貫通するように設けられている。貫通電極２５は、一端がランド２４と接続されており、他端が配線パターン２５と接続されている。これにより、貫通電極２５は、ランド２４と配線パターン２５とを電気的に接続している。   The through electrode 25 is provided so as to penetrate the insulating substrate 21 located between the wiring pattern 22 and the land 24. The through electrode 25 has one end connected to the land 24 and the other end connected to the wiring pattern 25. Thus, the through electrode 25 electrically connects the land 24 and the wiring pattern 25.

応力分散用パターン２７は、絶縁基材２１の一面２１ａに設けられている。応力分散用パターン２７は、複数の外部接続端子（第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃ）のうち、第１の半導体チップ１４の４つのコーナー部１４Ａの下方に位置する第１の外部接続端子１２Ａ、及びの４つのコーナー部１４Ａの外側に配置された第２の外部接続端子１２Ｂと対向するように配置されている。   The stress distribution pattern 27 is provided on the one surface 21 a of the insulating base material 21. The stress distribution pattern 27 is a first one located below the four corner portions 14A of the first semiconductor chip 14 among the plurality of external connection terminals (first to third external connection terminals 12A, 12B, 12C). The external connection terminals 12 </ b> A and the second external connection terminals 12 </ b> B disposed outside the four corner portions 14 </ b> A are disposed.

このように、第１の半導体チップ１４が実装される配線パターン１１に、第１の半導体チップ１４の４つのコーナー部１４Ａの下方に位置する第１の外部接続端子１２Ａ、及び４つのコーナー部１４Ａの外側に配置された第２の外部接続端子１２Ｂと対向配置された応力分散用パターン２７を設けることにより、温度サイクルにより第１の半導体チップ１４のコーナー部１４Ａの下方に位置する第１の外部接続端子１２Ａの歪みや第１の外部接続端子１２Ａへの応力集中を分散させることが可能となる。   As described above, the first external connection terminal 12A and the four corner portions 14A located below the four corner portions 14A of the first semiconductor chip 14 are arranged on the wiring pattern 11 on which the first semiconductor chip 14 is mounted. By providing the stress distribution pattern 27 disposed opposite to the second external connection terminal 12B disposed outside the first external connection terminal 12B, the first external portion located below the corner portion 14A of the first semiconductor chip 14 due to the temperature cycle It becomes possible to disperse the distortion of the connection terminal 12A and the stress concentration on the first external connection terminal 12A.

これにより、ダミーチップを備えた従来の半導体装置と比較して、配線基板１１（半導体装置１０）を大型化させることなく、温度サイクルに起因して、第１の半導体チップ１４のコーナー部１４Ａの下方に位置する第１の外部接続端子１２Ａの破断を抑制できる。
したがって、半導体装置１０をマザーボード等の基板に実装する際の接続信頼性を向上させることができる。 Thereby, compared with the conventional semiconductor device provided with the dummy chip, the wiring substrate 11 (semiconductor device 10) is not enlarged, and the corner portion 14A of the first semiconductor chip 14 is caused by the temperature cycle. Breakage of the first external connection terminal 12A located below can be suppressed.
Therefore, connection reliability when the semiconductor device 10 is mounted on a substrate such as a mother board can be improved.

応力分散用パターン２７としては、開口部や溝等の形成されていないベタパターンを用いるとよい。
このように、応力分散用パターン２７として、開口部や溝等の形成されていないベタパターンを用いることにより、開口部や溝等が形成されたパターンを使用した場合と比較して、第１の外部接続端子１２Ａの歪みや第１の外部接続端子１２Ａへの応力集中を十分に分散させることができる。 As the stress distribution pattern 27, it is preferable to use a solid pattern in which openings and grooves are not formed.
As described above, the use of a solid pattern in which no openings, grooves, or the like are formed as the stress distribution pattern 27 makes it possible to compare the first pattern with the pattern in which the openings, grooves, etc. are used. Distortion of the external connection terminal 12A and stress concentration on the first external connection terminal 12A can be sufficiently dispersed.

応力分散パターン２７の形状としては、例えば、矩形を用いることができる。また、応力分散パターン２７は、同一平面（この場合、絶縁基材２１の一面２１ａ）上に配置された配線パターン２２と同じ材料で、かつ配線パターン２２と同じ厚さに構成するとよい。
これにより、配線基板１１を製造する際、配線パターン２２と同時に形成することが可能となる。よって、応力分散パターン２７を形成する工程を別途設ける必要がなくなるため、第１の実施の形態の半導体装置１０のコストの増加を抑制できる。 As the shape of the stress distribution pattern 27, for example, a rectangle can be used. The stress distribution pattern 27 is preferably made of the same material as the wiring pattern 22 arranged on the same plane (in this case, one surface 21 a of the insulating base material 21) and has the same thickness as the wiring pattern 22.
As a result, when the wiring substrate 11 is manufactured, it can be formed simultaneously with the wiring pattern 22. Therefore, it is not necessary to separately provide a process for forming the stress distribution pattern 27, and thus an increase in the cost of the semiconductor device 10 of the first embodiment can be suppressed.

また、温度サイクルによる応力は、配線基板１１のうち、第１の半導体チップ１４のコーナー部１４Ａとの接触した部分において大きい。
そのため、他面２１ｂではなく、絶縁基材２１の一面２１ａに、ベタパターンとされた応力分散用パターン２７を設けることで、良好に応力を分散させることができる。 In addition, the stress due to the temperature cycle is large in the portion of the wiring substrate 11 in contact with the corner portion 14A of the first semiconductor chip 14.
Therefore, the stress can be favorably dispersed by providing the stress dispersion pattern 27 as a solid pattern not on the other surface 21b but on the one surface 21a of the insulating base material 21.

また、複数のランド２４が形成される絶縁基材２１の他面２１ｂではなく、絶縁基材２１の一面２１ａに応力分散用パターン２７を設けることで、グリッドアレイ状に配置された複数のランド２４の配置を邪魔することなく、応力分散用パターン２７を配置することができる。   Further, by providing the stress distribution pattern 27 on one surface 21a of the insulating base material 21 instead of the other surface 21b of the insulating base material 21 on which the plurality of lands 24 are formed, the plurality of lands 24 arranged in a grid array shape. The stress distribution pattern 27 can be arranged without disturbing the arrangement.

第１のソルダーレジスト２９は、接続パッド部２２Ａを除く配線パターン２２、及び応力分散パターン２７を覆うように、絶縁基材２１の一面２１ａに設けられている。第１のソルダーレジスト２９は、接続パッド部２２Ａを露出する開口部２９Ａを有する。
第２のソルダーレジスト３１は、絶縁基材２１の他面２１ｂに設けられている。第２のソルダーレジスト３１は、ランド２４を露出する開口部３１Ａを有する。 The first solder resist 29 is provided on the one surface 21 a of the insulating base material 21 so as to cover the wiring pattern 22 excluding the connection pad portion 22 </ b> A and the stress distribution pattern 27. The first solder resist 29 has an opening 29A that exposes the connection pad portion 22A.
The second solder resist 31 is provided on the other surface 21 b of the insulating base material 21. The second solder resist 31 has an opening 31 </ b> A that exposes the land 24.

第１の半導体チップ１４は、矩形とされている。第１の半導体チップ１４は、第１の半導体チップ１４の主面１４ａの外周部に枠状に配置された複数の第１の電極パッド３４を有する。
第１の半導体チップ１４は、接着部材１５により、主面１４ａが上側となるように、第１のソルダーレジスト２９の上面２９ａの中央に接着されている。接着部材１５としては、例えば、絶縁性の接着剤や、或いはＤＡＦ（Ｄｉｅ Ａｔｔａｃｈｅｄ Ｆｉｌｍ）を用いることができる。 The first semiconductor chip 14 is rectangular. The first semiconductor chip 14 has a plurality of first electrode pads 34 arranged in a frame shape on the outer peripheral portion of the main surface 14 a of the first semiconductor chip 14.
The first semiconductor chip 14 is bonded to the center of the upper surface 29a of the first solder resist 29 by the bonding member 15 so that the main surface 14a is on the upper side. For example, an insulating adhesive or DAF (Die Attached Film) can be used as the adhesive member 15.

第１の電極パッド３４は、導電性ワイヤ１７の他端と接続されている。これにより、第１の電極パッド３４は、導電性ワイヤ１７を介して、配線基板１１と電気的に接続されている。
つまり、第１の半導体チップ１４は、配線基板１１に対してワイヤボンディング接続されている。 The first electrode pad 34 is connected to the other end of the conductive wire 17. Thereby, the first electrode pad 34 is electrically connected to the wiring board 11 via the conductive wire 17.
That is, the first semiconductor chip 14 is connected to the wiring substrate 11 by wire bonding.

封止樹脂１８は、第１の半導体チップ１４及び導電性ワイヤ１７を覆うように、配線基板１１上に設けられている。これにより、第１の半導体チップ１４及び導電性ワイヤ１７は、封止樹脂１８により封止されている。
封止樹脂１８の上面１８ａは、平坦な面とされている。封止樹脂１８としては、例えば、モールド樹脂を用いることができる。 The sealing resin 18 is provided on the wiring substrate 11 so as to cover the first semiconductor chip 14 and the conductive wire 17. Thereby, the first semiconductor chip 14 and the conductive wire 17 are sealed with the sealing resin 18.
The upper surface 18a of the sealing resin 18 is a flat surface. As the sealing resin 18, for example, a mold resin can be used.

第１の実施の形態の半導体装置によれば、第１の半導体チップ１４が実装される配線パターン１１に、第１の半導体チップ１４の４つのコーナー部１４Ａの下方に位置する第１の外部接続端子１２Ａ、及び４つのコーナー部１４Ａの外側に配置された第２の外部接続端子１２Ｂと対向配置された応力分散用パターン２７を設けることにより、温度サイクルにより第１の半導体チップ１４のコーナー部１４Ａの下方に位置する第１の外部接続端子１２Ａの歪みや第１の外部接続端子１２Ａへの応力集中を分散させることが可能となる。   According to the semiconductor device of the first embodiment, the first external connection located below the four corner portions 14A of the first semiconductor chip 14 is connected to the wiring pattern 11 on which the first semiconductor chip 14 is mounted. By providing the terminal 12A and the stress distribution pattern 27 disposed opposite to the second external connection terminal 12B disposed outside the four corner portions 14A, the corner portion 14A of the first semiconductor chip 14 is subjected to a temperature cycle. It is possible to disperse the distortion of the first external connection terminal 12A located below and the stress concentration on the first external connection terminal 12A.

これにより、ダミーチップを備えた従来の半導体装置と比較して、配線基板１１（半導体装置１０）を大型化させることなく、温度サイクルに起因して、第１の半導体チップ１４のコーナー部１４Ａの下方に位置する第１の外部接続端子１２Ａの破断を抑制できる。
したがって、半導体装置１０をマザーボード等の基板に実装する際の接続信頼性を向上させることができる。 Thereby, compared with the conventional semiconductor device provided with the dummy chip, the wiring substrate 11 (semiconductor device 10) is not enlarged, and the corner portion 14A of the first semiconductor chip 14 is caused by the temperature cycle. Breakage of the first external connection terminal 12A located below can be suppressed.
Therefore, connection reliability when the semiconductor device 10 is mounted on a substrate such as a mother board can be improved.

図４乃至図８は、本発明の第１の実施の形態に係る半導体装置の製造工程を示す断面図である。図４乃至図７に示す構造体の切断面、及び図８に示す半導体装置１０の切断面は、図２に示す半導体装置１０の切断面に対応している。図４〜図８において、図２に示す半導体装置１０と同一構成部分には、同一符号を付す。   4 to 8 are cross-sectional views showing the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. The cut surface of the structure shown in FIGS. 4 to 7 and the cut surface of the semiconductor device 10 shown in FIG. 8 correspond to the cut surface of the semiconductor device 10 shown in FIG. 4 to 8, the same components as those of the semiconductor device 10 shown in FIG.

次いで、図４乃至図８を参照して、第１の実施の形態の半導体装置１０の製造方法について説明する。
始めに、図４に示す工程では、ダイシングラインＤにより区画された複数の配線基板形成領域Ｃを有した絶縁基材４１を準備する。絶縁基材４１は、後述する図８に示す工程において、個片化されることで、複数の絶縁基材２１（図２及び図３参照）となる。つまり、絶縁基材４１は、絶縁基材２１の母材である。 Next, a method for manufacturing the semiconductor device 10 according to the first embodiment will be described with reference to FIGS.
First, in the step shown in FIG. 4, an insulating base material 41 having a plurality of wiring board forming regions C partitioned by dicing lines D is prepared. The insulating base material 41 becomes a plurality of insulating base materials 21 (see FIGS. 2 and 3) by being separated into pieces in the process shown in FIG. 8 described later. That is, the insulating base material 41 is a base material of the insulating base material 21.

次いで、各配線基板形成領域Ｃに、周知の手法により、絶縁基材４１の一面４１ａ（絶縁基材２１の一面２１ａ）に配置された配線パターン２２、応力分散用パターン２７（図示せず）、及び第１のソルダーレジスト２９と、絶縁基材４１の他面４１ｂ（絶縁基材２１の他面２１ａ）に配置された複数のランド２４及び第２のソルダーレジスト３１と、絶縁基材４１を貫通する貫通電極２５と、を形成する。
これにより、複数の配線基板形成領域Ｃのそれぞれに配線基板１１が形成された配線母基板４２が形成される。この段階では、複数の配線基板１１は、連結されており、個片化されていない。 Next, in each wiring board formation region C, the wiring pattern 22 disposed on the one surface 41a (one surface 21a of the insulating base material 21), the stress distribution pattern 27 (not shown), The first solder resist 29, the plurality of lands 24 and the second solder resist 31 arranged on the other surface 41b of the insulating base material 41 (the other surface 21a of the insulating base material 21), and the insulating base material 41. Penetrating electrode 25 to be formed.
Thereby, the wiring mother board 42 in which the wiring board 11 is formed in each of the plurality of wiring board forming regions C is formed. At this stage, the plurality of wiring boards 11 are connected and are not separated.

また、図４に示す工程では、サブトラクティブ法またはセミアディティブ法により、絶縁基材４１の一面４１ａに、Ｃｕ膜よりなる配線パターン２２及び応力分散用パターン２７を一括形成する。
このように、複数の配線基板１１（配線母基板４２）を製造する際、サブトラクティブ法またはセミアディティブ法により、配線パターン２２及び応力分散用パターン２７を一括形成することで、応力分散用パターン２７を形成する工程を別途設ける必要がなくなるため、第１の実施の形態の半導体装置１０のコストの増加を抑制できる。 In the step shown in FIG. 4, the wiring pattern 22 and the stress distribution pattern 27 made of a Cu film are collectively formed on the one surface 41a of the insulating substrate 41 by the subtractive method or the semi-additive method.
As described above, when the plurality of wiring boards 11 (wiring mother board 42) are manufactured, the wiring pattern 22 and the stress distribution pattern 27 are collectively formed by the subtractive method or the semi-additive method, thereby the stress distribution pattern 27. Since there is no need to provide a separate process for forming the semiconductor device, an increase in the cost of the semiconductor device 10 of the first embodiment can be suppressed.

次いで、図５に示す工程では、複数の第１の半導体チップ１４を準備しておき、各配線基板１１の中央に位置する第１のソルダーレジスト２９の上面２９ａに、主面１４ａが上側となるように、接着部材１５により第１の半導体チップ１４を接着する。
その後、ワイヤボンディング装置（図示せず）を用いて、第１の電極パッド３４と接続パッド部２２Ａとを電気的に接続する導電性ワイヤ１７（例えば、Ａｕワイヤ）を形成する。これにより、第１の半導体チップ１４と配線基板１１とがワイヤボンディング接続される。 Next, in the process shown in FIG. 5, a plurality of first semiconductor chips 14 are prepared, and the main surface 14 a is on the upper surface 29 a of the first solder resist 29 located at the center of each wiring substrate 11. As described above, the first semiconductor chip 14 is bonded by the bonding member 15.
Thereafter, a conductive wire 17 (for example, an Au wire) that electrically connects the first electrode pad 34 and the connection pad portion 22A is formed by using a wire bonding apparatus (not shown). Thereby, the first semiconductor chip 14 and the wiring substrate 11 are connected by wire bonding.

次いで、図６に示す工程では、複数の半導体チップ１４及び導電性ワイヤ１７を封止し、かつ上面１８ａが平坦な面とされた封止樹脂１８を形成する。封止樹脂１８は、例えば、トランスファーモールド法により形成することができる。   Next, in a step shown in FIG. 6, a plurality of semiconductor chips 14 and conductive wires 17 are sealed, and a sealing resin 18 having a flat upper surface 18a is formed. The sealing resin 18 can be formed by, for example, a transfer mold method.

次いで、図７に示す工程では、配線母基板４２に設けられた複数のランド２４に、第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃ（第１及び第２の外部接続端子１２Ａ， １２Ｂは図示せず）のうち、いずれか１つの外部接続端子を形成する。
これにより、各配線基板形成領域Ｃに、半導体装置１０が形成されるが、この段階では、複数の半導体装置１０は、連結されており、個片化されていない。 Next, in the process shown in FIG. 7, the first to third external connection terminals 12A, 12B, and 12C (first and second external connection terminals 12A, 12B) are formed on the plurality of lands 24 provided on the wiring motherboard 42. Are not shown), and one of the external connection terminals is formed.
As a result, the semiconductor device 10 is formed in each wiring board formation region C, but at this stage, the plurality of semiconductor devices 10 are connected and not separated.

次いで、図８に示す工程では、ダイシングラインＤに沿って、図７に示す構造体を切断することで、個片化された複数の半導体装置１０が製造される。   Next, in the process shown in FIG. 8, the structure shown in FIG. 7 is cut along the dicing line D, whereby a plurality of individual semiconductor devices 10 are manufactured.

第１の実施の形態の半導体装置の製造方法によれば、応力分散用パターン２７を形成する工程を別途設けることなく、応力分散用パターン２７を形成することが可能なため、第１の実施の形態の半導体装置１０の製造工程を煩雑にすることなく、温度サイクルに起因して、第１の半導体チップ１４のコーナー部１４Ａの下方に位置する第１の外部接続端子１２Ａが破断することを抑制できる。つまり、半導体装置１０の歩留まりを向上させることができる。   According to the manufacturing method of the semiconductor device of the first embodiment, the stress distribution pattern 27 can be formed without separately providing a step of forming the stress distribution pattern 27. The first external connection terminal 12 </ b> A located below the corner portion 14 </ b> A of the first semiconductor chip 14 is prevented from breaking due to the temperature cycle without complicating the manufacturing process of the semiconductor device 10 of the embodiment. it can. That is, the yield of the semiconductor device 10 can be improved.

（第２の実施の形態）
図９は、本発明の第２実施の形態に係る半導体装置の平面図である。図１０は、図９に示す第２の実施の形態の半導体装置のＥ−Ｅ線方向の断面図であり、図１１は、図９に示す第２の実施の形態の半導体装置のＦ−Ｆ線方向の断面図である。 (Second Embodiment)
FIG. 9 is a plan view of a semiconductor device according to the second embodiment of the present invention. FIG. 10 is a cross-sectional view of the semiconductor device according to the second embodiment shown in FIG. 9 in the EE line direction, and FIG. It is sectional drawing of a line direction.

図９では、説明の便宜上、図１０及び図１１に示す封止樹脂１８の図示を省略する。また、図９では、配線基板５１の一面５１ａ側からは見ることのできない配線基板５１の他面５１ｂ側に配置された第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃ、及び応力分散用パターン２７を点線で図示する。
また、図９〜図１１において、第１の半導体装置１０と同一構成部分には、同一符号を付す。 9, illustration of the sealing resin 18 shown in FIGS. 10 and 11 is omitted for convenience of explanation. In FIG. 9, the first to third external connection terminals 12A, 12B, 12C arranged on the other surface 51b side of the wiring substrate 51 that cannot be seen from the one surface 51a side of the wiring substrate 51, and the stress distribution The pattern 27 is illustrated by a dotted line.
9 to 11, the same components as those of the first semiconductor device 10 are denoted by the same reference numerals.

図９乃至図１１を参照するに、第２の実施の形態の半導体装置５０は、配線基板５１と、第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃ（複数の外部接続端子）と、第１の半導体チップ５２と、接着部材１５と、導電性ワイヤ１７と、封止樹脂１８と、を有する。   Referring to FIGS. 9 to 11, the semiconductor device 50 of the second embodiment includes a wiring board 51, first to third external connection terminals 12A, 12B, and 12C (a plurality of external connection terminals), The first semiconductor chip 52, the adhesive member 15, the conductive wire 17, and the sealing resin 18 are included.

配線基板５１は、配線基板５１の中央ではなく、配線基板５１の第１の辺５１−１側に第１の半導体チップ５２が実装可能なように、第１の実施の形態の配線基板１１に設けられた配線パターン２２、貫通電極２５、及び応力分散用パターン２７を配置すると共に、配線基板５１の第１の辺５１−１側よりも該第１の辺５１−１と対向する配線基板５１の第２の辺５１−２側に多くの数の接続パッド部２２を配置したこと以外は、配線基板１１と同様な構成とされている。   The wiring board 51 is arranged on the wiring board 11 of the first embodiment so that the first semiconductor chip 52 can be mounted not on the center of the wiring board 51 but on the first side 51-1 side of the wiring board 51. The provided wiring pattern 22, the through electrode 25, and the stress distribution pattern 27 are arranged, and the wiring board 51 that faces the first side 51-1 rather than the first side 51-1 side of the wiring board 51. The configuration is the same as that of the wiring board 11 except that a large number of connection pad portions 22 are arranged on the second side 51-2 side.

応力分散用パターン２７は、第１の半導体チップ５２の４つのコーナー部５２Ａの直下に配置される第１の外部接続端子１２Ａと、第１の外部接続端子１２Ａの外側（言い換えれば、コーナー部５２Ａの外側）に配置された第２の外部接続端子１２Ｂと対向するように絶縁基材２１の一面２１ａに配置されている。   The stress distribution pattern 27 includes a first external connection terminal 12A disposed immediately below the four corner portions 52A of the first semiconductor chip 52, and the outside of the first external connection terminal 12A (in other words, the corner portion 52A). Is disposed on one surface 21a of the insulating base material 21 so as to face the second external connection terminal 12B disposed on the outer side.

第１の半導体チップ５２は、矩形とされており、対向する２辺５２−１，５２−２のみに、第１の電極パッド３４を配置したこと以外は、第１の実施の形態で説明した第１の半導体チップ１４と同様な構成とされている。
また、第１の半導体チップ５２の１辺５２−２（第２の辺５１−２側に位置する辺）に配置された第１の電極パッド３４の数は、第１の半導体チップ５２の１辺５２−１（第１の辺５１−１側に位置する辺）に配置された第１の電極パッド３４の数よりも多くなるように構成されている。 The first semiconductor chip 52 has a rectangular shape, and has been described in the first embodiment except that the first electrode pad 34 is disposed only on the two opposite sides 52-1 and 52-2. The configuration is the same as that of the first semiconductor chip 14.
In addition, the number of first electrode pads 34 arranged on one side 52-2 of the first semiconductor chip 52 (side located on the second side 51-2 side) is 1 in the first semiconductor chip 52. The number of the first electrode pads 34 arranged on the side 52-1 (side located on the first side 51-1 side) is increased.

第１の半導体チップ５２は、主面５２ａが上側となり、かつ第１の半導体チップ５２の１辺５２−１が配線基板５１の第１の辺５１−１に近接するように、接着部材１５により、第１のソルダーレジスト２９の上面２９ａに接着されている。
言い換えれば、配線基板５１の第１の辺５１−１側に寄せた状態で、配線基板５１に第１の半導体チップ５２が実装されている。 The first semiconductor chip 52 is formed by the adhesive member 15 so that the main surface 52a is on the upper side and one side 52-1 of the first semiconductor chip 52 is close to the first side 51-1 of the wiring substrate 51. The first solder resist 29 is adhered to the upper surface 29a.
In other words, the first semiconductor chip 52 is mounted on the wiring board 51 in a state of being brought closer to the first side 51-1 side of the wiring board 51.

これにより、配線基板５１の第２の辺５１−２と第１の半導体チップ５２との間に位置する配線基板の第１の非チップ実装領域Ｇ１は、配線基板５１の第１の辺５１−１と第１の半導体チップ５２との間に位置する配線基板５１の第２の非チップ実装領域Ｇ２よりも広くなるように構成されている（図９参照）。 Thus, the first non-chip mounting region G 1 of the wiring board positioned between the second side 51-2 and the first semiconductor chip 52 of the wiring substrate 51, first side 51 of the wiring board 51 -1 and is configured to be wider than the second non-chip mounting region G 2 of the wiring board 51 positioned between the first semiconductor chip 52 (see FIG. 9).

第２の実施の形態の半導体装置によれば、配線基板５１の第１の辺５１−１側に寄せた状態で、配線基板５１に第１の半導体チップ５２を実装し、配線基板５１の第２の辺５１−２と第１の半導体チップ５２との間に位置する配線基板５１の第１の非チップ実装領域Ｇ１を第２の非チップ実装領域Ｇ２よりも広くすると共に、第２の辺５１−２側に位置する第１の半導体チップ５２に数多くの第１の電極パッド３４を配置することにより、第１の非チップ実装領域Ｇ１に位置する絶縁基材２１の一面２１ａに十分な配線スペース（言い換えれば、配線パターン２２を配置するためのスペース）を確保することが可能となる。
これにより、第１の非チップ実装領域Ｇ１に配置される配線パターン２２間の間隔を広くすることが可能となるので、配線パターン２２間のショートのリスクを低減できる。 According to the semiconductor device of the second embodiment, the first semiconductor chip 52 is mounted on the wiring substrate 51 in a state where the first semiconductor chip 52 is brought closer to the first side 51-1 side of the wiring substrate 51. 2 sides 51-2 and with wider than the first non-chip mounting regions G 1 and the second non-chip mounting region G 2 of the wiring board 51 positioned between the first semiconductor chip 52, the second By disposing a large number of first electrode pads 34 on the first semiconductor chip 52 located on the side 51-2 side of the insulating substrate 21 on the one surface 21a located in the first non-chip mounting region G1 A sufficient wiring space (in other words, a space for arranging the wiring pattern 22) can be secured.
As a result, the interval between the wiring patterns 22 arranged in the first non-chip mounting region G1 can be widened, so that the risk of a short circuit between the wiring patterns 22 can be reduced.

なお、第２の実施の形態の半導体装置５０は、第１の実施の形態の半導体装置１０と同様な効果を得ることができる。
具体的には、ダミーチップを備えた従来の半導体装置と比較して、配線基板５１（半導体装置５０）を大型化させることなく、温度サイクルに起因して、第１の半導体チップ５２のコーナー部５２Ａの下方に位置する第１の外部接続端子１２Ａが破断することを抑制できる。したがって、半導体装置５０をマザーボード等の基板に実装する際の接続信頼性を向上させることができる。 The semiconductor device 50 according to the second embodiment can obtain the same effects as the semiconductor device 10 according to the first embodiment.
Specifically, compared with a conventional semiconductor device provided with a dummy chip, the corner portion of the first semiconductor chip 52 is caused by the temperature cycle without increasing the size of the wiring substrate 51 (semiconductor device 50). The first external connection terminal 12A located below 52A can be prevented from breaking. Therefore, connection reliability when the semiconductor device 50 is mounted on a substrate such as a mother board can be improved.

また、上記構成とされた第２の実施の形態の半導体装置５０は、先に説明した第１の実施の形態の半導体装置１０の製造方法と同様な手法により製造することができ、第１の実施の形態の半導体装置１０の製造方法と同様な効果を得ることができる。   Further, the semiconductor device 50 of the second embodiment having the above-described configuration can be manufactured by the same method as the method of manufacturing the semiconductor device 10 of the first embodiment described above. The same effects as those of the method for manufacturing the semiconductor device 10 of the embodiment can be obtained.

（第３の実施の形態）
図１２は、本発明の第３実施の形態に係る半導体装置の平面図である。図１３は、図１２に示す第３の実施の形態の半導体装置のＨ−Ｈ線方向の断面図である。 (Third embodiment)
FIG. 12 is a plan view of a semiconductor device according to the third embodiment of the present invention. FIG. 13 is a cross-sectional view taken along the line HH of the semiconductor device of the third embodiment shown in FIG.

図１２では、説明の便宜上、図１３に示す封止樹脂１８の図示を省略する。また、図１２では、配線基板１１の一面１１ａ側からは見ることのできない配線基板１１の他面１１ｂ側に配置された第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃ、及び応力分散用パターン２７を点線で図示する。
また、図１２及び図１３において、第１の半導体装置１０と同一構成部分には、同一符号を付す。 In FIG. 12, the illustration of the sealing resin 18 shown in FIG. 13 is omitted for convenience of explanation. In FIG. 12, the first to third external connection terminals 12A, 12B, 12C arranged on the other surface 11b side of the wiring substrate 11 that cannot be seen from the one surface 11a side of the wiring substrate 11, and the stress distribution The pattern 27 is illustrated by a dotted line.
12 and 13, the same components as those of the first semiconductor device 10 are denoted by the same reference numerals.

図１２及び図１３を参照するに、第３の実施の形態の半導体装置６０は、第１の実施の形態の半導体装置１０に設けられた開口部２９Ａにより応力分散用パターン２７の一部２７Ａを露出させ、導電性ワイヤ１７により、応力分散用パターン２７の一部２７Ａと第１の電極パッド３４とを電気的に接続し、かつ貫通電極２５を介して、応力分散用パターン２７と第１の外部接続端子１２Ａが設けられたランド２４とを電気的に接続させたこと以外は、半導体装置１０と同様な構成とされている。   Referring to FIGS. 12 and 13, in the semiconductor device 60 of the third embodiment, a portion 27A of the stress distribution pattern 27 is formed by the opening 29A provided in the semiconductor device 10 of the first embodiment. A portion 27A of the stress distribution pattern 27 and the first electrode pad 34 are electrically connected to each other by the conductive wire 17, and the stress distribution pattern 27 and the first electrode pad 34 are connected to each other through the through electrode 25. The configuration is the same as that of the semiconductor device 10 except that the land 24 provided with the external connection terminal 12A is electrically connected.

これにより、応力分散用パターン２７を、接続パッドを有した配線として機能させることができる。また、応力分散用パターン２７が電気的に接続される第１の外部接続端子１２Ａとしては、例えば、電源用外部接続端子やグラウンド用外部接続端子を用いることができる。   Thereby, the stress distribution pattern 27 can function as a wiring having connection pads. Further, as the first external connection terminal 12A to which the stress distribution pattern 27 is electrically connected, for example, a power supply external connection terminal or a ground external connection terminal can be used.

第３の実施の形態の半導体装置によれば、応力分散用パターン２７の一部２７Ａと第１の電極パッド３４とを電気的に接続し、かつ貫通電極２５を介して、応力分散用パターン２７と第１の外部接続端子１２Ａが設けられたランド２４とを電気的に接続させることで、応力分散用パターン２７を、接続パッドを有した配線として機能させることができる。   According to the semiconductor device of the third embodiment, a portion 27A of the stress distribution pattern 27 and the first electrode pad 34 are electrically connected, and the stress distribution pattern 27 is connected via the through electrode 25. By electrically connecting the lands 24 provided with the first external connection terminals 12A, the stress distribution pattern 27 can function as a wiring having connection pads.

なお、第３の実施の形態の半導体装置６０は、第１の実施の形態の半導体装置１０と同様な効果を得ることができる。
具体的には、ダミーチップを備えた従来の半導体装置と比較して、配線基板１１（半導体装置６０）を大型化させることなく、温度サイクルに起因して、第１の半導体チップ１４のコーナー部１４Ａの下方に位置する第１の外部接続端子１２Ａが破断することを抑制できる。したがって、半導体装置６０をマザーボード等の基板に実装する際の接続信頼性を向上させることができる。 The semiconductor device 60 according to the third embodiment can obtain the same effects as the semiconductor device 10 according to the first embodiment.
Specifically, the corner portion of the first semiconductor chip 14 is caused by the temperature cycle without increasing the size of the wiring substrate 11 (semiconductor device 60) as compared with the conventional semiconductor device including the dummy chip. It can suppress that the 1st external connection terminal 12A located under 14A breaks. Therefore, connection reliability when the semiconductor device 60 is mounted on a substrate such as a mother board can be improved.

また、上記構成とされた第３の実施の形態の半導体装置６０は、先に説明した第１の実施の形態の半導体装置１０の製造方法と同様な手法により製造することができ、第１の実施の形態の半導体装置１０の製造方法と同様な効果を得ることができる。   Further, the semiconductor device 60 of the third embodiment having the above-described configuration can be manufactured by the same method as the method of manufacturing the semiconductor device 10 of the first embodiment described above. The same effects as those of the method for manufacturing the semiconductor device 10 of the embodiment can be obtained.

（第４の実施の形態）
図１４は、本発明の第４実施の形態に係る半導体装置の断面図である。図１４において、先に説明した第１の実施の形態の半導体装置１０と同一構成部分には同一符号を付す。 (Fourth embodiment)
FIG. 14 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention. In FIG. 14, the same components as those of the semiconductor device 10 of the first embodiment described above are denoted by the same reference numerals.

図１４を参照するに、第４の実施の形態の半導体装置７０は、第１の実施の形態の半導体装置１０を構成する配線基板１１の替わりに、配線基板７１を有したこと以外は、半導体装置１０と同様に構成される。   Referring to FIG. 14, the semiconductor device 70 of the fourth embodiment is a semiconductor device except that it has a wiring board 71 instead of the wiring board 11 constituting the semiconductor device 10 of the first embodiment. The configuration is the same as that of the device 10.

配線基板７１は、第１の実施の形態で説明した配線基板１１の構成に、さらに、第１の絶縁層７３、第２の絶縁層７４、第１の配線パターン７６、及び第２の配線パターン７７を設け、かつ配線パターン２２、複数のランド２４、第１のソルダーレジスト２９、及び第２のソルダーレジスト３１の配設位置を配線基板１１とは異ならせたこと以外は、配線基板１１と同様に構成される。   The wiring board 71 has the same structure as the wiring board 11 described in the first embodiment, and further includes a first insulating layer 73, a second insulating layer 74, a first wiring pattern 76, and a second wiring pattern. 77, and the wiring board 22, the plurality of lands 24, the first solder resist 29, and the second solder resist 31 are arranged in different positions from the wiring board 11, except for the wiring board 11. Configured.

第１の絶縁層７３は、絶縁基材２１の一面２１ａに配置された応力分散用パターン２７を覆うように、絶縁基材２１の一面２１ａに設けられている。
配線パターン２２は、第１の絶縁層７３の上面７３ａ（配線基板７１の一面７１ａ）に設けられている。
つまり、配線パターン２２は、応力分散用パターン２７とは異なるレイヤー（階層）に配置されている。 The first insulating layer 73 is provided on the one surface 21 a of the insulating base material 21 so as to cover the stress distribution pattern 27 disposed on the one surface 21 a of the insulating base material 21.
The wiring pattern 22 is provided on the upper surface 73 a (one surface 71 a of the wiring substrate 71) of the first insulating layer 73.
That is, the wiring pattern 22 is arranged in a layer (hierarchy) different from the stress distribution pattern 27.

第１の配線パターン７６は、第１の絶縁層７３に内設されており、一端が配線パターン２２と接続され、他端が貫通電極２５の上端と接続されている。これにより、配線パターン２２は、第１の配線パターン７６を介して、貫通電極２５と電気的に接続されている。   The first wiring pattern 76 is provided in the first insulating layer 73 and has one end connected to the wiring pattern 22 and the other end connected to the upper end of the through electrode 25. Thereby, the wiring pattern 22 is electrically connected to the through electrode 25 via the first wiring pattern 76.

第１のソルダーレジスト２９は、接続パッド部２２Ａを除いた配線パターン２２を覆うように、第１の絶縁層７３の上面７３ａに設けられている。第１のソルダーレジスト２９の上面２９ａには、接着部材２５により、第１の半導体チップ１４が接着されている。
また、導電性ワイヤ１７を介して、第１の電極パッド３４と接続パッド部２２Ａとが電気的に接続されている。 The first solder resist 29 is provided on the upper surface 73a of the first insulating layer 73 so as to cover the wiring pattern 22 excluding the connection pad portion 22A. The first semiconductor chip 14 is bonded to the upper surface 29 a of the first solder resist 29 by an adhesive member 25.
Further, the first electrode pad 34 and the connection pad portion 22 </ b> A are electrically connected via the conductive wire 17.

第２の絶縁層７４は、絶縁基材２１の他面２１ｂを覆うように設けられている。複数のランド２４は、第２の絶縁層７４の下面７４ａ（配線基板７１の他面７１ｂ）に設けられている。
第２のソルダーレジスト３１は、複数のランド２４を露出するように、第２の絶縁層７４の下面７４ａに設けられている。 The second insulating layer 74 is provided so as to cover the other surface 21 b of the insulating base material 21. The plurality of lands 24 are provided on the lower surface 74 a (the other surface 71 b of the wiring board 71) of the second insulating layer 74.
The second solder resist 31 is provided on the lower surface 74 a of the second insulating layer 74 so as to expose the plurality of lands 24.

第２の配線パターン７７は、第２の絶縁層７４に内設されており、一端が貫通電極２５の下端と接続され、他端がランド３４と接続されている。これにより、ランド３４は、第２の配線パターン７７を介して、貫通電極２５と電気的に接続されている。
ランド２４に設けられた第１乃至第３の外部接続端子１２Ａ，１２Ｂ，１２Ｃは、第２の絶縁層７４の下面７４ａから突出している。 The second wiring pattern 77 is provided in the second insulating layer 74 and has one end connected to the lower end of the through electrode 25 and the other end connected to the land 34. Thereby, the land 34 is electrically connected to the through electrode 25 via the second wiring pattern 77.
The first to third external connection terminals 12 </ b> A, 12 </ b> B, 12 </ b> C provided on the land 24 protrude from the lower surface 74 a of the second insulating layer 74.

このように、絶縁基材２１の一面２１ａに第１の絶縁層７３を設け、応力分散用パターン２７と配線パターン２２とを異なるレイヤーに配置した第４の実施の形態の半導体装置７０においても、第１の実施の形態の半導体装置１０と同様な効果を得ることができる。   Thus, also in the semiconductor device 70 of the fourth embodiment in which the first insulating layer 73 is provided on the one surface 21a of the insulating base material 21 and the stress distribution pattern 27 and the wiring pattern 22 are arranged in different layers, The same effect as that of the semiconductor device 10 of the first embodiment can be obtained.

（第５の実施の形態）
図１５及び図１６は、本発明の第５実施の形態に係る半導体装置の断面図であり、図１６は、図１５とは異なる切断位置で第５の実施の形態の半導体装置８０を切断した際の断面図である。
図１５及び図１６において、先に説明した第１の実施の形態の半導体装置１０と同一構成部分には同一符号を付す。 (Fifth embodiment)
15 and 16 are cross-sectional views of the semiconductor device according to the fifth embodiment of the present invention. FIG. 16 shows the semiconductor device 80 of the fifth embodiment cut at a cutting position different from that in FIG. FIG.
15 and 16, the same reference numerals are given to the same components as those of the semiconductor device 10 of the first embodiment described above.

図１５及び図１６を参照するに、第５の実施の形態の半導体装置８０は、第１の実施の形態の半導体装置１０を構成する配線基板１１の替わりに、配線基板８１を設けると共に、第１の半導体チップ１４上に第２の半導体チップ８３を搭載した以外は、半導体装置１０と同様に構成される。   Referring to FIGS. 15 and 16, the semiconductor device 80 of the fifth embodiment is provided with a wiring board 81 instead of the wiring board 11 constituting the semiconductor device 10 of the first embodiment. The configuration is the same as that of the semiconductor device 10 except that the second semiconductor chip 83 is mounted on one semiconductor chip 14.

配線基板８１は、第１の実施の形態で説明した配線基板１１に設けられた配線パターン２２の替わりに、配線パターン９１〜９３を設けた以外は、配線基板１１と同様に構成される。
配線パターン９１〜９３は、応力分散用パターン２７が形成された絶縁基材２１の一面２１ａ（配線基板８１の一面８１ａ）に設けられている。
配線パターン９１は、第１のソルダーレジスト２９から露出された接続パッド部９１Ａを有する。接続パッド部９１Ａは、導電性ワイヤ１７，８５（例えば、Ａｕワイヤ）と接続されている。 The wiring board 81 is configured in the same manner as the wiring board 11 except that wiring patterns 91 to 93 are provided instead of the wiring pattern 22 provided on the wiring board 11 described in the first embodiment.
The wiring patterns 91 to 93 are provided on the one surface 21 a (one surface 81 a of the wiring substrate 81) on which the stress distribution pattern 27 is formed.
The wiring pattern 91 has a connection pad portion 91 </ b> A exposed from the first solder resist 29. The connection pad portion 91A is connected to the conductive wires 17 and 85 (for example, Au wires).

接続パッド部９１Ａは、導電性ワイヤ１７を介して、第１の半導体チップ１４の第１の電極パッド３４と電気的に接続されると共に、導電性ワイヤ８５を介して、第２の半導体チップ８３の第２の電極パッド９６と電気的に接続されている。
また、配線パターン９１は、貫通電極２５を介して、ランド３４と電気的に接続されている。 The connection pad portion 91 </ b> A is electrically connected to the first electrode pad 34 of the first semiconductor chip 14 via the conductive wire 17, and is connected to the second semiconductor chip 83 via the conductive wire 85. The second electrode pad 96 is electrically connected.
The wiring pattern 91 is electrically connected to the land 34 through the through electrode 25.

配線パターン９２は、第１のソルダーレジスト２９から露出された接続パッド部９２Ａを有する。接続パッド部９２Ａは、導電性ワイヤ１７と接続されている。
接続パッド部９２Ａは、導電性ワイヤ１７を介して、第１の半導体チップ１４の第１の電極パッド３４と電気的に接続されている。また、配線パターン９２は、貫通電極２５を介して、ランド３４と電気的に接続されている。 The wiring pattern 92 has a connection pad portion 92 </ b> A exposed from the first solder resist 29. The connection pad portion 92A is connected to the conductive wire 17.
The connection pad portion 92 </ b> A is electrically connected to the first electrode pad 34 of the first semiconductor chip 14 through the conductive wire 17. Further, the wiring pattern 92 is electrically connected to the land 34 through the through electrode 25.

配線パターン９３は、第１のソルダーレジスト２９から露出された接続パッド部９３Ａを有する。接続パッド部９３Ａは、導電性ワイヤ８５と接続されている。
接続パッド部９３Ａは、導電性ワイヤ８５を介して、第２の半導体チップ８３の第２の電極パッド９６と電気的に接続されている。また、配線パターン９２は、貫通電極２５を介して、ランド３４と電気的に接続されている。 The wiring pattern 93 has a connection pad portion 93 </ b> A exposed from the first solder resist 29. The connection pad portion 93A is connected to the conductive wire 85.
The connection pad portion 93 </ b> A is electrically connected to the second electrode pad 96 of the second semiconductor chip 83 through the conductive wire 85. Further, the wiring pattern 92 is electrically connected to the land 34 through the through electrode 25.

このように、配線基板８１が応力分散用パターン２７を有すると共に、配線基板８１に対してワイヤボンディング接続された第１の半導体チップ１４上に、配線基板８１に対してワイヤボンディング接続される第２の半導体チップ８３が搭載された第５の実施の形態の半導体装置８０においても、第１の実施の形態の半導体装置１０と同様な効果を得ることができる。   As described above, the wiring substrate 81 has the stress distribution pattern 27 and the second semiconductor substrate 14 is wire-bonded to the wiring substrate 81 on the first semiconductor chip 14 that is wire-bonded to the wiring substrate 81. Also in the semiconductor device 80 of the fifth embodiment on which the semiconductor chip 83 is mounted, the same effect as that of the semiconductor device 10 of the first embodiment can be obtained.

つまり、応力分散用パターン２７を第５実施の形態の半導体装置８０のようなＭＣＰ（Ｍｕｌｔｉ Ｃｈｉｐ Ｐａｃｋａｇｅ）タイプの半導体装置に適用してもよい。
この場合、第１の半導体チップ１４の上段に積層される第２の半導体チップ８３の４つのコーナー部８３Ａの下方には応力分散用パターン２７を配置しなくてもよい。 That is, the stress distribution pattern 27 may be applied to an MCP (Multi Chip Package) type semiconductor device such as the semiconductor device 80 of the fifth embodiment.
In this case, the stress distribution pattern 27 may not be disposed below the four corner portions 83A of the second semiconductor chip 83 stacked on the upper stage of the first semiconductor chip 14.

なお、図９では、一例として、第１の半導体チップ１４上に、１つの半導体チップ（この場合、第２の半導体チップ８３）のみを搭載した場合を例に挙げて説明したが、第１の半導体チップ１４上に、２つ以上の半導体チップを積み重ねて搭載してもよい。   In FIG. 9, as an example, the case where only one semiconductor chip (in this case, the second semiconductor chip 83) is mounted on the first semiconductor chip 14 has been described as an example. Two or more semiconductor chips may be stacked and mounted on the semiconductor chip 14.

以上、本発明の好ましい実施の形態について詳述したが、本発明はかかる特定の実施の形態に限定されるものではなく、特許請求の範囲内に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

例えば、第２の実施の形態の半導体装置５０において、開口部２９Ａの近傍に位置する応力分散用パターン２７の一部を露出させ、導電性ワイヤ１７により、開口部２９Ａから露出された応力分散用パターン２７の一部と第１の電極パッド３４とを電気的に接続してもよい。この場合、第３の実施の形態の半導体装置６０と同様な効果を得ることができる。   For example, in the semiconductor device 50 of the second embodiment, a part of the stress distribution pattern 27 located in the vicinity of the opening 29A is exposed, and the stress distribution pattern exposed from the opening 29A by the conductive wire 17 is exposed. A part of the pattern 27 and the first electrode pad 34 may be electrically connected. In this case, the same effect as that of the semiconductor device 60 of the third embodiment can be obtained.

また、第４の実施の形態の半導体装置７０において、第１のソルダーレジスト２９から応力分散用パターン２７の一部を露出させ、導電性ワイヤ１７により、第１のソルダーレジスト２９から露出された応力分散用パターン２７の一部と第１の電極パッド３４とを電気的に接続してもよい。この場合、第３の実施の形態の半導体装置６０と同様な効果を得ることができる。   In the semiconductor device 70 of the fourth embodiment, a part of the stress distribution pattern 27 is exposed from the first solder resist 29, and the stress exposed from the first solder resist 29 by the conductive wire 17. A part of the dispersion pattern 27 and the first electrode pad 34 may be electrically connected. In this case, the same effect as that of the semiconductor device 60 of the third embodiment can be obtained.

また、第５の実施の形態の半導体装置８０において、第１のソルダーレジスト２９から応力分散用パターン２７の一部を露出させ、導電性ワイヤ１７及び／または導電性ワイヤ８５により、第１のソルダーレジスト２９から露出された応力分散用パターン２７の一部と第１の電極パッド３４及び／または第２の電極パッド９６とを電気的に接続してもよい。この場合、第３の実施の形態の半導体装置６０と同様な効果を得ることができる。   In the semiconductor device 80 of the fifth embodiment, a part of the stress distribution pattern 27 is exposed from the first solder resist 29, and the first solder is formed by the conductive wire 17 and / or the conductive wire 85. A part of the stress distribution pattern 27 exposed from the resist 29 may be electrically connected to the first electrode pad 34 and / or the second electrode pad 96. In this case, the same effect as that of the semiconductor device 60 of the third embodiment can be obtained.

さらに、第３乃至第５の実施の形態の半導体装置６０，７０，８０において、第２の実施の形態の半導体装置５０（図９参照）のように、第２の非チップ実装領域Ｇ２よりも第１の非チップ実装領域Ｇ１を広く構成してもよい。 Further, in the semiconductor device 60, 70, 80 of the third to fifth embodiments, as in the semiconductor device 50 of the second embodiment (see FIG. 9), than the second non-chip mounting region G 2 it may also be broadly constitute a non-chip mounting region G 1 of the first.

本発明は、半導体装置に適用可能である。   The present invention is applicable to semiconductor devices.

１０，５０，６０，７０，８０…半導体装置、１１，５１，７１，８１…配線基板、１１ａ，２１ａ，４２ａ，５１ａ，７１ａ，８１ａ…一面、１１ｂ，２１ｂ，４２ｂ，５１ｂ，７１ｂ，８１ｂ…他面、１２Ａ…第１の外部接続端子、１２Ｂ…第２の外部接続端子、１２Ｃ…第３の外部接続端子、１４，５２…第１の半導体チップ、１４ａ…主面、１４Ａ，５２Ａ，８３Ａ…コーナー部、１５…接着部材、１７，８５…導電性ワイヤ、１８…封止樹脂、１８ａ，２９ａ，５２ａ，７３ａ…上面、２１，４１…絶縁基材、２２，９１〜９３…配線パターン、２２Ａ，９１Ａ，９２Ａ，９３Ａ…接続パッド部、２４…ランド、２５…貫通電極、２７…応力分散用パターン、２７Ａ…一部、２９…第１のソルダーレジスト、２９Ａ，３１Ａ…開口部、３１…第２のソルダーレジスト、３１ａ，７４ａ…下面、３４…第１の電極パッド、４２…配線母基板、５１−１…第１の辺、５１−２…第２の辺、５２−１，５２−２…１辺、７３…第１の絶縁層、７４…第２の絶縁層、７６…第１の配線パターン、７７…第２の配線パターン、８３…第２の半導体チップ、９６…第２の電極パッド、Ｃ…配線基板形成領域、Ｄ…ダイシングライン、Ｇ１…第１の非チップ実装領域、Ｇ２…第２の非チップ実装領域 10, 50, 60, 70, 80... Semiconductor device, 11, 51, 71, 81... Wiring board, 11a, 21a, 42a, 51a, 71a, 81a .. One side, 11b, 21b, 42b, 51b, 71b, 81b. Other surface, 12A ... first external connection terminal, 12B ... second external connection terminal, 12C ... third external connection terminal, 14,52 ... first semiconductor chip, 14a ... main surface, 14A, 52A, 83A ... corner part, 15 ... adhesive member, 17, 85 ... conductive wire, 18 ... sealing resin, 18a, 29a, 52a, 73a ... upper surface, 21, 41 ... insulating substrate, 22, 91-93 ... wiring pattern, 22A, 91A, 92A, 93A ... connection pad, 24 ... land, 25 ... penetrating electrode, 27 ... stress distribution pattern, 27A ... part, 29 ... first solder resist, 29A, 31A ... opening 31 ... 2nd soldering resist, 31a, 74a ... lower surface, 34 ... 1st electrode pad, 42 ... wiring mother board, 51-1 ... 1st edge | side, 51-2 ... 2nd edge | side, 52-1 , 52-2 ... 1 side, 73 ... 1st insulating layer, 74 ... 2nd insulating layer, 76 ... 1st wiring pattern, 77 ... 2nd wiring pattern, 83 ... 2nd semiconductor chip, 96 ... second electrode pads, C ... wiring board formation regions, D ... dicing line, G 1 ... first non-chip mounting region, G 2 ... second non-chip mounting region

Claims (8)

複数の第１の電極パッドを有する第１の半導体チップと、
一面に配置され、前記第１の半導体チップと電気的に接続される配線パターン、及び他面に配置され、前記配線パターンと電気的に接続された複数のランドを有する配線基板と、
複数の前記ランドのそれぞれに対して設けられた外部接続端子と、
を有する半導体装置であって、
前記配線基板は、複数の前記外部接続端子のうち、前記第１の半導体チップのコーナー部の下方に位置する第１の外部接続端子、及び該コーナー部の外側に配置された第２の外部接続端子と対向配置された応力分散用パターンを有することを特徴とする半導体装置。 A first semiconductor chip having a plurality of first electrode pads;
A wiring pattern disposed on one surface and electrically connected to the first semiconductor chip, and a wiring substrate disposed on the other surface and having a plurality of lands electrically connected to the wiring pattern;
An external connection terminal provided for each of the plurality of lands;
A semiconductor device comprising:
The wiring board includes: a first external connection terminal positioned below a corner portion of the first semiconductor chip among the plurality of external connection terminals; and a second external connection disposed outside the corner portion. A semiconductor device having a stress distribution pattern arranged to face a terminal. 前記応力分散用パターンは、ベタパターンであることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the stress distribution pattern is a solid pattern. 前記第１の半導体チップ及び前記配線基板は、それぞれ矩形とされており、
前記第１の半導体チップを前記配線基板の第１の辺側に寄せて配置し、
前記第１の辺の反対側に位置する前記配線基板の第２の辺と前記第１の半導体チップとの間に位置する前記配線基板の第１の非チップ実装領域を、前記第１の辺と前記第１の半導体チップとの間に位置する前記配線基板の第２の非チップ実装領域よりも広くし、
前記第２の辺側に配置された前記第１の電極パッドの数を、前記第１の辺側に配置された前記第１の電極パッドの数よりも多くしたことを特徴とする請求項１または２記載の半導体装置。 Each of the first semiconductor chip and the wiring board is rectangular,
Placing the first semiconductor chip close to the first side of the wiring board;
A first non-chip mounting region of the wiring board located between the second side of the wiring board located on the opposite side of the first side and the first semiconductor chip; And a second non-chip mounting region of the wiring board located between the first semiconductor chip and the first semiconductor chip,
2. The number of the first electrode pads disposed on the second side is larger than the number of the first electrode pads disposed on the first side. Or the semiconductor device of 2. 前記ランドと前記応力分散用パターンとを電気的に接続すると共に、前記第１の電極パッドと前記応力分散用パターンとをワイヤボンディング接続したことを特徴とする請求項１ないし３のうち、いずれか１項記載の半導体装置。   4. The device according to claim 1, wherein the land and the stress distribution pattern are electrically connected, and the first electrode pad and the stress distribution pattern are connected by wire bonding. 5. The semiconductor device according to 1. 前記配線基板は、絶縁基材を有し、
前記絶縁基材の一面に、前記配線パターン及び前記応力分散用パターンを配置し、
前記絶縁基材の他面に、複数の前記ランドを配置したことを特徴とする請求項１ないし４のうち、いずれか１項記載の半導体装置。 The wiring board has an insulating base material,
On one surface of the insulating substrate, the wiring pattern and the stress distribution pattern are arranged,
5. The semiconductor device according to claim 1, wherein a plurality of the lands are arranged on the other surface of the insulating base material. 前記応力分散用パターンは、前記配線パターンと同じ材料で構成され、かつ前記配線パターンと同じ厚さであることを特徴とする請求項５記載の半導体装置。   6. The semiconductor device according to claim 5, wherein the stress distribution pattern is made of the same material as the wiring pattern and has the same thickness as the wiring pattern. 前記配線基板は、絶縁基材と、該絶縁基材の一面に設けられた第１の絶縁層と、前記絶縁基材の他面に設けられた第２の絶縁層と、を有し、
前記絶縁基材の一面に、前記応力分散用パターンを配置し、
前記第１の絶縁層の上面に、前記配線パターンを配置し、
前記第２の絶縁層の下面に、複数の前記ランドを配置したことを特徴とする請求項１なし４のうち、いずれか１項記載の半導体装置。 The wiring board has an insulating base, a first insulating layer provided on one surface of the insulating base, and a second insulating layer provided on the other surface of the insulating base,
The stress distribution pattern is disposed on one surface of the insulating substrate,
Placing the wiring pattern on the top surface of the first insulating layer;
5. The semiconductor device according to claim 1, wherein a plurality of the lands are arranged on a lower surface of the second insulating layer. 前記第１の半導体チップ上に、前記第１の電極パッドを露出させるように、複数の第２の電極パッドを有する第２の半導体チップを設け、
前記第２の電極パッドと前記配線パターンとをワイヤボンディング接続したことを特徴とする請求項１ないし７のうち、いずれか１項記載の半導体装置。 A second semiconductor chip having a plurality of second electrode pads is provided on the first semiconductor chip so as to expose the first electrode pads,
8. The semiconductor device according to claim 1, wherein the second electrode pad and the wiring pattern are connected by wire bonding.
JP2012008246A 2012-01-18 2012-01-18 Semiconductor device Pending JP2013149744A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111769101A (en) * 2020-07-09 2020-10-13 中国科学院微电子研究所 Packaging structure and packaging method based on multiple transfer boards

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111769101A (en) * 2020-07-09 2020-10-13 中国科学院微电子研究所 Packaging structure and packaging method based on multiple transfer boards
CN111769101B (en) * 2020-07-09 2022-05-03 中国科学院微电子研究所 Packaging structure and packaging method based on multiple transfer boards

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