JP2013149318A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an increase in a circuit scale, and secure read-out margin even when electrical characteristics of a real memory cell are degraded.SOLUTION: The semiconductor memory includes a nonvolatile real memory cell and a reference memory cell, a first load and a first switch which are arranged in series between the reference memory cell and a power source line, a second load and a second switch which are arranged in series between the reference memory cell and the power source line, a load control circuit in which the first switch is turned on when a set signal is at a first level, the second switch is turned on when the set signal is at a second level, and load amounts of the first load and the second load are different from each other, and a sense amplifier for comparing a cell current flowing in the real memory cell with a reference current in a read-out operation.

Description

  The present invention relates to a nonvolatile semiconductor memory.

  In a nonvolatile semiconductor memory such as a flash memory, the logic held in the memory cell is determined by comparing a cell current flowing according to the threshold voltage of the memory cell with a reference current. In a semiconductor memory manufacturing process, a method has been proposed in which a read margin of a memory cell is measured using a plurality of reference currents, and a current source that generates a reference current having the largest read margin is selected (for example, Patent Document 1). reference.).

  In order to set a criterion used at the time of testing an over-erased memory cell set to a negative threshold voltage more strictly than a criterion after shipment, a method of switching a reference current has been proposed (for example, a patent) Reference 2).

  In order to consider the wiring load that changes depending on the position of the memory cell, a method of switching the reference current according to the position of the memory cell to be accessed has been proposed (for example, see Patent Document 3). A method has been proposed in which a reference memory cell is formed by a main transistor and an adjustment transistor, and the threshold voltage of the adjustment transistor is adjusted in order to make the cell current characteristics of the memory cell storing data and the reference memory cell equal to each other. (For example, refer to Patent Document 4).

JP 2007-207343 A JP 2005-129167 A JP 2004-39184 A JP 2002-163893 A

  When a circuit for adjusting or switching the reference current is provided in the semiconductor memory in order to improve the read margin, if a redundant circuit or a complicated circuit is formed, the circuit scale increases and the cost increases.

  It is an object of the present invention to secure a read margin even when the electrical characteristics of a real memory cell are deteriorated by suppressing an increase in circuit scale.

  In one embodiment of the present invention, a semiconductor memory includes a nonvolatile real memory cell into which data is written, a reference memory cell that generates a reference current during a read operation for reading data from the real memory cell, a reference memory cell, and a power supply line. A first load and a first switch arranged in series between the reference memory cell and a power supply line, and a second load and a second switch arranged in series between the reference memory cell and the power supply line. Is turned on when the setting signal is at the second level, the second switch is turned on when the setting signal is at the second level, and the load control circuit in which the load amounts of the first load and the second load are different from each other, and during the read operation, A sense amplifier that compares a cell current flowing through the memory cell with a reference current is provided.

  An increase in circuit scale is suppressed, and a read margin can be ensured even when the electrical characteristics of the real memory cell deteriorate.

1 illustrates an example of a semiconductor memory in one embodiment. The example of the semiconductor memory in another embodiment is shown. 3 shows an example of the real cell array shown in FIG. 3 shows an example of the layout of the real cell array shown in FIG. 3 shows an example of a main part of the reference cell array for read operation shown in FIG. 3 shows an example of a reference cell array for the read operation shown in FIG. An example of the layout of the reference cell array for the read operation shown in FIG. 6 is shown. 3 shows an example of a manufacturing method of the semiconductor memory MEM shown in FIG. An example of the distribution of threshold voltages of real memory cells is shown. The voltage setting examples in the read operation, erase operation, write operation, and various verify operations are shown. In the manufacturing method shown in FIG. 8, the change of the characteristic of the reference cell transistor for read-out operation is shown. The example of the principal part of the reference cell array for read-out operation in another embodiment is shown. The example of the semiconductor memory in another embodiment is shown. An example of a main part of the X decoder shown in FIG. 13 is shown. 14 illustrates an example of a main part of the reference cell array for the read operation illustrated in FIG.

  Hereinafter, embodiments will be described with reference to the drawings. A signal line indicated by a bold line indicates a bus signal line through which a signal of a plurality of bits is transmitted. A signal preceded by “/” indicates negative logic. Double square marks indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 shows an example of a semiconductor memory MEM in one embodiment. For example, the semiconductor memory MEM is a nonvolatile semiconductor memory such as a flash memory. The semiconductor memory MEM may operate in synchronization with the clock or may operate asynchronously with the clock.

  The semiconductor memory MEM includes a real memory cell MC, a reference memory cell RMC, a load control circuit LDCNT, and a sense amplifier SA. For example, the real memory cell MC is a non-volatile memory cell including a real cell transistor CT having a control gate and a floating gate connected to the real word line WL. Data of logic 0 or logic 1 written in the real memory cell MC is held even when the power supply voltage VCC is not supplied. For example, the real memory cell MC is set to logic 0 by a write operation in which charges are accumulated in the floating gate. The real memory cell MC is set to logic 1 by the erase operation in which charges are released from the floating gate.

  The reference memory cell RMC is a nonvolatile memory cell including a reference cell transistor RCT having a control gate and a floating gate connected to the reference word line RWL. The reference cell transistor RCT is set in advance to a predetermined threshold voltage, and generates a reference current IR during a read operation for reading data from the real memory cell MC. The reference current IR flows to the ground line GND through the load control circuit LDCNT.

  The load control circuit LDCNT includes a load LD1 and a switch SW1 arranged between the reference memory cell RMC and the ground line GND, and a load LD2 and a switch SW2 arranged between the reference memory cell RMC and the ground line GND. Have. For example, the switch SW1 is turned on when the setting signal SET is at the first level, and the switch SW2 is turned on when the setting signal SET is at the second level opposite to the first level. For example, the first level is one of logic 0 and logic 1, and the second level is the other of logic 0 and logic 1. The load amounts of the load LD1 and the load LD2 are different from each other. The ground line GND is an example of a power supply line.

  The setting signal SET is generated by a program circuit or the like formed in the semiconductor memory MEM. Alternatively, the setting signal SET is supplied from outside the semiconductor memory MEM. The setting signal SET may be set to the first level or the second level by fixing an external terminal that receives the setting signal SET to logic 0 or logic 1.

  The sense amplifier SA compares the cell current IC flowing through the real memory cell MC with the reference current IR during a read operation. The cell current IC is a current that flows between the source and drain of the real cell transistor CT. The reference current IR is a current that flows between the source and drain of the reference cell transistor RCT. The sense amplifier SA determines the logic of the data held in the real memory cell MC based on the comparison result of the currents IC and IR, and outputs the determined logic as a read data signal RDT.

  In this embodiment, for example, when the switch SW1 is turned on and the switch SW2 is turned off, the reference memory cell RMC is connected to the ground line GND via the load LD1. When the switch SW1 is turned off and the switch SW2 is turned on, the reference memory cell RMC is connected to the ground line GND via the load LD2. Since the load amounts of the loads LD1 and LD2 are different from each other, the reference current IR flowing during the read operation is different when the setting signal SET is at the first level and at the second level.

  For example, the difference between the cell current IC and the reference current IR when reading logic 1 from the real memory cell MC is relatively small when the setting signal SET is at the first level, and when the setting signal SET is at the second level. It becomes relatively large. In other words, the logic 1 read margin of the real memory cell MC is larger when the setting signal SET is at the second level than when the setting signal SET is at the first level.

  For example, the operation test performed after the manufacture of the semiconductor memory MEM is performed in a state where the switch SW1 is turned on and the switch SW2 is turned off and the read margin is small. After the operation test, the switch SW1 is turned off, the switch SW2 is turned on, the reference current IR becomes smaller than that during the operation test, and the read margin becomes larger than that during the operation test. When the semiconductor memory MEM is shipped, the read margin is set to a large state. Therefore, after the semiconductor memory MEM is mounted on the user system and operated for a long period of time, a read margin can be secured even if the cell current IC during the read operation decreases. As a result, malfunction of the semiconductor memory MEM can be prevented, and the reliability of the semiconductor memory MEM can be ensured.

  As described above, in this embodiment, even when the electrical characteristics of the real memory cell MC are deteriorated by suppressing any increase in circuit scale by turning on one of the switches SW1 and SW2 on the side where the read margin is increased. A read margin can be secured.

  Since the value of the reference current IR is set small after the operation test, for example, even when the semiconductor memory MEM mounted in the user system is used for a long period of time and the cell current IC during the read operation decreases, the read margin Can be secured. In other words, even when the current capability of the real cell transistor CT is lowered, for example, the read operation of the real memory cell MC holding the logic 1 can be correctly executed, and the reliability of the semiconductor memory MEM can be ensured.

  During the operation test, the value of the reference current IR is set to be relatively large, so that the read margin can be reduced and the operation test can be performed under severe conditions. Thus, in this embodiment, the reference current IR of the reference cell transistor RCT can be switched by adding a minimum circuit, and the reliability of the semiconductor memory MEM operating on the user system can be ensured.

  FIG. 2 shows an example of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the semiconductor memory MEM is a nonvolatile semiconductor memory such as a flash memory. The semiconductor memory MEM may operate in synchronization with the clock or may operate asynchronously with the clock.

  The semiconductor memory MEM includes a state controller 10, an address latch circuit 12, a high voltage generation circuit 14, a negative voltage generation circuit 16, a sector switch circuit 18, a reference cell array 20, a Y decoder 22, an X decoder 24, a program circuit 26, and a data input buffer. 28, a data latch circuit 30, a data output buffer 32, a sense amplifier 34, a Y gate 36, and a memory cell array 38. The memory cell array 38 has a real cell array 40 and a reference cell array 42.

  The state controller 10 receives a write enable signal / WE, a chip enable signal / CE, an output enable signal / OE, and a write data signal WDT, and outputs a plurality of control signals for executing an access operation of the memory cell array 38. The write enable signal / WE, the chip enable signal / CE, the output enable signal / OE, and the write data signal WDT are examples of command signals for operating the semiconductor memory MEM. The access operation includes a write operation, a read operation, and an erase operation. The write operation includes a program operation and a program verify operation, and the erase operation includes an erase operation and an erase verify operation.

  The control signal from the state controller 10 is an operation of the address latch circuit 12, the high voltage generation circuit 14, the negative voltage generation circuit 16, the Y decoder 22, the program circuit 26, the data latch circuit 30, the data output buffer 32, the sense amplifier 34, and the like. To control these circuits. The control signal includes a timing signal that determines the operation timing of the circuit.

  For example, the address latch circuit 12 outputs the upper bits of the address signal AQ received at the address terminal as the row address signal RA, and outputs the lower bits of the address signal AQ as the column address signal CA. The row address signal RA is supplied to the X decoder 24, and the column address signal CA is supplied to the Y decoder 22. The memory cell MC to be accessed is selected by the row address signal RA and the column address signal CA.

  The high voltage generation circuit 14 generates, for example, a plurality of types of high voltages higher than the power supply voltage VCC and a positive internal voltage lower than the power supply voltage VCC based on the power supply voltage VCC and the ground voltage GND supplied to the power supply terminal. To do. The high voltage generation circuit 14 supplies the generated high voltage and internal voltage to the Y decoder 22 and the X decoder 24 and the like. For example, the high voltage is used as the voltage of the real word line WL during the write operation and the read operation of the memory cell MC.

  The negative voltage generation circuit 16 generates a negative voltage based on the power supply voltage VCC and the ground voltage GND, and supplies the generated negative voltage to the sector switch circuit 18. For example, the negative voltage is used as the voltage of the real word line WL during the erase operation of the memory cell MC.

  The sector switch circuit 18 has a sector switch that selectively supplies the negative voltage from the negative voltage generation circuit 16 to the area of the X decoder 24 corresponding to the sector in the real cell array 42 that executes the erase operation during the erase operation. doing. A plurality of sectors formed in the real cell array 24 is a minimum area where the erase operation is executed.

  The reference cell array 20 includes program reference memory cells for generating a program reference voltage used for a program verify operation during a write operation. The reference cell array 20 has an erase reference memory cell for generating an erase reference voltage used for an erase verify operation during an erase operation. The program reference voltage and the erase reference voltage are supplied to the sense amplifier 34 via the reference bit line PEBL.

  The Y decoder 22 generates a column selection signal CL for selecting the real bit line BL indicated by the column address signal CA, and outputs the generated column selection signal CL to the Y gate 36.

  The X decoder 24 has a word line decoder for selecting the real word line WL indicated by the row address signal RA and setting the selected real word line WL to a predetermined voltage. The X decoder 24 has a source line decoder for selecting the real source line SL indicated by the row address signal RA and setting the selected real source line SL to a predetermined voltage. Further, the X decoder 24 has a reference word line decoder for setting the reference word line RWL to a high voltage for read operation.

  For example, the real source line SL is wired for each sector. When the X decoder 24 includes a source line driver and a word line driver, the signal lines extending from the X decoder to the real cell array 42 are the real source line SL and the real word line WL. When the source line driver and the word line driver are formed in the real cell array 42, the signal line extending from the X decoder 24 to the real cell array 42 is a decode signal obtained by decoding the row address signal RA.

  The program circuit 26 is formed using electrically rewritable nonvolatile memory cells. The program circuit 26 is an example of a setting circuit that sets the setting signal SHIP to logic 1 or logic 0. The memory cells of the program circuit 26 are programmed by the state controller 10 during the test mode, for example. Then, the program circuit 26 outputs a high level or low level setting signal SHIP according to the value programmed in the memory cell.

  For example, the semiconductor memory MEM shifts from the normal operation mode to the test mode or returns from the test mode to the normal operation mode according to the logic of the command signal supplied to the state controller 10. By making it possible to execute the program of the program circuit 26 only in the test mode, it is possible to prevent the setting value of the program circuit 26 from being erroneously changed after the semiconductor memory MEM is shipped.

  In this example, as will be described later with reference to FIG. 8, the program circuit 26 is programmed to set the setting signal SHIP to the low level before the operation test of the semiconductor memory MEM is performed. , Maintained at a low level during the operation test. The program circuit 26 is programmed to set the setting signal SHIP to a high level after the operation test. For this reason, the setting signal SHIP always maintains a high level when the semiconductor memory MEM is shipped and mounted in the user system. The setting signal SHIP is used to change a reference current IR that is one of the electrical characteristics of the reference memory cell RMC.

  The program circuit 26 may be formed using a fuse circuit or the like. In this case, the program circuit 26 outputs the low level setting signal SHIP in a state where the semiconductor memory MEM is manufactured and the fuse of the fuse circuit is not cut. Then, in a test process or the like of the semiconductor memory MEM, the fuse is cut after the operation test, and thereafter, the program circuit 26 outputs a high level setting signal SHIP.

  The data input buffer 28 receives the logic of data to be written in the real memory cell MC via the data input terminal DIN, and outputs the received logic to the data latch circuit 30 as a write data signal WDT. The data input buffer 28 receives a command signal via the data input terminal DIN and outputs the received logic to the state controller 10 as a write data signal WDT. For example, the number of data input terminals DIN is 16.

  The data latch circuit 30 operates during a program operation, latches the logic of the write data signal WDT from the data input buffer 28, and supplies the latched logic to the real cell array 42 via the Y gate 36. Note that the data latch circuit 30 may operate to supply the logic of the write data signal WDT to the reference cell array 40 via the Y gate when the reference memory cell RMC is programmed.

  The sense amplifier 34 compares the cell current IC flowing through the real memory cell MC with the reference current IR flowing through the reference memory cell RMC during the read operation. The sense amplifier 34 determines the logic of the data held in the real memory cell MC based on the comparison result. For example, instead of comparing the cell current IC and the reference current IR, the sense amplifier 34 compares the voltage of each global read bit line GRBL connected to the real memory cell MC from which data is read with the voltage of the reference bit line RBL. To do. The sense amplifier 34 outputs the logic obtained by the determination to the data output buffer 32 as a read data signal RDT.

  The sense amplifier 34 also has a voltage of each global read bit line GRBL connected to a real memory cell MC to which data is written and a reference bit line PEBL connected to a program reference memory cell during a program verify operation during a write operation. Compare with the voltage of. The sense amplifier 34 determines whether or not data is written in the real memory cell MC according to the comparison result, and outputs the determination result to the state controller 10 as a logical value of the read data signal RDT. In the real memory cell MC in which data is written, the threshold voltage of the real cell transistor CT is higher than that in the erased state, and, for example, is in a logic 0 holding state.

  Further, the sense amplifier 34 is configured such that the voltage of each global read bit line GRBL connected to the real memory cell MC from which data is erased and the reference bit line connected to the erase reference memory cell during the erase verify operation during the erase operation. The voltage of PEBL is compared. The sense amplifier 34 determines whether or not the data in the real memory cell MC has been erased according to the comparison result, and outputs the determination result to the state controller 10 as a logical value of the read data signal RDT. In the real memory cell MC from which data has been erased, the threshold voltage of the real cell transistor CT is lower than that in the programmed state, and, for example, is in a logic 1 holding state. For example, the semiconductor memory MEM has the same number of sense amplifiers 34 as the number of bits of the data output terminal DOUT and the number of bits of the data input terminal DIN.

  The data output buffer 32 operates during a read operation and outputs the logic of the read data signal RDT output from the sense amplifier 34 to the data output terminal DOUT. For example, the number of data output terminals DOUT is 16.

  The Y gate 36 connects the real bit line BL to the sense amplifier SA via the global read bit line GRBL for each data output terminal DOUT in response to the column selection signal CL from the Y decoder 22 during the read operation. During the write operation, the Y gate 36 connects the output of the data latch circuit 30 to the real bit line BL via the global write bit line GWBL, for example, for each data input terminal DIN in accordance with the column selection signal from the Y decoder 22. To do.

  The real cell array 42 has a plurality of real memory cells MC arranged in a matrix. The real cell array 42 is divided into a plurality of sectors which are units of the erase operation. Each memory cell MC has a real cell transistor CT arranged between the real source line SL and the real bit line BL. For example, the real cell transistor CT has an nMOS transistor structure, and has a floating gate for accumulating electric charges (for example, electrons) and a control gate connected to the real word line WL. The real cell transistor CT may be formed using a trap gate in which charges are accumulated in a predetermined place, instead of the floating gate.

  The reference cell array 40 has a plurality of reference memory cells RMC arranged in a matrix. For example, the structure of the reference memory cell RMC is the same as that of the real memory cell MC and includes a reference cell transistor RCT. The reference cell transistor RCT has an nMOS transistor structure and is arranged between the reference source line RSL and the reference bit line RBL. In the read operation, one of the reference memory cells RMC that generates the reference current IR is connected to the sense amplifier SA via the reference bit line RBL. For example, the reference current IR flows from the precharged reference bit line RBL to the reference source line RSL via the reference cell transistor RCT.

  FIG. 3 shows an example of the real cell array 42 shown in FIG. FIG. 3 shows a partial region of the real cell array 42. In the column of the real memory cells MC arranged in the horizontal direction in FIG. 3, the control gate is connected to the common real word line WL. In the column of the real memory cells MC arranged in the vertical direction in FIG. 3, the drain is connected to the common real bit line BL, and the source is connected to the common real source line SL for each sector.

  The real source line SL is connected to global real source lines GSLL and GSLR wired in the vertical direction of FIG. 3 at a predetermined interval. For example, the global real source lines GSLL and GSLR are wired for every eight real memory cells MC arranged in the horizontal direction. The global real source lines GSLL and GSLR are formed using a metal wiring layer. The real source line SL is formed using a diffusion region formed on a semiconductor substrate such as silicon. The wiring resistance of the real source line SL is greater than the resistance of the wiring formed using the metal wiring layer. For this reason, in the figure, the parasitic resistance formed in the diffusion region in the real source line SL is shown.

  FIG. 4 shows an example of the layout of the real cell array 42 shown in FIG. A region shown by hatching in FIG. 4 indicates a diffusion region. Wirings extending in the vertical direction indicated by broken lines and one-dot chain lines in FIG. 4 indicate metal wirings. For example, metal wirings indicated by broken lines and alternate long and short dash lines have different wiring layers used. The rectangle marked with X indicates a contact for connecting the diffusion region to the metal wiring. A thick two-dot chain line indicates a region of one real memory cell MC.

  FIG. 5 shows an example of a main part of the reference cell array 40 for read operation shown in FIG. As described above, for example, one of the reference memory cells RMC formed in the reference cell array 40 operates. The reference cell transistor RCT of the reference memory cell RMC has a drain connected to the reference bit line RBL, a source connected to the reference source line RSL, and a control gate connected to the reference word line RWL. The threshold voltage of the reference cell transistor RCT is programmed to a predetermined value in a test process after manufacturing the semiconductor memory MEM.

  The reference source line RSL is connected to the global reference source line GRSLL via the resistor RL, and is connected to the global reference source line GRSLR via the resistor RH. The resistance value of the resistor RH is designed to be higher than the resistance value of the resistor RL. The resistor RL is connected to the ground line GND through the nMOS transistor NM1, and the resistor RH is connected to the ground line GND through the nMOS transistor NM2. For example, the structures and sizes of the nMOS transistors NM1 and NM2 are the same, and the electrical characteristics of the nMOS transistors NM1 and NM2 are the same.

  The resistor RL and the nMOS transistor NM1 are an example of a first load and a first switch arranged between the reference memory cell RMC and the ground line GND. The resistor RH and the nMOS transistor NM2 are an example of a second load and a second switch arranged between the reference memory cell RMC and the ground line GND. The resistors RL and RH and the nMOS transistors NM1 and NM2 operate as a load control circuit that switches the value of the reference current IR.

  The gate of the nMOS transistor NM1 receives a logic opposite to that of the setting signal SHIP via the inverter IV. The nMOS transistor NM1 is turned on when the setting signal SHIP is at the low level, and connects the reference bit line RBL to the ground line GND via the reference memory cell RMC and the resistor RL. The gate of the nMOS transistor NM2 receives the setting signal SHIP. The nMOS transistor NM2 is turned on when the setting signal SHIP is at a high level, and connects the reference bit line RBL to the ground line GND via the reference memory cell RMC and the resistor RH. As a result, the reference current IR flowing through the reference memory cell RMC during the read operation is larger in the test mode in which the setting signal SHIP is at the low level than in the normal operation mode in which the setting signal SHIP is at the high level. Details of the reference current IR will be described with reference to FIG.

  FIG. 6 shows an example of the reference cell array 40 for read operation shown in FIG. White circles shown on the wirings in the figure indicate that no contact connecting the wirings is formed. That is, since a part of the contact in the reference cell array 40 is not formed, only one of the memory cells formed in the reference cell array 40 operates as the reference memory cell RMC.

  The arrangement interval of the memory cells in the reference cell array 40 is the same as the arrangement interval of the real memory cells MC in the real cell array 42 shown in FIG. The wiring interval between the global reference source lines GSLL and GSLR is the same as the wiring interval between the global real source lines GSLL and GSLR shown in FIG. In this example, among the eight memory cells arranged in the horizontal direction in FIG. 6, the third memory cell from the left operates as the reference memory cell RMC. Other memory cells are arranged as dummy memory cells that do not pass the reference current IR.

  The bit line connected to the drain of the reference memory cell RMC functions as the reference bit line RBL. The other bit lines are wired as dummy bit lines DBL. A source line connected to the source of the reference memory cell RMC functions as a reference source line RSL. The other source lines are wired as dummy source lines DSL. The word line connected to the control gate of the reference memory cell RMC functions as the reference word line RWL. The other word lines are wired as dummy word lines DWL. For example, the dummy bit line DBL, the dummy source line DSL, and the dummy word line DWL are connected to the ground line GND.

  The source of the reference memory cell RMC is connected to the global reference source line GRSLL via two dummy memory cell formation regions, and is connected to the global reference source line GRSLR via five memory cell formation regions. For this reason, the resistance value of the wiring portion of the reference source line RSL on the global reference source line GRSLR side is higher than the resistance value of the wiring portion of the reference source line RSL on the global reference source line GRSLL side. That is, the resistors RL and RH shown in FIG. 5 are formed using the wiring resistance of the reference source line RSL using the position where the reference memory cell RMC is formed.

  The global reference source line GRSLL is connected to the drain of the nMOS transistor NM1 outside the reference cell array 40. The global reference source line GRSLR is connected to the drain of the nMOS transistor NM2 outside the reference cell array 40. By forming the nMOS transistors NM1 and NM2 operating as switches outside the reference cell array 40, dummy memory cells and reference memory cells RMC can be regularly arranged in the reference cell array 40. As a result, the deviation of the electrical characteristics of the reference memory cell RMC from the design value can be reduced, and the reference memory cell RMC that allows the reference current IR having a desired value to flow can be formed.

  A part of the reference source line RSL that connects the reference memory cell RMC to the global reference source line GRSLL is an example of a first branch line. Another part of the reference source line RSL that connects the reference memory cell RMC to the global reference source line GRSLR is an example of a second branch line.

  FIG. 7 shows an example of the layout of the reference cell array 40 in the read operation shown in FIG. The meanings of the broken line, the alternate long and short dash line, the thick alternate long and two short dashes line, the rectangle with X mark, and the shaded pattern are the same as those in FIG. The layout of the reference cell array 40 is the same as the layout of the real cell array 42 shown in FIG. 4 except that some of the contacts are not formed.

  That is, a part of the reference source line RSL is formed using a diffusion region formed along the horizontal direction of the drawing. In the reference memory cell RMC, the length of a part (diffusion region) of the reference source line RSL from the reference memory cell RMC to the global reference source line GRSLL is the reference source line RSL from the reference memory cell RMC to the global reference source line GRSLR. It is arrange | positioned in the position shorter than the length of another part (diffusion area | region). Since the resistance value per unit length of the diffusion region is higher than that of the metal wiring, the resistors RL and RH can be formed with a short diffusion region.

  FIG. 8 shows an example of a manufacturing method of the semiconductor memory MEM shown in FIG. First, in step S10, a semiconductor manufacturing process is performed, and a semiconductor memory chip (MEM in FIG. 2) is formed on a wafer such as silicon. After forming the semiconductor memory chip, the program circuit 26 shown in FIG. 2 is programmed in step S20, and the setting signal SHIP is set to the low level L. For example, the logic of the setting signal SHIP is set by accessing each semiconductor memory chip on the wafer by a test system such as an LSI tester.

  By the low level L setting signal SHIP, the source of the reference memory cell RMC is connected to the ground line GND via the resistor RL having a relatively low resistance value. When the program circuit 26 is formed of a fuse circuit, the semiconductor memory MEM is designed so that the setting signal SHIP is at the low level L in the initial state where the semiconductor memory chip is formed. For this reason, the process of step S20 is unnecessary.

  Next, in step S30, an operation test of the semiconductor memory chip is performed using a test system such as an LSI tester. At this time, the operation test is performed using the reference memory cell RMC connected to the ground line GND through the resistor RL having a relatively low resistance value, as shown in FIG. Therefore, in a read operation RD (FIG. 10) described later, the value of the reference current IR is larger than the value of the reference current IR when the setting signal SHIP is at the high level H. The larger the value of the reference current IR, the smaller the read margin of the real memory cell MC that stores logic 1, and a strict test can be performed. The read margin will be described with reference to FIG.

  In step S40, the semiconductor memory chip that has failed in the operation test is treated as a defective product. In step S50, the setting signal SHIP of the semiconductor memory chip that has passed the operation test is set to a high level H by a test system such as an LSI tester. By the high level H setting signal SHIP, the source of the reference memory cell RMC is connected to the ground line GND via the resistor RH having a relatively high resistance value, as shown in FIG. Therefore, the subsequent read operation of the semiconductor memory MEM is performed using the reference memory cell RMC connected to the ground line GND via the resistor RH having a relatively high resistance value even after the semiconductor memory MEM is shipped. Is done. That is, the subsequent read operation of the semiconductor memory MEM is executed using the reference current IR having a relatively large value.

  FIG. 9 shows an example of the threshold voltage distribution of the real memory cell MC. The threshold voltage of the real memory cell MC is the reference current in which the value of the cell current IC flows to the reference memory cell RMC, the program reference memory cell or the erase reference memory cell when the gate voltage VG is applied to the control gate of the real cell transistor CT. It is determined by whether or not it is larger than the value of

  In the read operation RD, the logic held in the real memory cell MC is determined by whether or not the threshold voltage of the real memory cell MC is higher than the voltage VGR. In the erase verify operation ERSV of the erase operation, it is confirmed that the threshold voltage of the real memory cell MC is smaller than the voltage VGE. In the program verify operation PGMV of the write operation, it is confirmed that the threshold voltage of the real memory cell MC is higher than the voltage VGP.

  FIG. 10 shows voltage setting examples in the read operation, erase operation, write operation, and various verify operations. Reference symbol FLT indicates a floating state. The symbol PW indicates the p-type well region PW which is the back gate of the cell transistors of the real memory cell MC, the reference memory cell RMC for read operation, the erase reference memory cell, and the program reference memory cell.

  The selection line includes a real word line WL (selected word line) and a real bit line BL (selected bit) connected to the real memory cell MC in the sector (selected sector) in which the program operation PGM in the read operation RD or the write operation is executed. Line). The non-selected lines are real word lines WL (non-selected word lines) other than the selected word line and real bit lines BL (non-selected bit lines) other than the selected bit line. The unselected sector indicates a sector that does not execute the read operation RD, the erase operation, and the write operation.

  In the read operation, the selected word line WL is set to the voltage VGR. The selected bit line BL is precharged to 0.6 V, for example, before the voltage VGR is supplied to the selected word line WL. The unselected word line WL and the unselected bit line BL are set to 0V, for example. In the program operation PGM, the selected word line WL is set to 9V, for example, and the selected bit line BL is set to 5V, for example. The unselected word line WL and the unselected bit line BL are set to 0V, for example.

  In the erase operation ERS in the erase operation, all the real word lines WL in the sector executing the erase operation are set to −9V, for example. All the real bit lines BL and source lines SL in the sector are set to, for example, the floating state FLT. The p-type well region PW is set to 9 V, for example. In sectors other than the sector where the erase operation ERS is executed, the real word line WL, the source line SL, and the p-type well region are set to, for example, 0 V, and the real bit line BL is set to the floating state FLT.

  The erase verify operation ERSV of the erase operation and the program verify operation PGMV of the write operation are executed in the same manner as the read operation except that the voltages of the real word lines WL are different. Note that the voltages shown in FIG. 10 are merely examples, and other voltages may be used. For example, the voltage of the real word line WL of the selected line during the write operation PGM may be 9.3V.

  FIG. 11 shows changes in the characteristics of the reference cell transistor RCT for read operation in the manufacturing method shown in FIG. Waveform (a) shows the characteristics of the reference cell transistor RCT when the setting signal SHIP is set to the low level. That is, the waveform (a) shows the characteristics of the reference cell transistor RCT during the operation test in step S30 of FIG. A waveform (b) shows the characteristics of the reference cell transistor RCT when the setting signal SHIP is set to a high level. That is, the waveform (b) shows the characteristics of the reference cell transistor RCT after the operation test of FIG.

  Waveform (c) shows the characteristics of the reference cell transistor for erasure and the characteristics of the real cell transistor CT memory cell MC having the maximum threshold voltage among the real cell transistors CT set to logic 1. Waveform (e) shows the characteristics of the reference cell transistor for writing and the characteristics of the real cell transistor CT having the minimum threshold voltage among the real cell transistors CT set to logic 0. Waveform (d) shows an example in which the characteristics of the real cell transistor CT set to logic 1 have deteriorated.

  In the read operation RD, the gate voltage VGR is applied to the control gate of the real cell transistor CT and the control gate of the reference cell transistor RCT, and the cell current IC and the reference current IR are compared. When the value of the cell current IC is larger than the value of the reference current IR, it is determined that the logic 1 (erased state) is held in the real memory cell MC. When the value of the cell current IC is smaller than the value of the reference current IR, it is determined that the logic 0 (programmed state) is held in the real memory cell MC.

  When the logic 1 of the real memory cell MC having the characteristic of the waveform (c) is read using the reference memory cell RMC having the characteristic of the waveform (a), the difference between the cell current IC and the reference current IR is the waveform (b ) Is smaller than when the reference memory cell RMC having the characteristics of Therefore, the read margin of logic 1 when the setting signal SHIP is low level (waveform (a)) is smaller than the read margin of logic 1 when the setting signal SHIP is high level (waveform (b)).

  In an actual read operation, a read voltage generated on the global read bit line GRBL shown in FIG. 2 according to the cell current IC and a reference voltage generated on the reference bit line RBL according to the reference current IR The comparison is made by the sense amplifier 34. When the read voltage is lower than the reference voltage, it is determined that the logic 1 is held in the real memory cell MC. When the read voltage is higher than the reference voltage, it is determined that logic 0 is held in the real memory cell MC.

  In the erase operation in the erase operation, the charge accumulated in the floating gate of the real cell transistor CT is released for each sector of the real cell array 42 in order to lower the threshold voltage of the real cell transistor CT. In the erase verify operation in the erase operation, the voltage VGE is applied to the control gates of the real cell transistors CT and the erase reference cell transistors. The cell current IC flowing through each real cell transistor CT in the sector is compared with the erasing reference current flowing through the erasing reference cell transistor. Then, the erase operation and the erase verify operation are repeatedly performed until the value of the cell current IC of all the real cell transistors CT becomes larger than the value of the erase reference current. As a result, the threshold voltages of all the real memory cells MC in the sector become lower than the voltage value VGE and are distributed in the region indicated by logic 1 in FIG.

  In the actual erase verify operation, the read voltage generated on the global read bit line GRBL according to the cell current IC and the erase reference voltage generated on the reference bit line PEBL according to the erase reference current are sense amplifiers 34. Are compared. When the read voltage is lower than the erase reference voltage, it is determined that the real memory cell MC is set to logic 1. When the read voltage is higher than the erase reference voltage, it is determined that the erase of the real memory cell MC is not completed.

  Note that in the real cell transistor CT having a characteristic that is easily erased, the threshold voltage may become negative due to repeated erase operations. In order to prevent this, a write-back operation and a write-back verify operation for returning a negative threshold voltage to a positive value (however, a region of logic 1) may be performed for each real cell transistor CT. .

  In the program operation in the write operation, charges are injected into the floating gate of the real cell transistor CT in order to increase the threshold voltage of the real cell transistor CT. In the program verify operation in the write operation, the voltage VGP is applied to the control gates of the real cell transistor CT and the write reference cell transistor. The cell current IC flowing through the real cell transistor CT is compared with the write reference current flowing through the reference cell transistor for writing. Then, the program operation and the program verify operation are repeatedly performed until the value of the cell current IC becomes smaller than the value of the erase reference current. That is, by the write operation, the threshold voltage of the real cell transistor CT becomes higher than the voltage value VGP and is distributed in the region indicated by logic 0 in FIG.

  In the actual program verify operation, the read voltage generated on the global read bit line GRBL according to the cell current IC and the write reference voltage generated on the reference bit line PEBL according to the write reference current are sense amplifiers 34. Are compared. When the read voltage is higher than the write reference voltage, it is determined that the real memory cell MC is set to logic 0. When the read voltage is lower than the write reference voltage, it is determined that the writing of the real memory cell MC is not completed.

  For example, the characteristics of the deteriorated real cell transistor CT shown in the waveform (d) are considered to be caused by deterioration of the film quality of the tunnel insulating film of the real cell transistor CT, charge trapping near the tunnel insulating film, or both. It is done. This type of degradation occurs when a large number of erase operations, write operations, and read operations are performed on the semiconductor memory MEM. That is, this type of deterioration is more likely to occur as the operation period of the semiconductor memory MEM mounted on the user system becomes longer after the semiconductor memory MEM is shipped. When the degradation occurs, the erase operation time and the write operation time become longer, and the current capability (transconductance gm) of the real cell transistor CT is lowered.

  When the characteristics of the real cell transistor CT deteriorate and change from the waveform (c) to the waveform (d), the value of the cell current IC during the read operation RD becomes small. If the value of the cell current IC becomes smaller than the value of the reference current IR when the gate voltage VGR is generated in the read operation RD, the sense amplifier 34 changes the logic held in the erased real memory cell MC. It is determined as “0” (program state).

  However, in this embodiment, the setting signal SHIP is set to the high level H in the semiconductor memory MEM that has passed the operation test. As a result, the reference cell transistor RCT shown in FIG. 5 is connected to the ground line GND via the resistor RH and is in a state in which characteristics are artificially deteriorated. That is, the value of the reference current IR of the reference cell transistor RCT having the characteristics of the waveform (b) is smaller than the value of the reference current IR of the reference cell transistor RCT having the characteristics of the waveform (a). Therefore, even when the read operation of the real memory cell MC in the erased state whose characteristics are deteriorated, the logic 1 can be read correctly. For a real memory cell MC whose characteristics are not degraded, the read margin can be improved.

  Even when the current capability of the real cell transistor CT holding logic 0 deteriorates due to long-term use of the semiconductor memory MEM, the cell current IC decreases and the threshold voltage increases. However, the difference between the cell current IC and the reference current IR increases due to the decrease in the cell current IC of the real cell transistor CT holding the logic 0. For this reason, when the current capability of the real cell transistor CT holding logic 0 is lowered, a sufficient read margin can be secured.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, by forming the resistors RL and RH using the existing reference source line RSL, an increase in circuit scale is suppressed, and a read margin can be secured even when the current capability of the real cell transistor CT is reduced. . As a result, the reliability of the semiconductor memory MEM can be ensured. Particularly, by forming the resistors RL and RH using diffusion regions having a resistance value per unit length higher than that of the metal wiring, the waveforms (a) and (b) shown in FIG. ) Characteristics. Furthermore, since the values of the resistors RL and RH can be set by the position of the reference memory cell RMC disposed in the reference cell array 40, the values of the resistors RL and RH can be adjusted using the existing reference cell array 40.

  FIG. 12 shows an example of a main part of a reference cell array 40A for read operation in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration excluding the reference cell array 40A is the same as that in FIG. That is, the semiconductor memory MEM in which the reference cell array 40A is formed is a nonvolatile semiconductor memory such as a flash memory. The semiconductor memory MEM may operate in synchronization with the clock or may operate asynchronously with the clock.

  Also in this embodiment, as in FIGS. 6 and 7, one of the reference memory cells RMC formed in the reference cell array 40A operates. The reference cell array 40A includes nMOS transistors NMS and NML instead of the nMOS transistors NM1 and NM2 of the reference cell array 40 shown in FIG. In the reference cell array 40A, the resistors RL and RH are deleted from the reference cell array 40 shown in FIG.

  Actually, the diffusion resistance of the reference source line RSL cannot be deleted. For this reason, in this embodiment, the reference memory cell RMC is arranged at the center (for example, the fourth or fifth from the left) in FIG. Alternatively, a metal wiring connected to the reference source line RSL is formed on the diffusion region of the reference source line RSL. Alternatively, a silicide wiring is formed along the reference word line RWL on the diffusion region of the reference source line RSL in order to reduce the resistance value of the reference source line RSL. Thereby, the resistance components RL and RH shown in FIG. 5 can be made equal to each other, and it can be considered that the resistances RL and RH are deleted. The other configuration of the reference cell array 40A is the same as that of the reference cell array 40.

  The gate width of the nMOS transistor NMS is designed to be larger than the gate width of the nMOS transistor NML. The nMOS transistors NMS and NML have the same structure except for the gate width. As a result, the on-resistance of the nMOS transistor NML is lower than the on-resistance of the nMOS transistor NMS. The value of the reference current IR when the nMOS transistor NML is on is larger than the value of the reference current IR when the nMOS transistor NMS is on.

  In this embodiment, the operation test shown in FIG. 8 is performed using an nMOS transistor NMS having a small gate width. After the operation test, an nMOS transistor NML having a large gate width is used. Thereby, the characteristic of the reference cell transistor RCT can be the waveform (a) shown in FIG. 11 during the operation test, and the waveform (b) shown in FIG. 11 after the operation test. Therefore, even when the current capability of the real cell transistor CT is reduced due to the long-term use of the semiconductor memory MEM, a read margin of logic 1 can be secured, and the reliability of the semiconductor memory MEM can be secured.

  Note that the reference current IR of the reference memory cell RMC may be switched using both the nMOS transistors NMS and NML having different gate widths and the diffusion resistance of the reference source line RSL. That is, the nMOS transistor NM1 shown in FIG. 5 may be replaced with the nMOS transistor NMS, and the nMOS transistor NM2 may be replaced with the nMOS transistor NML.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, by switching the reference current of the reference memory cell RMC using the on-resistances of the nMOS transistors NMS and NML, an increase in circuit scale can be suppressed and a read margin can be secured. As a result, the reliability of the semiconductor memory MEM can be ensured.

  FIG. 13 shows an example of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The semiconductor memory MEM of this embodiment has an X decoder 24B and a reference cell array 40B instead of the X decoder 24 and the reference cell array 40 shown in FIG. The setting signal SHIP is supplied to the X decoder 24B.

  Other configurations of the semiconductor memory MEM are the same as those in FIG. That is, the semiconductor memory MEM is a non-volatile semiconductor memory such as a flash memory. The semiconductor memory MEM may operate in synchronization with the clock or may operate asynchronously with the clock.

  FIG. 14 shows an example of a main part of the X decoder 24B shown in FIG. FIG. 14 shows a part of the reference word line decoder for setting the reference word line RWL to the high voltage VGRR. In addition to the one shown in FIG. 14, the X decoder 24B has a word line decoder for selecting a real word line WL according to the row address signal RA and setting the selected real word line WL to a predetermined voltage. Yes. Further, the X decoder 24B has a source line decoder for selecting the real source line SL indicated by the row address signal RA and setting the selected real source line SL to a predetermined voltage in addition to that shown in FIG. doing.

  The X decoder 24B includes a voltage dividing circuit VDIV, pMOS transistors PM1 and PM2, and an inverter IV. The voltage dividing circuit VDIV divides the high voltage VGR for read operation supplied from the high voltage generation circuit 14 shown in FIG. 13 and generates a high voltage VGR1 lower than the high voltage VGR. The pMOS transistors PM1 and PM2 function as switches that are turned on and turned off in response to the setting signal SHIP. As shown in FIG. 8, the setting signal SHIP is set to a low level during the operation test of the semiconductor memory MEM, and is set to a high level after the operation test.

  The gate of the pMOS transistor PM1 receives a logic opposite to that of the setting signal SHIP via the inverter IV. The pMOS transistor PM1 is turned on when the setting signal SHIP is at a high level, and connects the high voltage line VGR1 to a high voltage line VGRR for supplying a high voltage to the reference word line RWL. The gate of the pMOS transistor PM2 receives the setting signal SHIP. The pMOS transistor PM2 is turned on when the setting signal SHIP is at a low level, and connects the high voltage line VGR to the high voltage line VGRR.

  As a result, during the read operation of the operation test (SHIP = L) of the semiconductor memory MEM, the common high voltage VGR is supplied as a read voltage to the real word line WL and the reference word line RWL. During the read operation after the operation test (SHIP = H), the high voltage VGR is supplied as a read voltage to the real word line WL, and the high voltage VGR1 is supplied as the voltage VGRR of the reference word line RWL.

  FIG. 15 shows an example of a main part of the reference cell array 40B for read operation shown in FIG. Reference cell array 40B is formed by removing nMOS transistors NM1, NM2 and inverter IV from the configurations of FIGS. That is, in the reference cell array 40B, one of the reference memory cells RMC is connected to the reference bit line RBL and the reference source line RSL. For example, the reference source line RSL is directly connected to the ground line GND via the resistors RL and RH which are diffusion resistors of the reference source line RSL shown in FIG. Note that, as described with reference to FIG. 12, the resistors RL and RH may be made equal to each other.

  In this embodiment, in the read operation of the operation test, the voltage VGRR having the same value as the voltage VGR is applied to the control gate (that is, the reference word line RWL) of the reference cell transistor RCT. In the read operation after the operation test, a voltage VGRR (VGR1 in FIG. 14) lower than the voltage VGR is applied to the control gate of the reference cell transistor RCT. Thus, the value of the reference current IR that flows through the reference cell transistor RCT during the read operation after the operation test is smaller than the value of the reference current IR that flows through the reference cell transistor RCT during the read operation of the operation test. Therefore, as in the above-described embodiment, the read margin during the read operation after the operation test can be increased. As a result, even when the current capability of the real cell transistor CT decreases due to the long-term use of the semiconductor memory MEM, a read margin can be ensured and the reliability of the semiconductor memory MEM can be ensured.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, in this embodiment, the voltage VGRR supplied to the reference word line RWL is set to the voltage VGR supplied to the real word line WL or to a voltage VGR1 lower than the voltage VGR according to the level of the setting signal SHIP. Is set. For example, the setting signal SHIP is set to a low level during the operation test and is set to a high level after the operation test. As a result, as in the above-described embodiment, an increase in circuit scale is suppressed, and even when the electrical characteristics of the real memory cell deteriorate, a read margin can be ensured and the reliability of the semiconductor memory MEM can be ensured.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A non-volatile real memory cell into which data is written;
A reference memory cell that generates a reference current during a read operation of reading data from the real memory cell;
A first load and a first switch arranged in series between the reference memory cell and the power supply line; a second load and a second switch arranged in series between the reference memory cell and the power supply line; The first switch is turned on when the setting signal is at the first level, and the second switch is turned on when the setting signal is at the second level, and the first load and the second load are Load control circuits with different load amounts, and
A semiconductor memory comprising: a sense amplifier that compares a cell current flowing in the real memory cell and the reference current during the read operation.
(Appendix 2)
A reference source line connected to the reference memory cell and having a first branch line and a second branch line branched from each other;
The first load is formed including a resistance of the first branch line,
The semiconductor memory according to appendix 1, wherein the second load includes a resistance of the second branch line.
(Appendix 3)
A plurality of first memory cells arranged in one direction, wherein one of the first memory cells includes a reference cell array that operates as the reference memory cell;
A part of the reference source line is formed using a diffusion region formed along the one direction,
The first branch line includes a part of the reference source line formed by the diffusion region extending from the reference memory cell to one end in the one direction,
The second branch line includes another part of the reference source line formed by the diffusion region extending from the reference memory cell to the other end in the one direction,
The semiconductor memory according to claim 2, wherein the length of the part of the reference source line is different from the length of the other part of the source line.
(Appendix 4)
A first global reference source line and a second global reference source line disposed at both ends of the one direction in the reference cell array and connected to the diffusion region;
The first switch is connected to the first global reference source line outside the reference cell array,
The semiconductor memory according to claim 3, wherein the second switch is connected to the second global reference source line outside the reference cell array.
(Appendix 5)
The first switch and the second switch are each formed of a transistor,
Each of said 1st load and said 2nd load is formed including the drain and source | sauce resistance of each said transistor. The semiconductor memory of any one of the additional statement 1 thru | or the additional statement 4 characterized by the above-mentioned.
(Appendix 6)
A non-volatile real memory cell into which data is written;
A reference memory cell that generates a reference current during a read operation of reading data from the real memory cell;
A real word line connected to the real memory cell and supplied with a first voltage during the read operation;
A reference word line connected to the reference memory cell and supplied with a second voltage during the read operation;
When the setting signal is at the first level, the second voltage having the same value as the first voltage is supplied to the reference word line, and when the setting signal is at the second level, the reference word line is supplied from the first voltage. A word control circuit for supplying the low second voltage;
A semiconductor memory, comprising: a sense amplifier that compares a current flowing through the real memory cell and the reference current during the read operation.
(Appendix 7)
7. The semiconductor memory according to claim 1, further comprising: a program circuit that outputs the setting signal having the first level or the second level according to a programmed state. .

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  DESCRIPTION OF SYMBOLS 10 State controller; 12 Address latch circuit; 14 High voltage generation circuit; 16 Negative voltage generation circuit; 18 Sector switch circuit; 20 Reference cell array; 22 Y decoder; Program circuit; 28 Data input buffer; 30 Data latch circuit; 32 Data output buffer; 34 Sense amplifier; 36 Y gate; 38 Memory cell array; 40, 40A, 40B Reference cell array; BL: Real bit line; CT: Real cell transistor; GRBL: Global read bit line; GWBL: Global write bit line; MC: Real memory cell; MEM: Semiconductor memory; Riffa RBL: Reference bit line; RH, RL: Resistance; RCT: Reference cell transistor; RMC: Reference memory cell; RSL: Reference source line; RWL: Reference word line; SHIP: Setting signal; VDIV: Voltage divider circuit; WL: Real word line

Claims (5)

A non-volatile real memory cell into which data is written;
A reference memory cell that generates a reference current during a read operation of reading data from the real memory cell;
A first load and a first switch arranged in series between the reference memory cell and the power supply line; a second load and a second switch arranged in series between the reference memory cell and the power supply line; The first switch is turned on when the setting signal is at the first level, and the second switch is turned on when the setting signal is at the second level, and the first load and the second load are Load control circuits with different load amounts, and
A semiconductor memory comprising: a sense amplifier that compares a cell current flowing in the real memory cell and the reference current during the read operation. A reference source line connected to the reference memory cell and having a first branch line and a second branch line branched from each other;
The first load is formed including a resistance of the first branch line,
The semiconductor memory according to claim 1, wherein the second load is formed including a resistance of the second branch line. A plurality of first memory cells arranged in one direction, wherein one of the first memory cells includes a reference cell array that operates as the reference memory cell;
A part of the reference source line is formed using a diffusion region formed along the one direction,
The first branch line includes a part of the reference source line formed by the diffusion region extending from the reference memory cell to one end in the one direction,
The second branch line includes another part of the reference source line formed by the diffusion region extending from the reference memory cell to the other end in the one direction,
3. The semiconductor memory according to claim 2, wherein the length of the part of the reference source line is different from the length of the another part of the source line. A first global reference source line and a second global reference source line disposed at both ends of the one direction in the reference cell array and connected to the diffusion region;
The first switch is connected to the first global reference source line outside the reference cell array,
The semiconductor memory according to claim 3, wherein the second switch is connected to the second global reference source line outside the reference cell array. A non-volatile real memory cell into which data is written;
A reference memory cell that generates a reference current during a read operation of reading data from the real memory cell;
A real word line connected to the real memory cell and supplied with a first voltage during the read operation;
A reference word line connected to the reference memory cell and supplied with a second voltage during the read operation;
When the setting signal is at the first level, the second voltage having the same value as the first voltage is supplied to the reference word line, and when the setting signal is at the second level, the reference word line is supplied from the first voltage. A word control circuit for supplying the low second voltage;
A semiconductor memory, comprising: a sense amplifier that compares a current flowing through the real memory cell and the reference current during the read operation.

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