JP2013041642A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a nonvolatile memory, which allows high-speed programming even for a charge trap type.SOLUTION: In a semiconductor device, a memory array is arranged in a matrix and includes a plurality of memory cells MC0 and MC1 each of which stores data by change in a threshold voltage level. A verification circuit 50 determines whether a threshold voltage has reached a program verification voltage for each program operation that is executed for a plurality of times for memory cells for programming. A current adjustment circuit 52 passes a program current of a first current value to memory cells, out of the plurality of memory cells for programming, for which it is determined by the verification circuit 50 that the threshold voltage has not reached the program verification voltage; and passes a program current of a second current value, which is smaller than the first current value, to memory cells for which it is determined that the threshold voltage has reached the program verification voltage.

Description

  The present invention relates to a semiconductor device including an electrically rewritable nonvolatile memory.

  In a microcomputer incorporating a non-volatile memory such as a flash memory, an increase in program (write) time has become a problem as the capacity of the non-volatile memory increases. In particular, in a writing method using hot electron injection such as a NOR flash memory, the current supply capability of the charge pump circuit is limited, so that the number of cells that can be simultaneously written is limited. This is one of the factors that increase the program time.

  Japanese Unexamined Patent Application Publication No. 2004-022112 (Patent Document 1) discloses a nonvolatile semiconductor memory device that enables high-speed page programming. In the nonvolatile memory device described in this document, one page of data is written for each of a plurality of addresses in the page. At this time, with respect to the address that has passed the determination in the verify read operation, the write operation and the verify read operation are skipped to increase the speed.

  Japanese Patent Application Laid-Open No. 09-307082 (Patent Document 2) discloses bit-by-bit verification as a technique for narrowing the threshold distribution width of memory cells. Although the purpose is different from the above document, it is technically similar. Specifically, the writing time is divided into short times, and writing and verifying are performed for each divided time. If it is determined that the threshold is sufficiently increased by the verify operation, writing is not performed from the next cycle.

  Japanese Laid-Open Patent Publication No. 09-307082 (Patent Document 2) further discloses a method of performing the writing operation in two steps. Specifically, a loose first determination level that is equal to or higher than the read setting level but lower than the originally required verify read determination level is set, and the first determination level is set based on the first determination level. Is written. Next, a second write operation is performed based on the second determination level that is originally required.

  Japanese Patent Publication No. 2007-520029 (Patent Document 3) also discloses a technique for performing writing in two stages of a coarse programming process and a fine programming process, as in the above-mentioned patent document. In the technique of this document, while verifying memory cells in a coarse programming process, verifying is performed efficiently by verifying other memory cells in a fine programming process.

  Each of the above references deals with the case where 1-bit data is stored in each memory cell, but by associating data with four threshold voltage distributions having different voltage ranges, 2-bit data can also be stored (see, for example, Japanese Patent Application Laid-Open No. 2007-141393 (Patent Document 4)).

  As is well known, the structure of a memory cell of a nonvolatile memory includes a floating gate type and a charge trap type. As a typical example of the charge trapping type, a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type using a silicon nitride film is known (for example, JP 2010-272156 A (Patent Document 5)). 2008-251096 gazette (refer patent document 6)).

JP 2004-022112 A Japanese Patent Laid-Open No. 09-307082 Special table 2007-520029 gazette JP 2007-141393 A JP 2010-272156 A JP 2008-251096 A

  The technique described in Japanese Patent Application Laid-Open No. 2004-022112 (Patent Document 1) is considered to be effective to some extent for speeding up the programming process of the floating gate type nonvolatile memory. However, this technique cannot be applied to a charge trapping nonvolatile memory using a silicon nitride film or the like. This is because the charge trapped in the silicon nitride film has the property of detrapping over time, but the detrapping rate is particularly large in a short time after the charge injection. Therefore, if the application of a subsequent program pulse is stopped for a memory cell that has been determined that the threshold voltage has reached the program verify voltage during program verification, the threshold voltage will drop below the program verify voltage.

  Such a problem of lowering the threshold voltage due to detrapping immediately after the application of the program pulse is a problem that may occur in the floating gate type even though it is not as significant as in the charge trapping type.

  Accordingly, an object of the present invention is to provide a semiconductor device including a nonvolatile memory that can be programmed at high speed even in the case of a charge trapping type.

  A semiconductor device according to an embodiment of the present invention includes a memory array, a verify circuit, and a current adjustment circuit. The memory array includes a plurality of memory cells arranged in a matrix and each storing data according to a level change of a threshold voltage. Each memory cell has first and second conduction electrodes and a gate electrode. The threshold voltage of each memory cell reaches a predetermined program verify voltage by causing a program current to flow between the first and second conductive electrodes and applying a program voltage to the gate electrode a plurality of times. . The verify circuit determines whether or not the threshold voltage has reached the program verify voltage for each program operation executed a plurality of times on the memory cell to be programmed. The current adjustment circuit adjusts the magnitude of the program current. The current adjustment circuit supplies a program current having a first current value to a memory cell in which the threshold voltage is determined not to reach the program verify voltage by the verify circuit among the plurality of memory cells to be programmed. A program current having a second current value smaller than the first current value is supplied to the memory cell determined to have reached the program verify voltage.

  According to the above embodiment, the threshold voltage of the threshold voltage is caused to flow by passing a program current having a second current value smaller than the first current value to the memory cell determined to have reached the program verify voltage. Thus, the program can be programmed at a higher speed than before until the threshold voltage becomes equal to or higher than a predetermined program verify voltage.

1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the structure of the memory cell MC. It is a figure which shows the memory | storage operation | movement of memory cell MC. FIG. 2 is a block diagram showing an overall configuration of the nonvolatile memory device 4 of FIG. 1. FIG. 5 is a plan view schematically showing the configuration of the memory array 30 of FIG. 4. FIG. 6 is a circuit diagram showing a configuration of a memory block MB0 of FIG. 7 is a diagram showing a portion related to a data program in the column system selection circuit 39 of FIGS. 5 and 6. FIG. It is a figure which shows the threshold voltage distribution at the time of an erase state and a program state. It is the figure which showed the table | surface which put together the electric current which flows into the memory cell MC at the time of a program pulse application operation. It is a timing diagram which shows roughly the voltage waveform applied to a memory gate at the time of programming. 4 is a flowchart showing a program procedure in the case of the first embodiment. It is the figure which showed the part relevant to the program of data among the non-volatile memory devices by Embodiment 2 of this invention. FIG. 13 is a diagram for explaining a program procedure by the nonvolatile memory device of FIG. 12. 5 is a timing chart showing voltage waveforms applied to a source line and a bit line in a normal state where simultaneous selection of memory blocks is not performed. 5 is a timing chart showing voltage waveforms applied to a source line and a bit line in a simultaneous selection state of memory blocks. 10 is a flowchart showing a program procedure in the case of the second embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
[Configuration of semiconductor device]
1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1 shows a microcomputer chip 1 as an example of a semiconductor device. The microcomputer chip 1 includes a CPU (Central Processing Unit) 2, a RAM (Random Access Memory) 3, a nonvolatile memory device 4, a peripheral circuit 5, an interface circuit 7, and a data bus 8 that interconnects them. And a power supply circuit 6.

  The power supply circuit 6 generates an internal power supply voltage VDD based on the external power supply voltage VCC received from the outside of the microcomputer chip 1. The internal power supply voltage VDD is supplied to each part of the microcomputer chip 1 (in FIG. 1, only supply to the nonvolatile memory device 4 is representatively shown).

  The nonvolatile memory device 4 is a semiconductor storage device such as an EEPROM (Electrically Erasable and Programmable Read-only Memory) or a flash memory. Each memory cell of these semiconductor memory devices has a charge storage portion between the gate electrode and the channel layer. The threshold voltage of the memory cell is changed by the charge stored in the charge storage unit, and thus information of “1” and “0” can be stored. Generally, a floating gate (floating gate) formed of a polycrystalline silicon film, a silicon nitride film, or the like is used as the charge storage portion. The silicon nitride film accumulates electric charges by trap levels that are dispersed in the film. In this embodiment, an example in which a silicon nitride film is used as a charge storage portion will be described. Next, a specific configuration of the memory cell will be described in more detail.

[Configuration of memory cell]
FIG. 2 is a diagram showing a configuration of the memory cell MC. FIG. 2A schematically shows a cross-sectional view of the memory cell MC, and FIG. 2B shows a circuit diagram symbol of the memory cell MC. Parts corresponding to those in FIGS. 2A and 2B are denoted by the same reference numerals.

  2A and 2B, memory cell MC includes a control gate 21, a silicon nitride film 22, a memory gate 23, a source 24, and a drain 25. The control gate 21 is formed on the surface of the P-type silicon substrate 20 via an insulating layer (not shown). The silicon nitride film 22 is formed on the sidewall of the control gate 21 as an ONO (Oxide-Nitride-Oxide) film made of a silicon oxide film (not shown), a silicon nitride film 22, and a silicon oxide film (not shown). . A memory gate 23 having a sidewall structure is formed on the ONO film. The source 24 and the drain 25 are formed by implanting N-type impurities on both sides of the gates 21 and 23, respectively.

  A memory array in which a plurality of memory cells MC are arranged is provided with a memory gate line MGL, a control gate line CGL, and a source line SL, each extending in the row direction X corresponding to the memory cell row. Bit lines BL extending in the column direction Y are provided corresponding to the memory cell columns. In each memory cell MC, the memory gate 23 is connected to the corresponding memory gate line MGL. The control gate 21 is connected to the corresponding control gate line CGL. Source 24 is connected to corresponding source line SL. The drain 25 is connected to the corresponding bit line BL.

[Memory cell storage operation]
A unique address is assigned to each memory cell MC, and each memory cell MC stores 1-bit data according to a threshold voltage level change.

  FIG. 3 is a diagram showing a storage operation of the memory cell MC. FIG. 3A shows the state during the program pulse application operation, FIG. 3B shows the state during the erase pulse application operation, and FIG. 3C shows the state during the read operation. FIG. 3D shows the state during the program verify operation.

  Referring to FIG. 3A, during the program pulse application operation, a selected voltage (referred to as “program voltage”) between 6.4 and 11 V is applied to memory gate 23, and control gate 21 is applied to control gate 21. 1.0 V is applied, a selected voltage between 3.2 and 7.0 V is applied to the source 24, and 0.8 V is applied to the drain 25. Thus, hot electrons are injected into the silicon nitride film 22 by the source side injection (SSI) method, and the threshold voltage of the memory cell MC is increased. At this time, the current flowing between the source and the drain is referred to as “program current”. The program pulse application operation is repeated until the threshold voltage of the memory cell MC becomes higher than a predetermined program verify voltage PV. For example, “1” of data “0” and “1” is stored in the programmed memory cell MC (“0” may be determined, but “1” is used in this specification). Note that the voltage of the memory gate 23 is set to a high level on the positive side when the threshold voltage of the memory cell MC is difficult to increase. The voltage of the source 24 is set according to the voltage of the memory gate 23 so that dielectric breakdown does not occur.

  Referring to FIG. 3B, during the erase pulse application operation, a voltage selected between −3.3 and −8V is applied to memory gate 23, 0V is applied to control gate 21, and the source The voltage 24 is applied with 3.2 to 7.0 V, and the drain 25 is set in the OPEN state. Accordingly, hot holes are injected into the silicon nitride film 22 by a band-to-band tunneling (BTBT) method, and the threshold voltage of the memory cell MC is lowered. The erase pulse application operation is repeated until the threshold voltage of the memory cell MC becomes lower than a predetermined erase verify voltage EV. For example, “0” of data “0” and “1” is stored in the erased memory cell MC. Note that the voltage of the memory gate 23 is set to a high level on the negative side when the threshold voltage of the memory cell MC is difficult to decrease. The voltage of the source 24 is set according to the voltage of the memory gate 23 so that dielectric breakdown does not occur.

  Referring to FIG. 3C, in the read operation, 0 V is applied to memory gate 23 and source 24, 1.5 V is applied to control gate 21 and drain 25, and flows between drain 25 and source 24. It is determined whether the current Id is larger than the threshold current. When the current Id is larger than the threshold current, the threshold voltage of the memory cell MC is low, so that the storage data of the memory cell MC is determined to be “0”. Conversely, when the current Id is smaller than the threshold current, the threshold voltage of the memory cell MC is high, so that the storage data of the memory cell MC is determined to be “1”.

  Referring to FIG. 3D, in the program verify operation, program verify voltage PV is applied to memory gate 23, 0V is applied to source 24, 1.5V is applied to control gate 21 and drain 25, It is determined whether or not the current Id flowing between the drain 25 and the source 24 is larger than the threshold current. When the current Id is larger than the threshold current, the threshold voltage of the memory cell MC is lower than the program verify voltage PV, so that it is determined that the programming is not completed. On the contrary, when the current Id is smaller than the threshold current, the threshold voltage of the memory cell MC is higher than the program verify voltage PV, so that it is determined that the programming is completed.

  In the erase verify operation, in FIG. 3D, the erase verify voltage EV is applied to the memory gate 23 instead of the program verify voltage PV. The voltage applied to other portions is the same as that in FIG. When the current Id flowing between the drain 25 and the source 24 is larger than the threshold current, the threshold voltage of the memory cell MC is lower than the erase verify voltage EV, so that it is determined that the erase has been completed. On the other hand, when the current Id is smaller than the threshold current, the threshold voltage of the memory cell MC is higher than the erase verify voltage EV, so that it is determined that the erase is not completed.

[Configuration of non-volatile memory device]
FIG. 4 is a block diagram showing the overall configuration of the nonvolatile memory device 4 of FIG. Referring to FIG. 4, the nonvolatile memory device 4 includes a memory array 30, an input / output circuit 31, a word line decoder unit 35, a control gate line driver unit 36, a memory gate line driver unit 37, a source line driver unit 38, a column. A system selection circuit 39, a control circuit 32, a power supply circuit 33, and a power supply switching circuit 34 are included.

  A large number of memory cells MC described in FIG. 2 are arranged in a matrix in the memory array 30. In this embodiment, the bit line includes a plurality of main bit lines BL and sub-bit lines SBL. Each main bit line BL (corresponding to the main bit lines BL0 to BL2047 in FIG. 5 and corresponding to the main bit lines BL0 to BL255 in FIG. 6) has a switching transistor QC (transistors QC0A, QC0B,. , QC255A, QC255B), a plurality of subbit lines SBL (corresponding to subbit lines BL0A, BL0B,..., BL255A, BL255B in FIG. 6) are connected. The drain 25 of the memory cell MC is connected to the corresponding sub bit line SBL.

  Input / output circuit 31 receives a command, an address, write data, and the like from the outside of nonvolatile memory device 4 (for example, CPU 2 in FIG. 1) and outputs read data to the outside.

  The word line decoder unit 35 outputs a signal designating the selected row of the memory array by decoding the row address signal received via the input / output circuit 31.

  The control gate line driver unit 36 supplies a predetermined operating voltage received via the power supply switching circuit 34 to the control gate line CGL corresponding to the selected row designated by the word line decoder unit 35.

  The memory gate line driver unit 37 supplies a predetermined operating voltage received via the power supply switching circuit 34 to the memory gate line MGL corresponding to the selected row designated by the word line decoder unit 35.

  The source line driver unit 38 supplies a ground voltage or a predetermined operating voltage received via the power supply switching circuit 34 to the source line SL. The source line driver section 38 is connected to a source line SL (corresponding to SL0_0 to SL0_15 in FIG. 6) via a switching transistor QA (corresponding to QA0 to QA31 in FIG. 5).

  Column system selection circuit 39 is provided with a column decoder circuit for decoding a column address signal received via input / output circuit 31. The column system selection circuit 39 receives a predetermined voltage received via the ground voltage or the power supply switching circuit 34 on the selected bit line BL (bit line BL corresponding to the selected column) based on the decoding result by the column decoder circuit. Supply operating voltage.

  The column system selection circuit 39 further includes a read sense amplifier (SA) circuit that detects a current flowing through the memory cell MC to be read through the selected bit line BL, and a selected bit line BL. And a verifying sense amplifier circuit for detecting a current flowing through the memory cell MC to be programmed via the.

  The control circuit 32 executes each operation mode such as a program pulse application operation, an erase pulse application operation, a read operation, a program verify operation, and an erase verify operation in accordance with a command from a host such as the CPU 2 in FIG. The control circuit 32 further controls the power supply circuit 33 and the power supply switching circuit 34 so that the operation voltage necessary for each operation mode is supplied to each driver unit.

  The power supply circuit 33 includes a charge pump circuit that generates operation voltages of various magnitudes according to each operation mode by boosting or stepping down the internal power supply voltage VDD generated by the power supply circuit 6 of FIG. The power supply switching circuit 34 is a group of switches (also referred to as a distributor) that receives operating voltages of various magnitudes generated by the power supply circuit 33 and switches the magnitude of the operating voltage to be supplied and the supply destination in accordance with each operation mode. .

[Configuration of memory array]
FIG. 5 is a plan view schematically showing the configuration of the memory array 30 of FIG. FIG. 5 also shows each driver section around the memory array 30.

  In the memory array 30 of FIG. 5, an example in which the memory cells MC of FIG. 2 are arranged in 64 rows and 4096 columns is shown as an example. Memory array 30 is divided into 32 memory blocks MB0 to MB31 each consisting of memory cells MC of 16 rows and 512 columns. Therefore, memory blocks MB0 to MB31 are arranged in 4 rows and 8 columns in memory array 30 (in FIG. 5, eight memory blocks are representatively shown for ease of illustration).

  The control gate line driver unit 36 is disposed in the center of the memory array 30 in the X direction, and drivers CGD0A to CGD63A for driving the control gate lines CGL0A to CGL63A on the left side of the figure, respectively, and the control gate lines CGL0B to CGL63B on the right side of the figure. Including drivers CGD0B to CGD63B, respectively. Control gate lines CGL0A to CGL15A are used in common in memory blocks MB0 to MB3, control gate lines CGL16A to CGL31A are used in common in memory blocks MB8 to MB11, and control gate lines CGL32A to CGL47A are used in common in memory blocks MB16 to MB19. The control gate lines CGL48A to CGL63A are commonly used in the memory blocks MB24 to MB27. Similarly, control gate lines CGL0B to CGL15B are used in common in memory blocks MB4 to MB7, control gate lines CGL16B to CGL31B are used in common in memory blocks MB12 to MB15, and control gate lines CGL32B to CGL47B are used in memory blocks MB20 to MB20. MB23 is commonly used, and control gate lines CGL48B to CGL63B are commonly used in memory blocks MB28 to MB31.

  Memory gate line driver unit 37 includes drivers MGD0 to MGD15. The driver MGDi (where 0 ≦ i ≦ 15) drives the memory gate lines MGLi, MGLi + 16, MGLi + 32, and MGLi + 48. The memory gate lines MGL0 to MGL15 are commonly used in the memory blocks MB0 to MB7, the memory gate lines MGL16 to MGL31 are commonly used in the memory blocks MB8 to MB15, and the memory gate lines MGL32 to MGL47 are commonly used in the memory blocks MB16 to MB23. The memory gate lines MGL48 to MGL63 are commonly used in the memory blocks MB24 to MB31.

  The source line driver unit 38 (38A, 38B) includes drivers SLD0 to SLD31 that drive the source lines of the memory blocks MB0 to MB31, respectively. Switching NMOS (Negative-channel Metal Oxide Semiconductor) transistors QA0 to QA31 are provided corresponding to the drivers SLD0 to SLD31, respectively. Each NMOS transistor QA is inserted in a transmission path between the corresponding driver SLD and the memory block MB corresponding to the driver. The NMOS transistors QA0 to QA31 are switched on or off in accordance with a signal output from the buffer SSD.

  From the column system selection circuit 39, main bit lines BL0 to BL2047 are drawn out. One main bit line BL is provided for every two columns of the memory array 30.

  FIG. 6 is a circuit diagram showing a configuration of memory block MB0 in FIG. Since the other memory blocks MB1 to MB31 have the same configuration, the configuration of the memory block MB0 will be representatively described below, and in particular, the source lines and sub-bit lines provided in the memory block MB0 will be described.

  Referring to FIG. 6, source lines SL0_0 to SL0_15 are provided corresponding to the memory cell rows of memory block MB0, respectively. One end of each of the source lines SL0_0 to SL0_15 is connected to a wiring SL0_bus extending in the Y direction. One end of the wiring SL0_bus is connected to the source line driver SLD0 via the NMOS transistor QA0 and to the ground node VSS via the switching NMOS transistor QB0. When a predetermined positive operating voltage is applied to the source of each memory cell MC, the NMOS transistor QA0 is turned on and the NMOS transistor QB0 is turned off. When a ground voltage is applied to the source of each memory cell MC, the NMOS transistor QA0 is turned off and the NMOS transistor QB0 is turned on.

  Sub bit lines BL0A, BL0B, BL1A, BL1B,..., BL255A, BL255B are provided corresponding to the memory cell columns of memory block MB0, respectively. One ends of the sub bit lines BL0A and BL0B are connected to the main bit line BL0 via switching NMOS transistors QC0A and QC0B, respectively. The other ends of the sub bit lines BL0A and BL0B are connected to the power supply node VDD via PMOS (Positive-channel Metal Oxide Semiconductor) transistors QD0A and QD0B. The PMOS transistors QD0A and QD0B are used as constant current sources when a predetermined bias voltage is applied to the gates. The same applies to the other sub-bit lines BLA and BLB. One end is connected to the corresponding main bit line BL via a switching transistor, and the other end is connected to the power supply node VDD via a constant current source PMOS transistor. Connected.

[Configuration of column selection circuit]
FIG. 7 is a diagram showing a portion related to the data program in the column system selection circuit 39 of FIGS.

  In FIG. 7, in the memory block MB representing one of the memory blocks MB0 to MB31 in FIG. 5, the memory cells MC0, MC0 connected to the sub-bit lines BLA, BLB of the selected column and the source line SL of the selected row. MC1 is shown.

  As already described, since the data is written by the SSI (Source Side Injection) method, the high voltage created by the charge pump 33 is connected to the source line SL via the distributor 41 and the source line driver SLD. It is supplied to the memory cells MC0 and MC1.

  One ends of the sub bit lines BLA and BLB are connected to the power supply node VDD via the PMOS transistors QDA and QDB. As already described, the PMOS transistors QDA and QDB are used as constant current sources that cause the current I1 to flow when a predetermined voltage is applied to their gates.

  The other ends of the sub bit lines BLA and BLB are connected to the main bit line BL via switching NMOS transistors QCA and QCB, respectively. The NMOS transistors QCA and QCB are controlled so as to be selectively turned on. In the case of FIG. 7, it is assumed that the NMOS transistor QCA is on and the NMOS transistor QCB is off. As a result, the program current I2 flows in the memory cell MC0 connected to the sub bit line BLA, but the program current does not flow in the memory cell MC1 connected to the sub bit line BLB. That is, the memory cell MC0 is selected as a program target.

  The main bit line BL is further connected to the column system selection circuit 39. The column system selection circuit 39 includes a selector 51, a verify sense amplifier 50, and a current adjustment circuit 52 as components related to the data program.

  The selector 51 and the verify sense amplifier 50 are provided for each of the plurality of main bit lines BL (for example, every 16 main bit lines BL). In this case, the verify sense amplifier 50 is connected to the main bit line BL selected by the selector 51. During the verify operation, the source line is set to the ground voltage, and the drain of the memory cell to be programmed is connected to the verify sense amplifier 50 via the sub bit line BLA and the main bit line BL in order.

  The verify sense amplifier 50 determines the pass / fail of the verify depending on whether or not the connected memory cell passes a current. Normally, in order to prevent reliability deterioration due to stress on the gate oxide film, the maximum voltage is not applied from the first application of the program pulse, but the voltage level of the program pulse is sandwiched between verify operations for each pulse application. Raise gradually. When the verification result is Fail, the program pulse is applied again. That is, a series of programs is completed by repeating the step of executing verification after applying a program pulse (write pulse).

  The current adjustment circuit 52 adjusts the amount of current flowing through the main bit line BL during the program pulse application operation.

  The current adjustment circuit 52 includes a write latch circuit 53, a verify latch circuit 54, an AND gate 55, and a current switching circuit 60. These components are provided corresponding to each main bit line BL individually.

  The write latch circuit 53 is a circuit for holding write data during programming. Specifically, when data is written (write data “1”), high level (H level) data is retained, and when data is not written (write data “0”), low level is retained. (L level) data is held.

  The verify latch circuit 54 is a circuit for holding the determination result of the verify sense amplifier 50 for the memory cell MC to be programmed connected to the corresponding bit line BL. Specifically, the H level data is held in the initial state before the start of the program, and the L level data is held after the verification is passed.

  Current switching circuit 60 includes a switching NMOS transistor 63, a write blocking current generator 80, a first write current generator 81, and a second write current generator 82.

  The drain of the NMOS transistor 63 is connected to the bit line BL via the node ND1. The NMOS transistor 63 is used as a switch for starting and ending application of the program pulse together with the NMOS transistor QA connected to the source line SL. At the time of programming, the NMOS transistors QA and 63 are turned on, so that a program current I2 flows through the selected cell MC0.

  Write blocking current generating unit 80 is connected between node ND1 and power supply node VDD. When no data is written to the selected cell MC0 (write data “0”), the write inhibition current generator 80 has one of the PMOS transistors QDA and QDB connected to one end of the sub-bit lines BLA and BLB, respectively. A current I6 that is equal in magnitude and opposite to the constant current I1 to be generated is generated and supplied to the main bit line BL. As a result, the current I3 flowing through the bit line BL and the current I2 flowing through the channel of the selected cell MC0 become 0, so that the write current is blocked.

  More specifically, write inhibit current generation unit 80 includes PMOS transistors 61 and 62 connected in series between power supply node VDD and node ND1. The PMOS transistor 61 is used as a constant current source for supplying a constant current I6 when a predetermined voltage is applied to the gate. The PMOS transistor 62 is used as a switch that is turned on or off in accordance with the output of the write latch circuit 53 input to the gate. When the output of the write latch circuit 53 is at the H level (write data “1”), the PMOS transistor 62 is turned off. When the output of the write latch circuit 53 is at L level (write data “0”), the PMOS transistor 62 is turned on, thereby preventing the write current.

  The first write current generator 81 is connected between the source (node ND2) of the switching NMOS transistor 63 and the ground node VSS. The first write current generator 81 generates a current I4 in the same direction as the constant current I1 generated by one of the PMOS transistors QDA and QDB when writing data to the selected cell MC0 (write data “1”). Generate.

  More specifically, first write current generator 81 includes NMOS transistors 64 and 65 connected in series between node ND2 and the ground node. The NMOS transistor 64 is used as a switch that is turned on or off in accordance with the output of the write latch circuit 53 input to the gate. When the output of the write latch circuit 53 is at the H level (write data “1”), the write current flows when the NMOS transistor 64 is turned on. When the output of the write latch circuit 53 is at L level (write data “0”), the NMOS transistor 64 is turned off. The NMOS transistor 65 is used as a constant current source for supplying a constant current I4 when a predetermined voltage is applied to the gate.

  The second write current generator 82 is connected in parallel with the first write current generator 81 between the source (node ND2) of the switching NMOS transistor 63 and the ground node VSS. The second write current generation unit 82 writes data to the selected cell MC0 (write data “1”), and before the verify result becomes Pass, one of the PMOS transistors QDA and QDB A current I5 in the same direction as the constant current I1 to be generated is generated. After the verify result becomes Pass, the current generated by the second write current generator 82 becomes zero.

  More specifically, second write current generator 82 includes NMOS transistors 66 and 67 connected in series between node ND2 and the ground node. The NMOS transistor 66 is used as a switching transistor. The gate of the NMOS transistor 66 receives the logical product (output signal of the AND gate 55) of the output of the write latch circuit 53 and the output of the verify latch circuit 54. Therefore, when writing the write data “1” to the memory cell MC0, the NMOS transistor 66 is turned on in the initial state before writing, and turned off after the verification result is Pass. When write data “0” is written to the memory cell MC0, the NMOS transistor 66 is turned off. The NMOS transistor 67 is used as a constant current source for supplying a constant current I5 when a predetermined voltage is applied to the gate.

  In summary, according to the data held in the write latch circuit 53 and the verify latch circuit, each of the switching transistors 62, 64, 66 is turned on or off, that is, The operation of the current switching circuit 60 is determined. Specifically, it is as follows.

  First, when the write data “0” is held in the write latch circuit 53, the PMOS transistor 62 is turned on and the NMOS transistors 64 and 66 are turned off. The main bit line BL is charged to the VDD side to prevent the write current from flowing.

  When the write data “1” is held in the write latch circuit 53 and the data “1” is held in the verify latch (before verification is passed), the PMOS transistor 62 is turned off. Thus, the NMOS transistors 64 and 66 are turned on. Therefore, the current switching circuit 60 charges the main bit line BL to the ground (VSS) side (that is, draws current from the main bit line BL). As a result, a current of I4 + I5 flows through the main bit line BL, and a current I2 of I4 + I5-I1 flows through the selected cell MC0 (strong writing).

  When the write data “1” is held in the write latch circuit 53 and the data “0” is held in the verify latch (after verification is passed), the PMOS transistor 62 and the NMOS transistor 66 Is turned off, and the NMOS transistor 64 is turned on. Therefore, the current switching circuit 60 charges the main bit line BL to the ground (VSS) side, that is, draws current from the main bit line BL. However, in this case, the current flowing through the main bit line BL is I4, and the current I2 flowing through the selected cell MC0 is I4-I1, which is smaller than before the verification is passed (weak writing). An example of specific set values of the currents I4, I5, and I6 will be described with reference to FIG.

[Problems of conventional programming methods]
In the following, a problem with a conventional programming method that does not use the column selection circuit 39 having the above configuration will be described.

FIG. 8 is a diagram showing threshold voltage distributions in the erase state and the program state.
Referring to FIG. 8A, when data is stored according to a difference in threshold voltage, the threshold voltage is set to be equal to or lower than erase verify voltage EV when data “0” is stored. As a result, the threshold voltage of the memory cell storing the data “0” is included in the erase distribution (ERS distribution). When storing data “1”, the threshold voltage is set to be equal to or higher than the program verify voltage PV. As a result, the threshold voltage of the memory cell storing the data “1” is included in the program distribution (PRG distribution). The voltage difference VD between the erase verify voltage EV and the program verify voltage PV is determined in consideration of the data guarantee period.

  With reference to FIG. 8B, first, problems in the case where a program pulse is applied to all memory cells until all memory cells to be programmed pass the program verify will be described. In this case, an excessive stress is applied to the gate oxide film for the memory cell (reference numeral 48 in FIG. 8B) for which the program verify is first passed.

  Another problem is a decrease in program speed. In the writing method using hot electron injection, it is necessary to pass a program current during programming. A voltage drop (IR drop) occurs due to the parasitic resistance of the current path. When a voltage drop occurs, only a voltage value lower than the set voltage value can be applied to the memory cell. Therefore, a memory cell with a slow program (reference numeral 49 in FIG. 8B) does not readily complete the program. This causes the program speed to decrease as a whole chip.

  On the other hand, there is a method of masking a memory cell that has passed program verification and not applying a subsequent program pulse, but this method cannot be used for a nitride-based trap memory. This is because there is a detrapping in a short time after the application of the PRG pulse, and therefore, if a memory cell that has been once program-verified is masked, the threshold voltage of the memory cell is shifted to the program verify voltage PV or lower.

[Operation at the time of programming in the first embodiment]
In the case of the nonvolatile memory device according to the first embodiment, the above-described problems can be solved. Hereinafter, the operation at the time of programming in the first embodiment will be specifically described.

  FIG. 9 is a diagram showing a table summarizing currents flowing through the memory cells MC during the program pulse application operation. In FIG. 9, the current I1 flowing through the constant current source transistors QDA and QDB of FIG. 7 is set to 3 μA, the current I4 flowing through the constant current source transistor 65 is set to 3.5 μA, and the constant current source transistors The case where the current I5 flowing through the transistor 67 is set to 1.5 μA and the current I6 flowing through the constant current source transistor 61 is set to 3 μA is shown. In this case, the following current flows through the memory cell in accordance with the states of the write latch circuit 53 and the verify latch circuit 54.

(1) After initialization of the write target cell, when the verify result after applying the previous pulse is Fail, the output of the write latch circuit 53 is “H”.
Output of verify latch circuit 54 ... "H"
Therefore,
Write current source transistor 65... Active Write current source transistor 67... Active Since a pulse is applied by strong writing of the write current I4 + I5, the program current (write current) I2 flowing in the write target memory cell Is I3-I1 = I4 + I5-I1 = 2 μA.

(2) When the verification result after applying the previous pulse is Pass The output of the write latch circuit 53 ... "H"
Output of verify latch circuit 54 ... "L"
Therefore,
Write current source transistor 65... Active Write current source transistor 67... Inactive Since a pulse is applied by weak writing of only the write current I4, the program current I2 flowing through the memory cell to be written is I3 −I1 = I4−I1 = 0.5 μA.

(3) Non-write target cell Output of write latch circuit 53: "L"
Output of verify latch circuit 54 ... "H"
Therefore,
Write current source transistor 65... Inactive Write current source transistor 67... Inactive That is, the program current I2 flowing through the memory cell to be inwritten becomes 0 and becomes in an inactive state.

  As described above, the write current source can be switched between the normal write mode and the weak write mode, thereby changing the write current for each memory cell to be written in accordance with the verify result. Can be made. In other words, if all the memory cells to be written are not passed during program verification and a program pulse is applied again, the write current is reduced by reducing the write current for some memory cells that have been verified. Can be included.

  As a result, the stress of the gate oxide film due to overprogramming can be reduced for a memory cell having a threshold voltage equal to or higher than the program verify voltage PV. Furthermore, by setting the weak write state, the lowering of the lower limit value can be suppressed without increasing the upper limit value of the threshold voltage program distribution, so that the distribution width can be further narrowed.

  There is also an effect that the write speed of the entire chip is improved by reducing the write current that flows to the memory cell that has passed the program verify. That is, by reducing the write current, there is no extra current consumption, so that the amount of voltage drop in the path from the charge pump 33 to the source line SL in FIG. 7 can be suppressed. Specifically, loss due to the wirings 43, 44, and 45 in FIG. 7, loss due to switches such as the distributor 41 and the transistor QA, and loss due to the driver SLD are suppressed. As a result, the voltage drop of the pulse voltage applied to the memory cell that has not yet reached the program verify voltage PV can be suppressed, so that the writing time can be reduced as compared with the case where the voltage drop amount is large.

  FIG. 10 is a timing diagram schematically showing voltage waveforms applied to the memory gate during programming. The timing chart of FIG. 10 also shows the timing at which the program pulse is applied (that is, the timing at which the program current flows through the source line SL).

  Referring to FIG. 10, between time t1 and time t2, predetermined voltage V1 generated by power supply circuit 33 in FIG. 4 is applied to memory gate 23 of each memory cell MC in the selected row. In this state, a pulse voltage is applied from the source line driver unit 38 of FIG. 4 to the source line SL of the selected row (that is, a program current flows through the source line SL of the selected row). Since the application of the pulse voltage is performed by turning on the NMOS transistors QA and 63 of FIG. 7, it is performed in units of memory blocks shown in FIG. For example, in FIG. 5, when the first row of the memory array 30 is selected, the NMOS transistor QA0 is first turned on, whereby the source line SL0 (first row provided in the memory block MB0) ( A pulse voltage is applied to the source line SL0_0 in FIG. At this time, in 512 memory cells of memory cells MC (0,0) to MC (0,511) in FIG. 6, 256 memory cells selected by the transistors QC0A, QC0B to QC255A, QC255B are pulsed. A voltage is applied simultaneously.

  Next, by turning on the NMOS transistor QA1, a pulse voltage is applied to the source line SL1 in the first row provided in the memory block MB1. As a result, a pulse voltage is applied to 256 memory cells connected to the source line SL1 in the first row. Similarly, by sequentially turning on the NMOS transistors QA2 to QA7, a pulse voltage is applied to the source lines SL2 to SL7 in the first rows provided in the memory blocks MB2 to MB7, respectively (see FIG. 5). Although not shown, source lines provided in the memory blocks MB0 to MB31 are SL0 to SL31, respectively).

  Between the next time t3 and time t4, the voltage applied to the memory gate 23 of each memory cell MC in the selected row is set to the program verify voltage PV. During this period, verify is executed for the memory cell to which the pulse voltage is applied at times t1 to t2. As a result, the data held in the corresponding verify latch circuit 54 shown in FIG. 7 is changed from “1” to “0” for the memory cell that has been verified.

  During the next time t5 to time t6, the programming voltage V2 is applied to the memory gate 23 of each memory cell MC in the selected row. The voltage V2 applied to the memory gate 23 is higher than the voltage V1 at the first pulse application (from time t1 to time t2). Thus, it is desirable to increase the voltage applied to the memory gate in a stepwise manner. In this state, a pulse voltage is sequentially applied from the source line driver unit 38 of FIG. 4 to the source lines SL0 to SL7 in the selected row (that is, a program current flows through the source line SL in the selected row). At this time, if the verify result obtained between time t3 and time t4 is Pass, the write current is weaker than usual.

  Similarly, between time t7 and time t8, similarly, the memory gate voltage applied to each memory cell in the selected row is set to the program verify voltage PV, and verification is executed on the memory cell in the selected row. In response to the verify result, the data held in the verify latch circuit 54 is updated. During the next time t9 to time t10, the programming voltage V3 is applied to the memory gate 23 of each memory cell MC in the selected row. In this state, a pulse voltage is sequentially applied from the source line driver unit 38 in FIG. 4 to the source lines SL0 to SL7 in the selected row.

  FIG. 11 is a flowchart showing a program procedure in the case of the first embodiment. Hereinafter, the program procedure described so far will be summarized with reference to FIGS. The following program procedure is executed under the control of the control circuit 32 in FIG.

  First, in step S10, all the write latch circuits 53 and all the verify latch circuits 54 are initialized.

  In the next step S20, the start address of the memory cell to be written is set in the register for designating the address. In this case, the row address is fixed to the selected row, and the column address is set to the first column among the memory cells to be written.

  In the next step S30, write data (“1” or “0”) is input to the write latch circuit 53 corresponding to the set column address.

  In the next step S40, it is confirmed whether or not the input of all the write data is completed. If not completed (NO in step S40), the address number set in the address designation register is increased. (Step S50). In this case, the row address is fixed to the selected row, and the column address is increased by two columns. Thereafter, the process returns to step S30. In the case of the first embodiment, one of the sub-bit lines BLA and BLB is selected by the NMOS transistors QCA and QCB in FIG. 7, so that the column number increases by two columns.

  When the input of all the write data is completed (YES in step S40), the process proceeds to step S60, and the program pulse is applied to the memory cell in which the write data is set to “1”. Since the application of the pulse voltage is performed by turning on the NMOS transistors QA and 63 of FIG. 7, it is performed in units of memory blocks shown in FIG. Specifically, a pulse voltage is sequentially applied to the source line of each memory block corresponding to the selected row. Each time the pulse voltage is applied, the number of blocks to which the pulse voltage is applied is counted by the SL counter provided in the control circuit 32 of FIG.

  In the next step S70, the head address of the memory cell to be written is set in the register for designating the address. In this case, the row address is fixed to the selected row, and the column address is set to the first column.

  In the next step S80, program verify is performed on the memory cell corresponding to the address set in the address designation register.

  In the next step S90, if the result of the verification executed in step S80 is a pass, the logic level of the data held in the verify latch circuit 54 corresponding to the passed memory cell MC is inverted.

  In the next step S100, it is checked whether or not the verification has been completed up to the memory cell at the final address among the memory cells to be written. If the verification has not been completed (NO in step S100), a register for address designation is used. The address number to be set is increased (step S110). In this case, the row address is fixed to the selected row, and the column address is increased to the column number of the memory cell of the next write data “1”. Thereafter, the process returns to step S80. The verify operation may be skipped for memory cells that have already passed verify.

  When verification is completed up to the memory cell at the final address (YES in step S100), the process proceeds to the next step S120. In step S120, it is determined whether or not verification has passed in all the write memory cells to which data “1” has been written. When verification is passed in all the write memory cells (YES in step S120), the process ends. If verification has not passed in all the write memory cells, the process returns to step S60.

<Embodiment 2>
FIG. 12 is a diagram showing portions related to a data program in the nonvolatile memory device according to the second embodiment of the present invention.

  The column system selection circuit 70 of FIG. 12 is different from the column system selection circuit 39 of FIG. 7 in that it further includes a selector 71 and a counter 72. The selector 71 sequentially selects and outputs the output signal of each AND gate 55 in the memory block. The counter 72 counts the outputs of the plurality of AND gates 55 received through the selector 71 whose logic level is H level (that is, the number of memory cells in which the verify result is Fail and the program is not completed). . The output result of the counter 72 is output to the control circuit 32 in FIG.

  FIG. 13 is a diagram for explaining a program procedure by the nonvolatile memory device of FIG.

  Generally, in a NOR type flash memory, since writing using hot electrons is performed, it is necessary to apply a high voltage to the source or drain in order to flow a write current having a predetermined magnitude. At this time, since the current capacity of the charge pump circuit is limited, there is an upper limit on the number of memory cells that can be simultaneously written. Therefore, the memory array is divided into a plurality of groups (memory block MB in FIG. 5) according to the number of memory cells that can be simultaneously written, and writing is performed in order for each group.

  In the case of the non-volatile memory device according to the second embodiment, since the number of memory cells that have not been programmed is counted for each group, the number of memory cells that have not yet been programmed (the number of Fail bits) decreases. By simultaneously applying a program pulse to a plurality of groups, the number of groups to be written simultaneously can be increased. As a result, the programming time for the entire chip can be shortened.

  Hereinafter, a specific description will be given with reference to FIGS. 5 and 13. In FIG. 13, in the memory array 30 shown in FIG. 5, the first row (corresponding to the memory gate line MGL0) is selected as the selected row corresponding to the row address signal, and data is stored in the memory cells of all the bits in this selected row. It is assumed that “1” (high threshold voltage distribution) is written.

  The first program pulse shown in FIG. 13A is programmed for each minimum division unit (that is, source line SL0 of memory block MB0, source line SL1 of memory block MB1,..., Source line SL7 of memory block MB7). A pulse will be applied. Each minimum division unit includes 256 bits (bits) of memory cells to be programmed.

  As the number of application times of the program pulse increases, the number of memory cells that pass verification increases. That is, the number of unprogrammed memory cells (also referred to as the number of fail bits) indicated by numerical values in FIG. 13 decreases. In the case of FIG. 13B, the number of Fail bits is 200 bits in each block. If weak writing is performed on a memory cell to which verification has been passed, the total write current that flows with each program pulse decreases as the number of Fail bits decreases.

  In FIG. 13C, the number of Fail bits corresponding to the source lines SL0, SL1, SL5, and SL6 is 120 bits. In this case, if the sum of the number of Fail bits of two consecutive blocks is 256 bits or less, two blocks can be multi-selected and a program pulse can be applied simultaneously. In the case of FIG. 13C, a program pulse is simultaneously applied to the memory cells corresponding to the source lines SL0 and SL1, and a program pulse is simultaneously applied to the memory cells corresponding to the source lines SL5 and SL6.

  As the number of application times of the program pulse increases, the number of Fail bits further decreases, so that the number of blocks to which the program pulse is applied simultaneously (that is, the number of source line drivers operated simultaneously) can be increased. In the case of FIG. 13D, a program pulse is simultaneously applied to the memory blocks MB0, MB1, and MB2 by simultaneously operating the source line drivers for the source lines SL0, SL1, and SL2. Similarly, the source line drivers for the source lines SL3 and SL4 can be operated simultaneously, and the source line drivers for the source lines SL5, SL6 and SL7 can be operated simultaneously. That is, the program pulse can be applied to all the memory cells in the selected row by applying the program pulse three times. Finally, in the case of FIG. 13E, the program pulse is simultaneously applied to all the memory cells in the selected row.

  In the above description, the case where data “1” is written in all the memory cells in the selected row has been described. However, data “1” and “0” written in the memory cells in the selected row are usually random. Therefore, even in the case of applying the first program pulse, the program pulse can be applied simultaneously to a plurality of blocks in accordance with the number of unprogrammed memory cells (the number of fail bits).

  In the above description, an example in which the program pulse is simultaneously applied to consecutive blocks has been described. However, it is not always necessary to simultaneously apply the program pulse to consecutive blocks. For example, in the case of FIG. 13C, the program pulse may be simultaneously applied to the memory cells corresponding to the source lines SL0 and SL5.

  FIG. 14 is a timing chart showing voltage waveforms applied to the source line and the bit line in a normal state where simultaneous selection of memory blocks is not performed.

  FIG. 15 is a timing chart showing voltage waveforms applied to the source line and the bit line in the simultaneous selection state of the memory blocks. In FIG. 15, the memory blocks corresponding to the source lines SL0 and SL1 are simultaneously selected.

  Referring to FIGS. 5 and 14, in a steady state (before time t1) when no program pulse is applied, the voltage output from each source line driver SLD is L level, and the voltage of each main bit line BL is H It is level.

  At time t1, an H level voltage is supplied from the source line driver SLD0 to the source line SL0. At the same time, the switching transistors 63 (see FIG. 12) corresponding to the main bit lines BL0 to BL255 are turned on, so that the voltages of the main bit lines BL0 to BL255 become L level (however, the main bit lines BL0 to BL0). It is assumed that data “1” is written in all selected memory cells connected to BL255).

  At the next time t2, the voltage supplied from the source line driver SLD0 to the source line SL0 returns to the L level, and the voltage supplied from the source line driver SLD1 to the source line SL1 changes to the H level. At the same time, the voltages on the main bit lines BL0 to BL255 return to the H level, and the voltages on the main bit lines BL256 to BL511 change to the L level.

  At the next time t3, the voltage supplied from the source line driver SLD1 to the source line SL1 returns to the L level, and the voltage supplied from the source line driver SLD2 to the source line SL2 changes to the H level. At the same time, the voltages of the main bit lines BL256 to BL511 return to the H level, and the voltages of the main bit lines BL512 to BL755 change to the L level. Thereafter, the process proceeds in the same manner.

  Next, a case where a program pulse is simultaneously applied to the memory cells corresponding to the source lines SL0 and SL1 will be described with reference to FIGS. In this case, at time t1, an H level voltage is supplied from the source line driver SLD0 to the source line SL0, and an H level voltage is supplied from the source line driver SLD1 to the source line SL1. At the same time, the voltages of the main bit lines BL0 to BL255 become L level, and the voltages of the main bit lines BL256 to BL511 become L level.

  Next, at time t3, the voltages supplied from the source line drivers SLD0 and SLD1 to the source lines SL0 and SL1 return to the L level, and the voltage supplied from the source line driver SLD2 to the source line SL2 changes to the H level. At the same time, the voltages of the main bit lines BL0 to BL511 return to the H level, and the voltages of the main bit lines BL512 to BL755 change to the L level. Thereafter, the process proceeds in the same manner as in FIG.

  FIG. 16 is a flowchart showing a program procedure in the case of the second embodiment. The flowchart of FIG. 16 differs from the flowchart of FIG. 11 in that it further includes steps S55 and S95. The same steps as those in FIG. 11 are denoted by the same reference numerals, and the description is simplified. The program procedure shown below is executed under the control of the control circuit 32 in FIG.

  First, in step S10, all the write latch circuits 53 and all the verify latch circuits 54 are initialized.

  In the next step S20, the head address of the memory cell to be written is set in the address designation register. In this case, the row address is fixed to the selected row, and the column address is set to the first column among the memory cells to be written.

  In the next step S30, write data (“1” or “0”) is input to the write latch circuit 53 corresponding to the set column address.

  In the next step S40, it is confirmed whether or not the input of all the write data is completed. If not completed (NO in step S40), the address number set in the address designation register is increased. (Step S50). Thereafter, the process returns to step S30.

  When the input of all the write data is completed (YES in step S40), the combination of blocks in which data is simultaneously written is determined in the next step S55. As already described, the pulse voltage is applied in units of the memory block shown in FIG. 5, and specifically, the pulse voltage is applied to the source line of each memory block corresponding to the selected row. At this time, if the current capacity of the charge pump circuit is not exceeded, it is possible to apply several pulse voltages to the blocks at the same time. Therefore, in step S55, based on the number of unprogrammed memory cells (the number of fail bits) counted for each block by the counter 72 in FIG. 13, data is simultaneously recorded within a range not exceeding the current capacity of the charge pump circuit. A combination of blocks to be written is determined.

  In the next step S60, a program pulse is applied in order for each combination of blocks determined in step S55. Each time the pulse voltage is applied, the number of blocks to which the pulse voltage is applied is counted by the SL counter provided in the control circuit 32 of FIG.

  In the next step S70, the head address of the memory cell to be written is set in the address designation register. In this case, the row address is fixed to the selected row, and the column address is set to the first column.

  In the next step S80, program verify is performed on the memory cell corresponding to the address set in the address designation register.

  In the next step S90, if the result of the verification executed in step S80 is a pass, the logic level of the data held in the verify latch circuit 54 corresponding to the passed memory cell MC is inverted.

  In the next step S95, if the result of the verification executed in step S80 is Fail, the number of Fail bits is counted by the counter 72 of FIG. 12 provided for each memory block.

  In the next step S100, it is checked whether or not the verification has been completed up to the memory cell at the final address among the memory cells to be written. If the verification has not been completed (NO in step S100), a register for address designation is used. The address number to be set is increased (step S110). In this case, the row address is fixed to the selected row, and the column address is increased to the column number of the memory cell of the next write data “1”. Thereafter, the process returns to step S80. The verify operation may be skipped for memory cells that have already passed verify.

  When verification is completed up to the memory cell at the final address (YES in step S100), it is determined in next step S120 whether verification has passed in all the write memory cells to which data “1” has been written. When verification is passed in all the write memory cells (YES in step S120), the process ends. If verification has not passed in all the write memory cells, the process returns to step S55.

  In step S55, based on the number of Fail bits for each block counted in step S95, a combination of blocks in which data is simultaneously written is newly determined within a range not exceeding the current capacity of the charge pump circuit.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 microcomputer chip, 4 nonvolatile memory device, 20 P-type silicon substrate, 21 control gate, 22 silicon nitride film, 23 memory gate, 24 source, 25 drain, 30 memory array, 32 control circuit, 33 charge pump (power supply circuit) ), 34 power supply switching circuit, 35 word line decoder section, 36 control gate line driver section, 37 memory gate line driver section, 38 source line driver section, 39, 70 column system selection circuit, 50 verify sense amplifier, 51, 71 Selector, 52 Current adjustment circuit, 53 Write latch circuit, 54 Verify latch circuit, 60 Current switching circuit, 65, 67 Current source transistor for write, 72 Counter, BL main bit line, BLA, BLB, SBL Subbit Line, CGL Cement roll gate line, EV erase verify voltage, MB0~MB31 memory block, MC, MC0, MC1 memory cell, MGL memory gate line, PV program verify voltage, SL source line, SLD source line driver.

Claims (5)

A semiconductor device,
A memory array including a plurality of memory cells arranged in a matrix and each storing data according to a threshold voltage level change;
Each of the memory cells has first and second conductive electrodes and a gate electrode,
The threshold voltage of each memory cell is set to a predetermined program verify voltage by causing a program current to flow between the first and second conductive electrodes and applying a program voltage to the gate electrode a plurality of times. To reach
The semiconductor device further includes:
A verify circuit for determining whether or not a threshold voltage has reached the program verify voltage for each of the program operations executed a plurality of times on the memory cell to be programmed;
A current adjustment circuit for adjusting the magnitude of the program current,
The current adjustment circuit passes a program current having a first current value to a memory cell determined by the verify circuit that the threshold voltage has not reached the program verify voltage among the plurality of memory cells to be programmed, A semiconductor device, wherein a program current having a second current value smaller than the first current value is supplied to a memory cell determined to have a threshold voltage reaching the program verify voltage. The semiconductor device further includes:
A plurality of first wirings provided corresponding to the memory cell rows, each connected to the first conductive electrode of each memory cell included in the corresponding memory cell row;
A plurality of second wirings provided corresponding to the memory cell columns, each connected to the second conductive electrode of each memory cell included in the corresponding memory cell column;
A drive circuit that applies a predetermined drive voltage to the plurality of first wirings during a program operation of each of the memory cells;
The current adjustment circuit is connected to the plurality of second wirings, and a current flowing through each of the plurality of second wirings so that a program current having the first or second current value flows through a memory cell to be programmed. The semiconductor device according to claim 1, wherein the value is adjusted. The current adjustment circuit includes:
A plurality of latch circuits provided for each one or a plurality of memory cell columns, each holding a determination result by the verify circuit for a memory cell to be programmed in the corresponding memory cell column;
A plurality of current source circuits provided corresponding to the plurality of latch circuits for each of one or a plurality of memory cell columns,
Each of the current source circuits
A first transistor that is connected to the second wiring of the corresponding memory cell column, and in which a constant current flows regardless of data held in the corresponding latch circuit during a program operation of the memory cell included in the corresponding memory cell column;
A second transistor that is connected in parallel with the first transistor and through which a constant current flows during a program operation of a memory cell included in the corresponding memory cell column until data held in the corresponding latch circuit changes; The semiconductor device according to claim 2, comprising: The plurality of memory cells constituting the memory array are divided into a plurality of groups for each of a plurality of columns,
The semiconductor device further includes:
A plurality of first wirings provided corresponding to the memory cell rows for each of the groups, each connected to the first conductive electrode of each memory cell included in the corresponding memory cell row;
A plurality of second wirings provided corresponding to the memory cell columns for each group, each connected to the second conductive electrode of each memory cell included in the corresponding memory cell column;
A plurality of drives provided corresponding to each of the plurality of groups, each applying a predetermined drive voltage to the plurality of first wirings of the corresponding group during a program operation of the memory cells included in the corresponding group With circuit,
The current adjustment circuit is connected to the plurality of second wirings of each of the groups, and the plurality of the plurality of groups of each of the groups are configured such that a program current having the first or second current value flows through a memory cell to be programmed. Adjust the current value that flows in each of the second wiring,
The semiconductor device further includes:
Based on the determination result of the verify circuit, for each group, a counter that counts the number of unprogrammed cells that is the number of memory cells whose threshold voltage has not reached the program verify voltage;
A control circuit for controlling the supply of drive voltage from each of the drive circuits to a corresponding group,
The control circuit limits the number of drive circuits operating simultaneously by sequentially supplying a drive voltage to one or a plurality of drive circuits. As the number of unprogrammed cells decreases, the control circuit operates simultaneously. The semiconductor device according to claim 1, wherein the number is increased.   5. The semiconductor according to claim 1, wherein each of the memory cells includes a silicon nitride film, and a threshold voltage level is changed by trapping charges in the silicon nitride film during a program operation. apparatus.

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