JP2013140549A - Semiconductor testing device, semiconductor test method and program for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing device that easily detects whether or not a data holding circuit such as a latch and a flip-flop in a circuit controls data holding in synchronization with an external clock by using any of static verification and dynamic timing verification.SOLUTION: The semiconductor testing device of the present invention comprises: a simulation section for performing dynamic timing verification on signal level of the terminals of the data holding circuit that controls data holding by the external clock within the circuit, for each of a plurality of external clocks of different frequencies, and for writing and storing a verification result into a storage section as waveform data for each frequency of the external clock; and a waveform comparison section for reading the waveform data from the storage section, comparing waveform shapes of the signal levels at the terminals of the data holding circuit among different frequencies of the external clock, and thereby determining whether or not the data holding circuit is synchronously-controlled for the external clock.

Description

  The present invention relates to a semiconductor test apparatus, a semiconductor test method, and a program thereof.

Conventionally, in circuit design of a semiconductor device, verification of whether or not a data holding circuit such as a latch and a flop flop whose data holding is controlled by an external clock in the circuit performs a data holding operation in synchronization with the external clock ( Hereinafter, synchronous control determination) is performed.
In other words, it is necessary to verify whether or not a data holding circuit designed to control data holding in synchronization with an external clock operates by simulation.

  When the static verification is used for verifying whether or not the data holding synchronization control corresponding to the external clock (hereinafter simply referred to as synchronization control) is performed, such verification is performed by each of the data holding circuits. It is assumed that it operates in synchronization with an external clock. Therefore, only the timing check based on the delay amount of each cell in the circuit is performed as the verification of the synchronous control on the assumption that it operates in synchronization with the external clock.

  In this case, it is necessary to indicate in advance whether each data holding circuit to be evaluated is synchronous control or asynchronous control. For this reason, topological determination processing is performed by path search of an external clock using a net list of a data holding circuit such as a latch or flip-flop in the circuit net list (see, for example, Patent Document 1).

In the circuit, the operation range in which the asynchronous control operation is performed is set as a predicted clock domain.
For this reason, a topological determination process of whether or not an external clock is input is performed by searching for a signal path of a wiring that connects between data holding circuits such as latches and flip-flops (see, for example, Patent Document 2).

JP 2004-86813 A JP 2009-187344 A

The static verification for the data holding circuit described above is not verification corresponding to the operation of the circuit arranged on the semiconductor substrate in both Patent Document 1 and Patent Document 2.
In other words, static verification does not include dynamic timing verification, and does not include delay information such as the resistance and capacitance of wiring between cells in the circuit and buffers used for distribution of external clocks. The detection accuracy of the control data holding circuit is insufficient.

When dynamic timing verification is used for verifying whether or not the synchronous operation is performed, verification pattern creation and simulation are performed, and verification of the simulation result is performed manually.
As described above, it is not realistic to manually verify the simulation result because it requires a large number of steps for checking the simulation result of each data holding circuit, although it depends on the circuit scale.

As described above, whether or not the data holding circuit such as the latch and the flip-flop in the circuit controls the data holding synchronized with the external clock regardless of whether the static verification or the dynamic timing verification is used. Cannot be easily detected.
In particular, even if the data holding circuit is designed to synchronize with an external clock, unexpected asynchronous control that occurs in data holding circuits such as latches and flip-flops is detected due to changes in the frequency of the external clock, etc. I can't do it.

  The semiconductor test apparatus according to the present invention provides a verification result obtained by dynamic timing verification of the signal level of the terminal of the data holding circuit whose data holding is controlled by the external clock in the circuit for each of a plurality of external clocks having different frequencies. , A simulation unit that writes and stores waveform data in the storage unit as waveform data for each frequency of the external clock, and the waveform data is read from the storage unit, and the waveform of the signal level at the terminal of the data holding circuit has a different frequency of the external clock And a waveform comparison unit for determining whether or not the data holding circuit is synchronously controlled with respect to the external clock.

  In the semiconductor test method of the present invention, the simulation unit performs dynamic timing verification of the signal level of the terminal of the data holding circuit whose data holding is controlled by the external clock in the circuit for each of a plurality of external clocks having different frequencies, A simulation process in which the verification result is written and stored in the storage unit as waveform data for each frequency of the external clock, and the waveform comparison unit reads the waveform data from the storage unit, and the waveform shape of the signal level at the terminal of the data holding circuit And a waveform comparison process for determining whether or not the data holding circuit is synchronously controlled with respect to the external clock.

  In the semiconductor test method of the present invention, the computer performs dynamic timing verification of the signal level of the terminal of the latch in the circuit for each of a plurality of external clocks having different frequencies, and the verification result is waveformd for each frequency of the external clock. Simulation means for writing and storing data in the result storage unit, reading waveform data from the result storage unit, and controlling the external clock in the signal level waveform shape at the terminal of the data holding circuit whose data holding is controlled by the external clock in the circuit This is a program for making a comparison between different frequencies and for functioning as a waveform comparison means for determining whether or not the data holding circuit is synchronously controlled with respect to an external clock.

  According to the present invention, a latch and a flip-flop that cause an unexpected asynchronous operation with respect to the external clock due to a change in the frequency of the external clock, etc., despite being designed to control data retention in synchronization with the external clock. It is possible to easily and accurately detect a data holding circuit such as a user's hand without troublesome user.

It is a schematic block diagram which shows the structural example of the semiconductor test apparatus by one Embodiment of this invention. It is a figure which shows the circuit example which the net list information memorize | stored in the circuit memory | storage part 16 in this embodiment shows. It is a figure for demonstrating the comparison of the waveform shape between the different frequencies in the waveform comparison part. It is a figure for demonstrating the process which extracts the setup margin time and hold margin time as an operation margin from the waveform shape between different frequencies in the margin comparison part. FIG. 10 is a diagram of a process in which a latch operation determination unit 19 determines whether a latch is a synchronous control data holding circuit or an asynchronous control data holding circuit from a frequency change of the setup margin time TSETUP or the hold margin time THOLD. FIG. 10 is a diagram of a process in which a latch operation determination unit 19 determines whether a latch is a synchronous control data holding circuit or an asynchronous control data holding circuit from a frequency change of the setup margin time TSETUP or the hold margin time THOLD. FIG. 10 is a diagram of a process in which a latch operation determination unit 19 determines whether a latch is a synchronous control data holding circuit or an asynchronous control data holding circuit from a frequency change of the setup margin time TSETUP or the hold margin time THOLD. FIG. 10 is a diagram of a process in which a latch operation determination unit 19 determines whether a latch is a synchronous control data holding circuit or an asynchronous control data holding circuit from a frequency change of the setup margin time TSETUP or the hold margin time THOLD. It is a flowchart which shows the operation example of the synchronous determination process whether the latch in the circuit of the semiconductor testing apparatus by one Embodiment of this invention is synchronous control or asynchronous control.

The present invention is a semiconductor test apparatus for detecting the operating state of a data holding circuit such as a latch or flip-flop that holds data by clock input in the circuit.
That is, according to the present invention, it is determined whether or not the data holding circuit in the circuit normally performs the data holding control in synchronization with the external clock.
In the present invention, the synchronization control data holding circuit holds data synchronized with the external clock when the frequency of the external clock input to the external clock input terminal is changed within the operating frequency range in the specifications of the semiconductor device. 2 shows a data holding circuit that performs normal control.
On the other hand, the asynchronous control data holding circuit controls data holding synchronized with the external clock when the frequency of the external clock input to the external clock input terminal is changed within the operating frequency range in the specifications of the semiconductor device. The data holding circuit which does not perform normally is shown.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing a configuration example of a semiconductor test apparatus according to an embodiment of the present invention.
1, the semiconductor test apparatus of this embodiment includes a system control unit 11, a latch extraction unit 12, a simulator unit 13, a waveform comparison unit 14, a margin comparison unit 15, a circuit storage unit 16, a test pattern storage unit 17, and a result storage. A unit 18 and a latch operation determination unit 19 are provided.
In the circuit storage unit 16, netlist information of a plurality of circuits to be tested is written and stored in advance.
Each test pattern used for testing each circuit stored in the circuit storage unit 16 is written and stored in the test pattern storage unit 17 in advance.

The latch extraction unit 12 reads from the circuit net list information stored in the circuit storage unit 16 the net list of the circuit under test selected by the input device (not shown) by the user.
Further, the latch extraction unit 12 uses the connection information indicating the connection relation of the elements of the data holding circuit (latch, flip-flop, etc.) written and stored in the internal storage unit in advance, from the net list information, the data holding circuit. Perform extraction.
In the present embodiment, whether or not the data holding circuit that holds data in synchronization with the external clock by design actually controls the data holding in synchronization with the external clock when it is created on the semiconductor chip. Perform verification. For this reason, when verifying whether or not the data holding control in synchronization with the external clock of the data holding circuit in the circuit is performed, the connection relationship of each cell constituting the circuit from the pattern layout data of the circuit to be inspected The netlist information extracted from is used. For this reason, the net list used in the circuit simulation (dynamic test) described later in the present embodiment includes load information such as wiring resistance and wiring capacitance of the wiring connecting the cells. Hereinafter, in the present embodiment, a latch is described as an example of the data holding circuit.

Further, the latch extraction unit 12 adds latch identification information as a data holding circuit to connection information between terminals between cells in the netlist information (connection information indicating a combination of pin connections between cells).
Here, the latch extraction unit 12 has a correspondence relationship between each terminal such as a clock input terminal, a data input terminal, a data output terminal, and an inverted data output terminal of each latch together with the latch identification signal, and a corresponding cell terminal. Is stored in the correspondence table of the result storage unit 18.

Next, FIG. 2 is a diagram illustrating a circuit example indicated by the netlist information stored in the circuit storage unit 16 in the present embodiment. In the latches L_1 and L_2 in FIG. 2, D is a data input terminal, ck is a clock input terminal, Q is a data output terminal, and QB is an inverted data output terminal.
FIG. 2A is a diagram showing, for example, the connection of the netlist information between the latch L_1 (data holding circuit, for example, D flip-flop) in the clock domain CD1, the latch L_2 in the clock domain CD2, and the clock domain CD3. . FIG. 2B is a diagram showing that the circuit configuration of the latches L_1 and L_2 is set topologically as the connection state of each cell terminal between cells such as transistors or inverters. The latch extraction unit 12 extracts the data holding circuit from the netlist information according to the connection state of the terminals of each cell shown in FIG. 2B, which is set in the internal storage unit.

The simulator unit 13 reads a test pattern for performing a dynamic test of a circuit designated by the user from the test pattern storage unit 17.
In addition, the simulator unit 13 performs a dynamic test on the circuit indicated by the netlist information described above (in this embodiment, a transient analysis simulation (dynamic timing verification including delays such as wiring between circuits in addition to the delay of the circuit itself). ) Circuit simulation). Note that the dynamic test may be performed using a transient analysis simulation (dynamic timing verification) that includes a delay of the circuit itself and does not include a delay of wiring between circuits.

That is, the simulator unit 13 displays the waveform of the signal level of each of the clock input terminal, the data input terminal, the data output terminal, and the inverted data output terminal of each latch extracted by the latch extraction unit 12 described above as the voltage at the time and the time. As the waveform data in which values are associated with each other, for each latch, the simulation result data corresponding to the circuit unit to be tested in the result storage unit 18 is written and stored together with the latch identification information. Here, the time corresponds to the time resolution of the dynamic test and is one point in the time course of the step unit of this time resolution.
At this time, the simulator unit 13 dynamically uses a plurality of frequencies within an operating frequency range (operating frequency range) in the operating specifications of the circuit, for example, two or more different frequencies, according to a test pattern corresponding to each circuit. Do the test.

That is, the same test pattern is used for each dynamic test using external clocks having different frequencies (external clocks having different periods). The simulator unit 13 writes and stores the waveform data of the signal level at each terminal of each latch in the simulation result data in the result storage unit 18 for each frequency for each circuit to be inspected.
Further, the simulator unit 13 writes the waveform data of the external clock at the external clock input terminal, which is input as a test pattern, into the result storage unit 18 and stores it in the same manner as the waveform data of the latch terminal.

The waveform comparison unit 14 compares the waveform shape of the waveform of the signal level of the latch terminal in the simulation result data of the test object stored in the result storage unit 18 between different frequencies.
Next, FIG. 3 is a diagram for explaining comparison of waveform shapes between different frequencies in the waveform comparison unit 14. The waveform shape shown in FIG. 3 is written into the result storage unit 18 by the simulator unit 13 and stored as waveform data.
In FIG. 3, as the waveform data of the simulation result, FIG. 3A shows the waveform data at the frequency f1 when the cycle of the external clock is T1, and FIG. 3B shows the waveform of the external clock from the cycle T1. This is waveform data at the frequency f2 when T2 is large.
Therefore, the frequency of the external clock in FIG. 3A is higher than the frequency of the external clock in FIG. For this reason, for example, within the range of the specification frequency, the frequency of the period T1 in FIG. 3A is set near the upper limit in the operating frequency range in the specification, and the vicinity of the lower limit in the operating frequency range of the period T2 in FIG. Set to.

That is, the waveform comparison unit 14 performs the comparison by comparing the waveform voltage levels at the relative positions of the periods, for example, the relative positions indicating the range of the period of the external clock.
In FIG. 3A, time tf1_1 is relative position 1, time tf1_2 is relative position 2, and time tf1_3 is relative position 3. In FIG. 3B, time tf2_1 is relative position 1, time tf2_2 is relative position 2, and time tf2_3 is relative position 3.

Returning to FIG. 1, the waveform comparison unit 14 reads the waveform data of the terminals of the latch corresponding to the waveform of FIG. 3A from the simulation result data stored in the result storage unit 18.
After reading, the waveform comparison unit 14 determines that the latch clock CK (the signal level of the clock input terminal of the latch) is level CK1 (for example, “L” level) at the relative position 1 in the waveform of FIG. D (the signal level of the data input terminal of the latch) is level D1 (eg, “L” level), and the latch QB (the signal level of the inverted data output terminal of the latch) is level QB0 (eg, “H” level). Is detected.

Similarly, at the relative position 2 in the waveform of FIG. 3A, the waveform comparison unit 14 has the latch clock CK at the level CK1, the latch D at the level D0 (eg, “H” level), and the latch QB at the level. QB1 (for example, “L” level) is detected.
Further, the waveform comparison unit 14 detects that the latch CK is level CK1, the latch D is level D1, and the latch QB is level QB0 at the relative position 3 in the waveform of FIG.

On the other hand, the waveform comparison unit 14 reads the waveform data of the latch terminals corresponding to the waveform of FIG. 3B from the simulation result data stored in the result storage unit 18.
After reading, the waveform comparison unit 14 detects that the latch CK is level CK1, the latch D is level D1, and the latch QB is level QB0 at the relative position 1 in the waveform of FIG. .
Similarly, the waveform comparison unit 14 detects that the latch CK is level CK1, the latch D is level D0, and the latch QB is level QB1 at the relative position 2 in the waveform of FIG.
Further, the waveform comparison unit 14 detects that the latch CK is level CK1, the latch D is level D1, and the latch QB is level QB0 at the relative position 3 in the waveform of FIG.

Here, for each latch to be inspected, the waveform comparison unit 14 uses the signal level of the terminal at each relative position at the frequency f1 in FIG. 3A and the relative position at the frequency f2 in FIG. 3B. The signal level of each terminal is compared for each corresponding relative position, and it is determined whether or not the transition of the signal level (that is, the waveform shape of the signal level at the terminal) is the same (or similar).
The waveform comparison unit 14 determines that the waveform shape in this latch is the same when the transition of the signal level at all the corresponding relative positions is the same in the simulation result waveform using the frequency f1 and the frequency f2.

Further, the waveform comparison unit 14 writes the determination result of the waveform shape comparison in the waveform comparison table provided for each circuit in the result storage unit 18. In this waveform comparison table, latch identification information indicating a latch and a determination result flag are stored in association with each other.
Here, the waveform comparison unit 14 adds a match flag indicating that the waveform shape is matched to the latch determination result flag whose waveform shape is matched as a result of the above-described waveform comparison processing, while the waveform shape is matched. A mismatch flag indicating that the waveform shape does not match is added to the determination result flag of the latch that is not.

Next, FIG. 4 is a diagram for explaining processing for extracting a setup margin time and a hold margin time as operation margins from waveforms between different frequencies in the margin comparison unit 15. In the present embodiment, the setup margin time is SETUP1, and the hold margin time is THOLD1 and THOLD2. In FIG. 4, the frequency relationship is the same as in FIG. 3, FIG. 4 (a) shows the waveform of the waveform data as a result of simulation at the frequency f1, and FIG. 4 (b) shows the waveform as a result of simulation at the frequency f2. The waveform of data is shown. Here, frequency f1> frequency f2.
In FIG. 4A, each of time tf1_4, time tf1_6, and time tf1_8 indicates the time indicating the period of the latch clock CK at the frequency f1, that is, the rising timing of the latch clock CK. Similarly, in FIG. 4B, each of the time tf2_4, the time tf2_6, and the time tf2_8 indicates a time indicating the cycle of the latch clock CK at the frequency f2, that is, a rising timing time of the latch CK.

Returning to FIG. 1, the margin comparison unit 15 reads waveform data at the time of simulation at the frequency f <b> 1 shown in FIG. 4A from the simulation result data in the result storage unit 18.
After the reading, the margin comparison unit 15 determines the hold margin time THOLD1 from the time tf1_4 to the signal level change time tf1_5 (rise in the drawing) from the waveform of FIG. Setup margin time TSETUP1 until and hold margin time THOLD2 from time tf1_6 to signal level change time tf1_7 (falling in the figure) of latch D are detected.

Similarly, the margin comparison unit 15 reads waveform data when a simulation is performed at the frequency f2 illustrated in FIG. 4B from the simulation result data in the result storage unit 18.
After the reading, the margin comparison unit 15 determines the hold margin time THOLD1 from the time tf2_4 to the change time tf2_5 of the signal level of the latch D and the setup margin time from the change time tf2_5 to the time tf2_6 from the waveform of FIG. TSETUP1 and hold margin time THOLD2 from time tf2_6 to signal level change time tf2_7 of latch D are detected.

Further, the margin comparison unit 15 extracts the hold margin time THOLD1, the hold margin time THOLD2, and the setup margin time TSETUP1 extracted from the waveform for each latch in frequency units, and extracts the result storage unit 18 in latch units in frequency units. Write and store in time table.
In this extraction time table, latch identification information and hold margin time THOLD1, hold margin time THOLD2, and setup margin time TSETUP1 are stored as a set of time data corresponding to the latch terminal indicated by the latch identification information in frequency units. Is done.

The latch operation determination unit 19 uses the waveform comparison result determined by the waveform comparison unit 14 and the hold margin time THOLD1, hold margin time THOLD2, and setup margin time TSETUP1 extracted from the waveform by the margin comparison unit 15. Whether the latch is a synchronous control data holding circuit that performs synchronous control for holding data with respect to an external clock, or an asynchronous control data holding circuit that does not perform synchronous control for holding data with respect to an external clock Judgment is made. Here, the latch operation determination unit 19 searches the determination result table of the result storage unit 18 for the latch identification information to which the mismatch flag is added.
Here, the latch operation determination unit 19 determines the latch indicated by the latch identification information loaded with the searched mismatch flag as an asynchronous control data holding circuit.
Then, the latch operation determination unit 19 writes and stores asynchronous control determination data as determination information in the latch to be inspected in the simulation result data in the result storage unit 18.

Further, the latch operation determination unit 19 searches the determination result table in the result storage unit 18 for the latch identification information to which the match flag is added as the determination result flag.
Then, the latch operation determination unit 19 reads the latch hold margin time THOLD1, the hold margin time THOLD2, and the setup margin time TSETUP1 indicated by the latch identification information searched in the determination result table from the extraction time table of the result storage unit 18.
After reading each time, the latch operation determination unit 19 determines whether the latch is a synchronous control data holding circuit or an asynchronous control data holding circuit, based on the read hold margin time THOLD1, hold margin time THOLD2, and The setup margin time TSETUP1 is used.

Next, in each of FIGS. 5, 6, 7 and 8, the latch operation determination unit 19 determines whether the latch is a synchronous control data holding circuit based on the frequency change of the setup margin time TSETUP or the hold margin time THOLD, or It is a figure of the process which determines whether it is an asynchronous control data holding circuit. 5, FIG. 6, FIG. 7 and FIG. 8 are respectively in the vicinity of the maximum operating frequency (spec max) in the operating frequency range in the specification, in the vicinity of the minimum operating frequency (spec min), and in the center of the operating frequency range (spec mid). The result of performing dynamic timing verification (circuit simulation) of the circuit at three different frequencies is shown. That is, FIG. 5, FIG. 6, FIG. 7 and FIG. 8 each show the correspondence between each different frequency and the corresponding margin value time (hold margin time THOLD1, hold margin time THOLD2, and setup margin time TSETUP1). FIG.
In each of FIGS. 5, 6, 7, and 8, the vertical axis indicates the setup margin time (tSETUP) or the hold margin time (tHOLD), and the horizontal axis indicates the reciprocal frequency (1 / f, that is, one period). Time).

FIG. 5 shows a fixed state in which each time of the margin value of the latch (hold margin time THOLD1, hold margin time THOLD2, and setup margin time TSETUP1) takes a constant value even when the frequency is different. There is no risk of timing violations at frequencies.
Therefore, when all of the hold margin time THOLD1, the hold margin time THOLD2, and the setup margin time TSETUP1 have the result of FIG. 5, the latch corresponding to these margin values is a synchronous control data holding circuit.
On the other hand, any one of the margin values of the hold margin time THOLD1, the hold margin time THOLD2, and the setup margin time TSETUP1 has a preset threshold (latch setup time or hold time). The latch corresponding to these margin values is an asynchronous control data holding circuit.

In FIG. 6, the latch margin values (hold margin time THOLD1, hold margin time THOLD2, and setup margin time TSETUP1) vary linearly in response to changes in frequency. Therefore, it is shown that it is possible to determine whether or not a margin value at a frequency within the operating frequency range in the specification is satisfied.
That is, in the case of FIG. 6, a straight line connecting the measurement points of the margin values at three different frequencies is obtained. Then, within the operating frequency range in the specification, it can be estimated that the obtained straight line intersects with the straight line indicating the margin value threshold and does not fall below this threshold (in this embodiment, as will be described later, the latch The operation determination unit 19 performs estimation processing).

Therefore, as shown in FIG. 6, when the hold margin time THOLD1, the hold margin time THOLD2, and the setup margin time TSETUP1 are all within the operating frequency range, the portion below the margin value threshold is not linear, that is, the operating frequency range. When the margin values within the threshold value exceed the threshold value, the latch corresponding to these margin values is a synchronous control data holding circuit.
On the other hand, if any one of the hold margin time THOLD1, the hold margin time THOLD2, and the setup margin time TSETUP1 falls below the threshold (setup time, hold time), the latch corresponding to the margin value is an asynchronous control data holding circuit.

In FIG. 7, as in FIG. 6, the latch margin values (hold margin time THOLD1, hold margin time THOLD2, and setup margin time TSETUP1) change linearly in response to changes in frequency. This indicates that it is possible to determine whether or not the margin value within the operating frequency range in the specification is satisfied. In the case of FIG. 7, a straight line connecting the measurement points of the margin values at three different frequencies is obtained. Then, it can be estimated that the obtained straight line intersects and falls below the straight line indicating the margin value threshold within the operating frequency range in the specification.
Therefore, as shown in FIG. 7, if any one of the hold margin time THOLD1, the hold margin time THOLD2, and the setup margin time TSETUP1 falls below the threshold value, the latch corresponding to the margin value is an asynchronous control data holding circuit. .

Since the latch margin values (hold margin time THOLD1, hold margin time THOLD2 and setup margin time TSETUP1) are not dependent on the linear change in frequency, the latch margin value shows the change in the vertical fluctuation. This indicates that it is impossible to determine whether or not the margin value is satisfied. Therefore, in the case of FIG. 8, the change of the margin value cannot be estimated from the line connecting the measurement points at three different frequencies within the operating frequency in the specification, and the margin value changes with respect to the frequency. Since it is unknown, it is estimated that the margin value is below any one.
Therefore, even if any one of the hold margin time THOLD1, the hold margin time THOLD2, and the setup margin time TSETUP1 corresponds to the change in frequency as shown in FIG. 8, the margin value does not change. The latch to be used is an asynchronous control data holding circuit.

Returning to FIG. 1, the latch operation determination unit 19 determines whether or not a straight line is formed by connecting the margin values of the simulated frequencies. Here, the latch operation determination unit 19 determines whether or not the line is a straight line based on whether or not the margin value increases with a certain width as the period time increases (frequency decreases).
That is, the latch operation determination unit 19 determines a straight line when the margin value changes linearly in response to an increase in frequency, and is not a straight line when the increase / decrease is repeated and does not change linearly as shown in FIG. To do.
In addition, the latch operation determination unit 19 determines a straight line even when the margin value is fixed with respect to an increase in frequency.

The latch operation determination unit 19 determines whether or not the line is a straight line, that is, whether or not the frequency and the margin value are in a linear relationship.
That is, the latch operation determination unit 19 detects whether or not the margin values measured at a plurality of different frequencies are on a straight line.
Then, as shown in FIG. 8, the latch operation determination unit 19 detects a latch having a signal level terminal as a margin value for performing increase / decrease without depending on a change in frequency, as shown in FIG. It is determined that

In addition, as shown in FIG. 5, when the margin value is fixed with respect to a change in frequency, that is, when the margin values measured at different frequencies are the same (including the same), the latch operation determining unit 19 It is determined whether or not the value exceeds the threshold value.
Here, when the margin value is below the threshold value, the latch operation determination unit 19 determines that the latch having the signal level terminal that becomes the margin value is the asynchronous control data holding circuit.

In addition, as shown in FIG. 7, when the margin value changes linearly with respect to the frequency change, the latch operation determination unit 19 determines whether the obtained margin value exceeds the threshold in the operating frequency range of the specification. Determine whether or not. Here, when the margin value in the frequency in the operating frequency range is below the threshold value, the latch operation determining unit 19 determines that the latch having the signal level terminal that becomes the margin value is the asynchronous control data holding circuit. .
Then, the latch operation determination unit 19 writes and stores asynchronous control determination data as determination information in the latch to be inspected in the simulation result data in the result storage unit 18.

Further, as shown in FIG. 5, the latch operation determination unit 19 has a fixed margin value even when the frequency changes as shown in FIG. 5, and the margin value does not fall below the threshold value, or FIG. As shown in FIG. 4, if the margin value is a linear value that changes linearly with respect to the change in frequency and does not fall below the threshold value in the operating frequency range, the latch is determined to be a synchronous control data holding circuit.
Then, the latch operation determination unit 19 writes and stores the synchronization control determination data as determination information in the latch to be inspected in the simulation result data in the result storage unit 18.

Next, with reference to FIG. 1 and FIG. 9, a determination process for determining whether the latch in the circuit of the semiconductor test apparatus according to the embodiment of the present invention is the synchronous control or the asynchronous control will be described. FIG. 9 is a flowchart showing an operation example of the synchronization determination process whether the latch in the circuit of the semiconductor test apparatus according to the embodiment of the present invention is the synchronous control or the asynchronous control.
At the start of the operation, the user operates the semiconductor test apparatus and designates a circuit that performs synchronization determination processing from an input device (not shown).
Step S1:
The latch extraction unit 12 reads the net list information of the circuit designated by the user from the circuit storage unit 16.
Then, the latch extraction unit 12 extracts the latch from the read netlist information based on the latch connection information stored in the internal storage unit.
After the extraction, the latch extraction unit 12 adds latch identification information for each extracted latch, and indicates the correspondence between the latch terminals and the cell terminals in the netlist information in correspondence with the latch identification information. Information is written and stored in the correspondence table of the result storage unit 18.

Step S2:
Next, the system control unit 11 causes each unit to sequentially execute circuit simulation and synchronization determination processing for each test pattern stored in the test pattern storage unit 17 and corresponding to the circuit specified by the user. In the test pattern storage unit 17, test pattern data for performing a dynamic test of the circuit in units of circuits corresponding to the net list information stored in the circuit storage unit 16 indicates the respective test patterns. Along with the pattern identification information, it is written and stored in advance.

Step S3:
Next, the simulator unit 13 reads the pattern identification information of the test pattern stored in the result storage unit 18, and extracts the test pattern from the test pattern corresponding to the circuit under test stored in the storage unit 17. Read test patterns other than pattern identification information.
In addition, since the test pattern identification information is not written in the result storage unit 18 at the first time of the processing loop, the simulator unit 13 reads out the first test pattern data stored in the test pattern storage unit 17. Further, the simulation unit 13 reads the latch information of the circuit under test from the result storage unit 18.
Then, the simulator unit 13 executes a dynamic test of the circuit under test based on the read test pattern data. At this time, in the dynamic test, the simulator unit 13 acquires the waveform data of the signal level at the terminal of the latch indicated by the latch information (actually, the terminal of the cell corresponding to the terminal of this latch).

At this time, the simulator unit 13 performs the frequency of the external clock for each of a plurality of different frequencies with respect to one test pattern.
For example, the first frequency near the lower limit frequency of the operating frequency range in the circuit specifications, the second frequency near the upper limit frequency, and the third frequency between the first frequency and the second frequency are used. The frequency relationship is such that the first frequency <the third frequency <the second frequency.

Step S4:
Then, as a result of the dynamic test, the simulator unit 13 uses the circuit identification information of the circuit as a unit, the simulation result data of the result storage unit 18, the waveform data of the terminals of each latch, the test pattern identification information, the frequency, Write and store in correspondence with the terminals of the latch.

Step S5:
Next, the system control unit 11 uses the waveform data corresponding to the pattern identification information of the current test pattern in the circuit under test stored in the simulation result data of the result storage unit 18 to synchronize each latch. The determination process is performed by each unit (the waveform comparison unit 14, the margin comparison unit 15, and the latch operation determination unit 19).

Step S6:
The waveform comparison unit 14 reads the latch waveform data for each frequency from the simulation result data in the result storage unit 18.
Here, the waveform comparison unit 14 obtains, from the simulation result data in the result storage unit 18, the waveform data of the latch corresponding to the latch identification information in which neither the match flag nor the mismatch flag is written for the determination result flag. read out.

The waveform comparison unit 14 compares the waveform data of each terminal for each latch between different frequencies, and has the same shape even if the waveform changes in frequency (similar signal level transitions are performed). Is determined for each terminal of the latch.
At this time, if the waveform comparison unit 14 determines that the waveforms indicated by the waveform data of all the terminals in the latch have the same shape and match, the waveform comparison unit 14 writes a match flag to the result determination flag, and the process proceeds to step S7. Proceed.
On the other hand, when the waveform indicated by the waveform data does not have the same shape in the latch and there is a terminal determined to be inconsistent, the waveform comparing unit 14 writes the inconsistency flag in the result determination flag, and the process proceeds to step S9. Proceed.

Step S7:
The margin comparison unit 15 reads the waveform data of each latch terminal for each frequency from the simulation result data in the result storage unit 18.
Here, the margin comparison unit 15 reads, from the simulation result data in the result storage unit 18, the waveform data of each terminal of the latch in which the match flag is written for the determination result flag.

The margin comparison unit 15 detects a setup margin time and a hold margin time for each input terminal of the latch.
That is, the margin comparison unit 15 detects the setup margin time and the hold margin time for each frequency from the waveform data of each input terminal (clock input terminal, data input terminal).
Then, the margin comparison unit 15 writes the setup margin time and hold margin time at each input terminal of the extracted latch into the extraction time table of the result storage unit 18 for each frequency in units of latches and stores them.

Next, when the latch operation determination unit 19 indicates a change in which the setup margin time or the hold margin time is increased or decreased with respect to the linear change in frequency (for example, a change exceeding a preset time width), it has already been described. Since it is the state of FIG. 8, it determines as follows.
That is, the latch operation determination unit 19 determines that the latch having an input terminal corresponding to the setup margin time or the hold margin time is an asynchronous control data holding circuit, and advances the processing to step S9.

  The latch operation determination unit 19 is a value in which the setup margin time (or hold margin time) is fixed without corresponding to a linear change in frequency due to the relationship between the frequency and the setup margin time (or hold margin time). When the fixed setup time falls below a preset threshold value (setup time, hold time), an asynchronous control data holding circuit includes a latch having an input terminal corresponding to the setup margin time (or hold margin time). Determination is made, and the process proceeds to step S9.

In addition, the latch operation determination unit 19 responds to a linear change in frequency from the relationship between the frequency and the setup margin time (or hold margin time), and the setup margin time (or hold margin time) similarly changes linearly. From the setup margin time (or hold margin time), a straight line is obtained as shown in FIGS.
Then, the latch operation determination unit 19 determines whether or not the straight line is less than the setup time (or hold time) of the latch as the threshold value of the setup margin time (or hold margin time) within the specified operating frequency range. Do.
At this time, as shown in FIG. 7, when the latch operation determination unit 19 detects that the straight line falls below the setup time (or hold time) as a threshold within the operating frequency range of the specification, the setup margin time (or The latch having the input terminal corresponding to (hold margin time) is determined as the asynchronous control data holding circuit, and the process proceeds to step S9.

On the other hand, as shown in FIG. 6, the latch operation determination unit 19 detects that both the setup margin time and the hold margin time exceed the setup time and the hold time as thresholds within the operating frequency range of the specification as shown in FIG. The latch having input terminals corresponding to both the setup margin time and the hold margin time is determined as the synchronization control data holding circuit, and the process proceeds to step S8.
Similarly, as shown in FIG. 5, the latch operation determination unit 19 is a value in which both the setup margin time and the hold margin time are fixed without corresponding to the linear change in frequency, and the fixed setup margin. When the time (or hold margin time) exceeds a setup time (or hold time) as a preset threshold, a latch having an input terminal corresponding to the setup margin time and the hold margin time is set as a synchronous control data holding circuit. And the process proceeds to step S8.
The latch operation determination unit 19 also corresponds to the setup margin time and the hold margin time when either the setup margin time or the hold margin time corresponds to FIG. 5 and the other corresponds to FIG. The latch having the input terminal is determined as the synchronization control data holding circuit, and the process proceeds to step S8.

Step S8:
Next, the latch operation determination unit 19 corresponds to the latch identification information of the latch determined to be the synchronization control data holding circuit, and indicates that it is a synchronization control data holding circuit for the latch of simulation result data in the result storage unit 18. The synchronization control determination data is written as determination information, and the process proceeds to step S10.

Step S9:
Next, the latch operation determination unit 19 corresponds to the latch identification information of the latch determined to be the asynchronous control data holding circuit, and indicates that it is an asynchronous control data holding circuit for the latch of simulation result data in the result storage unit 18. Asynchronous control determination data is written as determination information, and the process proceeds to step S10.

Step S10:
In the simulation result data stored in the result storage unit 18, the system control unit 11 latches corresponding to the latch identification information in which the determination information (information indicating the synchronous control data holding circuit or the asynchronous control data holding circuit) is not written. The presence or absence of is determined.
The system control unit 11 advances the process to step S5 when there is a latch in which the determination information is not written. On the other hand, there is no latch in which the determination information is not written (the control determination process for all the latches in the circuit is completed). If so, the process proceeds to step S11.

Step S11:
Next, in the operation test, the system control unit 11 determines whether or not all test patterns stored in the test pattern storage unit 17 and stored for the circuit designated by the user have been used.
At this time, the system control unit 11 advances the process to step S12 when all the test patterns are used, and advances the process to step S2 when there is an unused test pattern.
Here, the system control unit 11 extracts the pattern identification information stored in the circuit unit and compares it with the pattern identification information of the test pattern stored in the test pattern storage unit 17. It is determined that not all of them are used, and on the other hand, if they match, it is determined that all of the test patterns are used.

Step S12:
Next, the system control unit 11 counts the number of latches in the correspondence table in the result storage unit 18 and obtains the total number of latches which is the number of all latches in the circuit designated by the user.
Further, the system control unit 11 calculates the number of latches in which synchronous control determination data is written as determination information and the number of latches in which asynchronous control determination data is written as determination information in the simulation result data.

Here, when determination information is written between simulation result data based on a plurality of test patterns, the latches having the same latch identification information are counted (counted) as one.
In addition, the system control unit 11 includes the simulation result data based on a plurality of test patterns, when the synchronous control determination data is described in any test pattern and the asynchronous control determination data is described in any pattern. This latch is determined as an asynchronous control data holding circuit and counted as a latch of asynchronous control determination data.

Next, the system control unit 11 adds the number of latches in which the synchronous control determination data is written and the number of latches in which the asynchronous control determination data is written. Divide the number of latches in which the control determination data is written, and output the division result as an asynchronous verification coverage.
Then, the system control unit 11 counts the total number of latches, the number of latches of synchronous control determination data, the number of latches of asynchronous control determination data, and the asynchronous verification coverage ratio (ratio of latches for which synchronous determination processing is performed in all latches in the circuit). Is displayed on a display unit (not shown) of the semiconductor test apparatus.

  The system control unit 11 also includes a latch that is extracted from the netlist information but the test pattern is incomplete and the synchronization determination process has not been performed, and a latch in which the result of the synchronization determination process is determined to be an asynchronous control data holding circuit, Is notified to the user by using image information that can be identified on the circuit diagram shown in FIG. 2 displayed on the display unit of the semiconductor test apparatus. For example, the system control unit 11 displays each of the latch determined as the synchronous control data holding circuit, the latch determined as the asynchronous control data holding circuit, and the latch that has been extracted but has not been subjected to the synchronous determination process. Change the color.

The semiconductor test apparatus according to the present embodiment performs a dynamic test based on a test pattern on a circuit indicated by netlist information with an external clock having a different frequency, and changes the signal level of each latch terminal extracted from the netlist information to waveform data. Is stored in the result storage unit 18.
For this reason, according to the semiconductor test apparatus of the present embodiment, waveform data between different frequencies are compared, whether or not they show the same waveform shape, or the setup margin time associated with the frequency change of waveform data between different frequencies From the change state of (or hold margin time), the latch which is the asynchronous control data holding circuit can be detected with high accuracy from the latch in the circuit.

  Further, the semiconductor test apparatus according to the present embodiment was obtained by dynamic timing verification of the signal level of the terminal of the data holding circuit whose data holding is controlled by the external clock in the circuit for each of a plurality of external clocks having different frequencies. A simulation unit (simulation unit 13) that writes and stores the verification result as waveform data in the storage unit (result storage unit 18) for each frequency of the external clock, and the waveform data is read from the storage unit, and the signal at the terminal of the data holding circuit And a waveform comparison unit (waveform comparison unit) that compares the waveform of the level waveform between different frequencies of the external clock and determines whether the data holding circuit is synchronously controlled with respect to the external clock. Yes.

  The semiconductor test apparatus of this embodiment is a margin comparison that extracts the setup margin time and the hold margin time at the terminals of the data holding circuit at different frequencies from the waveform data of the data holding circuit determined by the waveform comparison unit to be synchronous control. Change of the setup margin time and the hold margin time from the setup margin time and the hold margin time at different frequencies, and the setup margin time and the hold margin time within the operating frequency. And a threshold value set in advance to determine whether the data holding circuit is a data holding circuit that is synchronously controlled with respect to the external clock (latch operation judging unit 19). And further.

  In the semiconductor test apparatus of the present embodiment, the latch operation determination unit (latch operation determination unit 19) changes the linearity of the frequency change between different frequencies in the relationship between the frequency and the setup margin time and the hold margin time. Correspondingly, when each of the setup margin time and the hold margin time has a change in linearity, each of the setup margin time and the hold margin time within the operating frequency is provided with a corresponding threshold value (setup time, hold time). It is determined whether or not the data holding circuit is synchronously controlled with respect to the external clock.

  In the semiconductor test apparatus of the present invention, the latch operation determination unit (latch operation determination unit 19) does not cope with frequency changes between different frequencies in the relationship between the frequency and the setup margin time and the hold margin time. If the frequency and / or the setup margin time and / or the hold margin time are fixed even if the frequency changes, the data holding circuit is controlled synchronously with the external clock depending on whether the fixed time exceeds the threshold. It is determined whether or not.

  In the semiconductor test apparatus of the present invention, the latch operation determination unit (latch operation determination unit 19) copes with a change in linearity of frequency change between different frequencies in the relationship between the frequency and the setup margin time and the hold margin time. If either or both of the setup margin time and hold margin time fluctuate up and down, the data holding circuit controls asynchronously with respect to the external clock regardless of whether the setup margin time or hold margin time exceeds the threshold. It is judged that it is.

The semiconductor test apparatus of this embodiment performs dynamic timing verification using a plurality of test patterns.
With the configuration described above, according to the present embodiment, the latch is designed to operate in synchronization with the external clock, and is controlled asynchronously with respect to the external clock without using human hands. It is possible to easily detect a latch in a circuit with high accuracy.

  Further, the program for realizing the function of the semiconductor test apparatus in FIG. 1 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into the computer system and executed, thereby executing the synchronization determination process. May be performed. Here, the “computer system” includes an OS and hardware such as peripheral devices.

Further, the “computer system” includes a homepage providing environment (or display environment) if a WWW system is used.
The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” dynamically holds a program for a short time like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. In this case, a volatile memory in a computer system serving as a server or a client in that case, and a program that holds a program for a certain period of time are also included. The program may be a program for realizing a part of the functions described above, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design and the like within a scope not departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 11 ... System control part 12 ... Latch extraction part 13 ... Simulator part 14 ... Waveform comparison part 15 ... Margin comparison part 16 ... Circuit memory | storage part 17 ... Test pattern memory | storage part 18 ... Result memory | storage part 19 ... Latch operation | movement determination part

Claims (8)

The verification result obtained by the dynamic timing verification of the signal level of the terminal of the data holding circuit whose data holding is controlled by the external clock in the circuit for each of a plurality of different external clocks is obtained for each frequency of the external clock. A simulation unit for writing and storing the waveform data in the storage unit;
Whether waveform data is read from the storage unit, the waveform shape of the signal level at the terminal of the data holding circuit is compared between different frequencies of the external clock, and the data holding circuit is synchronously controlled with respect to the external clock. A semiconductor test apparatus comprising: a waveform comparison unit that determines whether or not. A margin comparison unit that extracts a setup margin time and a hold margin time at a terminal of the data holding circuit for each different frequency from the waveform data of the data holding circuit determined that the waveform comparison unit is synchronous control;
A change in frequency of the setup margin time and the hold margin time is detected from each of the setup margin time and the hold margin time at different frequencies, and each of the setup margin time and the hold margin time within the operating frequency and a preset threshold value are detected. The latch operation determination unit for determining whether or not the data holding circuit is a data holding circuit that is synchronously controlled with respect to an external clock by comparison with Semiconductor test equipment. The latch operation determination unit,
When the setup margin time and the hold margin time each have a change in linearity corresponding to the change in the linearity of the frequency change between different frequencies in the relationship between the frequency and each of the setup margin time and the hold margin time, the operation Whether the data holding circuit is synchronously controlled with respect to the external clock according to whether each of the setup margin time and the hold margin time exceeds a threshold value corresponding to the set margin time and the hold margin time within the frequency. The semiconductor test apparatus according to claim 2, wherein: The latch operation determination unit,
The relationship between the frequency and each of the setup margin time and the hold margin time does not correspond to the frequency change between different frequencies, and either the setup margin time or the hold margin time or both of the frequencies change at any frequency. In the case of being fixed, it is determined whether or not the data holding circuit is synchronously controlled with respect to the external clock depending on whether or not the fixed time exceeds a threshold value. Item 4. The semiconductor test apparatus according to Item 3. The latch operation determination unit,
The relationship between the frequency and each of the setup margin time and the hold margin time does not correspond to the change in linearity of the frequency change between different frequencies, and either or both of the setup margin time and the hold margin time fluctuate up and down. In this case, it is determined that the data holding circuit is asynchronously controlled with respect to an external clock regardless of whether the setup margin time or the hold margin time exceeds a threshold value. The semiconductor test apparatus according to claim 4.   The semiconductor test apparatus according to claim 1, wherein the dynamic timing verification is performed using a plurality of test patterns. The simulation unit performs dynamic timing verification of the signal level of the terminal of the data holding circuit whose data holding is controlled by the external clock in the circuit for each of a plurality of external clocks having different frequencies, and the verification result is the frequency of the external clock. A simulation process for writing and storing waveform data in the storage unit every time,
The waveform comparison unit reads the waveform data from the storage unit, compares the waveform shape of the signal level at the terminal of the data holding circuit between the different frequencies of the external clock, and the data holding circuit And a waveform comparison process for determining whether or not the synchronization control is performed. Computer
Simulation of verifying the dynamic timing of the signal level of the latch terminal in the circuit for each of a plurality of external clocks of different frequencies, and writing and storing the verification result in the result storage unit as waveform data for each frequency of the external clock means,
Read the waveform data from the result storage unit, compare the waveform shape of the signal level at the terminal of the data holding circuit whose data holding is controlled by the external clock in the circuit between the different frequencies of the external clock, and the data holding circuit Is a program for functioning as a waveform comparison means that determines whether or not is synchronized with an external clock.

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