JP2013135189A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of reducing a leakage current in an inter-gate insulating film.SOLUTION: A nonvolatile semiconductor memory device includes: a gate insulating film 11A formed on a semiconductor substrate 10; a floating gate electrode 12A formed on the gate insulating film 11A; a silicon oxide film 13B formed on a top surface and side surfaces of the floating gate electrode 12A; an insulating film 13C formed on the silicon oxide film 13B and having a higher dielectric constant than the silicon oxide film; a silicon oxide film 13D formed on the insulating film 13C; a control gate electrode 14A formed on the silicon oxide film 13D. The film thickness of the silicon oxide film 13D on the top surface of the floating gate electrode 12A is thicker than that of the silicon oxide film 13D on the side surfaces of the floating gate electrode 12A.

Description

  Embodiments described herein relate generally to a nonvolatile semiconductor memory device.

  For example, a floating gate type NAND flash memory which is a nonvolatile semiconductor memory device is a stack in which a gate insulating film (tunnel insulating film), a floating gate electrode, a gate insulating film (inter-gate insulating film), and a control gate electrode are stacked. A memory cell having a gate structure is included. In this memory cell structure, the upper part of the floating gate electrode becomes thinner as the generation progresses, the electric field concentration on the upper part increases, and the leakage current in the inter-gate insulating film increases at the time of writing.

  For this reason, if the memory cell is miniaturized with the conventional structure, a large write voltage is applied, the tunnel current passing through the tunnel insulating film is increased, and the amount of electrons injected into the floating gate electrode is increased. The injected electrons escape to the control gate electrode due to the increased leakage current. For this reason, a memory cell having multiple values may be in a write saturation state where writing cannot be performed up to a threshold required for writing multiple values.

JP 2007-305966 A

  Provided is a nonvolatile semiconductor memory device capable of reducing leakage current in an inter-gate insulating film.

  A nonvolatile semiconductor memory device according to an embodiment is formed on a gate insulating film formed on a semiconductor substrate, a floating gate electrode formed on the gate insulating film, and an upper surface and a side surface of the floating gate electrode. A first silicon oxide film, an insulating film formed on the first silicon oxide film and having a dielectric constant higher than that of the silicon oxide film, and formed on the insulating film, and having a film thickness on the upper surface of the floating gate electrode. A second silicon oxide film thicker than a film thickness on a side surface of the floating gate electrode and a control gate electrode formed on the second silicon oxide film are provided.

1 is a plan view illustrating a configuration of a nonvolatile semiconductor memory device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line 2-2 in FIG. FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. 1. It is an energy band figure in the inter-gate insulating film (NONON film) between the floating gate electrode and the control gate electrode. It is an energy band figure in the insulating film between gates (NONO film) between the floating gate electrode and control gate electrode of a 1st embodiment. 6 is a cross-sectional view showing a method of manufacturing the memory cell array in the nonvolatile semiconductor memory device of the first embodiment. FIG. 6 is a cross-sectional view showing a method of manufacturing the memory cell array in the nonvolatile semiconductor memory device of the first embodiment. FIG. 6 is a cross-sectional view showing a method of manufacturing the memory cell array in the nonvolatile semiconductor memory device of the first embodiment. FIG. 6 is a cross-sectional view showing a method of manufacturing the memory cell array in the nonvolatile semiconductor memory device of the first embodiment. FIG. 6 is a cross-sectional view showing a method of manufacturing the memory cell array in the nonvolatile semiconductor memory device of the first embodiment. FIG. It is sectional drawing which shows the structure of the non-volatile semiconductor memory device of 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the memory cell array in the non-volatile semiconductor memory device of 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the memory cell array in the non-volatile semiconductor memory device of 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the memory cell array in the non-volatile semiconductor memory device of 2nd Embodiment.

  The nonvolatile semiconductor memory device of the embodiment will be described below with reference to the drawings. Here, a NAND flash memory is taken as an example of the nonvolatile semiconductor memory device. In the following description, components having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[First Embodiment]
[1] Configuration of Memory Cell Array FIG. 1 is a plan view showing a configuration of a memory cell array in the NAND flash memory according to the first embodiment. 2 is a cross-sectional view taken along line 2-2 in FIG. 1, and FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. 2 shows a cross section along the channel length direction (bit line direction) of the memory cell MC, and FIG. 3 shows a cross section along the channel width direction (word line direction) of the memory cell MC.

  As shown in FIG. 1, an element isolation region and an element region (active area) AA separated by the element isolation region are formed in the surface region of the semiconductor substrate 10. A plurality of element regions AA are arranged in the word line direction, and each of the element regions AA extends in the bit line direction. A plurality of memory cells MC and select transistors STD and STS are formed on the element region AA.

  The plurality of memory cells MC arranged on the element region AA are connected in series. Hereinafter, the plurality of memory cells MC connected in series are referred to as a memory cell string. Select transistors STD and STS are arranged at both ends of the memory cell string. Hereinafter, a configuration that further includes a memory cell string and select transistors STD and STS is referred to as a NAND cell unit.

  The word lines WL (WL1 to WLn) and the select gate lines SGL1 and SGL2 are arranged in the bit line direction, and each of them extends in the word line direction. That is, the word lines WL (WL1 to WLn) and the select gate lines SGL1 and SGL2 are arranged so as to be orthogonal to the element region AA.

  A plurality of NAND cell units are arranged in the word line direction. Each memory cell MC of the NAND cell unit is connected to a word line WL (WL1 to WLn). Here, the memory cells MC located in the word line direction are connected to a common word line WL. Further, the selection transistors STD and STS are connected to selection gate lines SGL1 and SGL2, respectively.

  One end of the NAND cell unit is connected to a bit line (not shown) extending in the same direction as the element region AA via a bit line contact BC. Furthermore, the other end of the NAND cell unit is connected to a source line (not shown) extending in the word line direction via a source line contact SC.

  Next, a cross-sectional structure of the memory cell array in the first embodiment will be described.

  As shown in FIGS. 2 and 3, the memory cell MC is a memory cell transistor having a stack gate structure in which a control gate electrode 14A is stacked on a floating gate electrode 12A.

  The semiconductor substrate 10 is provided with a well region (not shown), and the NAND cell unit is formed on the well region. In the surface region of the semiconductor substrate 10, an element isolation region 15 and an element region AA separated by the element isolation region 15 are arranged.

  On a semiconductor substrate (element region AA) 10, a memory cell MC comprising a gate insulating film 11A, a floating gate electrode 12A, an intergate insulating film 13T, and a control gate electrode 14A, a gate insulating film 11B, and a lower gate electrode 12B Select transistors STD and STS each including an inter-gate insulating film 13T and an upper gate electrode 14B are disposed.

  The gate insulating film 11A is formed on the element region AA. The gate insulating film 11A functions as a tunnel insulating film between the element region AA and the floating gate electrode 12A. Hereinafter, the gate insulating film 11A of the memory cell MC is referred to as a tunnel insulating film.

  The floating gate electrode 12A is formed on the tunnel insulating film 11A. The floating gate electrode 12A functions as a charge storage layer for holding data written in the memory cell MC. The floating gate electrode 12A is formed of, for example, a polysilicon film.

  In the plurality of memory cells MC arranged on the element region AA adjacent in the channel width direction (word line direction), the floating gate electrodes 12A are electrically connected by the element isolation region 15 embedded in the semiconductor substrate 10. Insulated. Here, the upper surface of the element isolation region 15 is set back toward the semiconductor substrate 10 with respect to the upper surface of the floating gate electrode 12A. That is, the upper surface of the element isolation region 15 is higher than the lower surface of the floating gate electrode 12A and is lower than the upper surface.

  An intergate insulating film 13T is formed on the upper surface of the floating gate electrode 12A, and an intergate insulating film 13S is formed on the side surface of the floating gate electrode 12A and on the element isolation region 15.

  The inter-gate insulating film 13T formed on the upper surface of the floating gate electrode 12A has a bottom silicon nitride film 13A, a bottom silicon oxide film 13B, and an insulating film (for example, a center silicon nitride film) from the floating gate electrode 12A side. 13C and the top silicon oxide film 13D are stacked in this order (so-called NONO film). “N” indicates a silicon nitride film, and “O” indicates a silicon oxide film.

  The inter-gate insulating film 13S formed on the side surface of the floating gate electrode 12A and on the element isolation region 15 has a bottom silicon nitride film 13A, a bottom silicon oxide film 13B, from the floating gate electrode 12A and element isolation region 15 side. An insulating film (for example, a center silicon nitride film) 13C, a top silicon oxide film 13D, and a top silicon nitride film 13E are stacked in this order (a so-called NONON film).

  The silicon oxide film 13D on the upper surface of the floating gate electrode 12 is thicker than the silicon oxide film 13D on the side surface of the floating gate electrode 12A and on the element isolation region 15.

The materials used for the inter-gate insulating films 13T and 13S are not limited to the materials described above, and other materials may be used. As the insulating film 13C, an insulating film (High-k film) having a dielectric constant higher than that of the silicon oxide film, for example, a silicon oxynitride film (SiON) or a metal oxide film is used in addition to the silicon nitride film (SiN) described above. Also good. Examples of the metal oxide film include aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), yttrium oxide (Y ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminate (LaAlO ₃ ), Examples thereof include hafnium aluminate (HfAlOx), tantalum oxide (Ta ₂ O ₅ ), and titanium oxide (TiO ₂ ). These materials are not limited to the composition ratio in parentheses.

  The intergate insulating film 13T has a four-layer structure (NONO film) on the upper surface of the floating gate electrode 12A, and the intergate insulating film 13S has a five-layer structure (NONON) on the side surface of the floating gate electrode 12A and on the element isolation region 15. However, the present invention is not limited to this. For example, a three-layer structure (ONO film) may be provided on the upper surface of the floating gate electrode 12A, and a four-layer structure (ONON film) may be provided on the side surface of the floating gate electrode 12A and on the element isolation region 15. Furthermore, you may have a multilayer structure other than these.

  The control gate electrode 14A is formed on the intergate insulating films 13T and 13S. That is, the control gate electrode 14A is disposed on the upper surface and the side surface of the floating gate electrode 12A via the intergate insulating films 13T and 13S, respectively. The control gate electrode 14A corresponds to the word line WL.

  For example, a silicide film is used for the control gate electrode 14A in order to reduce electric resistance. However, the control gate electrode 14A is not limited to a silicide film, and may have a single layer structure of a polysilicon film or a two-layer structure (polycide structure) in which a polysilicon film and a silicide film are stacked. As the silicide film, for example, a tungsten silicide film, a molybdenum silicide film, a cobalt silicide film, a titanium silicide film, a nickel silicide film, or the like is used.

  The control gate electrode 14A functions as a word line and is shared between adjacent memory cells MC. For this reason, the control gate electrode 14A is formed not only on the floating gate electrode 12A but also on the element isolation region 15.

  As shown in FIG. 2, a source / drain diffusion layer 16 </ b> A of the memory cell MC is formed in the semiconductor substrate 10. The source / drain diffusion layer 16A is formed in the element region AA on both sides of the memory cell MC, and is shared by adjacent memory cells MC. Thereby, a plurality of memory cells MC are connected in series to form one memory cell string.

  Select transistors STD and STS are formed at one end and the other end of a plurality of memory cells MC connected in series, that is, a memory cell string.

  The selection transistors STD and STS are formed in the same process as the memory cell MC. Therefore, the gate structure of the select transistors STD and STS has a structure in which the upper gate electrode 14B is stacked on the lower gate electrode 12B via the intergate insulating film 13. The lower gate electrode 12B has the same structure as the floating gate electrode 12A, and the upper gate electrode 14B has the same structure as the control gate electrode 14A.

  However, in the select transistors STD and STS, the inter-gate insulating film 13 has an opening. Lower gate electrode 12B and upper gate electrode 14B are electrically connected via an opening.

  A diffusion layer 16B is formed on the memory cell side of the selection transistor STD, and a diffusion layer 16D is formed on the opposite side. A diffusion layer 16B is formed on the memory cell side of the selection transistor STS, and a diffusion layer 16S is formed on the opposite side.

  The diffusion layers 16B, 16D, and 16S function as source / drain regions of the selection transistors STD and STS. The selection transistors STD and STS share the diffusion layer 16B with the adjacent memory cell MC. As a result, the plurality of memory cells MC and the select transistors STD and STS are connected in series in the element region AA, thereby forming a NAND cell unit.

  A selection transistor STD is arranged on the drain side of the NAND cell unit. The diffusion layer 16D of the selection transistor STD is connected to a bit line contact BC formed in the interlayer insulating film 17. The bit line contact BC is connected to the bit line BL through the metal wiring M0 and the via contact VC arranged in the interlayer insulating film 18.

  A selection transistor STS is arranged on the source side of the NAND cell unit. The diffusion layer 16S of the select transistor STS is connected to the source line SL via the source line contact SC formed in the interlayer insulating film 17.

  In the first embodiment, a bottom silicon nitride film 13A, a bottom silicon oxide film 13B, an insulating film (for example, a center silicon nitride film) 13C, and a top silicon oxide film 13D are formed on the upper surface of the floating gate electrode 12A. An inter-gate insulating film 13T stacked in order is formed, and a bottom silicon nitride film 13A, a bottom silicon oxide film 13B, an insulating film 13C, a top silicon oxide film 13D, and a top are formed on the side surface of the floating gate electrode 12A. The inter-gate insulating film 13S is formed in the order of the silicon nitride film 13E. The top silicon oxide film 13D on the upper surface of the floating gate electrode 12A is thicker than the top silicon oxide film 13D on the side surface of the floating gate electrode 12A. Thereby, in the memory cell of the first embodiment, the leakage current in the inter-gate insulating film can be reduced, and the writing saturation state in which writing cannot be performed to a necessary threshold value can be improved.

  The reason why the leakage current can be reduced and the write saturation state can be improved is as follows. For example, if the inter-gate insulating film in contact with the control gate electrode is a silicon nitride film, the silicon nitride film has a lower barrier height against holes compared to the silicon oxide film, so that the hole from the control gate electrode to the center silicon nitride film Injection is likely to occur. FIG. 4A shows an energy band diagram when the inter-gate insulating film is a NONON film. As can be seen from FIG. 4A, since the NONON film has a low barrier height against holes, the amount of holes injected from the control gate electrode to the center silicon nitride film is large, and the electrons and holes trapped in the center silicon nitride film are small. Recombination occurs, trap electrons in the center silicon nitride film are reduced, and leakage current in the inter-gate insulating film easily flows.

  On the other hand, when the inter-gate insulating film in contact with the control gate electrode 14A is not the silicon nitride film but the top silicon oxide film 13D as in the present embodiment, the barrier height against holes becomes high, and the control gate electrode 14A Less hole injection. FIG. 4B shows an energy band diagram when the inter-gate insulating film is a NONO film. As can be seen from FIG. 4B, in this case, the injection of holes is small, and the recombination of trap electrons and holes in the insulating film 13C is also small. For this reason, since the NONO film has a larger amount of trapped electrons in the insulating film 13C than the NONON film, the leakage current in the inter-gate insulating film can be reduced.

  Here, a large leak current is generated near the upper surface of the floating gate electrode 12A due to the concentration of the electric field. Therefore, the top silicon oxide film 13D is used instead of the silicon nitride film on the upper surface of the floating gate electrode 12A, and the thickness of the top silicon oxide film 13D is increased, thereby greatly increasing the leakage current in the inter-gate insulating film 13T. Can be reduced.

  In the first embodiment, the bottom silicon nitride film 13A, the bottom silicon oxide film 13B, the insulating film (for example, the center silicon nitride film) 13C, and the top silicon oxide film 13D are formed on the side surface of the floating gate electrode 12A. And the inter-gate insulating film (NONON film) stacked in the order of the top silicon nitride film 13E, the multi-value threshold distribution of the memory cell, which is generated when writing and erasing are repeated, is obtained. The spreading phenomenon can be suppressed.

  The phenomenon that the threshold distribution of the memory cell is widened can be suppressed for the following reason. For example, when the inter-gate insulating film in contact with the control gate electrode 14A on the side surface of the floating gate electrode 12A is a silicon oxide film, electrons trapped in the insulating film 13C are difficult to escape to the control gate electrode 14A side. For this reason, it becomes difficult to suppress the phenomenon in which each multi-value threshold distribution of the memory cell spreads.

  On the other hand, when the intergate insulating film 13S in contact with the control gate electrode 14A on the side surface of the floating gate electrode 12A is the top silicon nitride film 13E as in this embodiment, the electrons trapped in the insulating film 13C are It becomes easy to escape to the control gate electrode 14A side through the silicon nitride film 13E. For this reason, it is possible to suppress a phenomenon in which each multi-value threshold distribution is widened.

  In the first embodiment, since the leakage current in the intergate insulating film can be reduced, the thickness of the intergate insulating film can be reduced. The ability to reduce the thickness of the inter-gate insulating film has the following advantages.

  First, since the thickness of the inter-gate insulating film can be reduced, the coupling ratio between the floating gate electrode 12A and the control gate electrode 14A can be increased. Further, since the distance between the floating gate electrodes 12A in which the control gate electrode 14A is embedded can be increased, the control gate electrode 14A can be easily embedded between the floating gate electrodes 12A. Further, since the distance between the floating gate electrodes 12A in which the control gate electrode 14A is embedded can be increased, the volume of the control gate electrode 14A can be increased, and depletion of the control gate electrode 14A can be suppressed. In addition, since the inter-gate insulating film can be made thin, the floating gate electrode 12A can be made thin while maintaining the coupling ratio between the floating gate electrode 12A and the control gate electrode 14A.

  As described above, according to the present embodiment, the inter-gate insulating film in contact with the control gate electrode on the upper surface of the floating gate electrode is a silicon oxide film, and the film thickness is thicker than the silicon oxide film on the side surface of the floating gate electrode. By doing so, leakage current in the inter-gate insulating film can be reduced.

  Further, as an inter-gate insulating film disposed between the floating gate electrode and the control gate electrode, a NONO film is disposed on the upper surface of the floating gate electrode, and a NONON film is disposed on the side surface of the floating gate electrode, Leakage current in the inter-gate insulating film can be reduced without deteriorating the threshold distribution of the memory cell.

[2] Manufacturing Method of Memory Cell Array Next, a manufacturing method of the NAND flash memory according to the first embodiment will be described. 5 to 9 are cross-sectional views illustrating a method of manufacturing a memory cell array in the NAND flash memory according to the first embodiment.

  After forming a gate insulating film and a floating gate electrode on the semiconductor substrate, an insulating film (element isolation region) is embedded between the element regions AA and between the floating gate electrodes. The gate insulating film and the element isolation region are formed from, for example, a silicon oxide film, and the floating gate electrode is formed from, for example, a polysilicon film.

  In the structure described above, first, as shown in FIG. 5, the element isolation region 15 is etched back by etching back, and the element isolation region 15 is moved backward. Thereby, the upper surface and side surfaces of the floating gate electrode 12A are exposed.

  Subsequently, the upper surface and side surfaces of the floating gate electrode 12A and the surface of the element isolation region 15 are nitrided, and silicon nitride is applied to the upper surface and side surfaces of the floating gate electrode 12A and the upper surface of the element isolation region 15 as shown in FIG. A film 13A is formed.

  Next, as shown in FIG. 7, a silicon oxide film 13B, a silicon nitride film 13C, and a silicon oxide film 13D are formed in this order on the silicon nitride film 13A. Further, as shown in FIG. 8, the surface of the silicon oxide film 13D is nitrided to form a silicon nitride film 13E on the silicon oxide film 13D.

  Next, anisotropic oxidation is performed on the silicon nitride film 13E on the upper surface of the floating gate electrode 12A, and the silicon nitride film 13E on the upper surface of the floating gate electrode 12A is oxidized to form silicon oxide as shown in FIG. Replace with a membrane. As a result, the silicon oxide film 13D disposed on the silicon nitride film 13C on the upper surface of the floating gate electrode 12A is thicker than the silicon oxide film 13D on the silicon nitride film 13C on the side surface of the floating gate electrode 12A. . In the anisotropic oxidation, for example, plasma oxidation or oxygen (O) ion implantation oxidizes only the upper surface of the floating gate electrode 12A and does not oxidize the side surface.

  Thereafter, on the structure shown in FIG. 9, that is, on the silicon oxide film 13D on the upper surface of the floating gate electrode 12A and on the side surface of the floating gate electrode 12A and on the silicon nitride film 13E on the element isolation region 15. As shown in FIG. 5, the control gate electrode 14A is formed. Thus, the NAND flash memory according to the first embodiment is manufactured.

  As described above, in the manufacturing method of the present embodiment, the following steps are used. As shown in FIG. 8, a NONON film is formed on the top and side surfaces of the floating gate electrode 12A. Thereafter, the uppermost silicon nitride film 13E on the upper surface of the floating gate electrode 12A is oxidized by anisotropic oxidation to be replaced with a silicon oxide film. Thereby, the film thickness of the uppermost silicon oxide film on the upper surface of the floating gate electrode 12A can be made larger than the film thickness of the uppermost silicon oxide film on the side surface of the floating gate electrode.

[Second Embodiment]
In the second embodiment, an example in which an inter-gate insulating film having a three-layer structure (ONO film) is formed between a floating gate electrode and a control gate electrode will be described.

[1] Configuration of Memory Cell Array FIG. 10 is a cross-sectional view showing the configuration of the memory cell array in the NAND flash memory according to the second embodiment.

  In the surface region of the semiconductor substrate 10, an element isolation region 15 and an element region AA separated by the element isolation region 15 are arranged. On the semiconductor substrate (element region AA) 10, a memory cell MC is disposed in which a gate insulating film (tunnel insulating film) 11A, a floating gate electrode 12A, an inter-gate insulating film 13F, and a control gate electrode 14A are stacked in this order. ing.

  An inter-gate insulating film 13F is formed on the top and side surfaces of the floating gate electrode 12A and on the element isolation region 15.

  The intergate insulating film 13F is laminated in the order of the bottom silicon oxide film 13B, the insulating film (for example, the center silicon nitride film) 13C, and the top silicon oxide film 13D from the floating gate electrode 12A and the element isolation region 15 side. A laminated film (so-called ONO film). The silicon oxide film 13D on the upper surface of the floating gate electrode 12A is thicker than the silicon oxide film 13D on the side surface of the floating gate electrode 12A and on the element isolation region 15. Other configurations are the same as those of the first embodiment.

  In the second embodiment, the inter-gate insulating film 13F is formed by laminating the bottom silicon oxide film 13B, the center silicon nitride film 13C, and the top silicon oxide film 13D in this order on the top and side surfaces of the floating gate electrode 12A. The top silicon oxide film 13D on the upper surface of the floating gate electrode 12A is thicker than the top silicon oxide film 13D on the side surface of the floating gate electrode 12A. Thereby, in the memory cell according to the second embodiment, the leakage current in the inter-gate insulating film 13F can be reduced, and the write saturation state in which writing cannot be performed up to a necessary threshold can be improved.

  As described above, according to the present embodiment, the inter-gate insulating film in contact with the control gate electrode on the upper surface of the floating gate electrode is a silicon oxide film, and the film thickness is thicker than the silicon oxide film on the side surface of the floating gate electrode. By doing so, leakage current in the inter-gate insulating film can be reduced.

[2] Manufacturing Method of Memory Cell Array Next, a manufacturing method of the NAND flash memory according to the second embodiment will be described. 11 to 13 are cross-sectional views illustrating a method of manufacturing a memory cell array in the NAND flash memory according to the second embodiment.

  Similar to the first embodiment, first, as shown in FIG. 11, the element isolation region 15 is etched back by etch back, and the element isolation region 15 is made to recede. Thereby, the upper surface and side surfaces of the floating gate electrode 12A are exposed.

  Subsequently, as shown in FIG. 12, a silicon oxide film 13B, a silicon nitride film 13C, and a silicon oxide film 13D are sequentially formed on the upper surface and side surfaces of the floating gate electrode 12A and on the element isolation region 15.

  Next, anisotropic oxidation is performed on the silicon oxide film 13D on the upper surface of the floating gate electrode 12A to increase the thickness of the silicon oxide film 13D on the upper surface of the floating gate electrode 12A. As a result, the silicon oxide film 13D disposed on the silicon nitride film 13C on the upper surface of the floating gate electrode 12A is thicker than the silicon oxide film 13D on the silicon nitride film 13C on the side surface of the floating gate electrode 12A. . Other steps are the same as those in the first embodiment.

  As described above, in the manufacturing method of the embodiment, the following steps are used. As shown in FIG. 12, an ONO film is formed on the upper surface and side surfaces of the floating gate electrode 12A. Thereafter, the uppermost silicon oxide film 13D on the upper surface of the floating gate electrode 12A is thickened by anisotropic oxidation. Thereby, the film thickness of the uppermost silicon oxide film on the upper surface of the floating gate electrode 12A can be made larger than the film thickness of the uppermost silicon oxide film on the side surface of the floating gate electrode.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11A, 11B ... Gate insulating film, 12A ... Floating gate electrode, 12B ... Lower gate electrode, 13F, 13S, 13T ... Inter-gate insulating film, 13A ... Bottom silicon nitride film, 13B ... Bottom silicon oxide Film, 13C ... Insulating film, 13D ... Top silicon oxide film, 13E ... Top silicon nitride film, 14A ... Control gate electrode, 14B ... Upper gate electrode, 15 ... Element isolation region, 17, 18 ... Interlayer insulating film, AA ... element region (active area), BC ... bit line contact, BL ... bit line, MC ... memory cell, SGL1, SGL2 ... selection gate line, STD, STS ... selection transistor, VC ... via contact, WL, WL1-WLn ... Word line.

Claims (5)

A gate insulating film formed on a semiconductor substrate;
A floating gate electrode formed on the gate insulating film;
A first silicon oxide film formed on an upper surface and a side surface of the floating gate electrode;
An insulating film formed on the first silicon oxide film and having a dielectric constant higher than that of the silicon oxide film;
A second silicon oxide film formed on the insulating film, the film thickness on the upper surface of the floating gate electrode being thicker than the film thickness on the side surface of the floating gate electrode;
A control gate electrode formed on the second silicon oxide film;
A non-volatile semiconductor memory device comprising:   The nonvolatile semiconductor memory device according to claim 1, further comprising a silicon nitride film formed on the second silicon oxide film on a side surface of the floating gate electrode.   The nonvolatile semiconductor memory device according to claim 1, further comprising a silicon nitride film disposed between an upper surface and a side surface of the floating gate electrode and the first silicon oxide film.   4. The nonvolatile semiconductor memory according to claim 1, wherein the insulating film on the first silicon oxide film includes any one of a silicon nitride film, a silicon oxynitride film, and a metal oxide film. apparatus.   The nonvolatile metal according to claim 4, wherein the metal oxide film includes any one of aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, lanthanum aluminate, hafnium-aluminate, tantalum oxide, and titanium oxide. Semiconductor memory device.

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