JP2011066348A - Three-dimensional laminate nonvolatile semiconductor memory, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To relax an electric field applied to a tunnel insulating film formed nearby a corner part of a control gate electrode. <P>SOLUTION: A three-dimensional laminate nonvolatile semiconductor memory includes a semiconductor layer, a columnar semiconductor region 101 which is formed on the semiconductor layer and perpendicular to the semiconductor layer, a first insulating film 102 formed on a side face of the semiconductor region 101, a charge accumulation film 103 formed on a side face of the first insulating film 102, a second insulating film 104 formed on a side face of the charge accumulation film 103, a plurality of control gate electrodes 105 formed in a flat plate shape parallel to the semiconductor layer in contact with a side face of the second insulating film 104, and a third insulating film 106 formed on respective side faces of the second insulating film 104 and the control gate electrodes 105, wherein the distance of the third insulating film 106 opposed across the semiconductor region 101 is longer than the distance of the control gate electrodes 105 opposed across the semiconductor region 101, and corner parts of the control gate electrodes 105 have curvature. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a three-dimensional stacked nonvolatile semiconductor memory, and more particularly to a three-dimensional stacked nonvolatile semiconductor memory having a curvature at a corner of a control gate electrode and a method for manufacturing the same.

  A BiCS (Bit Cost Scalable) technique is known as a technique for increasing the capacity by a three-dimensional structure and suppressing the bit cost.

  Non-volatile semiconductor memory to which BiCS technology is applied (hereinafter referred to as BiCS memory) is not just a three-dimensional structure, but is proportional to an increase in the number of stacked layers due to device structure and process technology. It enables bit cost scalability that reduces bit cost.

  In the cross section when the cell string of the BiCS memory is cut in the vertical direction, the corners of the control gate electrode are substantially perpendicular (see, for example, Patent Document 1).

  During a write operation, a strong electric field is applied to the tunnel insulating film formed near the corner of the control gate electrode, so that electrons are locally held in the charge storage film formed near the corner of the control gate electrode. End up. For this reason, the charge density in the charge storage film becomes non-uniform. In this case, electrons held in the charge storage film formed in the vicinity of the corner of the control gate electrode easily move out of the influence of the control gate electrode by moving in the charge storage film when the channel is turned on / off. . As a result, the threshold value of the memory cell changes, and there is a problem that the Data Retention characteristic is deteriorated.

  Furthermore, when the electric field concentrates on the corner of the control gate electrode, the insulating property of the insulating film formed in the vicinity of the corner of the control gate electrode is deteriorated, and the endurance characteristic is also deteriorated.

JP 2007-266143 A

  The present invention relates to a three-dimensional stacked nonvolatile semiconductor memory formed so as to have a curvature at a corner of a control gate electrode and to alleviate an electric field applied to a tunnel insulating film formed in the vicinity of the corner of the control gate electrode, and a method for manufacturing the same Is to propose.

  A three-dimensional stacked nonvolatile semiconductor memory according to an example of the present invention is formed on a semiconductor layer, a columnar semiconductor region formed on the semiconductor layer and perpendicular to the semiconductor layer, and on a side surface of the semiconductor region. A first insulating film; a charge storage film formed on a side surface of the first insulating film; a second insulating film formed on a side surface of the charge storage film; and a side surface of the second insulating film. A plurality of control gate electrodes formed in contact with and parallel to the semiconductor layer, and a third insulating film formed on the surface of each of the second insulating film and the control gate electrode, The distance between the third insulating films opposed via the semiconductor region is longer than the distance between the first control gate electrodes opposed via the semiconductor region, and the corner of the control gate electrode has a curvature. have.

A method of manufacturing a three-dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a step of forming a stacked film in which control gate electrodes and first insulating films are alternately stacked on a surface of a semiconductor layer, Etching to form a hole exposing the semiconductor layer; forming a second insulating film on the inner wall of the hole; forming a charge storage film on the inner wall of the second insulating film;
Forming a third insulating film on the inner wall of the charge storage film; and forming a semiconductor region so as to fill the hole in the inner wall of the third insulating film, and forming the hole And a step of rounding corners of the control gate electrode on the semiconductor region side after the formation of the charge storage film.

  A method of manufacturing a three-dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a step of forming a stacked film in which control gate electrodes and first insulating films are alternately stacked on a surface of a semiconductor layer, Etching to form a hole in which the semiconductor layer is exposed; forming a second insulating film having a thicker film on the surface of the stacked film in the hole; the farther from the semiconductor layer, the control gate electrode, Etching a first insulating film and a second insulating film, rounding corners of the control gate electrode, forming a second insulating film on an inner wall of the hole, and an inner wall of the second insulating film Forming a charge storage film on the substrate, forming a third insulating film on the inner wall of the charge storage film, and forming a semiconductor region so as to embed the hole in the inner wall of the third insulating film; It comprises.

  According to the present invention, the electric field applied to the tunnel insulating film formed near the corner of the gate electrode is relaxed by forming the corner of the gate electrode to have a curvature.

The figure which shows the BiCS memory concerning 1st Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 1st Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 1st Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 1st Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 1st Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 1st Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 1st Embodiment. The figure which shows the BiCS memory concerning 2nd Embodiment. The figure which shows the result of having calculated the electric field strength in the insulating film between conductors. The figure which shows the result of having calculated the hole diameter dependence of the semiconductor region in the electric field strength in an insulating film between conductors. The figure which shows the BiCS memory concerning the modification of 2nd Embodiment. The figure which shows the result of having calculated the electric field strength in the insulating film between conductors. The figure which shows the manufacturing process of the BiCS memory concerning 2nd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 2nd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 2nd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 2nd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 2nd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 2nd Embodiment. The figure which shows the BiCS memory concerning 3rd Embodiment. The figure which shows the BiCS memory concerning the modification of 3rd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 3rd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 3rd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 3rd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 3rd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 3rd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning 3rd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning the modification of 3rd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning the modification of 3rd Embodiment. The figure which shows the manufacturing process of the BiCS memory concerning the modification of 3rd Embodiment.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

1. Embodiment
(1) First Embodiment (1-1) Device Structure FIG. 1A is a bird's-eye view showing one memory cell in a BiCS memory. FIG.1 (b) is sectional drawing along the AA line of Fig.1 (a). Further, it is assumed that the channel width of the memory cell is about 50 nm and the interval between adjacent memory cells is also about 50 nm.

  1 includes a tunnel insulating film 102 (first insulating film), a charge storage film 103 formed of an insulating film, and a charge blocking film 104 (second insulating film) on the outer periphery of a cylindrical semiconductor region 101. ) Are formed in order. Further, a control gate electrode 105 isolated from each other by an inter-cell insulating film 106 (third insulating film) is formed on the outer periphery thereof. Therefore, the memory cell in the first embodiment has a MONOS structure.

  Further, as shown in FIG. 1B, the distance between the control gate electrodes 105 opposed via the semiconductor region 101 is wider than the distance between the inter-cell insulating films 106 opposed via the semiconductor region 101. . Therefore, the control gate electrode 105 is formed so as to protrude into the semiconductor region 101 as compared with the inter-cell insulating film 106. Hereinafter, the portion protruding into the semiconductor region 101 is defined as an end portion of the control gate electrode 105.

  Although omitted in FIG. 1, the lower portion of the semiconductor region 101 is connected to the semiconductor substrate via the source diffusion layer and the source line side select gate line, and the upper portion of the semiconductor region 101 is connected to the bit line.

  The semiconductor region 101 has, for example, silicon as a main component.

  The tunnel insulating film 102 is, for example, a silicon oxide film containing silicon and oxygen as main components, or a silicon oxynitride film containing silicon, oxygen, and nitrogen as main components, and has a film thickness of 2 nm to 7 nm, for example. .

  The charge storage film 103 is, for example, a silicon nitride film containing silicon and nitrogen as main components, and has a film thickness of, for example, 1 nm to 9 nm.

  The charge blocking film 104 is, for example, an alumina film containing aluminum and oxygen as main components, a silicon oxide film containing silicon and oxygen as main components, or a silicon oxynitride film containing silicon, oxygen, and nitrogen as main components. Yes, the film thickness is, for example, 8 nm to 20 nm.

  Further, the control gate electrode 105 is, for example, a silicon film doped with impurities or tantalum nitride.

  The inter-cell insulating film 106 is, for example, a silicon oxide film containing silicon and oxygen as main components.

  In the end portion of the control gate electrode 105 of the first embodiment, the corner portion has a curvature. That is, the corner portion of the control gate electrode 105 has a rounded structure. This can alleviate the concentration of the electric field on the tunnel insulating film 102 near the corner of the control gate electrode 105. For this reason, it is possible to suppress the localization of electrons in the charge storage film 103 formed in the vicinity of the corner of the control gate electrode 105 during the write operation. Therefore, even if electrons move in the charge storage film when the channel is turned on / off, the number of electrons that escape from the influence of the control gate electrode 105 is reduced, and fluctuations in the threshold value of the memory cell can be suppressed. . As a result, deterioration of Data Retention can be suppressed.

  Furthermore, since the electric field applied to the tunnel insulating film 102 formed in the vicinity of the corner portion of the control gate electrode 105 is relaxed, the deterioration of the insulating property of the tunnel insulating film 102 is suppressed.

(1-2) Manufacturing Method Hereinafter, a manufacturing method of the BiCS memory according to the first embodiment will be described with reference to FIGS.

  2 (a) to 7 (a) are cross-sectional views in which the region where the cell unit of the BiCS memory is formed is cut in the vertical direction, and FIGS. 2 (b) to 7 (b). Each shows a plan view of the region shown in FIGS. 2 (a) to 7 (a).

  First, as shown in FIG. 2, the surface of the semiconductor layer 100 is made of a silicon oxide film, for example, by a CVD (Chemical Vapor Deposition) method, and is formed of an inter-cell insulating film 106 having a thickness of 50 nm and a silicon film doped with impurities. Thus, the control gate electrodes 105 having a thickness of 50 nm are alternately deposited to form a multi-layered structure. Although FIG. 2 shows the case where the control gate electrode 105 has two layers, any number of layers may be formed in this multiple stacked structure. Further, it is assumed that a source diffusion layer and a source line side select gate line are formed in the semiconductor layer 100.

  The control gate electrode 105 may be tungsten and silicon silicide. In this case, the etching chemical may be the same as the silicon film.

  Next, as shown in FIG. 3, for example, the control gate electrode 105 and the inter-cell insulating film 106 are selectively etched by an RIE (Reactive Ion Etching) method using a resist mask to expose the surface of the semiconductor layer 100. Let Thereby, for example, a cylindrical groove 111 having a diameter of about 60 nm is formed in the multi-layered structure.

  Next, as shown in FIG. 4, after etching by the RIE method, for example, cleaning is performed using a dilute hydrofluoric acid (dHF) chemical solution. At this time, the inter-cell insulating film 106 facing the cylindrical groove 111 is scraped, and the inter-cell insulating film facing the cylindrical groove 111 is recessed compared to the end of the control gate electrode 105. Become. Further, the inter-cell insulating film 106 may be etched by wet etching using dilute hydrofluoric acid to be further recessed.

  Next, as shown in FIG. 5, the control gate electrode 105 is wet-etched using, for example, KOH or NaOH as an etchant. By this isotropic wet etching, the corner of the control gate electrode 105 is rounded and has a curvature.

  Next, as shown in FIG. 6, on the inner wall of the cylindrical groove 111, for example, an ALD (Atomic Layer Deposition) method is used to form a 15 nm-thick charge blocking film made of an alumina film mainly composed of aluminum and oxygen. 104 is deposited, and then a charge storage film 103 made of a silicon nitride film and having a thickness of 3 nm is deposited. Thereafter, a tunnel insulating film 102 made of a silicon oxide film and having a thickness of 5 nm is deposited.

  Next, as shown in FIG. 7, the tunnel insulating film 102, the charge storage film 103, and the charge block film 104 formed on the bottom surface of the cylindrical groove 111 are selectively etched by RIE using a resist mask. Then, the surface of the semiconductor layer 100 is exposed. Thereafter, for example, a silicon film 107 doped with an impurity serving as a channel region is deposited by CVD, and then heat treatment is performed in a nitrogen atmosphere at 600 ° C. Thereafter, a wiring layer or the like is formed using a known technique, and the BiCS memory according to the first embodiment is completed.

  Here, as another manufacturing method for rounding the corners of the control gate electrode 105, both the control gate electrode 105 and the inter-cell insulating film 106 may be etched simultaneously using hot phosphoric acid. In this case, since the etching rate of the inter-cell insulating film 106 is higher than that of the control gate electrode 105, the corner of the control gate electrode 105 can be rounded in one step.

  Further, as another manufacturing method for rounding the corners of the control gate electrode 105, the inter-cell insulating film 106 is first etched by etching using a diluted hydrofluoric acid chemical solution. Thereafter, oxidation treatment is performed in a high-temperature oxygen atmosphere or a radical oxygen atmosphere to oxidize corner portions of the control gate electrode 105. Thereafter, the corners of the control gate electrode 105 may be rounded by wet etching using dilute hydrofluoric acid. In this case, the oxide concentration of the inter-cell insulating film 106 is increased by performing high temperature oxidation treatment. Therefore, the withstand voltage of the inter-cell insulating film 106 is improved.

  Furthermore, as another manufacturing method for rounding the corners of the control gate electrode 105, after the charge blocking film 104 is formed, oxidation treatment is performed in a high-temperature oxygen atmosphere or a radical oxygen atmosphere. By this oxidation treatment, a silicon oxide film is formed at the corner of the control gate electrode 105, and the corner of the control gate electrode 105 is rounded. Accordingly, since the charge blocking film 104 of the control gate electrode 105 is formed thick, the insulating property at the corners is improved.

(2) Second Embodiment (2-1) Device Structure FIG. 8A is a bird's-eye view showing one memory cell of a BiCS memory. In FIG. 8B, the channel width of the memory cell transistor is assumed to be about 50 nm, and the distance between adjacent memory cells is assumed to be about 50 nm.

  In the memory cell of FIG. 8, a columnar semiconductor region 201 is formed in the vertical direction. A tunnel insulating film 202, a charge storage film 203, and a charge block film 204 are sequentially formed on the outer periphery of the semiconductor region 201. Further, a control gate electrode 205 isolated from each other by an inter-cell insulating film 206 is formed on the outer periphery.

  Here, since the configurations of the semiconductor region 201, the tunnel insulating film 202, the charge storage film 203, the charge block film 204, the control gate electrode 205, and the inter-cell insulating film 206 are the same as those in the first embodiment, Detailed description is omitted.

  Further, as shown in FIG. 8B, the distance between the control gate electrodes 205 opposed via the semiconductor region 201 is wider than the distance between the inter-cell insulating films 206 opposed via the semiconductor region 201. . Therefore, the control gate electrode 205 is formed so as to protrude into the semiconductor layer as compared with the inter-cell insulating film 206. Hereinafter, as in the first embodiment, a portion protruding into the semiconductor region 201 is defined as an end portion of the control gate electrode 205.

  In the second embodiment, the entire end portion of the control gate electrode 205 has a curvature. Therefore, the end portion of the control gate electrode 205 has a rounded structure.

  By adopting the structure as described above, the concentration of the electric field at the corners of the memory cell is mitigated as in the first embodiment. Therefore, it is possible to suppress the localization of electrons in the charge storage film 203 formed in the vicinity of the corner of the control gate electrode 205. Further, since the entire end portion of the control gate electrode 205 has a curvature, the electric field applied to the tunnel insulating film 202 is made uniform. Therefore, the charge density in the charge storage film 203 of the memory cell is made uniform. As a result, deterioration of Data Retention is suppressed.

  Further, as in the first embodiment, there is a feature that the deterioration of the insulating property of the tunnel insulating film 202 formed in the vicinity of the corner of the control gate electrode 205 is suppressed.

  Here, in the BiCS memory, in order to increase the degree of integration of the memory cells, it is necessary to reduce the hole diameter of the semiconductor layer formed in a columnar shape. However, in the conventional control gate electrode 205, a strong electric field is applied to the tunnel insulating film in the memory cell as the hole diameter is reduced. Therefore, even if a weak voltage for reading data from the memory cell is applied to the control gate electrode 205, there is a problem that a strong electric field is applied to the tunnel insulating film and erroneous writing is performed.

  However, in the second embodiment, the average of the tunnel insulating film 202 in the vicinity of the semiconductor region 201 is compared with the conventional case in which the end of the control gate electrode 205 is squared by rounding the entire end of the control gate electrode 205. The electric field can be weakened.

  Here, FIG. 9 shows a result of calculating the electric field strength in the inter-conductor insulating film when the entire control gate electrode 205 is rounded.

  As shown in FIG. 9A, the curvature of the control gate electrode 205 is represented by R, and the distance between the conductors (the sum of the film thicknesses of the tunnel insulating film 202, the charge storage layer 203, and the block insulating film 204) is represented by ToX. The electric field strength in the vicinity of the gate electrode 205 is used as a reference, and the electric field strength and the relative position X / ToX in the film thickness direction when it is set to 1. FIG. 9B shows the relationship between the electric field strength ratio and the total position in the film thickness direction. As shown in FIG. 9B, the electric field strength at X / ToX = 1 is reduced by providing the curvature. FIG. 9B also shows that the electric field strength decreases as the curvature increases.

  FIG. 10 shows the calculation result of the hole diameter dependence of the semiconductor region 201 in the electric field strength in the inter-conductor insulating film. As shown in FIG. 10A, the hole radius of the semiconductor region 201 is represented by R ′, and the distance between conductors (the sum of the film thicknesses of the tunnel insulating film 202, the charge storage layer 203, and the block insulating film 204) is represented by ToX. FIG. 10B shows the relationship between R ′ / Tox and the electric field strength in the vicinity of the semiconductor region 201 when R ′ / ToX = 5 is a reference and the relative position X / ToX = 1 in the film thickness direction. . As shown in FIG. 10B, the electric field strength near the channel silicon increases as the memory hole diameter R ′ decreases.

  Therefore, in the second embodiment, even when the hole diameter of the semiconductor region 201 is reduced by rounding the entire end portion of the control gate electrode 205, erroneous writing does not occur when data is read from the memory cell. Another feature is that the degree of integration can be improved.

(2-2) Modification Hereinafter, a modification according to the second embodiment will be described.

  FIG. 11A is a bird's eye view showing one memory cell in the BiCS memory. FIG. 11B is a cross-sectional view of the memory cell along the line AA in FIG.

  In the modification according to the second embodiment, the end of the control gate electrode 205 has a structure with a smaller curvature toward the center of the end. That is, the center of the end has a flatter structure. As a result, the concentration of the electric field at the corners of the memory cell is suppressed as in the second embodiment. Therefore, it can be suppressed that electrons are localized in the charge storage film 203 formed in the vicinity of the corner of the control gate electrode 205. Further, the end portion of the control gate electrode 205 has a structure having a curvature as a whole, and the electric field applied to the tunnel insulating film 202 is made uniform. Therefore, the charge density in the charge storage film 203 of the memory cell is made uniform. As a result, deterioration of Data Retention is suppressed.

  In addition, since the deterioration of the tunnel insulating film 202 formed in the vicinity of the corner portion of the control gate electrode 205 is suppressed, the endurance characteristics of the memory cell are improved.

  In the modification according to the second embodiment, the end of the control gate electrode 205 has a structure with a smaller curvature toward the center of the end. Therefore, the surface area of the control gate electrode 205 facing the semiconductor layer is reduced as compared with the conventional case where the end portion of the control gate electrode 205 is formed square. As a result, the electric field applied from the control gate electrode 205 to the tunnel insulating film 202 can be weakened as compared with the conventional case. Accordingly, as in the second embodiment, even when the hole diameter of the semiconductor region 201 is reduced, there is a feature that when data is read from the memory cell, erroneous writing does not occur and the degree of integration of the memory can be improved. Have.

  For reference, the result of calculating the electric field strength in the inter-conductor insulating film when the curvature of the control gate electrode 205 changes will be described with reference to FIG. As shown in FIG. 12A, the curvature of the inner control gate electrode 205 is a in the x direction and b in the y direction, and the change in curvature is shown by b / a. Therefore, the larger b / a means that the curvature increases toward the center of the electrode end. The distance between conductors (the sum of the film thicknesses of the tunnel insulating film 202, the charge storage layer 203, and the block insulating film 204) is represented by Tox. FIG. 12B shows the relationship between the insulating film average electric field strength in the vicinity of the channel silicon (X / ToX = 1) and the curvature b / a with reference to the electric field in the case of parallel plates. As can be seen from FIG. 12B, it is shown that the smaller the b / a, that is, the greater the curvature toward the center, the smaller the electric field strength.

(2-3) Manufacturing Method Hereinafter, a manufacturing method of the BiCS memory according to the second embodiment will be described with reference to FIGS.

  FIGS. 13A to 18A are cross-sectional views taken along the line AA in FIG. 8, and FIGS. 13B to 18B are plan views of the BiCS memory. The figure is shown.

  First, as shown in FIG. 13, the surface of the semiconductor layer 200 is made of, for example, a silicon oxide film by a CVD (Chemical Vapor Deposition) method, an inter-cell insulating film 206 having a thickness of 50 nm, and a silicon film doped with impurities. Thus, the control gate electrodes 205 having a thickness of 50 nm are alternately deposited to form a multi-layered structure. In FIG. 13, the semiconductor layer 100 also includes a select gate transistor. Further, although FIG. 13 shows a case where the silicon film has two layers, any number of layers of this multi-layer structure may be formed.

  Next, as shown in FIG. 14, for example, the control gate electrode 205 and the inter-cell insulating film 206 are selectively etched by RIE (Reactive Ion Etching) using a resist mask to expose the surface of the semiconductor layer 200. Let Thereby, for example, a cylindrical groove 211 having a diameter of about 60 nm is formed in the multi-layered structure.

  Next, as shown in FIG. 15, for example, oxidation treatment is performed in a high-temperature oxygen atmosphere or a radical oxygen atmosphere. By subjecting the control gate electrode 205 to oxidation, the end of the control gate electrode 205 is rounded, and a silicon oxide film 208 is formed in a region facing the cylindrical groove 211.

  Next, as shown in FIG. 16, for example, the inter-cell insulating film 206 is etched and the silicon oxide film 208 is removed by wet etching using a diluted hydrofluoric acid chemical solution. At this time, the surface where the inter-cell insulating film 206 is in contact with the columnar groove 211 is recessed as compared with the end of the control gate electrode 205.

  Further, in the case of a structure like the modified example of the second embodiment, it can be formed by shortening the oxidation treatment time, shortening the wet etching time, and repeating it.

  Next, as shown in FIG. 17, on the inner wall of the cylindrical groove 211, for example, an ALD (Atomic Layer Deposition) method is used to form a 15 nm-thick charge blocking film made of an alumina film mainly composed of aluminum and oxygen. 204, and then a charge storage film 203 made of a silicon nitride film and having a thickness of 3 nm is laminated, and then a tunnel insulating film 202 made of a silicon oxide film and having a thickness of 5 nm is deposited.

  Next, as shown in FIG. 18, the tunnel insulating film 202, the charge storage film 203, and the charge block film 204 formed on the bottom surface of the cylindrical groove 211 are selectively etched by RIE using a resist mask. Then, the surface of the semiconductor layer 200 is exposed. Thereafter, for example, a silicon film 207 doped with an impurity serving as a channel region is deposited by CVD, and then heat treatment is performed in a nitrogen atmosphere at 600 ° C. Thereafter, a wiring layer or the like is formed using a known technique, and the BiCS memory according to the second embodiment is completed.

(3) Third Embodiment In a batch-processed BiCS memory, a plurality of element isolation insulating films and electrode films are alternately stacked on a semiconductor layer, and then a memory hole for installing a memory cell is formed. In this process, it is difficult to form a completely vertical memory hole. Therefore, a forward tapered memory hole is formed in which the hole diameter is small on the semiconductor substrate side and the hole diameter is large on the opposite bit line side. Since the memory cell is formed in the forward tapered memory hole, the electric field applied to the tunnel insulating film is different between the memory cell formed on the semiconductor layer side and the memory cell formed on the bit line side. . For this reason, the threshold values of the memory cells vary, and the deterioration rate of the tunnel insulating film in the write and erase operations varies. As a result, there is a problem that the charge retention characteristics vary.

(3-1) Device Structure FIG. 19A is a cross-sectional view showing a part of a cell string of a BiCS memory. FIG. 16B shows an enlarged view of the memory cell close to the bit line side (the upper part of the semiconductor layer) in FIG. 19A, and FIG. 19C shows the semiconductor in FIG. An enlarged memory cell close to the substrate side (lower semiconductor layer) is shown. Further, it is assumed that the channel width of the memory cell is about 50 nm and the interval between adjacent memory cells is also about 50 nm.

  In the memory cell of FIG. 19, a cylindrical semiconductor region 301 that is elongated in the vertical direction is formed. A tunnel insulating film 302, a charge storage film 303, and a charge blocking film 304 are sequentially formed on the outer periphery of the semiconductor region 301. Further, a control gate electrode 305 isolated from each other by an inter-cell insulating film 306 is formed on the outer periphery.

  Here, since the configurations of the semiconductor region 301, the tunnel insulating film 302, the charge storage film 303, the charge blocking film 304, the control gate electrode 305, and the inter-cell insulating film 306 are the same as those in the first embodiment, Detailed description is omitted.

  Further, as shown in FIGS. 19B and 19C, the distance between the control gate electrodes 305 opposed via the semiconductor region 301 is the same as the distance between the inter-cell insulating films 306 opposed via the semiconductor region 301. Wide compared. Therefore, the control gate electrode 305 is formed so as to protrude into the semiconductor layer as compared with the inter-cell insulating film 306. Hereinafter, as in the first and second embodiments, the portion protruding into the semiconductor region 301 is defined as the end portion of the control gate electrode 305.

  In the third embodiment, as in the first and second embodiments, the end of the control gate electrode 305 has a curvature over the corner or all the regions. Therefore, the end portion of the control gate electrode 305 has a rounded structure. This can alleviate the concentration of the electric field on the semiconductor region 101 near the corner of the control gate electrode 305. Therefore, it is possible to suppress the localization of electrons in the charge storage film 103 formed in the vicinity of the corner of the control gate electrode 305 during the write operation. Therefore, the charge density in the charge storage film of the memory cell is made uniform. As a result, deterioration of Data Retention is suppressed. Furthermore, since the electric field at the corner of the memory cell is relaxed, deterioration of the insulating property of the tunnel insulating film formed in the vicinity of the corner of the control gate electrode 305 is suppressed, so that the endurance characteristic of the memory cell is improved. In addition, since the entire end portion of the control gate electrode 305 has a curvature, the electric field applied to the tunnel insulating film 302 is made uniform. Therefore, the charge density in the charge storage film 303 of the memory cell is made uniform. As a result, deterioration of Data Retention is suppressed.

  In the BiCS memory, the semiconductor region 301 has a forward tapered shape in which the hole diameter is small at the top and the hole diameter is large at the bottom. In such a structure, the electric field applied to the channel region of the memory cell formed above the semiconductor layer is weaker than the electric field applied to the channel region of the memory cell formed below the semiconductor region 301.

  Therefore, in the third embodiment, the end portion of the control gate electrode 305 of the memory cell formed in the upper portion of the semiconductor region 301 is formed so as to have a curvature only in the corner portion, and is formed in the lower portion of the semiconductor region 301. The end portion of the control gate electrode 305 of the memory cell is formed so that the entire end portion has a curvature. That is, the curvature of the end of the control gate electrode 305 of the memory cell formed on the semiconductor region 301 is smaller.

  With the above-described structure, the electric field applied to the tunnel insulating film 302 from the control gate electrode 305 of the memory cell formed in the lower portion of the semiconductor region 301 is controlled by the control gate of the memory cell formed in the upper portion of the semiconductor region 301. The electric field applied from the electrode 305 to the tunnel insulating film 302 becomes weaker. Accordingly, a difference in electric field due to the hole diameter of the semiconductor region 301 being formed in a tapered shape can be reduced. Therefore, variation in the threshold value of the memory cell can be reduced. As a result, since the number of times of applying the write voltage is reduced during the write operation, the high-speed write can be performed.

  Furthermore, since the electric field applied to the tunnel insulating film of the memory cell formed on the upper and lower portions is made uniform, variation in the deterioration rate of the insulating film in the write and erase operations is reduced, and the charge retention characteristic is maintained. It also has the feature.

(3-2) Modified Examples Hereinafter, modified examples according to the third embodiment will be described with reference to the drawings.

FIG. 17A is a cross-sectional view showing a part of the NAND string of the BiCS memory. FIG. 17B shows an enlarged memory cell close to the bit line side (upper part of the semiconductor layer) in FIG. 17A, and FIG. 17C shows the memory cell in FIG. The memory cell close to the semiconductor substrate side (lower part of the semiconductor layer) is shown enlarged. The structure of the memory cell is the same as that of the third embodiment.

  In the modification according to the third embodiment, the end portion of the control gate electrode 305 of the memory cell formed in the upper portion of the semiconductor region 301 has a curvature in the entire end portion, and the closer to the center of the end portion. It is formed so that the curvature becomes small. Further, the end portion of the control gate electrode 305 of the memory cell formed in the lower portion of the semiconductor region 301 is formed so that the entire end portion has a curvature, and the curvature increases toward the center of the end portion. That is, the curvature of the end portion of the control gate electrode 305 of the memory cell formed in the upper portion of the semiconductor region 301 becomes smaller.

  Further, as in the second embodiment, the surface area of the control gate electrode 305 facing the semiconductor layer is smaller than in the conventional case where the end portion of the control gate electrode 305 is formed in a square shape. As a result, the electric field applied from the control gate electrode 305 to the insulating film can be weakened as compared with the conventional case. Therefore, even when the hole diameter of the semiconductor region 301 is reduced, there is a feature that erroneous data writing does not occur when data is read from the memory cell, and the degree of memory integration can be improved.

  Similarly to the third embodiment, the electric field applied to the tunnel insulating film 302 from the control gate electrode 305 of the memory cell formed in the lower part of the semiconductor region 301 is the control gate of the memory cell formed in the upper part of the semiconductor region 301. The electric field applied from the electrode 305 to the tunnel insulating film 302 becomes weaker. Accordingly, a difference in electric field due to the hole diameter of the semiconductor region 301 being formed in a tapered shape can be reduced. Therefore, variation in the threshold value of the memory cell can be reduced. As a result, since the number of times of applying the write voltage is reduced during the write operation, the high-speed write can be performed.

  Furthermore, since the electric field applied to the tunnel insulating film of the memory cell formed on the upper and lower portions is made uniform, variation in the deterioration rate of the insulating film in the write and erase operations is reduced, and the charge retention characteristic is maintained. It also has the feature.

(3-3) Manufacturing Method A BiCS memory manufacturing method according to the third embodiment will be described below with reference to FIGS.

FIGS. 21A to 26A are cross-sectional views showing a part of the NAND string of the BiCS memory, and FIGS. 21B to 26B are semiconductor layers. FIG. 21 (c) to FIG. 26 (c) each show an enlarged cross-sectional view of a memory cell in a region close to the semiconductor layer. As shown in FIG. 21, the surface of the semiconductor layer 300 is made of, for example, a silicon oxide film by a CVD (Chemical Vapor Deposition) method, made of a 50 nm thick inter-cell insulating film 306 and a silicon film doped with impurities, The control gate electrodes 305 having a thickness of 50 nm are alternately deposited to form a multi-layered structure.

  Next, as shown in FIG. 22, for example, the control gate electrode 305 and the inter-cell insulating film 306 are selectively etched by an RIE (Reactive Ion Etching) method using a resist mask to expose the surface of the semiconductor layer 300. Let Thereby, for example, a cylindrical groove 311 having a diameter of about 60 nm is formed in the multi-layered structure.

  Next, as shown in FIG. 23, a silicon nitride film 312 is formed in the cylindrical groove 311 by using a PECVD method with loading or a sputtering method. At this time, as shown in FIGS. 23B and 23C, the silicon nitride film 312 is formed thin in a region near the semiconductor layer 300 and thick in a region away from the semiconductor layer 300.

  Next, as shown in FIG. 24, the silicon nitride film 312, the control gate electrode 305, and the inter-cell insulating film 306 are etched by wet etching using hot phosphoric acid. At this time, the silicon nitride film 312 formed in a region close to the semiconductor layer 300 is thin. Therefore, the time during which the control gate electrode 305 and the inter-cell insulating film 306 are exposed to hot phosphoric acid is longer than that of the control gate electrode 305 and the inter-cell insulating film 306 formed in a region away from the semiconductor layer. Therefore, the control gate electrode 305 and the inter-cell insulating film 306 formed in the region close to the semiconductor layer 300 are etched more than the control gate electrode 305 and the inter-cell insulating film 306 that are separated from the semiconductor layer 300. As a result, the end portion of the control gate electrode 305 formed in the region close to the semiconductor layer 300 has a larger curvature than the control gate electrode 305 far from the semiconductor layer 300.

  Next, as shown in FIG. 25, the inner wall of the cylindrical groove 311 is made of an alumina film mainly composed of aluminum and oxygen, for example, by an ALD (Atomic Layer Deposition) method, and has a thickness of 15 nm. 304 is deposited, and then a charge storage film 303 made of a silicon nitride film and having a thickness of 3 nm is deposited. Thereafter, a tunnel insulating film 302 made of a silicon oxide film and having a thickness of 5 nm is deposited.

  Next, as shown in FIG. 26, the tunnel insulating film 302, the charge storage film 303, and the charge block film 304 formed on the bottom surface of the cylindrical groove 311 are selectively etched by RIE using a resist mask. Then, the surface of the semiconductor layer 300 is exposed. Thereafter, for example, a silicon film 307 doped with an impurity serving as a channel region is deposited by CVD, and then heat treatment is performed in a nitrogen atmosphere at 600 ° C. Thereafter, a wiring layer or the like is formed using a known technique, and the BiCS memory according to the third embodiment is completed.

(3-4) Manufacturing Method of Modification Since the manufacturing method of the BiCS memory according to the third embodiment is the same up to FIG.

  Next, as shown in FIG. 27, a silicon nitride film 312 is formed in the cylindrical groove 311 by using the ALD method. At this time, as shown in FIGS. 27B and 27C, the silicon nitride film 312 is uniformly formed in the memory hole as compared with FIG.

  Thereafter, the surface of the silicon nitride film 312 formed in the cylindrical groove 311 is etched by RIE. At this time, since the upper portion is etched more than the lower portion, the silicon nitride film 312 is formed thick in a region near the semiconductor layer 300 and thin in a region far from the semiconductor 300 as shown in FIG.

  Next, as shown in FIG. 29, the silicon nitride film 312, the control gate electrode 305, and the inter-cell insulating film 306 are etched by wet etching using hot phosphoric acid. At this time, the silicon nitride film 312 formed in a region away from the semiconductor layer 300 is thin. Therefore, the time during which the control gate electrode 305 and the inter-cell insulating film 306 are exposed to hot phosphoric acid is longer than that of the control gate electrode 305 and the inter-cell insulating film 306 formed in a region away from the semiconductor layer. Therefore, the control gate electrode 305 and the inter-cell insulating film 306 formed in a region away from the semiconductor layer 300 are etched more than the control gate electrode 305 and the inter-cell insulating film 306 close to the semiconductor layer 300. As a result, the curvature of the control gate electrode 305 formed in a region away from the semiconductor layer 300 is smaller than that of the control gate electrode 305 close to the semiconductor layer 300.

  Thereafter, the BiCS memory according to the modified example of the third embodiment is completed by forming the BiCS memory according to the third embodiment in the same manner as described in FIG.

3. Application examples
In the embodiment of the present invention, the channel width of the memory cell is about 50 nm, and the interval between adjacent memory cells is also about 50 nm. However, the channel width of the memory cell and the interval between adjacent memory cells are The present invention can be applied whether the value is larger or smaller than these values.

4). Conclusion
According to the present invention, the electric field applied to the tunnel insulating film formed near the corner of the control gate electrode is relaxed by forming the corner of the control gate electrode to have a curvature.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

  DESCRIPTION OF SYMBOLS 100: Semiconductor layer, 101: Semiconductor region, 102: Tunnel insulating film, 103: Charge storage film, 104: Charge block film, 105: Control gate electrode, 106: Inter-cell insulating film, 107: Silicon film, 111: Column shape , 200: semiconductor layer, 201: semiconductor region, 202: tunnel insulating film, 203: charge storage film, 204: charge block film, 205: control gate electrode, 206: inter-cell insulating film, 207: silicon film, 208 : Silicon oxide film, 211: cylindrical groove, 300: semiconductor layer, 301: semiconductor region, 302: tunnel insulating film, 303: charge storage film, 304: charge block film, 305: control gate electrode, 306: between cells Insulating film, 307: Silicon film, 311: Cylinder Groove, 312: silicon nitride film.

Claims (8)

A semiconductor layer;
A columnar semiconductor region formed on the semiconductor layer and perpendicular to the semiconductor layer;
A first insulating film formed on a side surface of the semiconductor region;
A charge storage film formed on a side surface of the first insulating film;
A second insulating film formed on a side surface of the charge storage film;
A plurality of control gate electrodes in contact with a side surface of the second insulating film and formed in a flat plate shape parallel to the semiconductor layer;
A third insulating film formed on the surface of each of the second insulating film and the control gate electrode;
The distance of the third insulating film facing through the semiconductor region is formed longer than the distance of the control gate electrode facing through the semiconductor region,
The three-dimensional stacked nonvolatile semiconductor memory according to claim 1, wherein corners of the control gate electrode have a curvature.   The three-dimensional stacked nonvolatile semiconductor memory according to claim 1, wherein an entire end portion of the control gate electrode on the semiconductor region side has a curvature.   3. The three-dimensional stacked nonvolatile semiconductor memory according to claim 1, wherein an end portion of the control gate electrode has different curvatures at a corner portion and a central portion of the control gate electrode.   4. The three-dimensional stacked nonvolatile semiconductor according to claim 1, wherein a curvature of a corner portion of the control gate electrode is smaller as the control gate electrode is formed farther from the semiconductor layer. 5. memory. Forming a laminated film in which control gate electrodes and first insulating films are alternately laminated on the surface of the semiconductor layer;
Etching the laminated film to form a hole exposing the semiconductor layer;
Forming a second insulating film on the inner wall of the hole;
Forming a charge storage film on the inner wall of the second insulating film;
Forming a third insulating film on the inner wall of the charge storage film;
Forming a semiconductor region so as to fill the hole in the inner wall of the third insulating film,
Between the step of forming the hole and the formation of the charge storage film,
And a step of rounding corners of the control gate electrode on the semiconductor region side. A method for manufacturing a three-dimensional stacked nonvolatile semiconductor memory, comprising: Forming a laminated film in which control gate electrodes and first insulating films are alternately laminated on the surface of the semiconductor layer;
Etching the laminated film to form a hole exposing the semiconductor layer;
Forming a second insulating film having different thicknesses on the top and bottom of the hole on the surface of the laminated film in the hole;
Etching the control gate electrode, the first insulating film and the second insulating film, and rounding corners of the control gate electrode;
Forming a second insulating film on the inner wall of the hole;
Forming a charge storage film on the inner wall of the second insulating film;
Forming a third insulating film on the inner wall of the charge storage film;
Forming a semiconductor region so as to embed the hole in the inner wall of the third insulating film. A method of manufacturing a three-dimensional stacked nonvolatile semiconductor memory, comprising: The three-dimensional stack according to claim 6, wherein the second insulating film formed on the stacked surface in the hole is formed to be a thick film at an upper part of the hole and to be a thin film at a lower part. A method for manufacturing a nonvolatile semiconductor memory. The three-dimensional laminate according to claim 6, wherein the second insulating film formed on the laminate surface in the hole is formed to be a thin film at an upper portion of the hole and to be a thick film at a lower portion. A method for manufacturing a nonvolatile semiconductor memory.

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