JP2013127438A - Sensor signal processing circuit and sensor signal processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sensor signal processing circuit capable of reducing power consumption of a sensor.SOLUTION: The sensor signal processing circuit includes a control circuit 30 which outputs a sample timing signal P1, and an AD converter 40 which has an integrator 41 for sampling a sensor voltage value Vs output from the sensor 10 according to the sampling timing signal P1. The control circuit 30 has a switch SW1 which limits electric power supplied to the sensor 10 to small electric power in a period in which the sensor voltage value Vs is not sampled based upon the sampling timing signal P1.

Description

  The present invention relates to a sensor signal processing circuit that samples a sensor output signal in accordance with a sampling timing signal, and a sensor signal processing apparatus including the sensor signal processing circuit.

  FIG. 1 is a configuration diagram of a conventional sensor signal processing apparatus 100. The sensor signal processing apparatus 100 includes a resistance bridge type sensor 110, a signal generation circuit 131 that generates sampling timing signals P11 and P12, and a ΔΣ modulator 144 that samples the output signal of the sensor 110 according to the sampling timing signals P11 and P12. And.

  The sampling timing signal P11 is a signal for controlling on / off of the switches SW12a, 12b, 14a, and 14b constituting the switched capacitor 141 in the ΔΣ modulator 144, and the sampling timing signal P12 is a switch that constitutes the switched capacitor 141. This is a signal for controlling on / off of the SWs 13a and 13b.

  The sensor signal processing apparatus 100 also includes a sensor control circuit 160 that generates a signal for controlling on / off of the switch SW11 for energizing the sensor 110. The sensor control circuit 160 cuts off the current flowing through the sensor 110 by turning off the switch SW11 when the ΔΣ modulator 144 is disabled, and turns on the switch SW11 when the ΔΣ modulator 144 is enabled. As a result, the sensor 110 is energized.

  Patent Document 1 discloses a sensor circuit that supplies intermittent current to a bridge circuit.

JP-A-8-136309

  However, in the above-described conventional sensor signal processing apparatus 100, regardless of whether or not the ΔΣ modulator 144 is sampling the output signal of the sensor 110, when the ΔΣ modulator 144 is enabled, the switch SW11 is turned on so that the current flows. Is constantly flowing to the sensor 110, so the power consumption of the sensor is large.

  Accordingly, an object of the present invention is to provide a sensor signal processing circuit and a sensor signal processing device that can reduce the power consumption of the sensor.

In order to achieve the above object, the present invention provides:
A control unit that outputs a sampling timing signal;
A sensor signal processing circuit comprising a discrete circuit for sampling the output signal of the sensor according to the sampling timing signal,
The control section provides a sensor signal processing circuit and a sensor signal processing apparatus including the sensor signal processing circuit that intermittently limit the power supplied to the sensor based on the sampling timing signal.

  According to the present invention, the power consumption of the sensor can be reduced.

It is a block diagram of the conventional sensor signal processing apparatus 100. It is a lineblock diagram of sensor signal processing device 1 which is a 1st embodiment of the present invention. It is a block diagram of the sensor signal processing apparatus 2 which is the 2nd Embodiment of this invention. It is a block diagram of the sensor signal processing apparatus 3 which is the 3rd Embodiment of this invention. This is a specific example of the delay circuit 35. It is a time chart of sampling timing signals P1, P1d, P1dd, and P2.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 is a configuration diagram of the sensor signal processing apparatus 1 according to the first embodiment of the present invention. The sensor signal processing device 1 is a sensor system including a sensor 10 and a sensor signal processing circuit 20. The sensor 10 detects a predetermined physical quantity and outputs a signal corresponding to the detected value. The sensor signal processing circuit 20 is a semiconductor integrated circuit including a control circuit 30 and an AD converter 40.

  The control circuit 30 is a control unit including a signal generation circuit 31 and a switch SW1. The signal generation circuit 31 is a signal generation unit that generates sampling timing signals P1 and P2, and the switch SW1 is power supplied to the sensor 10 based on one sampling signal P1 of the sampling timing signals P1 and P2. It is a limiting part which restricts intermittently small.

  The AD converter 40 is a discrete circuit that samples the output signal of the sensor 10 in accordance with the sampling timing signals P1 and P2 output from the signal generation circuit 31 of the control circuit 30.

  Since the sensor signal processing circuit 20 has such a configuration, intermittently limiting the power supplied to the sensor 10 can be synchronized with the sampling operation of the AD converter 40. As a result, the control circuit 30 controls the switch SW1 to sample the power supplied to the sensor 10 during a period when the output signal of the sensor 10 is not sampled by the AD converter 40, and the output signal of the sensor 10 is sampled by the AD converter 40. It is possible to limit the time to be smaller than the period of time. Further, the control circuit 30 can release the restriction of the power supplied to the sensor 10 during the period when the output signal of the sensor 10 is sampled by the AD converter 40 by controlling the switch SW1. .

  Here, if power necessary for the sensor 10 is supplied during a period when the output signal of the sensor 10 is sampled by the AD converter 40, the output signal of the sensor 10 is supplied to the sensor 10 during a period when the output signal is not sampled by the AD converter 40. The power that can be limited may be limited. This is because, if the output signal of the sensor 10 is not sampled by the AD converter 40, the output signal of the sensor 10 may fluctuate by limiting the power supplied to the sensor 10.

  Thus, according to the sensor signal processing circuit 20, the power supply to the sensor 10 can be suppressed to the minimum necessary time. Further, the power consumption of the sensor 10 can be reduced without affecting the result of the AD converter 40 sampling the output signal of the sensor 10.

  Next, the configuration of FIG. 2 will be described in more detail.

  The sensor 10 is a resistance bridge type sensor having a resistance bridge circuit composed of four resistors R1, R2, R3, and R4. The resistance bridge circuit outputs an analog sensor voltage value Vs as an output signal of the sensor 10. The sensor voltage value Vs is a potential difference between the potential Vsa at the connection point a between the resistors R1 and R2 and the potential Vsb at the connection point b between the resistors R3 and R4.

  The high potential side power supply terminal 11 of the sensor 10 is connected to the VDD voltage, and the low potential side power supply terminal 12 of the sensor 10 is connected to the VSS voltage lower than the VDD voltage via the switch SW1. The connection point c between the resistors R1 and R3 is connected to the VDD voltage via the high potential side power supply terminal 11, and the connection point d between the resistors R2 and R4 is connected to the low potential side power supply terminal 12 and the switch SW1. To the VSS voltage. The VDD voltage is a constant power supply voltage supplied from a predetermined power supply.

  Specific examples of the sensor 10 include sensors that detect physical quantities such as pressure sensors, temperature sensors, voltage sensors, current sensors, strain sensors, magnetic sensors, and flow velocity sensors. A specific example of the switch SW1 is a switch circuit having a transistor such as a MOSFET or a bipolar transistor.

  The signal generation circuit 31 of the control circuit 30 causes the sampling timing signal P2 to be low level when the sampling timing signal P1 is high level, and the sampling timing signal P1 to be low level when the sampling timing signal P2 is high level. In addition, sampling timing signals P1 and P2 are generated. In addition, the signal generation circuit 31 generates the sampling timing signals P1 and P2 so that both the sampling timing signals P1 and P2 have a low level.

  The AD converter 40 is a ΔΣ type analog-digital conversion circuit that samples the sensor voltage value Vs according to the sampling timing signals P 1 and P 2 output from the signal generation circuit 31 of the control circuit 30. The AD converter 40 includes, for example, a ΔΣ modulator 44 and a digital filter 45.

  The ΔΣ modulator 44 includes an integrator 41 to which the sensor voltage value Vs is input, and a comparator 43 that compares the output signal of the integrator 41 with a predetermined reference voltage. With such a configuration, the ΔΣ modulator 44 outputs a 1-bit digital data string that changes according to the sensor voltage value Vs. The digital filter 45 is a filter that performs signal processing on digital data output from the ΔΣ modulator 44 and includes, for example, a CIC filter.

  The integrator 41 has two capacitors C1a and C1b and six switches SSW2a, 2b, 3a, 3b, 4a and 4b. One electrode of the capacitor C1a is connected to the switch SW4a and the non-inverting input terminal of the operational amplifier A1, and the other electrode is connected to the switches SW2a and 3a. One electrode of the capacitor C1b is connected to the switch SW4b and the inverting input terminal of the operational amplifier A1, and the other electrode is connected to the switches SW2b and 3b. The switch SW2a is connected to the connection point a of the resistance bridge circuit of the sensor 10, the switch SW2b is connected to the connection point b of the resistance bridge circuit of the sensor 10, and the switches SW3a, 3b, 4a, and 4b are connected to the reference voltage VCM. It is connected.

  The switches SW2a, 2b, 4a, 4b are turned on / off according to the sampling timing signal P1, turned on when the sampling timing signal P1 is at a high level, and turned off when at a low level. The switches SW3a and 3b are turned on / off according to the sampling timing signal P2, turned on when the sampling timing signal P2 is at a high level, and turned off when at a low level.

  The integrator 41 includes a differential operational amplifier A1 and capacitors C2a and C2b. The capacitor C2a is inserted between the non-inverting input terminal and the inverting output terminal of the operational amplifier A1, and the capacitor C2b is inserted between the inverting input terminal and the non-inverting output terminal of the operational amplifier A1.

  When the sampling timing signal P1 is high level and the sampling timing signal P2 is low level, the integrator 41 turns on the switches SW2a, 2b, 4a, 4b and turns off the switches SW3a, 3b. Sampling is performed at C1a and C1b.

  In addition, when the sampling timing signal P1 is at a low level and the sampling timing signal P2 is at a high level, the integrator 41 turns off the switches SW2a, 2b, 4a, 4b and turns on the switches SW3a, 3b, thereby turning on the capacitors C1a, C1b. Is transferred to the capacitors C2a and C2b.

  Here, since the switches SW2a and 2b are turned off when the sampling timing signal P1 is at a low level, the signal path between the connection points a and b of the resistance bridge circuit of the sensor 10 and the capacitors C1a and C1b of the integrator 41 is Blocked. Therefore, the sensor voltage value Vs is not sampled by the integrator 41 when the sampling timing signal P1 is at least at a low level.

  On the other hand, the switch SW1 of the control circuit 30 is turned on / off according to the sampling timing signal P1, similarly to the switches SW2a, 2b, 4a, 4b, turned on when the sampling timing signal P1 is at a high level, and turned off when at a low level. When the switch SW1 is turned on, power is supplied to the sensor 10, and when the switch SW1 is turned off, the power supplied to the sensor 10 is cut off.

  Therefore, power can be supplied to the sensor 10 during a period when the sensor voltage value Vs is sampled by the integrator 41, and power supplied to the sensor 10 can be cut off during a period when the sensor voltage value Vs is not sampled by the integrator 41.

  FIG. 3 is a configuration diagram of the sensor signal processing device 2 according to the second embodiment of the present invention. The description of the same points as in the above-described embodiment will be omitted. Unlike the control circuit 30 of the sensor signal processing circuit 20 of FIG. 2, the control circuit 32 of the sensor signal processing circuit 21 of FIG. 3 includes an inverter 33. The control circuit 32 includes the switch SW1 and the inverter 30 as a limiting unit that intermittently limits the power supplied to the sensor 10 based on one sampling signal P2 of the sampling timing signals P1 and P2. Yes.

  The inverter 33 is an inverting circuit that generates a signal (sampling timing signal P2b) obtained by inverting the sampling timing signal P2 and supplies the sampling timing signal P2b to the switch SW1. The switch SW1 is turned on when the sampling timing signal P2b is at a high level and turned off when the sampling timing signal P2b is at a low level.

  Therefore, even in the configuration as shown in FIG. 3, power can be supplied to the sensor 10 during a period when the sensor voltage value Vs is sampled by the integrator 41, and the sensor voltage value Vs is supplied to the sensor 10 during a period when the sensor voltage value Vs is not sampled by the integrator 41. Can be cut off.

  FIG. 4 is a configuration diagram of the sensor signal processing device 3 according to the third embodiment of the present invention. The description of the same points as in the above-described embodiment will be omitted. The control circuit 34 of the sensor signal processing circuit 22 in FIG. 4 includes a delay circuit 35 unlike the control circuit 30 of the sensor signal processing circuit 20 in FIG. The control circuit 34 includes the switch SW1 and the delay circuit 35 as a limiting unit that intermittently limits the power supplied to the sensor 10 based on one sampling signal P1 of the sampling timing signals P1 and P2. ing.

  The delay circuit 35 is a circuit that generates a signal (sampling timing signal P1d) obtained by delaying the sampling timing signal P1 for a predetermined time and generates a signal (sampling timing signal P1dd) obtained by delaying the sampling timing signal P1d for a predetermined time.

  FIG. 5 is a specific example of the delay circuit 35. The delay circuit 35 includes a delay unit 36 composed of two columns of CMOS inverters to which the sampling timing signal P1 is input, and a delay unit 37 composed of two columns of CMOS inverters to which the output signal of the delay unit 36 is input. Have a circuit connected in series. By such a series circuit, the delay unit 36 generates a sampling timing signal P1d obtained by delaying the sampling timing signal P1 by a predetermined time, and the delay unit 37 generates a sampling timing signal P1dd obtained by delaying the sampling timing signal P1d by a predetermined time. Can be generated.

  As shown in FIG. 4, the delay circuit 35 supplies the sampling timing signal P1d to the integrator 41 of the AD converter 40, and supplies the sampling timing signal P1dd to the switch SW1.

  The switches SW4a and 4b are turned on / off according to the sampling timing signal P1, turned on when the sampling timing signal P1 is at a high level, and turned off when at a low level. The switches SW2a and 2b are turned on / off according to the sampling timing signal P1d, turned on when the sampling timing signal P1d is at a high level, and turned off when at a low level. The switches SW3a and 3b are turned on / off according to the sampling timing signal P2, turned on when the sampling timing signal P2 is at a high level, and turned off when at a low level. The switch SW1 is turned on / off according to the sampling timing signal P1dd, turned on when the sampling timing signal P1dd is at a high level, and turned off when at a low level.

  FIG. 6 is a time chart of the sampling timing signals P1, P1d, P1dd, and P2.

  When the sampling timing signals P1, P1d, and P1dd are at a high level and the sampling timing signal P2 is at a low level, the integrator 41 turns on the switches SW2a, 2b, 4a, and 4b and turns off the switches SW3a and 3b. The value Vs is sampled by the capacitors C1a and C1b (sampling period).

  Further, the integrator 41 is configured such that when the sampling timing signals P1, P1d, and P1dd are at a low level and the sampling timing signal P2 is at a high level, the switches SW2a, 2b, 4a, and 4b are turned off and the switches SW3a and 3b are turned on. The sensor voltage value Vs sampled by the capacitors C1a and C1b is transferred to the capacitors C2a and C2b (integration period). Note that the rising timing of the sampling timing signal P2 only needs to be later than the falling timings t7 and t15 of the sampling timing signal P1d.

  Accordingly, since the control circuit 34 can turn off the switch SW1 when the sampling timing signal P1dd is at a low level, the power supplied to the sensor 10 can be cut off every time the sampling period of the sensor voltage value Vs ends. .

  Further, the control circuit 34 turns off the switches SW2a and 2b at the falling timings t7 and t15 of the sampling timing signal P1d, and then turns off the switch SW1 at the falling timings t8 and t16 of the sampling timing signal P1dd. Thereby, it is possible to prevent the erroneous sensor voltage value Vs (for example, the power supply voltage VDD) from being sampled by turning off the switch SW1 during the sampling period of the sensor voltage value Vs.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications, combinations, and the like can be made to the above-described embodiments without departing from the scope of the present invention. Improvements, substitutions, etc. can be made.

  For example, when the power supplied to the resistance bridge circuit of the sensor 10 is intermittently limited to be small, in the above-described embodiment, the current flowing through the resistance bridge circuit of the sensor 10 is limited by the switch SW1, but the sensor 10 The voltage (for example, power supply voltage VDD) applied to the resistor bridge circuit may be limited to a small value.

  Further, for example, the switch SW1 may be outside the sensor signal processing circuit 20, may be inside the sensor 10, or may be outside the sensor 10. The switch SW1 may be between the power supply voltage VDD and the connection point c.

  The sensor is not limited to a sensor having a resistance bridge circuit, and may be any sensor that detects a predetermined physical quantity and outputs a voltage signal that can be sampled according to the detected value. For example, the resistance bridge circuit in the sensor 10 may be replaced with one resistor. This resistor is used as, for example, a current detection resistor inserted in series in the current path. The sensor output signal is not limited to a differential signal, and may be a single-ended signal. The sensor 10 may be inside the sensor signal processing circuit 20.

  The discrete circuit that samples the output signal of the sensor is not limited to the AD converter, and any circuit that samples the output signal of any sensor may be used. For example, instead of the illustrated AD converter 40, a switched capacitor amplifier including a switch, a capacitor, and an operational amplifier may be used.

  Further, the configuration of the switched capacitor and the integrator is not limited to the illustrated configuration, and any known circuit may be used as the signal generation circuit for generating the sampling timing signal.

1, 2, 100 Sensor signal processing device 10, 110 Sensor 20, 21, 22 Sensor signal processing circuit 30, 32, 34 Control circuit 31, 131 Signal generation circuit 33 Inverter 35 Delay circuit 36, 37 Delay unit 40 AD converter 41 Integration Unit 43 Comparator 44, 144 ΔΣ Modulator 45 Digital Filter 160 Sensor Control Circuit

Claims (8)

A control unit that outputs a sampling timing signal;
A sensor signal processing circuit comprising a discrete circuit for sampling the output signal of the sensor according to the sampling timing signal,
The said control part is a sensor signal processing circuit which restrict | limits the electric power supplied to the said sensor intermittently based on the said sampling timing signal.   The sensor signal processing circuit according to claim 1, wherein the control unit limits power supplied to the sensor during a period in which the output signal is not sampled.   The sensor signal processing circuit according to claim 2, wherein the control unit releases the restriction on the power supplied to the sensor during a period in which the output signal is sampled.   4. The sensor signal processing circuit according to claim 1, wherein the control unit intermittently limits the power supplied to the sensor based on a signal obtained by delaying the sampling timing signal. 5. The sensor has a resistance bridge circuit;
The sensor signal processing circuit according to any one of claims 1 to 4, wherein the control unit intermittently limits power supplied to the resistance bridge circuit.   The sensor signal processing circuit according to claim 1, wherein the discrete circuit is an AD converter.   The sensor signal processing circuit according to claim 1, wherein the discrete circuit is a switched capacitor amplifier.   A sensor signal processing device comprising the sensor signal processing circuit according to claim 1 and the sensor.

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