JP2013121411A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine preventing a drawback in power interruption which is caused by a control integrated circuit.SOLUTION: The game machine includes: a first DC voltage generating integrated circuit 901 for generating first DC voltage used for the operation of an external interface in a control microcomputer 91; and a second DC voltage generating integrated circuit 902 used for the operation of a CPU 91a for controlling the operation of the external interface in the control microcomputer 91, and generating second DC voltage lower than the first DC voltage. The first DC voltage generating integrated circuit 901 stops the generation of the first DC voltage when the input of a specified voltage output signal whose output is stopped on condition that output voltage from the second DC voltage generating integrated circuit 902 drops to a specified voltage is stopped.

Description

  The present invention relates to a gaming machine such as a pachinko machine or a slot machine that allows a player to play a predetermined game.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and multiple types of identification information are variably displayed when the game medium wins in a start prize area such as a prize opening provided in the game area. There are pachinko machines in which a predetermined number of bets are set and a slot machine in which a plurality of types of identification information are variably displayed when a start operation is performed. In a gaming machine configured to be able to execute variable display of identification information in this way, when the display result of variable display of identification information becomes a predetermined display result in the variable display unit, a predetermined game value (for example, jackpot) Some are configured to give the player a transition to a state, etc.).

  As this type of gaming machine, for example, as shown in Patent Document 1, a game control means including an integrated circuit (IC) such as a control microcomputer for controlling the progress of a game is provided as a control means. A pachinko machine is known. And in patent document 1, with respect to these integrated circuits (IC), the voltage of 12V mainly used by the peripheral electronic circuit, for example, the I / O circuit for implementing input / output with an external memory, Some of them are supplied with a voltage of 3.3 V mainly used in a central processing unit (CPU) that executes a control program for performing control, and the voltage of 3.3 V is supplied to an integrated circuit (IC). There is one that is generated and supplied by a DC / DC converter in which a voltage of 12 V supplied to is input in parallel.

JP 2009-285059 A (page 32, FIG. 17)

  As shown in these patent documents 1, the voltage of 3.3V which is an operating voltage of a central processing unit (CPU) is generated and supplied from the voltage of 12V supplied in parallel with the integrated circuit (IC). For example, even if 3.3V voltage cannot be generated due to a failure of the DC / DC converter or the like, the 12V voltage is continuously supplied, so the 3.3V voltage supply stops. Even when the central processing unit (CPU) is inoperable, the I / O circuit is operable, so that these I / O circuits malfunction without being controlled by the central processing unit (CPU). When the external circuit connected to the I / O circuit malfunctions or the external circuit is an external memory storing backup data, for example, the backup data is inappropriately rewritten. Failure there is a problem that there is a case in which occurs of.

  The present invention has been made paying attention to such a problem, and prevents the occurrence of a malfunction at the time of power interruption by a control integrated circuit (IC) mounted in a gaming machine for performing predetermined control. It is an object of the present invention to provide a gaming machine that can handle such a situation.

In order to solve the above-mentioned problem, a gaming machine according to claim 1 of the present invention provides:
A gaming machine (slot machine 1) capable of performing a predetermined game,
A control microcomputer (for example, a sub-control unit 91) for performing control related to the game;
A first DC voltage (eg, DC 3.3V) used for operation of an external interface (eg, I / O port 91d) in the control microcomputer is generated from a predetermined power supply voltage (eg, DC 12V). A first DC voltage generating integrated circuit (first switching regulator IC 901) for outputting;
The integrated circuit is separate from the first DC voltage generating integrated circuit, and is used for the operation of a central processing unit (for example, the CPU 91a) that performs the operation control processing of the external interface in the control microcomputer. A second DC voltage generation integrated circuit (second switching regulator IC 902) that generates and outputs a second DC voltage lower than the first DC voltage (for example, DC 1.15V) from the power supply voltage (DC 12V);
With
The second DC voltage generation integrated circuit includes a signal output unit (PG signal output terminal) that outputs an output permission signal (PG signal) that permits output of the first DC voltage from the first DC voltage generation integrated circuit. And stopping the output of the output permission signal on the condition that the second DC voltage to be output has decreased to a predetermined specified voltage (for example, 0.6 V),
The first DC voltage generation integrated circuit has a signal input unit (RMT2 terminal) to which the output permission signal is input, and when the input of the output permission signal from the signal input unit stops, the first DC voltage generation integrated circuit The generation of voltage (oscillation of a DC-DC conversion switching circuit of 3.3 V DC) is stopped.
According to this feature, the first DC voltage generating integrated circuit and the second DC voltage generating integrated circuit for generating the first DC voltage and the second DC voltage from the common power supply voltage are separately provided, and the first DC voltage is provided. Since the voltage generation integrated circuit stops generating the first DC voltage when the input of the output permission signal from the second DC voltage generation integrated circuit is stopped, for example, the maximum of the second DC voltage is interrupted. When the power consumption is larger than the maximum power consumption of the first DC voltage, the second DC voltage used for the operation of the central processing unit of the control microcomputer is used for the external interface. Even if the voltage drops before the first DC voltage, the output of the first DC voltage is also stopped by stopping the output of the output permission signal, and the external interface is disabled, so the supply of the second DC voltage is stopped. After the operation of the central processing unit is stopped, the output of the first DC voltage is continued, so that the external interface can be kept in an operable state and can be prevented from malfunctioning. Can be prevented from malfunctioning due to malfunction of the external interface.
Therefore, the first DC voltage is used for the first load including the operation of the electronic device other than the operation of the external interface, and the second DC voltage is used for the central operation. In addition to the operation of the processing apparatus, it is used for a second load including the operation of an electronic device other than the central processing unit, and the maximum power consumption by the second load is the maximum power consumption by the first load. It may be larger than the amount.

The gaming machine of means 1 of the present invention is the gaming machine according to claim 1,
The second DC voltage generation integrated circuit (second switching regulator IC 902) outputs the output permission signal (PG) on condition that the output second DC voltage has reached the specified voltage (0.6V) at the time of startup. Signal),
The first DC voltage generation integrated circuit (first switching regulator IC 901) generates the first DC voltage (DC 3.3V DC-DC conversion switching circuit) on condition that the output permission signal is input. (Oscillation) is started.
According to this feature, the first DC voltage generating integrated circuit is the first DC voltage generating integrated circuit when the second DC voltage used for the operation of the central processing unit of the control microcomputer becomes a specified value and the output permission signal is output. Since the generation of the DC voltage of 1 is started, the external interface becomes operable after the central processing unit is first operated by the output of the second DC voltage. That is, the external interface is operated until the central processing unit is stably operated. Since the interface is not operable, it is possible to prevent the occurrence of problems due to the malfunction of the external interface at the time of startup by these control microcomputers.

The gaming machine of means 2 of the present invention is the gaming machine described in means 1,
The first DC voltage generation integrated circuit (first switching regulator IC 901) includes the first DC voltage (for example, DC 3.3V) and a third DC voltage (for example, different from the first DC voltage). DC1.0V) can be generated and the generation of the third DC voltage (oscillation of a DC-DC conversion switching circuit of 1.0V DC) is started on condition that the output permission signal (PG signal) is input. Then, the generation of the first DC voltage is started when the generation of the third DC voltage (the output voltage of the Pout1 terminal reaches 1.0 V) is triggered.
According to this feature, not only the first DC voltage but also the start of generation of the third DC voltage can be controlled to be output after the output of the second DC voltage is started.

A gaming machine according to means 3 of the present invention is the gaming machine according to means 2,
The third DC voltage (DC 1.0 V) is a voltage lower than the first DC voltage (DC 3.3 V).
According to this feature, the third DC voltage lower than the first DC voltage can be generated before the first DC voltage also in the first DC voltage generation integrated circuit.

The gaming machine of means 4 of the present invention is the gaming machine according to claim 1 or means 1 to means 3, wherein
The first DC voltage generating integrated circuit (first switching regulator IC 901) includes a switching regulator circuit (DC-DC conversion switching circuit for DC 3.3V) that generates the first DC voltage (DC 3.3V), The switching regulator circuit starts oscillating on condition that the output permission signal (PG signal) is input.
According to this feature, since the oscillation of the switching regulator circuit is started by the input of the output permission signal, the first DC voltage is prevented from being generated and output before the output permission signal is input. be able to.

The gaming machine according to means 5 of the present invention is the gaming machine according to any one of claim 1 or means 1 to means 4, wherein
The first lower limit value (for example, 6 V) of the power supply voltage at which the first DC voltage generation integrated circuit (first switching regulator IC 901) cannot generate the first DC voltage (DC 3.3 V) is the second DC voltage generation integrated circuit (first switching regulator IC 901). A DC voltage generation integrated circuit (second switching regulator IC 902) is higher than a second lower limit value (for example, 5V) of the power supply voltage at which the second DC voltage (DC 1.15V) cannot be generated. .
According to this feature, when the power supply voltage decreases during a normal power interruption, the first DC voltage is generated before the second DC voltage because the first lower limit value is higher. Since the operation of the external interface is stopped before the central processing unit, it is possible to further prevent the occurrence of a malfunction due to the malfunction of the external interface at the time of power interruption.

The gaming machine according to means 6 of the present invention is the gaming machine according to any one of claim 1 or means 1 to 5,
Data used for control performed by the control microcomputer (sub-control unit 91) can be read and written, and the state before the power supply is stopped after the power supply is resumed even if the power supply to the gaming machine is stopped Backup data storage means (for example, SRAM 99) capable of holding backup data for returning to
Detecting that the power supply voltage has reached a predetermined power failure detection voltage (for example, 9 V), and outputting a power failure detection signal (voltage drop signal) indicating that the power failure detection voltage has been reached to the control microcomputer. Power failure detection means (power failure detection circuit 98);
With
The control microcomputer performs a backup process (power interruption process) for writing the backup data to the backup data storage means in response to the input of the power failure detection signal,
The power failure detection voltage (DC9V) is a lower limit at which either the first DC voltage generation integrated circuit or the second DC voltage generation integrated circuit cannot generate the first DC voltage or the second DC voltage. The voltage is higher than the voltage (for example, DC 6 V which is the lower limit value of the first switching regulator IC 901).
According to this feature, the power supply voltage is lower than a lower limit voltage at which one of the first DC voltage generation integrated circuit and the second DC voltage generation integrated circuit cannot generate the first DC voltage or the second DC voltage. When the power failure detection voltage becomes high, that is, before the first DC voltage and the second DC voltage cannot be generated, the backup processing is executed according to the input of the power failure detection signal. It can be avoided that the voltage and the second DC voltage cannot be generated and the backup process is not performed well.

It is a front view of the slot machine to which the present invention is applied. It is an internal structure figure of a slot machine. It is a figure which shows the symbol arrangement | sequence of a reel. It is a block diagram which shows the structure of a slot machine. (A) is a block diagram showing the connection between the main control unit and the SRAM, (b) is a timing chart showing the output status of the signal at the time of reading, and (c) is the signal at the time of writing. It is a timing chart which shows an output condition. It is explanatory drawing of a game control program. It is explanatory drawing of a production control program. It is a flowchart which shows the control content of the starting process (main) which a main control part performs at the time of starting. It is a flowchart which shows the control content of the starting process (main) which a main control part performs at the time of starting. It is a flowchart which shows the control content of the starting process (main) which a main control part performs at the time of starting. It is a flowchart which shows the control content of the game control process which a main control part performs. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the power interruption process (main) performed according to having detected the power interruption in the timer interruption process (main). It is explanatory drawing which shows the storage state of the data when storing in the backup RAM when storing the backup data for every program module in a game control program. It is a figure for demonstrating the kind of symbol combination, symbol combination, and the payout number of medals at the time of winning a prize. It is a figure for demonstrating the technical matter relevant to the kind of replay, a symbol combination, and a small part. It is a figure for demonstrating the symbol combination of a transfer turn. It is a figure for demonstrating a game state and transition of RT. It is a figure for demonstrating the navigation object combination in AT. It is a figure for demonstrating the reel control at the time of several re-game player winning. It is a figure for demonstrating the reel control at the time of several small part winning. It is a flowchart which shows the control content of the starting process (sub) which a sub control part performs at the time of starting. It is a flowchart which shows the control content of the starting process (sub) which a sub control part performs at the time of starting. It is a flowchart which shows the control content of the timer interruption process (sub) which a sub control part performs for every fixed interval. It is a flowchart which shows the control content of the timer interruption process (sub) which a sub control part performs for every fixed interval. It is explanatory drawing which shows the storage state of the data when storing in the backup RAM when storing the backup data for every program module in an effect control program. It is explanatory drawing which shows the storage state when backup data is stored in backup RAM, when (A) bus width of work RAM and back wrap RAM corresponds, and (B) bus width differs. It is explanatory drawing which shows the difference with the case where (A) data conversion is not performed and the case where (B) data conversion is performed when the bus widths of work RAM and backlap RAM differ. It is explanatory drawing which shows the storage state of the data in backup RAM when data conversion is performed when the bus width of work RAM and backlap RAM differs. It is a figure which shows the production | generation circuit of the direct current supplied to the sub-control part 91 and SRAM99 in an effect control board. It is a figure which shows the supply start timing and supply stop timing of the direct current of each voltage. It is a figure which shows the timing which this output voltage is stopped when there exists abnormality in the fall of output voltage (3.3V / 1.0V) from 1st switching regulator IC at the time of a power failure.

  Examples of the present invention will be described below.

  An embodiment of a slot machine to which the present invention is applied will be described with reference to the drawings. A slot machine 1 according to the present embodiment includes a housing 1a having an open front surface, and a pivotable pivot at a side end of the housing 1a. The front door 1b is supported.

  Inside the casing 1a of the slot machine 1 of the present embodiment, as shown in FIG. 2, reels 2L, 2C and 2R (hereinafter referred to as a left reel, a middle reel and a right reel) in which a plurality of types of symbols are arranged on the outer periphery. ) Are juxtaposed in the horizontal direction, and as shown in FIG. 1, three consecutive symbols out of the symbols arranged on the reels 2L, 2C, 2R can be seen from the see-through window 3 provided on the front door 1b. Are arranged as follows.

  As shown in FIG. 3, on the outer periphery of the reels 2L, 2C, and 2R, “black 7”, “net 7 (shaded 7 in the figure)”, “white 7”, “BAR”, “replay”, A plurality of types of mutually distinguishable symbols such as “plum”, “watermelon”, “cherry”, “bell”, and “orange” are drawn in a predetermined order. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in upper, middle, and lower three stages in the see-through window 3 provided in the approximate center of the reel panel 1c of the front door 1b.

  The reels 2L, 2C, and 2R are provided in correspondence with each other and rotated by reel motors 32L, 32C, and 32R (see FIG. 4), so that the symbols of the reels 2L, 2C, and 2R are continuously formed in the see-through window 3. In addition to being displayed while changing, by stopping the rotation of the reels 2L, 2C, and 2R, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Inside the reels 2L, 2C, and 2R are reel sensors 33L, 33C, and 33R that detect a reference position for each of the reels 2L, 2C, and 2R, and a reel LED 55 that irradiates the reels 2L, 2C, and 2R from the back side. , Is provided. The reel LED 55 includes 12 LEDs corresponding to three consecutive symbols of the reels 2L, 2C, and 2R, and can irradiate each symbol independently.

  At the position corresponding to each reel 2L, 2C, 2R on the front door 1b, a horizontally long rectangular see-through window 3 that allows the reels 2L, 2C, 2R to be seen through from the front side is provided. The reels 2L, 2C, 2R can be visually recognized from the player side.

  The front door 1b uses a medal insertion unit 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a player's own game value). The MAXBET switch 6 that is operated when setting the maximum bet number (3 in any game state in this embodiment) among the prescribed number of bets determined according to the game state, is stored as credits. Settlement switch 10 operated when paying out medals used for setting medals and betting numbers (returning medals used for setting credits and betting numbers), start switch operated when starting a game 7. Stop switches 8L, 8C, 8R operated when stopping the rotation of the reels 2L, 2C, 2R, and an effect switch 56 for use in effects. It is provided so as to be operated by the skill person.

  In this embodiment, among the three reels 2L, 2C, and 2R that have started to rotate, the reel that stops first is referred to as a first stop reel, and the stop is referred to as a first stop. Similarly, the reel that stops second is called the second stop reel, the stop is called second stop, the reel that stops third is called the third stop reel, and the stop is the third stop. Alternatively, it is called final stop.

  The front door 1b also displays a credit indicator 11 that displays the number of medals stored as credits, the number of medals paid out due to the occurrence of a prize, an error code indicating the contents when an error occurs, and the like. Game assist indicator 12, 1BETLED14 that notifies that the bet number is set by 1 by lighting, 2BETLED15 that notifies that the bet number is set by 2 and 2 that the bet number is set by 3 3BET LED 16 to notify, insertion request LED 17 to notify that a medal can be inserted by lighting, start effective LED 18 to notify that the game start operation by the operation of the start switch 7 is effective, wait (the previous game start) Waiting for the start of reel rotation because a certain period has not elapsed since Weight in LED19 for notifying by lighting a a is that during the game display section 13 in the replay LED20 is provided for informing is provided by lighting the effect that during replay game, which will be described later.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 4) for notifying that the setting operation of the bet amount by the operation of the MAXBET switch 6 is valid, and stop switches 8L, 8C, The left, middle, and right stop valid LEDs 22L, 22C, and 22R (see FIG. 4) are provided inside the 8R to notify that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is valid by lighting. It has been.

  Further, below the stop switches 8L, 8C, 8R on the front door 1b, a lower panel 1d on which a title of the slot machine 1 and a payout table are printed is provided.

  Inside the front door 1b, there is a reset switch 23 for detecting a reset operation for releasing an error state described later and a stop state described later by a predetermined key operation, while changing a set value and confirming a set value described later. The set value display 24 that displays the set value at that time, and the validity / invalidity of the stop function for controlling the stop state at the end of the BB, which will be described later (a state in which the progress of the game is restricted until a reset operation is performed) A check switch 36a for selecting the automatic settlement function that controls automatic settlement at the end of BB, which will be described later (processing to settle (return) medals stored as credits regardless of the player's operation). An automatic settlement switch 36b for selecting invalidity, and a flow path for medals inserted from the medal insertion unit 4 are provided in a hopper tank 34a (described later with reference to FIG. 2) provided inside the housing 1a. And a medal having a insertion medal sensor 31 for detecting a medal that has been inserted from the medal insertion unit 4 and flowed down to the hopper tank 34a side. A selector (not shown) and a door open detection switch 25 (see FIG. 4) for detecting the open state of the front door 1b are provided.

  As shown in FIG. 2, a reel sensor 33L that can detect the reel reference positions of the reels 2L, 2C, and 2R, the reel motors 32L, 32C, and 32R, and the reels 2L, 2C, and 2R, as shown in FIG. , 33C, 33R (see FIG. 4), an external output board 1000 for outputting an external output signal, a hopper tank 34a for storing medals inserted from the medal insertion section 4, and a hopper tank 34a. A hopper unit 34 including a hopper motor 34b for paying out medals from the medal payout opening 9, a payout sensor 34c for detecting medals paid out by driving the hopper motor 34b, and a power supply box 100 are provided.

  On the side of the hopper unit 34, an overflow tank 35 is provided for storing medals overflowing from the hopper tank 34a. Inside the overflow tank 35, a full sensor 35 a made up of a pair of electrically conductive members spaced apart from each other and provided at a height capable of detecting a predetermined amount of stored medals is provided. It is possible to detect that the medal storage amount stored in the inside when it is conductive by contacting through the medal stored in the inside exceeds a predetermined amount, that is, that the overflow tank is full. It has become.

  The front side of the power supply box 100 functions as a setting key switch 37 for switching to a setting change state or a setting confirmation state, and functions as a reset switch for canceling an error state or a stop state in a normal state. There are provided a reset / setting switch 38 that functions as a setting switch for changing a setting value of a winning probability (outtake rate) of internal lottery to be described later, and a power switch 39 that is operated when the power is turned on / off. .

  When a game is played in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or a bet number is set using credits. To use the credit, the MAXBET switch 6 may be operated. When a predetermined number of bets determined according to the gaming state are set, the winning line LN (see FIG. 1) becomes valid, and the operation of the start switch 7 is valid, that is, the state where the game can be started. Become. In the present embodiment, when the prescribed number of bets is set to three regardless of the gaming state and the prescribed number of bets is set, the pay line LN becomes valid. In addition, when a medal is inserted exceeding the maximum number out of the prescribed number corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether a combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a winning symbol combination. In this embodiment, as shown in FIG. 1, only the winning line LN set across the symbols arranged in the horizontal direction in the middle stage of the reel 2L, the middle stage of the reel 2C, the middle stage of the reel 2R, that is, the middle stage, is used as the winning line. It has been established. In this embodiment, only one winning line is applied, but a plurality of winning lines may be applied.

  In the present embodiment, invalid lines LM1 to LM1-4 are set apart from the winning line LN in order to make it easy to recognize that the winning line LN has a combination of symbols constituting the winning line. The invalid lines LM1 to LM4 are not determined based on the combination of symbols aligned with the invalid lines LM1 to LM4. When the combination of symbols constituting a specific prize is arranged on the winning line LN, the invalid line LM1 to LM4. When a combination of symbols (for example, bell-bell-bell) is awarded when the winning line LN is aligned with any of the LM1 to LM4, the symbols constituting the particular winning line LN It is easy to recognize that the combination is complete. In this embodiment, as shown in FIG. 1, an invalid line LM1 and a lower stage of the reel 2L, which are set across the symbols arranged horizontally in the upper stage of the reel 2L, the upper stage of the reel 2C, the upper stage of the reel 2R, that is, the upper stage. , The lower line of the reel 2C, the lower stage of the reel 2R, that is, the invalid line LM2 set across the symbols arranged horizontally in the lower stage, the upper stage of the reel 2L, the middle stage of the reel 2C, and the lower stage of the reel 2R, that is, lower right There are four types of invalid lines LM3 set across straddling symbols LM3, lower stage of reel 2L, middle stage of reel 2C, upper stage of reel 2R, that is, invalid line LM4 set straddling to the right. It is defined as.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  Then, when all the reels 2L, 2C and 2R are stopped, one game is finished, and a combination of symbols (hereinafter also referred to as a combination) predetermined on the winning line LN is a display result of each reel 2L, 2C and 2R. In the case of a stop, a winning occurs, and a predetermined number of medals are awarded to the player and added to the credit. Further, when the credit reaches the upper limit number (50 in this embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). In addition, when the combination of symbols accompanying the transition of the gaming state is stopped as a display result of each reel 2L, 2C, 2R on the winning line LN, the gaming state is shifted according to the combination of symbols.

  In the slot machine 1 according to the present embodiment, after the game is started and the reels 2L, 2C, and 2R are rotated and the symbols start to change, any one of the stop switches 8L, 8C, and 8R is operated. When this is done, the rotation of the reels corresponding to the stop switches 8L, 8C, 8R is stopped, and the symbols are stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (milliseconds).

  The reels 2L, 2C and 2R rotate 80 times per minute, and 80 × 21 (the number of symbols per reel) = 1680 frames, so the maximum of 4 symbols is drawn in 190 ms. Will be able to. In other words, the symbols that can be selected as the stop symbols are the symbols that are displayed when the stop switches 8L, 8C, and 8R are operated, and the symbols that are four frames ahead of them, for a total of five symbols.

  For this reason, for example, when any one of the stop switches 8L, 8C, 8R is operated and the symbol displayed on the lower stage of the reel corresponding to the stop switch is used as a reference, the symbol from the symbol to four frames ahead is used. Since the symbols can be displayed in the lower row, in each of the reels 2L, 2C, 2R, when any one of the stop switches 8L, 8R is operated, the symbol displayed in the middle row of the reel corresponding to the stop switch. Can be displayed on the winning line LN.

  FIG. 4 is a block diagram showing a configuration of the slot machine 1. As shown in FIG. 4, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The production according to the control is controlled, and the power supply board 101 generates the drive power for the electrical components constituting the slot machine 1 and supplies them to each part.

  The power supply board 101 is supplied with AC100V power from the outside, and from this AC100V power supply, a DC voltage necessary for driving electrical components constituting the slot machine 1 is generated, and the game control board 40 and the game control board 40 are generated. The direct current voltage (for example, 12V) for generating the voltage required for operation | movement of the various devices mounted in each board | substrate is supplied to the production | presentation control board | substrate 90 connected via this. In addition, a command transmission line from the main control unit 41 to the sub control unit 91, which will be described later, and a power supply line for supplying power from the game control board 40 to the effect control board 90 are connected via a single cable and connector. Are connected to each other, and all the connectors that connect these cables and the respective boards are connected to each other so that the respective parts on the side of the effect control board 90 can operate and receive commands from the main control part 41. Become. For this reason, unless the command transmission line for transmitting a command from the main control unit 41 is connected to the effect control board 90, power is not supplied to the effect control board 90, and only the effect control board 90 side operates. There is no end to it.

  Further, the above-described hopper motor 34b, payout sensor 34c, full sensor 35a, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101.

  On the game control board 40, the above-described MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, stop switch 36a, automatic settlement switch 36b, insertion medal sensor 31, door open The detection switch 25 and reel sensors 33L, 33C, and 33R are connected, and the above-described payout sensor 34c, full sensor 35a, setting key switch 37, and reset / setting switch 38 are connected via the power supply board 101. Detection signals from these connected switches are input.

  Further, the game control board 40 includes the credit display 11, the game auxiliary display 12, the payout display 13, 1 to 3 BET LEDs 14 to 16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 20, and the BET. The switch effective LED 21, left, middle, and right stop effective LEDs 22L, 22C, and 22R, the set value display 24, the flow path switching solenoid 30, and the reel motors 32L, 32C, and 32R are connected to each other, and are described above via the power supply board 101. The hopper motor 34b is connected, and these electric components are driven based on control of a main control unit 41 (described later) mounted on the game control board 40.

  The game control board 40 includes a main control unit 41, an external memory (SRAM) 50, a random number generation circuit 42, a sampling circuit 43, a switch detection circuit 44, a motor drive circuit 45, a solenoid drive circuit 46, an LED drive circuit 47, an electric interruption. A detection circuit 48 and a reset circuit 49 are mounted.

  The main control unit 41 is configured by a one-chip microcomputer and includes a main CPU 41a, a ROM 41b, a RAM 41c, and an I / O port 41d. The main control unit 41 executes a control program stored in the ROM 41b to perform processing related to the progress of the game, and directly or indirectly controls each part of the control circuit mounted on the game control board 40. In this embodiment, the main control unit 41 can only perform 16-bit or 32-bit bus access to an external device such as the SRAM 50.

  The random number generation circuit 42 is configured by a counter that counts up and updates the value every time a predetermined number of pulses are generated, and the sampling circuit 43 acquires the numerical value counted by the random number generation circuit 42. The random number generation circuit 42 defines a range of numerical values to be counted for each type of random number. In this embodiment, 0 to 65535 is defined as the range. The main CPU 41a sends an instruction to the sampling circuit 43 according to the processing to acquire the numerical value indicated by the random number generation circuit 42 as a random value (hereinafter, this function is referred to as a hardware random number function). Random numbers for internal lottery, which will be described later, are processed by software instead of using the random numbers extracted by the hardware random number function as they are. The main CPU 41a also has a function of updating a specific register value by the above-described timer interrupt process (main) and acquiring the updated numerical value as a random number (this function is hereinafter referred to as a software random number function). .

  The switch detection circuit 44 takes in detection signals input from switches connected directly to the game control board 40 or via the power supply board 101 and transmits them to the main control unit 41. The motor drive circuit 45 transmits the motor drive signal output from the main control unit 41 to the reel motors 32L, 32C, and 32R. The solenoid drive circuit 46 transmits the solenoid drive signal output from the main control unit 41 to the flow path switching solenoid 30. The LED drive circuit transmits the LED drive signal output from the main control unit 41 to various displays and LEDs connected to the game control board 40. The power interruption detection circuit 48 monitors the power supply voltage supplied to the slot machine 1 and outputs a voltage drop signal indicating that to the main control unit 41 when a voltage drop is detected. The reset circuit 49 gives a reset signal to the main control unit 41 in a state where the power supply is unstable, such as when the power is turned on or when the power is turned off.

  The CPU 41a of the main control unit 41 executes processing for controlling the progress of the game in the slot machine 1 by executing the program read from the ROM.

  As described above, in the main control unit 41, the CPU 41a executes control according to the program stored in the ROM 41b, so that the main control unit 41 (or CPU 41a) executes (or performs processing) hereinafter. Specifically, the CPU 41a executes control according to a program. The same applies to microcomputers mounted on boards other than the game control board 40.

  The RAM 41c included in the main control unit 41 provides a work area for game control and is used as a work RAM. In this embodiment, as will be described later, an SRAM 50 is connected to the main control unit 41 as an external memory, and this SRAM 50 is a backup RAM that is at least partially backed up by a backup power source. That is, even if the power supply to the slot machine is stopped, at least a part of the contents of the SRAM 50 is stored for a predetermined period. In this embodiment, all areas of the SRAM 50 are backup RAMs, and all contents of the SRAM 50 are stored for a predetermined period even when power supply to the slot machine is stopped. In this embodiment, the SRAM 50 serving as the backup RAM includes, for example, data used for control related to internal lottery, which will be described later, data used for control related to medal payout, and reel rotation and stop when power is cut off. Data used for control related to the command, data used for control related to command input / output, and the like are stored.

  The ROM 41a included in the main control unit 41 stores various selection data and table data used for controlling the progress of the game. For example, the ROM 41b stores data constituting a plurality of determination tables, determination tables, setting tables and the like prepared for the CPU 41a to perform various determinations, determinations, and settings. The ROM 41b stores table data constituting a plurality of command tables used for the CPU 41a to transmit control signals serving as various control commands from the game control board 40.

  The RAM 41c included in the main control unit 41 is provided with a game control data holding area as an area for holding various data used for controlling the progress of the game in the slot machine 1 and the like. For example, a DRAM is used as the RAM 41c, and a refresh operation is required to maintain the stored data contents. The CPU 41a has a built-in refresh register for performing this refresh operation. For example, the refresh register has 8 bits, and the lower 7 bits are automatically incremented every time the CPU 41a fetches an instruction from the ROM 41b. Accordingly, the stored value in the refresh register is updated every execution time of one instruction in the CPU 41a.

  The main control unit 41 transmits various commands to the sub control unit 91. A command transmitted from the main control unit 41 to the sub control unit 91 is sent in only one direction, and no command is sent from the sub control unit 91 toward the main control unit 41.

  The main control unit 41 receives the detection state of various switches connected to the game control board 40 from the input port. Then, the main control unit 41 executes basic processing that shifts in stages according to the detection states of various switches input from these input ports.

  Further, the main control unit 41 can execute an interrupt process by interrupting the basic process when an interrupt occurs. In the present embodiment, a timer interrupt process (main) described later is executed at regular time intervals (in the present embodiment, about 0.56 ms). In addition, the execution interval of the timer interrupt process (main) is set to a time longer than the sum of the time required to complete the repeated process according to the control state in the basic process and the execution time of the timer interrupt process (main) Therefore, the process that is repeated according to the control state between the current and next timer interrupt processes (main) is completed at least once.

  The main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, the main control unit 41 prioritizes according to a predetermined order. An interrupt to be executed is set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process is completed, a new interrupt will occur at that point. It will be.

  An effect switch 56 is connected to the effect control board 90, and a detection signal of the effect switch 56 is input.

  The effect control board 90 is connected to effect devices such as a liquid crystal display 51 (see FIG. 1), an effect LED 52, speakers 53 and 54, and the reel LED 55 described above, which are arranged on the front door 1b of the slot machine 1. These effect devices are driven based on control by a later-described sub-control unit 91 mounted on the effect control board 90.

  In this embodiment, the sub-control unit 91 mounted on the effect control board 90 controls the output of the effect devices such as the liquid crystal display 51, effect effect LED 52, speakers 53 and 54, and reel LED 55. However, in addition to the sub-control unit 91, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board, and the sub-control unit 91 is based on a command from the main control unit 41. The output control unit may determine the output pattern of the effect device, and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output control may be performed. The output control of the rendering device is performed by both of the units.

  Further, in the present embodiment, the liquid crystal display 51, the effect effect LED 52, the speakers 53 and 54, and the reel LED 55 are exemplified as the effect device, but the effect device is not limited to these, for example, a mechanically driven display. A device or a mechanically driven item may be applied as the effect device.

  Like the main control unit 41, the effect control board 90 includes a sub CPU 91a, a ROM 91b, a RAM 91c, and a microcomputer having an I / O port 91d. The sub control unit 91 controls the effect, and an external memory (SRAM). 99, a display control circuit 92 composed of a video display processor (VDP) that controls the display of the liquid crystal display 51 connected to the effect control board 90, an LED drive circuit 93 that controls the drive of the effect LED 52 and the reel LED 55, and a speaker An audio output circuit 94 that controls audio output from 53 and 54, a reset signal to the sub CPU 91a when the power source is unstable, such as when the power is turned on or when the power is turned off, or when the initialization command from the sub CPU 91a is not input for a certain time Effect that is connected to the reset circuit 95 and the effect control board 90 A switch detection circuit 96 that detects a detection signal input from the switch 56, a timepiece device 97 that outputs time information including date information and time information, and a power supply voltage (12V) supplied to the effect control board 90 are monitored. When detecting a drop (specifically, 9V), an interruption detection circuit 98 that outputs a voltage drop signal indicating that to the sub CPU 91a, other circuits, and the like are mounted. The sub CPU 91a In response to a command transmitted from the game control board 40, various controls for performing an effect are performed, and each part of the control circuit mounted on the effect control board 90 is directly or indirectly controlled. In this embodiment, the sub-control unit 91 can only perform 16-bit or 32-bit bus access to an external device such as the SRAM 99.

  The reset circuit 95 has a lower voltage for canceling the reset signal to the sub CPU 91a than the reset circuit 49 for giving the reset signal to the main CPU 41a of the main control unit 41 in the game control board 40, and the sub control unit when the power is turned on. 91 is activated at an earlier stage than the main control unit 41. On the other hand, the power interruption detection circuit 98 has a voltage that outputs a voltage drop signal lower than the power interruption detection circuit 48 that outputs a voltage drop signal to the main control unit 41 in the game control board 40. The sub control unit 91 detects a power failure at a later stage than the main control unit 41, and performs a power interruption process (sub) described later.

  Similar to the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. Execute command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 executes an interrupt process (sub), which will be described later, by generating an interrupt every time the number of input system clocks reaches a certain number, that is, every certain interval.

  Also, unlike the main control unit 41, the sub control unit 91 interrupts the process even when the timer interrupt process (sub) is being executed when an interrupt is generated based on the reception of the command. The command reception interrupt process is executed at the same time, and the command reception interrupt process is executed with the highest priority even if interrupts that trigger the timer interrupt process (sub) occur at the same time.

  The RAM 91c included in the sub control unit 91 provides a work area for various effects control such as liquid crystal display, lamp display, and sound output, and is used as a work RAM. In this embodiment, as will be described later, an SRAM 99 is also connected to the sub-control unit 91 as an external memory, and this SRAM 99 is a backup RAM that is at least partially backed up by a backup power source. That is, even if the power supply to the slot machine is stopped, at least a part of the contents of the SRAM 99 is stored for a predetermined period. In this embodiment, all areas of the SRAM 99 are used as a backup RAM, and even if the power supply to the slot machine is stopped, all contents of the SRAM 99 are stored for a predetermined period. In this embodiment, the SRAM 99 serving as a backup RAM includes, for example, data used for control related to sound and LED, data used for control related to AT, and control related to image display when power is cut off. Stores data to be used.

  As shown in FIG. 5A, the main control unit 41 and the SRAM 50 include a 16-bit address bus, a 32-bit data bus, a CS (chip select) signal line, an RD (read) signal line, and a WR (write). Connected via signal line.

  Here, the input / output state of signals when the main control unit 41 reads data from the SRAM 50 and writes data from the main control unit 41 to the SRAM 50 will be described. Note that the input / output status of signals when the main controller 91 reads data from the SRAM 99 and writes data from the main controller 91 to the SRAM 99 is the same.

  When the main control unit 41 reads data from the SRAM 50, as shown in FIG. 5B, the main control unit 41 designates an address at which data to be read from the SRAM 50 is stored on the address bus, and then The CS signal corresponding to the SRAM is turned ON, and the RD signal for instructing data reading is turned ON.

  The SRAM 50 that has detected the CS signal and the RD signal uses the data bus until the data stored in the address area designated by the address bus is turned off until the RD signal is turned off, that is, until the data fetching by the main control unit 41 is completed. Output to. On the other hand, the main control unit 41 turns off the RD signal by completing the data take-in from the data bus, and then turns off the CS signal and completes the reading of data from the SRAM 50.

  When the main control unit 41 writes data to the SRAM 50, as shown in FIG. 5C, the address where the data is stored is specified by the address bus and the data to be written to the SRAM 50 is output to the data bus. Thereafter, the CS signal corresponding to the SRAM is turned ON, and the WR signal for instructing data writing is turned ON.

  The SRAM 50 that has detected the CS signal and the WR signal fetches data from the data bus and writes the fetched data in the address area designated by the address bus. After that, the main control unit 41 turns off the WR signal and turns off the CS signal corresponding to the SRAM and writes the data to the SRAM 50 after a sufficient time has elapsed for the SRAM 50 to take in the data from the data bus. To complete.

  The sub-control unit 91 and the SRAM 99 are also connected via a 16-bit address bus, a 32-bit data bus, a CS (chip select) signal line, an RD (read) signal line, and a WR (write) signal line. 5B and 5C, the main control unit 41 reads data from the SRAM 50 and writes data from the main control unit 41 to the SRAM 50, and the sub control unit 91 reads data from the SRAM 99. Data reading and data writing from the sub-control unit 91 to the SRAM 99 are performed.

  In addition, the rated operating voltage of the SRAM 50 and the SRAM 99 is 3.3 V as shown in FIG. 32, and is mounted on the switching regulator IC (not shown) mounted on the game control board 40 or the effect control board 90. The first switching regulator IC 901 is supplied with a 3.3V DC voltage and operates.

  The SRAM 50 and the SRAM 99 have a built-in voltage monitoring circuit (not shown) for monitoring the supplied DC voltage. When the DC voltage reaches a predetermined voltage of 2.9 V, data writing is permitted and supplied. When the direct current voltage drops to 2.9 V, the data write instruction is reset and data write is prohibited. That is, when the supplied DC voltage is 2.9V or higher, that is, as will be described later, when the supplied DC voltage is 2.9V or higher, the sub CPU 91a of the sub control unit 91 is connected to the sub CPU 91a. Since writing is disabled in a state where operable 1.15 V is supplied, writing becomes impossible before the voltage supplied to the sub CPU 91a decreases and the operation of the sub CPU 91a becomes unstable. The data stored by the sub CPU 91a whose operation has become unstable due to the decrease in the supply voltage can be prevented from being erroneously rewritten.

  In the slot machine 1 of the present embodiment, the medal payout rate changes according to the set value. Specifically, the medal payout rate is changed by using a winning probability corresponding to a set value in an internal lottery described later. The set value is composed of 6 levels of 1 to 6, with 6 being the highest payout rate and the payout rate being lower as the value is decreased in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is highest for the player, and as the value decreases in order of 5, 4, 3, 2, 1, the advantage decreases stepwise.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after the setting key switch 37 is turned on. When the setting key switch 37 is turned on and the power is turned on, the setting value read from the RAM 41c is displayed as a display value on the setting value display 24, and the setting value can be changed by operating the reset / setting switch 38. Transition to the setting change state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the setting value display 24 is updated one by one (when further operation is performed from the setting 6, the display returns to the setting 1). . When the start switch 7 is operated, the display value is determined as the set value. When the setting key switch 37 is turned off, the determined display value (setting value) is stored in the RAM 41c of the main control unit 41, and the state shifts to a state in which the game can proceed.

  In order to check the set value, after the game is over, the setting key switch 37 may be turned on in a state where the bet amount is not set. When the setting key switch 37 is turned on in such a situation, the setting value read out from the RAM 41c is displayed on the setting value display 24, thereby shifting to a setting confirmation state in which the setting value can be confirmed. In the setting confirmation state, the game cannot be progressed, and by setting the setting key switch 37 to the off state, the setting confirmation state is ended and the state in which the game can proceed is returned.

  In the slot machine 1 of the present embodiment, each time the main control unit 41 and the sub control unit 91 execute the timer interrupt process (main) shown in FIG. 12 or the timer interrupt process (sub) shown in FIG. A power failure determination process (Sk2 in FIG. 12 or Sp2 in FIG. 25) is performed to determine whether or not a voltage drop signal from the power failure detection circuit 48 (98) is detected, and the voltage drop signal is detected in the power failure determination process. 14 is executed, the power interruption process (main) shown in FIG. 14 and the power interruption process (sub) shown in FIG. 26 are executed. In the power interruption process (main) and the power interruption process (sub), as described later, a backup flag is set in the SRAM 50 for each program module, and data used in the program module is calculated to generate a checksum. The generated checksum is stored in the SRAM 50. The checksum is a value stored in each bit of a corresponding area of the RAM 41c or RAM 91c (in this embodiment, all areas in the work RAM in which data used by the program module is stored). It is a value calculated as the exclusive OR of. For this reason, if the value obtained by calculating the exclusive OR based on the data stored in all areas in the work RAM in which the data used by the program module is stored is 0, the checksum is 0. If the value obtained by calculating the exclusive OR based on the data stored in all the areas in the work RAM in which the data used in the program module is stored is 1, the checksum is 1.

  The main control unit 41 and the sub control unit 91 store data used in the program module in the external memory (backup RAM) for each module, regardless of whether the system reset or the user reset is performed. Calculate the checksum based on the data of all the stored areas, check the backup flag, check that the calculated checksum matches the checksum value being backed up, and that the backup flag is also set. Based on the data stored in the SRAM 50 as a condition, the processing state of the main control unit 41 and the sub control unit 91 is restored to the state before the power interruption, but the checksum value does not match or the backup flag is set. If not, it is determined that the RAM is abnormal. At this time, if the main control unit 41 determines that the RAM is abnormal, the RAM abnormal error code is set in the register and controlled to a RAM abnormal error state to disable the progress of the game. Unlike the normal error state, the RAM abnormal error state is not canceled even if the reset switch 23 or the reset / setting switch 38 is operated, and a new set value is set in the above-described setting change state. It will not be released until On the other hand, when the sub control unit 91 determines that the RAM abnormality error has occurred, all the areas of the SRAM 99 and the RAM 91c are initialized.

  In this embodiment, all the data stored in the RAM 41c and RAM 91c are stored in the SRAM 50 and SRAM 99 and maintained by the backup power source even during a power failure, and the main control unit 41 and the sub control unit 91 The data stored in the RAM 41c and the RAM 91c is configured to return to the control state before the power interruption based on the data stored in the SRAM 50 and the SRAM 99 when it is determined that the data in the SRAM 50 and the SRAM 99 is normal at the time of turning on. Of these, only the data necessary for the return of the control state at the time of a power failure may be backed up in the SRAM 50 and SRAM 99, and the control state before the power interruption may be restored based on the backed up data when the power is turned on.

  In addition, when returning to the control state before the power interruption when the power is turned on, it is not necessary to return all the control states to the control state before the power interruption, and the minimum control state that does not disadvantage the player For example, it is not necessary to restore the state of all input ports to the state before power interruption.

  In the slot machine 1 of this embodiment, as described above, the prescribed number of bets that can be set according to the gaming state (usually inside, BB (RB)) is determined, and is determined according to the gaming state. The game can be started on the condition that the specified number of bets has been set. In this embodiment, the winning line LN is activated when a specified number of bets according to the gaming state are set.

  In the slot machine 1 of this embodiment, when all the reels 2L, 2C, and 2R are stopped, the activated winning line LN (hereinafter, the activated winning line LN is simply referred to as the winning line LN). A winning combination will be awarded when a combination of symbols called roles is complete. The combination may be a combination of the same symbols or a combination including different symbols. The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that allows the next game to be started without the need to set the number of bets. There are a game combination and a special combination with a transition to a game state advantageous to the player. Below, a small role and a re-playing role are collectively called a general role. In order for winning of each combination determined according to the gaming state to occur, it is necessary to win an internal lottery to be described later and set a winning flag of the combination in the RAM 41c.

  Of the winning flags for each of these combinations, the winning flag for the small role and the re-playing role is valid only in the game in which the flag is set, and is invalid in the next game. It is valid until the combination of combinations permitted by the flag is complete, and is invalid in a game having the combination of combinations permitted. In other words, once the winning flag for a special role is won, even if the combination of characters allowed by the flag cannot be aligned, the winning flag is not invalidated and is carried over to the next game. It becomes.

  In the internal lottery, it is determined whether or not the above winning combination is permitted before the display results of all the reels 2L, 2C, and 2R are derived and displayed (actually, when the start switch 7 is detected). To do. In the internal lottery, first, a random value for internal lottery (an integer from 0 to 65535) is acquired when the start switch 7 is detected. Specifically, the value of the random number value storage work assigned to the RAM 41c is set to the lottery work assigned to the RAM 41c. Then, for each combination determined according to the gaming state and whether or not the special combination is carried over, the numerical data stored in the lottery work, the value of the gaming state flag for specifying the gaming state, and the RT described later are specified. The determination is made according to the number of determination values of each combination determined according to the value of the RT flag, the number of bets, and the set value.

  In the internal lottery, an internal lottery target, a current gaming state flag value, an RT flag value, and the number of determination values determined corresponding to the set value are stored in a random number for internal lottery (a lottery work). When the result of addition overflows, it is determined that the winning combination is won. For this reason, a winning combination will be won with a probability (number of determination values / 65536) according to the number of determination values.

  If a winning combination of any combination is determined, a winning flag corresponding to the combination determined to be winning is set in the internal winning flag storing work assigned to the RAM 41c. The internal winning flag storage work consists of a 2-byte storage area, of which the upper byte is assigned as the special role storing work in which the winning flag for the special role is set, and the lower byte is the winning of the general role It is assigned as a general role storage work for which a flag is set. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination is won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When a general combination is won, a winning flag for the general combination indicating that the general combination is won is set in the general combination storing work. If no winning combination or combination of winning combinations is won, only the general winning combination storing work is cleared.

  Next, stop control of the reels 2L, 2C, 2R will be described.

  The main control unit 41 refers to the table index and table creation data stored in the ROM 41b when the reel starts to rotate and when the reel stops and the reel that is still rotating still remains. A stop control table is created for each reel that is rotating. When any of the stop switches 8L, 8C, and 8R corresponding to the rotating reel is effectively detected, the stop control table of the corresponding reel is referred to and the slip of the referred stop control table is referred to. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In the table index, an index that indicates the start address of the area in which the data for table creation is stored, from the reference address when referring to the table index, according to the setting state of the winning flag by internal lottery (hereinafter referred to as the internal winning state) Differences up to the address where the data is stored are registered. As a result, a difference corresponding to the internal winning state is acquired, and the corresponding index data can be acquired by adding the difference to the reference address. Even when the winning combinations are different, when the same control is applied, the same address is stored as the index data. In such a case, the same table creation data is referred to. Thus, a stop control table is created.

  The table creation data includes a stop control table indicating the number of sliding frames according to the stop operation position, and an address of the stop control table to be referred to according to the reel stop status.

  The stop control table referred to according to the reel stop status is whether all reels are rotating, only the left reel is stopped, only the middle reel is stopped, only the right reel is stopped, It may vary depending on whether the middle reel is stopped, the left and right reels are stopped, the middle and right reels are stopped, and if any reel is stopped, stop Since there may be differences depending on the stop position of the reels already completed, the address of the stop control table to be referred to is registered for each rotating reel for each situation, It is possible to specify the address of the stop control table that should be referred to according to the status of each, and it is necessary according to each status from this specified address. And to be able to identify the stop control table. Even when the reel stop status and the stopped position of the stopped reel are different, when the same stop control table is applied, the same address may be registered as the address of the stop control table. In such a case, the same stop control table is referred to.

  The stop control table is data that can specify the number of sliding frames for each timing when the stop operation is performed. In this embodiment, stepping motors that make one turn at a cycle of 168 steps (0 to 167) are used for the reel motors 32L, 32C, and 32R. That is, when the reel motors 32L, 32C, and 32R are driven for 168 steps, the reels 2L, 2C, and 2R make one round. 21 areas (frames) divided every 8 steps (the number of steps in which one symbol moves) per reel are defined, and these areas are areas 0 to 20 from the reel reference position. A number is assigned. On the other hand, the number of symbols arranged on one reel is 21, and symbol numbers 0 to 20 from the reel reference position are assigned to symbols on each reel, so symbols 0 to 20 are assigned to each reel. , Area numbers 0 to 20 are assigned in order. In the stop control table, the number of sliding symbols for each area number is compressed and stored according to a predetermined rule, and the number of sliding symbols for each area number can be acquired by expanding the stop control table. Yes.

  As described above, the stop control table created by referring to the table index and the table creation data corresponds to the area number, and the area corresponding to each area number is the stop reference position (in this embodiment, the perspective window 3). Sliding frame when an operation of the stop switches 8L, 8C, 8R is detected at a timing (a timing in which the number of steps from the reel reference position is included in the range of the number of steps of each region number). It is a table with each number set.

  Next, the procedure for creating the stop control table will be described. First, at the start of reel rotation, the top address of the table creation data corresponding to the internal winning state of the game is acquired. Specifically, the table index is first referred to, index data corresponding to the internal winning state is obtained, table creation data is identified based on the obtained index data, and all reels are identified from the identified table creation data. The address of the stop control table for each reel corresponding to the state of rotation is acquired, and the stop control table for each reel stored at the acquired address is expanded to generate a stop control table for all reels.

  Further, when any one reel stops or any two reels stop, the index data acquired at the start of reel rotation, that is, the top address of the table creation data corresponding to the internal winning state of the game The table creation data is identified based on the table creation data, and the stop control table address of the unreacted reel corresponding to the stopped reel and the area number of the stop position of the reel is obtained from the identified table creation data. The stop control table for each stored reel is expanded to create a stop control table for the unstopped reels.

  Next, when the main control unit 41 effectively detects any one of the stop switches 8L, 8C, and 8R corresponding to the rotating reel, the control when the display result is derived to the corresponding reel is described. To explain, when any operation corresponding to the rotating reel is detected effectively among the stop switches 8L, 8C, 8R, the stop operation position is based on the number of steps from the reel reference position when the stop operation is detected. The number of sliding symbols corresponding to the area number of the specified stop operation position is acquired by referring to the stop control table of the reel where the stop operation is detected. Then, control is performed to rotate and stop the reel by the number of acquired sliding frames. Specifically, from the number of steps from the reel reference position at the time when the stop operation is detected, the number of steps from the acquired number of sliding frames to the stop is calculated, and the reel is rotated and stopped by the calculated number of steps. Take control. As a result, the area corresponding to the area number that is the stop position ahead of the number of sliding frames from the area corresponding to the area number of the stop operation position where the stop operation is detected is the stop reference position (in this embodiment, the perspective window 3 It will stop in the lower symbol area).

  In the table index of this embodiment, only one address is stored as index data corresponding to one internal winning state in one gaming state, and further, one table creation data includes one reel. Only one address is stored as the address of the storage area of the stop control table corresponding to the stop status (and the stop position of the stopped reel). In other words, table creation data corresponding to one internal winning state in one gaming state and stop control tables corresponding to reel stop states (and stopped positions of stopped reels) are uniquely determined. The stop control table created with reference to is unique for one internal winning state in one gaming state and the reel stop status (and the stop position of the stopped reel). Therefore, when all of the gaming state, the internal winning state, and the reel stop status (and the stop position of the stopped reel) are the same, the reel is based on the same stop control table, that is, the same control pattern. The stop control is performed.

  Further, in this embodiment, a value of 0 to 4 is determined as the number of sliding frames, and the reel can be stopped by drawing a maximum of 4 symbols after detecting the stop operation. In other words, the stop position of the symbol can be designated from a range of a maximum of 5 frames including the stop operation position where the stop operation is detected. In addition, since it is necessary to move one frame to move the reel for one symbol, it is possible to stop the reel by pulling in a maximum of four symbols after detecting the stop operation. The symbol stop position can be designated from a range of up to five symbols including the operation position.

  In the present embodiment, when any winning combination is won, the winning combination is drawn to the winning line LN to the maximum extent within a range of 4 frames, and the winning combination is drawn so that the winning combination is not aligned with the winning line LN. A stop control table with a defined number of frames is created and reel stop control is performed. If no winning combination is selected, a stop control table with a determined number of sliding symbols that do not have any combination And stop control of the reel. As a result, when a stop operation is performed, if the winning combination can be stopped in the winning line LN within the drawing range of a maximum of 4 frames, the control is performed so that the winning combination is stopped. The combination that has not been performed will be controlled to be stopped in a drawing range of up to 4 frames.

  If a special role and a small role are elected at the same time, such as when a special role is elected while the special role has been carried over from before the previous game, the elected small role will be placed in the winning line LN within 4 frames. The number of sliding symbols is set so as to be pulled in as much as possible, and for the stop operation position where the selected small role cannot be drawn into the winning line LN within the range of up to 4 frames, the winning special role is set to 4 in the winning line LN. A stop control table in which the number of sliding frames is determined so as to be pulled in as much as possible within the range of frames is created, and reel stop control is performed. As a result, when a stop operation is performed, if it is possible to stop all the small roles that have been selected in the winning line LN within a drawing range of a maximum of 4 frames, the control is performed so that the winning combination is stopped. If it is not possible to withdraw a small role that has been won in the draw range of up to 4 frames to the line LN, if the special role that has been won in the draw range of up to 4 frames can be aligned and stopped on the winning line LN, Control is performed to align and stop this, and the winning combination that has not been won is controlled to be stopped within the drawing range of 4 frames. That is, in such a case, priority is given to the control for aligning the small role with the winning line LN over the special role, and the special role can be won only when the small role cannot be drawn. When a special combination and a small combination can be withdrawn at the same time, only the small combination is drawn, and the small combination is not aligned with the winning line LN at the same time as the special combination.

  In this example, when a special role is elected while the special role has been carried over from before the previous game, or when a special role and a small role are simultaneously elected, the special role and the small role are won simultaneously. If the winning combination is prioritized over the selected winning combination, and only when the winning combination cannot be withdrawn, control is performed to align the winning combination with the winning line LN. When winning simultaneously, priority is given to the control for aligning the special combination with the winning line LN over the small combination, and the control for aligning the small combination with the winning line LN may be performed only when the special combination cannot be drawn.

  If a special player and a replaying player are elected at the same time, such as when a replaying player is elected while the special role has been carried over from before the previous game, the winning line LN will be displayed when the stop operation is performed. In addition, a control is performed in which the symbols of the re-gamer are aligned and stopped within a drawing range of up to 4 frames. In this case, the symbols constituting the re-gamer or the symbols constituting the re-gamer to be simultaneously elected are arranged at intervals of 5 symbols or less, that is, within 4 frames, for any of the reels 2L, 2C, and 2R. Since it can always be stopped at any position within the 4-frame pull-in range, if the special combination and the re-playing combination are elected at the same time, the timing of the operation of the stop switches 8L, 8C, 8R by the player Without fail, the re-playing role will always be won. That is, in such a case, the control for aligning the re-games with the winning line LN has priority over the special game, and the re-games will always win. In the case where the special combination and the re-playing combination can be withdrawn at the same time, only the re-playing combination is drawn in and the special combination is not aligned with the winning line LN at the same time as the re-playing combination.

  In this embodiment, after the rotation of the reels 2L, 2C, and 2R is started, the main control unit 41 rotates the reels for which the stop operation has not been detected yet until the operation of the stop switches 8L, 8C, and 8R is detected. Continuously, on the condition that the operation of the stop switches 8L, 8C, and 8R is detected, control is performed to stop the display result on the corresponding reel. Even if the reel rotation temporarily stops due to the occurrence of a reel rotation error, the stop operation is still detected until the operation of the stop switches 8L, 8C, and 8R is detected after the reel rotation is restarted. Control is performed to stop the display result of the corresponding reels on the condition that the rotation of the reels that have not been continued is continued and the operation of the stop switches 8L, 8C, and 8R is detected.

  In this embodiment, control is performed to stop the display result on the corresponding reel on condition that the operation of the stop switches 8L, 8C, and 8R is detected. However, the rotation of the reel is started. When a predetermined automatic stop time has elapsed, even if the reel stop operation is not performed, it is assumed that the stop operation has been performed, and automatic stop control is performed to automatically stop each reel. May be. In this case, since the reels are stopped without the player's operation, for example, it is preferable to derive a display result that does not constitute any combination even if any combination is won.

  As shown in FIG. 6, the game control program is stored in the ROM 41 b of the game control board 41. The game control program includes an internal lottery control module that performs control related to the internal lottery process executed in Sd2 in the game control process of FIG. 11 and an input / output process executed in Sd7 of the game control process of FIG. An input / output control module that performs control related to input / output at the I / O port), a reel rotation control module that performs control related to reel rotation processing executed in Sd3 in the game control processing of FIG. 11, and FIG. A payout control module for performing control related to the payout process executed in Sd5 in the game control process. Thus, the game control program includes a plurality of control modules corresponding to each control executed on the main control board 41. Therefore, only one type of control module (one or more) may be replaced with another type. In this case, only the control module needs to be replaced, and the game control program can be easily changed.

  As shown in FIG. 7, an effect control program is stored in the ROM 91 b of the effect control board 91. The effect control program includes a game history control module that performs control such as accumulation of game history in the game history control process executed at Sp8 in the timer interrupt process (sub) of FIG. 25, and the timer of FIG. In the sound / LED control process executed at Sp5 in the interrupt process (sub), the sound / LED control module for performing control related to the effect LED 52, the speakers 53, 54, and the reel LED 55 described above, and the timer allocation of FIG. In the AT control module that performs control related to the AT control process executed in Sp6 in the interrupt process (sub), and in the image control process that is executed in Sp7 in the timer interrupt process (sub) in FIG. And an image control module for performing control related to image display. Thus, the effect control program includes a plurality of control modules corresponding to each control executed on the effect control board 91. Therefore, only one type of control module (one or more) may be replaced with another type. In this case, only the control module needs to be replaced, and the production control program can be easily changed.

  Next, various control contents executed by the main control unit 41 in the present embodiment will be described below with reference to FIGS.

  When a reset signal is input from the reset circuit 49 to the main CPU 41a, the main control unit 41 performs start-up processing (main) shown in the flowcharts of FIGS.

  First, after the built-in device, peripheral IC, interrupt mode, stack pointer, etc. are initialized (Sa1), the values of the I register and IY register are initialized (Sa2). By the initialization of the I register and the IY register, the address of the interrupt table to be referred to when an interrupt occurs is set in the I register, and the reference address for referring to the storage area of the RAM 41c is set in the IY register. . These values are fixed values and are always initialized at startup. Next, by setting the output of the general-purpose port corresponding to the general-purpose terminal to which the CS signal line connected to the SRAM 50 is connected (Sa3), after enabling the output of the chip select signal of the SRAM 50, the RAM 41c Access to (work RAM) is permitted (Sa4).

  After permitting access to the RAM 41c (work RAM), it is determined whether or not the backup flag for the internal lottery control module is set in the SRAM 50 (backup RAM) (Sa5). In this embodiment, in Sm5, Sm10, Sm15, and Sm20 in the power interruption process (main) of FIG. 14, when a power interruption occurs, a backup flag is set for each program module. That is, in this embodiment, regarding the processing performed by the main control unit 41, the backup flag corresponds to the backup flag corresponding to the internal lottery control module, the backup flag corresponding to the input / output control module, and the reach rotation control module. There are four types of backup flags and backup flags corresponding to the payout control module. In Sa5, the main control unit 41 first checks whether or not a backup flag corresponding to the internal lottery control module is set.

  When the backup flag corresponding to the internal lottery control module is set, the backup flag is cleared (Sa6). After clearing the backup flag, a checksum is calculated by obtaining an exclusive OR of data in an area where data used in the internal lottery control module of the SRAM 50 (backup RAM) is stored (Sa7). Thereafter, it is determined whether or not the calculated checksum matches the backed-up checksum (Sa8). In this embodiment, in Sm4, Sm9, Sm14, and Sm19 in the power interruption process (main) of FIG. 14, the data used in the module is excluded for each module when a power interruption occurs. Is generated by obtaining a logical OR, and stored in the SRAM 50 (backup RAM). That is, in this embodiment, regarding the processing performed by the main control unit 41, the checksum includes a checksum calculated using data used in the internal lottery control module and data used in the input / output control module. There are four types: a checksum calculated using the checksum, a checksum calculated using data used in the reach rotation control module, and a checksum calculated using data used in the payout control module. . In Sa8, the main control unit 41 first confirms whether or not the checksum calculated using the data used in the internal lottery control module matches that being backed up.

  If the checksums match, it is determined whether a backup flag corresponding to the input / output control module is set in the SRAM 50 (backup RAM) (Sa9). If the backup flag corresponding to the input / output control module is set, the backup flag is cleared (Sa10). After clearing the backup flag, a checksum is calculated by obtaining an exclusive OR of data in an area where data used by the input / output control module of the SRAM 50 (backup RAM) is stored (Sa11). Thereafter, it is determined whether or not the calculated checksum matches the backed-up checksum (Sa12).

  If the checksums match, it is determined whether a backup flag corresponding to the reel rotation control module is set in the SRAM 50 (backup RAM) (Sa14). If the backup flag corresponding to the reel rotation control module is set, the backup flag is cleared (Sa15). After clearing the backup flag, the exclusive sum of the data in the area where the data used in the reel rotation control module of the SRAM 50 (backup RAM) is stored is calculated to calculate the checksum (Sa16). Thereafter, it is determined whether or not the calculated checksum matches the backed-up checksum (Sa17).

  If the checksums match, it is determined whether a backup flag corresponding to the payout control module is set in the SRAM 50 (backup RAM) (Sa18). If the backup flag corresponding to the payout control module is set, the backup flag is cleared (Sa19). After clearing the backup flag, the checksum is calculated by obtaining the exclusive OR of the data in the area where the data used by the payout control module of the SRAM 50 (backup RAM) is stored (Sa20). Thereafter, it is determined whether or not the calculated checksum matches the backed-up checksum (Sa21).

  In Sa8, Sa12, Sa17, Sa21, when it is determined that even one checksum does not match, or in Sa5, Sa9, Sa14, Sa18, it is determined that no backup flag is set. In this case, after executing an initialization process for initializing all storage areas of the RAM 41c (work RAM) and the SRAM 50 (backup RAM) (Sa29), it is determined whether the setting key switch 37 is on (Sa30). . If the setting key switch 37 is on, a setting changing command indicating that the setting is being changed is generated, and the generated setting changing command is stored in the command buffer (Sa27). The setting changing command is immediately transmitted by executing the same process as the command transmission process of step Sk16 in the timer interrupt process described later after the process of step Sa27. Next, the main control unit 41 described in FIG. 12 permits the interruption of the timer interruption process (main) executed at regular intervals (0.56 ms interval) (Sa28), and changes the winning probability of the winning combination, etc. The process shifts to a setting change process for performing the setting, that is, a setting change state. When the setting change process is completed, the game control process shown in FIG. 11 is performed.

  If the setting key switch 37 is OFF in the step of Sa30, an error code indicating RAM abnormality is set in the register (Sa31), an error command indicating RAM abnormality is generated, and the generated error command is stored in the command buffer ( Sa32). The error command is transmitted immediately after the process of step Sa32 by executing the same process as the command transmission process of step Sk16 in the timer interrupt process described later. Next, the main control unit 41 described in FIG. 12 permits the interrupt of the timer interrupt process (main) executed at regular intervals (0.56 ms interval) (Sa33), and error processing, that is, the RAM abnormal error state Migrate to Then, for example, when the RAM abnormality error state is canceled by operating the reset / setting switch 38 by a game store clerk, the game control process shown in FIG. 11 is performed.

  If it is determined in Sa21 that the checksums match, it is determined whether or not the setting key switch 37 is on (Sa23). If the setting key switch 37 is on, the initialization process for initializing all storage areas of the RAM 41c (work RAM) and the SRAM 50 (backup RAM) is executed (Sa26), and then the processes of Sa27 to Sa28 described above are performed. , Transition to the setting change process, that is, the setting change state. When the setting change process is completed, the game control process shown in FIG. 11 is performed.

  If the setting key switch 37 is off in the step of Sa23, each register is returned to the state before power interruption, that is, the state stored in the stack (Sa24). Then, a return command is generated, the generated return command is stored in the command buffer (Sa24a), and a timer interrupt process (main interval of 0.56 ms) executed by the main control unit 41 described in FIG. Main) interrupt is permitted (Sa25), and the process executed last before power interruption is returned to. The return command is stored in a command transmission buffer assigned to a special work in the RAM 41c of the main control unit 41, and a process similar to the command transmission process in step Sk16 in the timer interrupt process described later is executed. Sent immediately when power is restored. If any one of the game control processes shown in FIG. 11 has been performed before the power interruption, the game control process Sd1 to Sd7 is executed based on the value of the program counter (PC) restored in Sa24. Return to the processing that was performed before power interruption. Further, for example, if any of the timer interrupt processing shown in FIG. 12 has been performed before power interruption, the timer interrupt is based on the value of the program counter (PC) restored in Sa24. Of the processes Sk1 to Sk26, the process returns to the process performed before power interruption.

  As described above, in the start-up process (main), all the checksums of the program modules match each other and all the backup flags for the program modules are set. Since the previous state is restored, it is possible to prevent the backup data of some modules from being restored even though they are not accurate. Thereby, even if backup data is created for each module, it can be reliably restored.

  Commands transmitted from the main control unit 41 to the sub-control unit 91 include a reel rotation start command, a reel stop command, a return command, a setting change command, and an error command.

  The reel rotation start command is a command for notifying the start of reel rotation. The reel stop command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, the area number of the corresponding reel stop operation position, and the area number of the corresponding reel stop position. It is. Since the reel stop command is transmitted when the stop switches 8L, 8C, and 8R are operated, it is possible to specify that the stop switches 8L, 8C, and 8R are operated by receiving the reel stop command. .

  The error command is a command indicating occurrence or cancellation of an error state and the type of error state.

  The return command is a command indicating that the main control unit 41 has returned to the control state before power interruption.

  The setting changing command is a command indicating that the setting is being changed. In addition, since the control state of the main control unit 41 is initialized with the transition to the setting change state, the control state of the main control unit 41 is initialized by a setting changing command indicating that the setting is being changed. Can be specified.

  With respect to the above-described multiple types of commands, when a command for changing settings, an error command, or a return command is transmitted in the startup process shown in FIGS. 8 to 10, these commands are stored in the RAM 41 c of the main control unit 41. Is stored in the command transmission buffer assigned to the special work, and is transmitted immediately in the startup process by executing the same process as the command transmission process in step Sk16 in the timer interrupt process described later.

  On the other hand, the reel rotation start command and the reel stop command are temporarily stored in a command transmission buffer provided in a special work in the RAM 41c of the main control unit 41, and executed by the timer interrupt process (main) shown in FIG. Is transmitted to the sub-control unit 91 in the command transmission process (Sk16).

  FIG. 11 is a flowchart showing the control content of the game control process executed by the main control unit 41.

  In the game control process, a BET process (Sd1), an internal lottery process (Sd2), a reel rotation process (Sd3), a winning determination process (Sd4), a payout process (Sd5), a game end process (Sd6), an input / output process ( When the input / output process (Sd7) is completed, the process returns to the BET process (Sd1) again.

  In the BET process in the step of Sd1, the process waits in a state where a bet number can be set, and a process for starting a game when a specified number of bets is set according to the gaming state and the start switch 7 is operated is executed. .

  The internal lottery process in step Sd2 is a process executed by the main control unit 41 according to the internal lottery module. In the internal lottery process in the step of Sd2, it is determined whether or not the above winning combination is allowed based on the internal lottery random value latched simultaneously with the start of the game by the detection of the start switch 7 in the step of Sd1. Process. In this internal lottery process, a winning flag is set in the RAM 41c based on the respective lottery results.

  The reel rotation process in step Sd3 is a process executed by the main control unit 41 according to the reel rotation control module. In the reel rotation process in the step of Sd3, the process of rotating each reel 2L, 2C, 2R and the operation of the corresponding reel 2L, 2C, 2R in response to the operation of the stop switch 8L, 8C, 8R detected by the player are detected. A process for stopping the rotation is executed. A reel rotation command indicating that the reels 2L, 2C and 2R have started rotating, a reel stop command indicating the type of reel to be stopped, and a symbol to be stopped for the reel are generated in the reel rotation processing and stored in the command buffer. . Each command stored in the command buffer is transmitted to the sub-control unit 91 in the command transmission process (Sk16) executed in the timer interrupt process (main) shown in FIG. Then, it waits until the rotation of the reel (2L, 2C, 2R) corresponding to the operated stop button stops (Sf12).

  In the winning determination process in the step Sd4, when it is determined in the step Sd3 that the rotation of all the reels 2L, 2C, and 2R is stopped, the winning is determined according to the display result derived for each reel 2L, 2C, and 2R. A process of determining whether or not it has occurred is executed.

  The payout process in step Sd5 is a process executed by the main control unit 41 according to the payout control module. In the payout process in step Sd5, when it is determined that a prize is generated in step Sd4, processing such as addition of credits and payout of medals is performed based on the number of payouts according to the win.

  In the game end process in the step of Sd6, a process of setting a gaming state in preparation for the next game is executed.

  The input / output process in step Sd7 is a process executed by the main control unit 41 according to the input / output control module. In the input / output process in step Sd7, the input state of the input port is monitored, the presence / absence of input of various switches is detected, and the detection result is set in the input buffer. In this embodiment, for example, in the switch input determination process of Sk21 in FIG. 13 and the stop switch process of Sk23 in FIG. 13 described later, whether or not each switch is turned on by looking at the state of the input buffer set in Sd7. To check. In the input / output process in step Sd7, a process of outputting output signals to various solenoids and LEDs is performed based on the state of the output buffer. In this embodiment, for example, various output values such as LEDs are set in the output buffer in the LED dynamic display process of Sk12 in FIG.

  12 and 13 are flowcharts showing the control contents of the timer interrupt process (main) executed by the main control unit 41 by interrupting and executing the activation process and the game control process at regular intervals (0.56 ms interval). Note that other interrupts are automatically prohibited during the execution period of the timer interrupt process (main).

  In the timer interrupt process (main), first, the register in use is saved in the stack area (Sk1).

  Next, a power failure determination process is performed (Sk2). In the power failure determination process, it is determined whether or not a voltage drop signal is input from the power failure detection circuit 48. If a voltage drop signal is input, whether or not the voltage drop signal is input in the previous power failure determination process as well. If a voltage drop signal has been input in the previous power failure determination process, it is determined that a power failure has occurred, and a power interruption flag indicating that is set.

  After the power failure determination process in the step of Sk2, it is determined whether or not the power interruption flag is set (Sk3). If the power interruption flag is not set, the process proceeds to Sk4 and the power interruption flag is set The process proceeds to a power interruption process (main) described later.

  In step Sk4, port input processing for inputting detection data of various switches from the input port is performed.

  Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt process (main) is advanced by 1 from the four types of timer interrupts 1 to 4 (Sk5). In this embodiment, the timer interrupt 1 is a branch process during a timer interrupt that controls the motor to control the start of the reel. Specifically, the processes from Sk9 to Sk11, such as a reel start process described later. Is done. Timer interrupt 2 is a branch process during timer interrupt that performs LED display control, time counter update, door open / close status monitoring, control signal output control, command and external output signal update, etc. Specifically, the processes of Sk12 to Sk17 such as the LED dynamic display process described later are performed. The timer interrupt 3 is a branching process during timer interrupt that detects the origin passage of the reel, monitors the switch input, and reads out the random number value. Processing of Sk20 to Sk22 such as time processing is performed. The timer interrupt 4 is a branching process during a timer interrupt that detects the input of a stop switch and performs reel stop control. Specifically, the processes of Sk23 to Sk25, such as a stop switch process described later. Is done. In the step of Sk5, 1 is added when the branch counter value is 0 to 2, and is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Each time the timer interrupt process (main) is executed.

  Next, the branch counter value is referenced to determine whether it is 2 or 3, that is, timer interrupt 3 or timer interrupt 4 (Sk6). If it is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt In the case of 1 or timer interrupt 2, it is checked whether the reel motors 32L, 32C, 32R are started or whether they are rotating at a constant speed, and whether the reel motors 32L, 32C, 32R are started or are rotating at a constant speed. For example, the motor phase signal output process for outputting the phase signal data changed in the motor step process of Sk10 described later and the phase signal data changed in the final stop process of Sk24 described later is executed (Sk7).

  Next, referring to the counter value for branching, it is determined whether or not it is 1, that is, timer interrupt 2 (Sk8). If it is not timer interrupt 2, that is, timer interrupt 1, the reel motor Reel starting process (Sk9) for controlling the step time interval when starting 32L, 32C, 32R, motor step process (Sk10) for changing phase signal data of the reel motors 32L, 32C, 32R, reel motors 32L, 32C After the stop of 32R, motor phase signal standby processing (Sk11) for changing the phase signal to one-phase excitation after a predetermined time has been sequentially executed, and then the process proceeds to step Sk25.

  In the case of timer interrupt 2 in the step of Sk8, LED dynamic display processing (Sk12) for dynamically lighting various indicators, and output processing of control signals and the like for outputting data such as lighting signals of various LEDs to the output port (Sk13), a time counter update process (Sk14) for updating various time counters, a door monitoring process (Sk15) for monitoring the detection state of the door open detection switch 25, a door command transmission request, etc., set in the command buffer A command transmission process (Sk16) for transmitting various commands such as a setting change command, a return command, and an error command to the sub-control unit 91 and an external output signal update process (Sk17) for updating the external output signal are sequentially executed, and then Sk25. Go to step.

  If it is timer interrupt 3 or timer interrupt 4 in the step of Sk6, it is further determined by referring to the counter value for branching whether it is 3, that is, timer interrupt 4 (Sk18). If it is not interrupt 4, that is, if it is timer interrupt 3, the passing of the origin of the rotating reels 2L, 2C, 2R (pass of the reel reference position) is checked, and the occurrence of a reel rotation error is detected and stopped. Check if the preparation is complete (whether the stop preparation completion code is set). If the stop preparation is complete and the motor is rotating at a constant speed, operate the stop switch corresponding to the rotating reel. Processing to pass through origin (Sk20), switch input determination processing (Sk21) for determining whether or not the detection state of switches has changed, operation detection command transmission request, etc. After executing random number reading process to be stored in the random number storing work the (SK22) sequentially reads numeric data from Staphylococcus R1D, the process proceeds to step Sk26.

  If the timer interrupt is 4 in the step of Sk18, the stop stored in the work on the stop reel is stored when the stop operation position is stored in the work on the stop reel in accordance with the detection of the stop switches 8L, 8C, 8R. The stop position is determined from the operation position, the stop switch process (Sk23) for calculating the number of steps after which the stop should be performed, and the number of steps until the stop calculated in the stop switch process is counted. A stop process (Sk24) for starting braking by two-phase excitation and a final stop process (Sk25) for three-phase excitation after a certain time from the start of braking in the stop process are sequentially executed, and then the process proceeds to step Sk26.

  In the step of Sk26, the register saved in the stack area in Sk1 is restored, and the processing before the interruption is returned.

  As described above, in this embodiment, the timer interrupt process (main) is executed by interrupting the basic process at regular intervals, and the process counter is updated each time the timer interrupt process (main) is executed. In addition to distributing the load required for one timer interrupt process (main), the power interruption condition based on the voltage drop signal regardless of the process counter value. A power failure determination process is performed to determine whether or not the power failure is satisfied.If the power interruption condition is satisfied, the power interruption processing is performed. Disconnection processing can be performed.

  In the timer interrupt process (main), it is determined whether or not the power interruption condition is satisfied. If the power interruption condition is satisfied, the process proceeds to the power interruption process. Since interruptions due to power interruptions do not occur during execution of interrupt processing (main), interruption processing can be interrupted during execution of timer interruption processing (main), or timer interruption processing (main) Since it is not necessary to wait for the end of the interruption to perform an interruption process associated with power interruption, the process associated with establishment of the power interruption condition is not complicated.

  FIG. 14 is a flowchart showing the control contents of the power interruption process (main) executed when the main control unit 41 determines that the power interruption flag is set in the timer interrupt process (main) described above.

  In the power interruption process (main), first, the main control unit 41 reads data used in the internal lottery control module from the work RAM (Sm1). Next, predetermined data conversion is performed on the data read from the work RAM to create backup data (Sm2). Then, the main control unit 41 stores the created backup data in the SRAM 50 (backup RAM) (Sm3). Next, the main control unit 41 calculates the exclusive OR of the backup data converted in Sm2, calculates the checksum of the backup data of the internal lottery control module, and sets this in the SRAM 50 (backup RAM) (Sm4) . After setting the checksum data, the main control unit 41 sets a backup flag indicating that the backup has been executed in the SRAM 50 (backup RAM) (Sm5).

  Here, the data conversion process in step Sm2 will be described. In Sm1, the main control unit 41 reads data of 2 bytes (16 bits) from the work RAM which is an internal memory. In this embodiment, an SRAM 50 capable of only 8-bit bus access is connected as an external memory and used as a backup RAM. As described above, in this embodiment, the main control unit 41 can only perform 16-bit or 32-bit bus access to an external device such as an external memory. Then, even if the 16-bit data read from the work RAM is stored in the SRAM 50 (backup RAM) as it is, only the 8-bit data can be recognized on the SRAM 50 (backup RAM) side, so the upper 8 bits are lost, A situation occurs in which only lower 8-bit data can be stored in the SRAM 50 (backup RAM). Therefore, in the step Sm2, the 16-bit data read in Sm1 is converted into two data by performing the following data conversion process.

  First, for the first conversion data, the 16-bit data read in Sm1 is masked with the mask value “00FF (H)” as it is, and only the lower 8 bits of the original data read in Sm1 are used as the lower 8 bits. Generate data set to. For the second conversion data, the 16-bit data read in Sm1 is shifted by 8 bits (therefore, the value in the upper 8 bits of the original data is moved to the lower 8 bits). ), The data after the shift processing is masked with the mask value “00FF (H)”, and data in which the upper 8 bits of the original data read in Sm1 are set to the lower 8 bits is generated. Then, by storing these two pieces of conversion data in the SRAM 50 (backup RAM) in the step Sm3, the upper and lower values of the original data read in Sm1 are not lost, although they are divided into two data. Can backup power.

  In Sm7, Sm12, and Sm17, which will be described later, the same data conversion process as that in Sm2 described above is executed.

  Next, the main control unit 41 reads data used in the input / output control module from the work RAM (Sm6). Next, predetermined data conversion is performed on the data read from the work RAM to create backup data (Sm7). The main control unit 41 stores the created backup data in the SRAM 50 (backup RAM) (Sm8). Next, the main control unit 41 calculates the exclusive OR of the backup data converted in Sm2, calculates the checksum of the backup data of the input / output control module, and sets it in the SRAM 50 (backup RAM) (Sm9). . After setting the checksum data, the main control unit 41 sets a backup flag indicating that the backup has been executed in the SRAM 50 (backup RAM) (Sm10).

  Next, the main control unit 41 reads data used in the reel rotation control module from the work RAM (Sm11). Next, predetermined data conversion is performed on the data read from the work RAM to create backup data (Sm12). The main control unit 41 stores the created backup data in the SRAM 50 (backup RAM) (Sm13). Next, the main control unit 41 calculates the exclusive OR of the backup data converted in Sm2, calculates the checksum of the backup data of the reel rotation control module, and sets it in the SRAM 50 (backup RAM) (Sm14). . After the checksum data is set, a backup flag indicating that the backup has been executed is set in the SRAM 50 (backup RAM) (Sm15).

  Next, the main control unit 41 reads data used in the payout control module from the work RAM (Sm16). Next, predetermined data conversion is performed on the data read from the work RAM to create backup data (Sm17). The main control unit 41 stores the created backup data in the SRAM 50 (backup RAM) (Sm18). Next, the main control unit 41 calculates the exclusive OR of the backup data converted in Sm2, calculates the checksum of the backup data of the payout control module, and sets it in the SRAM 50 (backup RAM) (Sm19). After setting the checksum data, the main control unit 41 sets a backup flag indicating that the backup has been executed in the SRAM 50 (backup RAM) (Sm20).

  After setting the backup flag in Sm20, access to the RAM 41c is prohibited (Sm21), and the setting of the general-purpose port corresponding to the general-purpose terminal to which the CS signal line connected to the SRAM 50 is connected is set as the input port. (Sm22), the function of outputting the chip select signal to the SRAM 50 is forcibly disabled. Thereafter, the voltage decreases, and the CPU 41a of the main control unit 41 stops and shifts to a standby state. And if a voltage falls in this standby state, it will be in an operation stop state internally. Therefore, the main control unit 41 reliably stops operation when power is interrupted.

  Here, a specific example of storing backup data of each program module in the game control board 40 in the SRAM 50 (backup RAM) will be described with reference to FIG.

  As described with reference to FIG. 14, among the four program modules of the internal lottery control module, the input / output control module, the reel rotation control module, and the payout control module, first, the backup data of the internal lottery control module is stored in the SRAM 50 (backup RAM). Store (Sm3). In the SRAM 50 (backup RAM), the start address designated when storing the backup data of the internal lottery control module is set to “A6000”. Therefore, the main control unit 41 designates “A6000” as the start address in the step of Sm3, and starts storing backup data of the internal lottery module generated by data conversion in the step of Sm2. Then, until all the data for the internal lottery control module stored in the work RAM are backed up, the processes of Sm1 to Sm3 are repeatedly executed while incrementing the storage destination address of the SRAM 50 (backup RAM).

  Next, after storing the backup data of the internal lottery control module, the backup data of the input / output control module is stored in the SRAM 50 (backup RAM) (Sm8). In the backup RAM, the start address designated when storing the backup data of the input / output control module is set to “A7000”. Therefore, the main control unit 41 designates “A7000” as the start address in the step Sm8, and starts storing the backup data of the input / output control module generated by data conversion in the step Sm7. The processes of Sm6 to Sm8 are repeatedly executed while incrementing the storage destination address of the SRAM 50 (backup RAM) until backup of all data for the input / output control module stored in the work RAM is completed.

  Next, after storing the backup data of the input / output control module, the backup data of the reel rotation control module is stored in the SRAM 50 (backup RAM) (Sm13). In the backup RAM, the start address designated when storing the backup data of the reel rotation control module is set to “A8000”. Therefore, the main control unit 41 designates “A8000” as the start address in step Sm13, and starts storing the backup data of the reel rotation control module generated by data conversion in step Sm12. Then, until all the data for the reel rotation control module stored in the work RAM is backed up, the processes of Sm11 to Sm13 are repeatedly executed while incrementing the storage destination address of the SRAM 50 (backup RAM).

  Next, after storing the backup data of the input / output control module, the backup data of the payout control module is stored in the SRAM 50 (backup RAM) (Sm18). In the backup RAM, the start address designated when storing the backup data of the payout control module is set to “A9000”. Therefore, in step Sm18, the main control unit 41 designates “A9000” as the start address, and starts storing backup data of the payout control module generated by data conversion in step Sm17. The processes of Sm16 to Sm18 are repeatedly executed while incrementing the storage destination address of the SRAM 50 (backup RAM) until backup of all data for the payout control module stored in the work RAM is completed.

  Thus, since backup data is stored for each program module, when only one of the program modules needs to be changed in another model, only that program module needs to be replaced, and the game control program can be easily changed. . Since the start address for storing the backup data of each program module is set for each program module, it is not necessary to maintain consistency for storing the backup data even if the model is changed. The backup data may be stored at the start address set in. For this reason, it is possible to simplify the program at the time of storing the backup data, and it is possible to reduce the man-hour for developing the program. Similarly, checksum data is also created for each program module, so even if the model is changed, there is no need to maintain consistency for storing checksum data, and the program for storing checksum data is simplified. Can reduce the man-hours for program development.

  In the slot machine 1 of this embodiment, the main control unit 41 controls the progress of the game. A MAXBET switch 6, a start switch 7, and stop switches 8L, 8C, and 8R are provided as operation switches. Of these operation switches, the start switch 7 is also used for setting value setting in a setting change state.

  The main control unit 41 detects these operation switches in a switch input determination process executed during a timer interrupt process (main) executed by interrupting at regular time intervals.

  The main control unit 41 executes a start-up process when power is turned on, and an interrupt is permitted at the end of the start-up process. Thereafter, a timer interrupt process (main) is executed at regular intervals. When the main control unit 41 can return to the state before the power interruption, a return command is transmitted to the sub-control unit 91 before interruption is permitted in the startup process. Further, if the main control unit 41 cannot return to the state before the power interruption due to an abnormality in the data stored in the RAM 41c, an error command indicating a RAM abnormality is issued before the interruption is permitted in the startup process. Sent to. If the setting key switch 37 is on and the RAM 41c is initialized and does not return to the state before the power interruption, it indicates that the setting is being changed before the interruption is permitted in the startup process. A setting change command is transmitted to the sub-control unit 91. Of the commands sent in the start-up process, the return command specifies that the main control unit 41 returns to the state before the power interruption, an error command indicating a RAM abnormality, and a setting change indicating that the setting is being changed. From the middle command, it is specified that the main control unit 41 does not return to the state before the power interruption.

  Next, the control of the effect performed by the sub-control unit 91 based on the command transmitted from the main control unit 41 to the effect control board 90 will be described.

  When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91c.

  The reception buffer is provided with an area capable of storing a maximum of 16 commands so that a plurality of commands can be accumulated.

  In the timer interrupt process (sub), the sub-control unit 91 determines whether or not an unprocessed command is stored in the reception buffer. If an unprocessed command is stored, the sub-control unit 91 is the earliest. The control pattern table stored in the ROM 91b is referred to based on the command received in the stage, and the liquid crystal display 51, effect effect LED 52, speakers 53, 54, reel LED 55, etc. are controlled based on the control contents registered in the control pattern table. Performs output control of various rendering devices.

  In the control pattern table, the display pattern of the liquid crystal display 51 corresponding to the type of command, the lighting mode of the lighting effect LED 52, the output mode of the speakers 53 and 54, the lighting mode of the reel LED, etc. Control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the sub-control unit 91 stores the control patterns registered corresponding to the effect patterns set in the RAM 91c in the game of the control pattern table. Among these, the control pattern corresponding to the type of the received command is referred to, and the output control of the rendering device is performed based on the control pattern. Thereby, the production according to the production pattern and the progress of the game is executed.

  If the sub-control unit 91 receives a new command during execution of an effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed, and changes to the newly received command. An effect based on the corresponding control pattern is executed. In other words, even if the production is not finished to the end, when a new command is received, the production that was being executed is canceled and a new command is received unless the received new command is not a command that triggers a new production. An effect based on the command is executed.

  When the internal winning command is received, the effect pattern is selected at a selection rate corresponding to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub control unit 91 receives the internal winning command, the sub control unit 91 stores the effect pattern in the effect table according to the result of the internal lottery indicated by the internal winning command. With reference to the registered selection rate, one of the effect patterns is selected from a plurality of types of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91c as the effect pattern of the game. Even if the same command is received, a different control pattern is selected depending on the effect pattern selected when the internal winning command is received. As a result, different effects may be performed depending on the effect pattern.

  In the slot machine 1 of the present embodiment, when a predetermined symbol combination is aligned on the winning line LN, a winning is achieved. The types of winning combinations are determined according to the state of the game, but can be broadly divided into special roles with transition to big bonus and regular bonus, small roles with payout of medals, and setting of bet number. There is a re-player who can start the next game without needing.

  The big bonus may be indicated as BB and the regular bonus may be indicated as RB. In some cases, a big bonus or a regular bonus is simply referred to as a bonus. In order for winning of each combination determined according to the gaming state to occur, it is necessary to set a winning flag in the RAM 41c to win the internal lottery and allow winning of the winning combination.

  FIG. 16 to FIG. 18 are diagrams for explaining the types of winning combinations, symbol combinations of winning combinations, and technical matters related to winning combinations. FIG. 19 is a diagram for explaining the gaming state controlled by the main control unit 41 and the transition of RT.

  As shown in FIG. 19, the slot machine according to the present embodiment is controlled as a normal gaming state, one in the inside, two in the inside, RB, or BB (RB) as the gaming state. In addition, RT is a replay time in which the probability of a replay is increased. In a normal gaming state (hereinafter, the normal gaming state is referred to as normal), any type of RT (replay) from RT0 to RT4 is used. Time).

  Among the winning combinations, the special combination includes 6 types of bonuses such as big bonuses 1 to 4 and regular bonuses 1 and 2.

  BB1 is awarded when the combination of “Black 7-Black 7-Black 7” is aligned on the winning line LN. BB2 is awarded when the combination of “network 7-network 7-network 7” is aligned on the winning line LN. BB3 is awarded when the combination of “white 7-white 7-white 7” is aligned on the winning line LN. BB4 is awarded when the combination of “BAR-BAR-BAR” is aligned on the winning line LN. BB4 is awarded when the combination of “black 7-white 7-net 7” is aligned on the winning line LN.

  When winning one of BB1 to BB4, the game shifts to a big bonus that is controlled by the game every time during the BB regular bonus (hereinafter referred to as BBRB).

  The big bonus generated due to the winning of any one of BB1 to BB4 is terminated on condition that 316 or more medals have been paid out.

  RB1 wins when the winning line LN has a combination of “net 7-net 7-black 7”. RB2 is awarded when the combination of “white 7-white 7-black 7” is aligned on the winning line LN.

  When winning one of RB1 and RB2, a transition is made to a regular bonus (hereinafter referred to as RB).

  The regular bonus generated due to the winning of either RB1 or RB2 ends on the condition that any winning combination has won 6 times or 12 games have been consumed.

  As shown in FIG. 19, from the internal winning one of BB1, BB3, RB2 to winning a prize, it is controlled to 1 inside / RT0, and after winning an internal winning one of BB2, BB4, RB1 Until this is done, the internal control is controlled to 2 · RT0. Further, as shown in FIG. 18, after the big bonus or regular bonus (collectively referred to as a bonus) is completed, the control is performed to normal RT4.

  Even if one of BB1 to BB4, RB1, or RB2 is won in an internal lottery to be described later, if the stop switches 8L, 8C, and 8R are not operated at an appropriate timing to enable winning of these roles, these I won't win a role. The symbols composing BB1 to BB4, RB1, and RB2 ("black 7", "white 7", and "net 7") are arranged within 5 frames on each of the left reel 2L, middle reel 2C, and right reel 2R. This is because it has not been done.

  Next, with reference to FIG. 16, the small combination among the winning combinations will be described. Among the winning roles, there are middle bells, lower right bells, upper bells 1-8, middle watermelons, right lower watermelons, upper watermelons, lower cherries, middle cherries, one role, right-up bells, right-up bevels, Includes a rising rivet.

  For example, the middle bell is awarded when the combination of “bell-bell-bell” is arranged on the winning line LN, and eight medals are paid out.

  Here, referring to FIG. 3, the bells are arranged within 5 frames in each of the left reel 2L, the middle reel 2C, and the right reel 2R. For this reason, it can be said that, in principle, when a middle bell is won in an internal lottery to be described later, it can be said that a winning can be made regardless of the operation timing of the stop switches 8L to 8R.

  Below, right-down bell, upper bell 1-8, middle watermelon, right-down watermelon, upper watermelon, lower cherry, middle cherry, single role, right-up bell, right-up bevel, right-up rebebe are also shown in FIG. When the combinations of the symbols shown are complete, a prize is awarded and the payout number of medals shown in FIG. 16 is paid out. As shown in FIG. 3, the right-down bell, the right-up bell, the right-up bevel, and the right-up bevel are arranged within 5 frames, so that a prize is won regardless of the operation timing of the stop switches 8L to 8R. Can be made, but the upper bell 1-8, middle watermelon, right-down watermelon, upper watermelon, lower cherry, middle cherry, 1 piece role, because there are places where the configuration symbol is not arranged within 5 frames, If a stop switch corresponding to a reel whose symbol is not arranged within 5 frames is not operated at an appropriate timing, no prize is won.

  Next, with reference to FIG. 17, the re-game player among the winning combinations will be described. Among the winning combinations, the replaying role includes normal replay, lower stage replay, fall replay, promotion replays 1 and 2, special replay, and SP (special) replay.

  For example, the normal replay is performed when a combination of “Replay-Replay-Replay”, “Replay-Replay-Plum”, “Plum-Replay-Replay”, and “Plum-Replay-Plum” is arranged on the winning line LN. Become. Replays and plums are arranged within 5 frames in each of the left reel 2L, middle reel 2C, and right reel 2R. Therefore, as a general rule, it can be said that the normal replay is a role that can be won regardless of the operation timing of the stop switches 8L to 8R if the winning is made.

  Hereinafter, the lower replay, the fall replay, the promoted replays 1 and 2, the special replay, and the SP (special) replay are similarly awarded when the combinations of symbols shown in FIG. Also, as shown in FIG. 3, each of these replays is arranged within 5 frames, so that if it is elected, it can be awarded regardless of the operation timing of the stop switches 8L to 8R. It can be said.

  As shown in FIG. 19, after winning the fall replay in normal / RT0, it is controlled to RT1.

  In addition, after winning a promotion replay (promotion replay 1 or promotion replay 2) in normal / RT1, it is controlled to normal / RT0. As will be described later, the promotion replay is set not to win independently in the internal lottery in normal / RT2, normal / RT3, and normal / RT4. Further, when the special combination and the promotion replay are won at the same time in the internal lottery in the normal / RT2, the normal / RT3, and the normal / RT4, it is controlled to the internal 1 / RT0 or the internal 2 / RT0 at that time. For this reason, no promotion replay is won in normal / RT2, normal / RT3, or normal / RT4. As a result, it is configured not to be controlled from normal / RT2, normal / RT3, normal / RT4 to normal / RT0, and only when it is normal / RT1 is promoted replay, and only from normal / RT1 is normal / RT0. It is comprised so that it may be controlled.

  In addition, after winning the special replay in normal / RT1 and normal / RT3, it is controlled to normal / RT2. As will be described later, the special replay is set so as not to be won independently in the internal lottery in the normal / RT1 and normal / RT4. Further, when the special combination and special replay are won at the same time in the internal / RT1 or normal / RT4 internal lottery, the internal 1 / RT0 or the internal 2 / RT0 is controlled at that time. Therefore, the special replay is not won in normal / RT1 and normal / RT4. As a result, it is configured not to be controlled from normal / RT1, normal / RT4 to normal / RT2, and a special replay is awarded only in normal / RT0, normal / RT3, and from normal / RT0 / normal / RT3. Only normal and RT2 are controlled. When the special replay is won in the normal RT2, the normal RT2 is maintained.

  As shown in FIG. 19, after winning the SP replay in normal / RT2, the control is performed in normal / RT3. As will be described later, the SP replay is set not to win independently in the internal lottery in the normal / RT0, normal / RT1, and normal / RT4. Further, when the special combination and SP replay are won at the same time in the internal lottery in the normal / RT0, normal / RT1, and normal / RT4, the internal one / RT0 or the internal two / RT0 is controlled at that time. Therefore, the SP replay is not won in the normal / RT0, normal / RT1, and normal / RT4. As a result, normal / RT0, normal / RT1, and normal / RT4 are not controlled to normal / RT3, and SP replay is awarded only when normal / RT2 and normal / RT3 only from normal / RT2. It is comprised so that it may be controlled. If the special replay is won in the normal RT3, the normal RT3 is maintained.

  Next, the transition outcome will be described with reference to FIG. As shown in FIG. 18, the transition items are composed of 20 types of combinations such as “Replay-Orange-Bell”. In this embodiment, left bells 1 to 4, middle bells 1 to 4 and right bells 1 to 4 which will be described later are elected, and the upper bells which are elected as the first stop other than the reels which become the winning conditions for the middle bells are elected. When the game is missed, the above-mentioned transition outcome is aligned with the winning line LN.

  As shown in FIG. 19, normal / RT1 is controlled after the transition points are aligned with the winning line LN in normal / RT0, normal / RT2, normal / RT3, and normal / RT4. Note that, when the transition outcomes are aligned with the winning line LN in the normal / RT1, the normal / RT1 is maintained.

  Next, a combination of lottery target combinations that are read out as lottery target combinations for each gaming state will be described. In this embodiment, the gaming state is the normal gaming state, the inside one (BB1, BB3, RB2 is elected) or the inside 2 (BB2, BB4, RB1 is won) State), BB (RB), or RB, and the winning combination and the winning probability for the internal lottery are different. Furthermore, if the gaming state is the normal gaming state, at least one of the re-game player and the winning probability to be subject to the internal lottery differs depending on the types of RT0 to RT4. As will be described later as a lottery target combination, a plurality of winning combinations can be read out simultaneously and can be won in duplicate. In the following, “+” is indicated between winning combinations to indicate that the winning combination is simultaneously read out in the internal lottery.

  When normal / RT0, BB1, BB1 + weak watermelon, BB1 + strong watermelon, BB1 + weak cherry, BB1 + strong cherry, BB1 + middle tier, BB1 + 1 double-player, BB1 + normal replay, BB1 + fall replay, BB1 + promoted replay, BB1 + special replay, BB1 + SP Replay, BB2, BB2 + weak watermelon, BB2 + strong watermelon, BB2 + weak cherry, BB2 + strong cherry, BB2 + middle cherries, BB2 + one piece, BB2 + normal replay, BB2 + tumble replay, BB2 + promoted replay, BB2 + special replay, BB3, BB3 + weak watermelon, BB3 + strong watermelon, BB3 + weak cherry, BB3 + strong cherry, BB3 + middle cherries, BB3 + 1 sheet, BB3 + normal replay, BB3 + tumble replay, BB3 + promoted replay, BB3 + Especially replay, BB4, BB4 + middle cherries, BB4 + 1 sheets, BB4 + special replay, RB1, RB1 + strong watermelon, RB1 + weak cherries, RB1 + strong cherry, RB1 + 1 sheets, RB2, RB2 + weak watermelon, RB2 + strong watermelon, RB2 + weak cherry, RB2 + Strong cherry, RB2 + 1 role, bell, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right Bell 3, right bell 4, weak watermelon, strong watermelon, weak cherry, strong cherry, middle tier cherry, 1 part, replay GR11, replay GR12, replay GR13, replay GR14, replay GR15, replay GR16, replay GR21, replay GR22, Replay GR23, Replay GR24, and Replay GR25 are internal lottery pairs The role.

  In addition, a weak watermelon is an upper stage watermelon + right-down watermelon. That is, when the upper watermelon wins, it can be recognized that it is a weak watermelon. A strong watermelon is a middle-stage watermelon + right-down watermelon. That is, when the middle stage watermelon wins, it can be recognized that it is a strong watermelon. A weak cherry is a lower cherry alone, and a strong cherry is a lower cherry plus one piece. In the weak cherries, the combination of “BAR-BAR-BAR” in the middle tier can be recognized as weak cherries, while the cherry stops at the lower tier of the left reel 2L and the BAR-BAR in the middle tier. It can be recognized that it is a strong cherry when the combination of “−BAR” is prepared.

  The promotion replay is promotion replay 1 + promotion replay 2. The bell is a middle bell + a downward-sloping bell. Left bell 1 is right falling bell 5 + upper bell 5 + upper bell 8, left bell 2 is right falling bell + upper bell 6 + upper bell 7, and left bell 3 is right falling bell + upper bell 2 + upper bell 3, left bell 4 is right falling bell + upper bell 2 + upper bell 4. The left bells 1 to 4 are also simply called left bells. The middle bell 1 is the middle bell + the upper bell 2 + the upper bell 5, the middle bell 2 is the middle bell + the upper bell 1 + the upper bell 6, and the middle bell 3 is the middle bell + the upper bell 4 + the upper bell. 7 and the middle bell 4 is the middle bell + the upper bell 3 + the upper bell 8. The middle bells 1 to 4 are also simply called middle bells. The right bell 1 is the middle bell + the upper bell 3 + the upper bell 5, the right bell 2 is the middle bell + the upper bell 1 + the upper bell 7, and the right bell 3 is the middle bell + the upper bell 4 + the upper bell. 6 and the right bell 4 is the middle bell + the upper bell 2 + the upper bell 8. The right bells 1 to 4 are also simply called right bells. The left bells 1 to 4, the middle bells 1 to 4, and the right bells 1 to 4 are also simply referred to as push order bells.

  Replay GR11 is a fall replay + promotion replay 2, replay GR12 is a fall replay + promotion replay 2 + normal replay, replay GR13 is a fall replay + promotion replay 1, and replay GR14 is a fall Replay + promotion replay 1 + normal replay, replay GR15 is fall replay + promotion replay 1 + promotion replay 2, and replay GR16 is fall replay + promotion replay 1 + promotion replay 2 + normal replay.

  Replay GR21 is tumble replay + special replay, replay GR22 is tumble replay + special replay + normal replay, replay GR23 is tumble replay + special replay + lower replay, and replay GR24 is Tumble replay + special replay + normal replay + lower replay. Replay GR25 is tumble replay + special replay + promotion replay 1.

  When it is normal / RT1, BB1, BB1 + weak watermelon, BB1 + strong watermelon, BB1 + weak cherry, BB1 + strong cherry, BB1 + middle cherries, BB1 + 1 sheet, BB1 + normal replay, BB1 + fall replay, BB1 + promoted replay, BB1 + special replay, BB1 + SP Replay, BB2, BB2 + weak watermelon, BB2 + strong watermelon, BB2 + weak cherry, BB2 + strong cherry, BB2 + middle cherries, BB2 + one piece, BB2 + normal replay, BB2 + tumble replay, BB2 + promoted replay, BB2 + special replay, BB3, BB3 + weak watermelon, BB3 + strong watermelon, BB3 + weak cherry, BB3 + strong cherry, BB3 + middle cherries, BB3 + 1 sheet, BB3 + normal replay, BB3 + tumble replay, BB3 + promoted replay, BB3 + Especially replay, BB4, BB4 + middle cherries, BB4 + 1 sheets, BB4 + special replay, RB1, RB1 + strong watermelon, RB1 + weak cherries, RB1 + strong cherry, RB1 + 1 sheets, RB2, RB2 + weak watermelon, RB2 + strong watermelon, RB2 + weak cherry, RB2 + Strong cherry, RB2 + 1 role, bell, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right Bell 3, right bell 4, weak watermelon, strong watermelon, weak cherry, strong cherry, middle tier cherry, 1 part, normal replay, replay GR1, replay GR2, replay GR3, replay GR4, replay GR5, replay GR6 are internal lottery It becomes a target role.

  Replay GR1 is normal replay + promotion replay 1, replay GR2 is normal replay + promotion replay 1 + promotion replay 2, replay GR3 is normal replay + promotion replay 1 + lower replay, and replay GR4. Is normal replay + promotion replay 1 + promotion replay 2 + lower replay, replay GR5 is normal replay + promotion replay 2, and replay GR6 is normal replay + promotion replay 2 + lower replay.

  When normal / RT2, BB1, BB1 + weak watermelon, BB1 + strong watermelon, BB1 + weak cherry, BB1 + strong cherry, BB1 + middle cherries, BB1 + 1 sheet, BB1 + normal replay, BB1 + fall replay, BB1 + promoted replay, BB1 + special replay, BB1 + SP Replay, BB2, BB2 + weak watermelon, BB2 + strong watermelon, BB2 + weak cherry, BB2 + strong cherry, BB2 + middle cherries, BB2 + one piece, BB2 + normal replay, BB2 + tumble replay, BB2 + promoted replay, BB2 + special replay, BB3, BB3 + weak watermelon, BB3 + strong watermelon, BB3 + weak cherry, BB3 + strong cherry, BB3 + middle cherries, BB3 + 1 sheet, BB3 + normal replay, BB3 + tumble replay, BB3 + promoted replay, BB3 + Especially replay, BB4, BB4 + middle cherries, BB4 + 1 sheets, BB4 + special replay, RB1, RB1 + strong watermelon, RB1 + weak cherries, RB1 + strong cherry, RB1 + 1 sheets, RB2, RB2 + weak watermelon, RB2 + strong watermelon, RB2 + weak cherry, RB2 + Strong cherry, RB2 + 1 role, bell, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right Bell 3, right bell 4, weak watermelon, strong watermelon, weak cherry, strong cherry, middle tier cherry, 1 part, normal replay, replay GR31, replay GR32, replay GR33, replay GR34, replay GR35, replay GR36 are internal lottery It becomes a target role.

  Replay GR31 is special replay + SP replay + normal replay, replay GR32 is special replay + SP replay + normal replay + falling replay, and replay GR33 is special replay + SP replay + lower replay, and replay GR34. Is special replay + SP replay + lower replay + falling replay, replay GR35 is special replay + SP replay + normal replay + lower replay, and replay GR36 is special replay + SP replay + normal replay + lower replay + It is a fall replay.

  When normal / RT3, BB1, BB1 + weak watermelon, BB1 + strong watermelon, BB1 + weak cherry, BB1 + strong cherry, BB1 + middle tier, BB1 + 1 double role, BB1 + normal replay, BB1 + fall replay, BB1 + promoted replay, BB1 + special replay, BB1 + SP Replay, BB2, BB2 + weak watermelon, BB2 + strong watermelon, BB2 + weak cherry, BB2 + strong cherry, BB2 + middle cherries, BB2 + one piece, BB2 + normal replay, BB2 + tumble replay, BB2 + promoted replay, BB2 + special replay, BB3, BB3 + weak watermelon, BB3 + strong watermelon, BB3 + weak cherry, BB3 + strong cherry, BB3 + middle cherries, BB3 + 1 sheet, BB3 + normal replay, BB3 + tumble replay, BB3 + promoted replay, BB3 + Especially replay, BB4, BB4 + middle cherries, BB4 + 1 sheets, BB4 + special replay, RB1, RB1 + strong watermelon, RB1 + weak cherries, RB1 + strong cherry, RB1 + 1 sheets, RB2, RB2 + weak watermelon, RB2 + strong watermelon, RB2 + weak cherry, RB2 + Strong cherry, RB2 + 1 role, bell, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right Bell 3, right bell 4, weak watermelon, strong watermelon, weak cherry, strong cherry, middle tier cherry, 1 part, replay GR31, replay GR32, replay GR33, replay GR34, replay GR35, replay GR36, SP replay are internal lottery It becomes a target role.

  When normal / RT4, BB1, BB1 + weak watermelon, BB1 + strong watermelon, BB1 + weak cherry, BB1 + strong cherry, BB1 + middle cherries, BB1 + 1 roll, BB1 + normal replay, BB1 + fall replay, BB1 + promoted replay, BB1 + special replay, BB1 + SP Replay, BB2, BB2 + weak watermelon, BB2 + strong watermelon, BB2 + weak cherry, BB2 + strong cherry, BB2 + middle cherries, BB2 + one piece, BB2 + normal replay, BB2 + tumble replay, BB2 + promoted replay, BB2 + special replay, BB3, BB3 + weak watermelon, BB3 + strong watermelon, BB3 + weak cherry, BB3 + strong cherry, BB3 + middle cherries, BB3 + 1 sheet, BB3 + normal replay, BB3 + tumble replay, BB3 + promoted replay, BB3 + Especially replay, BB4, BB4 + middle cherries, BB4 + 1 sheets, BB4 + special replay, RB1, RB1 + strong watermelon, RB1 + weak cherries, RB1 + strong cherry, RB1 + 1 sheets, RB2, RB2 + weak watermelon, RB2 + strong watermelon, RB2 + weak cherry, RB2 + Strong cherry, RB2 + 1 role, bell, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right Bell 3, right bell 4, weak watermelon, strong watermelon, weak cherry, strong cherry, middle cherries, one-piece combination, and normal replay are targeted for internal lottery.

  When internal center 1 · RT0, internal center 2 · RT0, bell, left bell 1, left bell 2, left bell 3, left bell 4, center bell 1, center bell 2, center bell 3, center bell 4, right Bell 1, Right bell 2, Right bell 3, Right bell 4, Weak watermelon, Strong watermelon, Weak cherry, Strong cherry, Middle cherry, Single role, Normal replay, Lower replay, SP replay, Tumble replay, Promotion replay, Special Replay is the target for internal lottery.

  When it is BBRB · RT0, the weak cherry and all roles are subject to internal lottery, and when it is RB · RT0, all roles, RB bell 1, RB bell 2, and RB bell 3 are subject to internal lottery.

  All roles are all small roles other than right-up bevel, ie middle bell + right-down bell + upper bell 1 + upper bell 2 + upper bell 3 + upper bell 4 + upper bell 5 + upper bell 6 + upper bell 7 + upper bell 8 + middle watermelon + Lower right watermelon + upper watermelon + lower cherry + middle cherries + 1 piece + right rising bell + right rising rivet.

  The RB bell 1 is a right-up bell + right-up bevel, the RB bell 2 is a right-up bell + right-up bevel + right-up beryl, and the RB bell 3 is all small roles, that is, the middle stage bell. + Downward bell + Upper bell 1 + Upper bell 2 + Upper bell 3 + Upper bell 4 + Upper bell 5 + Upper bell 6 + Upper bell 7 + Upper bell 8 + Middle watermelon + Lower watermelon + Upper watermelon + Lower cherry + Middle cherry + Single role + Upright Bell + bevel up to the right + bevel up to the right.

  Also, in normal / RT0-4, etc., weak watermelon, strong watermelon, weak cherry, strong cherry, middle cherries, single role, normal replay, fall replay, promotion that can be elected simultaneously with any of BB1-BB4, RB1, RB2 The replay and SP replay judgment values are read separately from the bonus in internal 1 · RT0 and internal 2 · RT0, respectively, strong watermelon, weak cherry, strong cherry, middle cherries, one-piece role, normal Since it is added to Replay, Tumble Replay, Promotion Replay, and SP Replay, the winning probability of each of Strong Watermelon, Weak Cherry, Strong Cherry, Middle Cherry, Single Role, Normal Replay, Tumble Replay, Promotion Replay, and SP Replay is constant. It is secured to be.

  In this way, the internal lottery role varies depending on whether the gaming state is the normal gaming state, 1 or 2 inside, BB (RB), or RB, and BB (RB) In RB, the internal lottery is performed using a lottery table in which the winning probability of the small role is set higher than that in the normal gaming state and inside.

  Also, when the game state is 1 or 2 in the inside, the subject of the internal lottery does not change depending on whether it is 1 in the inside or 2 in the inside, but it is 1 in the inside or inside The internal lottery is performed using a lottery table in which the winning probabilities of the target re-gamer are different.

  In addition, when the gaming state is the normal gaming state, the re-game player to be subject to the internal lottery differs depending on whether it is RT0-4, and depending on whether it is RT0-4 An internal lottery is performed using a lottery table with different re-game players and their winning probabilities.

  As will be described in detail later, in this embodiment, when a plurality of types of small roles (bells) and a plurality of types of replaying players are simultaneously elected, the type of the selected small role or replaying role and a stop switch Control is performed so that the symbol combination of the small combination and the combination of the re-playing combination determined according to the pressing order of 8L, 8C, and 8R are aligned and stopped on the winning line LN within the drawing range of up to four frames. Accordingly, the types of the small combination and re-playing combination to be won simultaneously will be specifically described with reference to FIGS. 20 to 22. FIG. FIG. 21 shows reel control when a plurality of replays are won simultaneously, and FIG. 22 shows reel control when a plurality of small roles are won simultaneously.

  As shown in FIG. 20 and FIG. 21, for example, when replay GR1 (normal replay + promotion replay 1) is won and a stop operation is performed in the order of left middle right, promoted replay among the replaying players selected. Control is performed so that one combination is aligned with the winning line LN and stopped, and when a stop operation is performed in an order other than the left middle right, control is performed so that the combination of normal replays is aligned with the winning line LN and stopped.

  Similarly, when the replays GR2 to 6 are stopped in a predetermined order, the combination of the promoted replay 1 or the promoted replay 2 among the selected re-playing players is stopped in alignment with the winning line LN. If the stop operation is performed in an order other than the predetermined order, control is performed so that the combination of the normal replays is aligned with the winning line LN and stopped.

  As shown in FIG. 3, the symbols constituting the promotion replay 1, the promotion replay 2, and the normal replay are arranged at intervals of 5 frames or less on all of the left reel 2L, the middle reel 2C, and the right reel 2R. The reel control is performed so that the promotion replay 1, the promotion replay 2 or the normal replay always wins regardless of the stop operation timing of the stop switches 8L to 8R according to the operation order.

  Therefore, in the normal / RT1 where the replays GR1 to 6 are the targets of the internal lottery, if any of the replays GR1 to GR6 is elected, the promoted replay wins with a probability of 1/6, and the normal / RT0 Will be migrated.

  Similarly, when the replays GR11 to 16 are stopped in a predetermined order, the combination of the promoted replay 1 or the promoted replay 2 among the selected re-playing players is aligned with the winning line LN and stopped. If the stop operation is performed in an order other than the predetermined order, control is performed so that the combination of falling replays is aligned with the winning line LN and stopped.

  As shown in FIG. 3, the symbols constituting the promotion replay 1, the promotion replay 2, and the fall replay are arranged at intervals of 5 frames or less on all of the left reel 2L, the middle reel 2C, and the right reel 2R. The reel control is performed so that the promotion replay 1, the promotion replay 2 or the fall replay always wins regardless of the stop operation timing of the stop switches 8L to 8R according to the operation order.

  Therefore, in the normal / RT0 where the replay GRs 11-16 are subject to internal lottery, if any of the replays GR11-16 is elected, the promoted replay wins with a probability of 1/6 and the normal / RT0 is maintained. On the other hand, the fall replay wins with a probability of 5/6 and shifts to normal RT1.

  In addition, in the replays GR21 to GR25, when a stop operation is performed in a predetermined order, the special replay combination among the selected replay players is controlled so as to be aligned with the winning line LN and stopped. When stop operations are performed in order, control is performed so that the combination of falling replays is aligned with the winning line LN and stopped.

  As shown in FIG. 3, since the symbols constituting the special replay and the fall replay are arranged at intervals of 5 frames or less in all of the left reel 2L, the middle reel 2C, and the right reel 2R, Regardless of the stop operation timing of the stop switches 8L to 8R, the reel control is performed so that the special replay or the fall replay is always won.

  For this reason, if one of the replays GR21 to 25 is elected in the normal / RT0 in which the replays GR21 to 25 are the targets of the internal lottery, the special replay wins with a probability of 1/5 and shifts to the normal / RT2. On the other hand, the fall replay wins with a probability of 4/5 and shifts to normal RT1.

  Further, in the replay GR31 to 36, when the stop operation is performed in a predetermined order (left push), the control for stopping the combination of the SP replay or the normal replay among the selected replay players in the winning line LN is stopped. If the stop operation is performed in an order other than the predetermined order, the special replay combination is controlled to be aligned with the winning line LN and stopped.

  As shown in FIG. 3, the symbols constituting the SP replay, special replay, and normal replay are arranged at intervals of 5 frames or less on all of the left reel 2L, the middle reel 2C, and the right reel 2R. Accordingly, the reel control is performed so that the SP replay, special replay, or normal replay always wins regardless of the stop operation timing of the stop switches 8L to 8R.

  In addition, in normal / RT3 where the replay GRs 31 to 36 are the targets of the internal lottery, if one of the replays GR31 to 36 is won, the SP replay wins with a probability of 1/6 and one navigation stock described later On the other hand, the normal replay wins with a probability of 1/6 and normal RT3 is maintained, and the special replay wins with a probability of 4/6 and shifts to normal RT2.

  As shown in FIG. 20 and FIG. 22, when the left bells 1 to 5 are elected, and the stop operation is performed by pressing the left button, the combination of the right falling bells among the selected small roles is aligned with the winning line LN and stopped. When the stop operation is performed by middle press or right press, the control is performed so that any combination of the upper bells 2 to 8 or the shift outcome is aligned with the pay line LN.

  As shown in FIG. 3, the configuration symbol of the right-down bell is arranged at intervals of 5 frames or less on all reels, and when the left bells 1 to 4 are elected, a stop operation is performed by pushing left. In this case, regardless of the timing of the stop operation, control is always performed so that the right lowering bell is aligned with the winning line LN, while the symbols constituting the upper bells 1 to 8 are at intervals of 5 frames or more on all reels. Even if the left bells 1 to 4 are elected because there are places that are arranged, if the stop operation is performed by pressing the middle or right, it becomes the drawing range of the constituent symbols of the elected upper bells 1 to 8 If the stop operation is not performed at an appropriate timing, the winning upper bell cannot be aligned with the winning line LN, and in this case, the control is performed so that the transition outcome is aligned with the winning line LN.

  In addition, when the middle bells 1 to 4 are elected and the stop operation is performed by pressing the middle bell, the combination of the middle bells among the selected small roles is controlled to be aligned with the winning line LN and stopped, and left or right pressed. When the stop operation is performed at, control is performed so that any combination of the upper bells 1 to 8 or the transition outcome is aligned with the winning line LN and stopped.

  As shown in FIG. 3, the configuration symbols of the middle bell are arranged at intervals of 5 frames or less on all reels, and when the middle bell 1 to 4 is elected, when the stop operation is performed by middle push Regardless of the timing of the stop operation, control is always performed so that the middle bell is aligned with the winning line LN, while the symbols constituting the upper bells 1 to 8 are arranged at intervals of 5 frames or more on all reels. Even if the middle bells 1 to 4 are elected, if the stop operation is performed by pressing left or right, an appropriate range that will be drawn in the constituent symbols of the elected upper bells 1 to 8 will be used. If the stop operation is not performed at the timing, the selected upper bell cannot be aligned with the winning line LN, and in this case, control is performed so that the shift outcome is aligned with the winning line LN.

  If right bells 1 to 4 are elected and stop operation is performed by pressing right, control is performed to stop the combination of middle bells in the selected small role in line with winning line LN, and stop by pressing left or middle. When an operation is performed, control is performed to stop any combination of the upper bells 1 to 8 or the transition outcome in line with the pay line LN.

  As shown in FIG. 3, the configuration symbols of the middle bell are arranged at intervals of 5 frames or less on all reels, and when the right bell 1 to 4 is elected, when the stop operation is performed by pushing right However, regardless of the timing of the stop operation, control is always performed so that the middle bell is aligned with the winning line LN, while the symbols constituting the upper bells 1 to 8 are arranged at intervals of 5 frames or more on all reels. Therefore, even if the right bells 1 to 4 are elected, if the stop operation is performed by left-pressing or middle-pressing, an appropriate drawing range of the constituent symbols of the elected upper bells 1 to 8 is appropriate. If the stop operation is not performed at the timing, the selected upper bell cannot be aligned with the winning line LN, and in this case, control is performed so that the shift outcome is aligned with the winning line LN.

  Thus, in this embodiment, when any of the left bell, middle bell, right bell, that is, the push order bell is won, by performing a stop operation in a specific operation mode according to the type of winning combination, While the right-down bell or middle bell always wins, if the stop operation is performed in an operation mode other than the specific operation mode according to the type of winning combination, the upper bell is aligned at 1/4, but at 3/4 In some cases, the upper bells are not aligned and the transition outcomes are aligned.

  For this reason, at the time of winning the push order bell, the expected value of the number of medals to be paid out can be changed depending on whether or not it is operated in a specific operation mode according to the type of winning combination. In other words, even if one of the push order bells is won, it is impossible to intentionally select a specific operation mode unless the type is known. Although a medal can be surely obtained by winning a prize, the upper bell can be won only by 1/4 at a ratio of 2/3, and a medal cannot be surely obtained.

  When RB bell 1 (Right-up bell + Right-up Rivebe) is elected and a stop operation is performed by left-pressing, control is performed so that the combination of right-up bells among the selected small roles is aligned with the winning line LN and stopped. If a stop operation is performed by middle pressing or right pressing, control is performed to align the combination of rising right ribs on the winning line LN and stop.

  If RB Bell 2 (Rising Right Bell + Right Rising Bevel + Right Rising Berri) is won and stopped by pressing the middle, the combination of the right rising bells of the selected small roles is aligned with the winning line LN and stopped. If the stop operation is performed by pressing the button to the left, the control is performed to stop the right-up bevel combination in alignment with the winning line LN. If the stop operation is performed by pressing the button to the right, Control is performed to stop the combination in line with the winning line LN.

  RB bell 3 (middle bell + lower right bell + upper bell 1 + upper bell 3 + upper bell 4 + upper bell 5 + upper bell 6 + upper bell 7 + upper bell 8 + middle watermelon + lower watermelon + upper watermelon + lower cherry + middle cherry +1 sheet role + right-up bell + right-up bevel + right-up bevel), and if the stop operation is performed by pressing right, the combination of right-up bells in the selected small role is aligned with the winning line LN Control to stop is performed, and when a stop operation is performed by left-pressing or middle-pressing, control is performed to stop the right-beveled bevel combination aligned with the winning line LN.

  As shown in FIG. 3, the configuration symbols of the right-up bell, the right-up bevel, and the right-up bevel are arranged at intervals of 5 frames or less on all reels, and when the RB bells 1 to 4 are won, Regardless of the timing of the stop operation, any combination of right-up bell, right-up ribebe and right-up bevel will be aligned on the winning line LN and 10 medals will be paid out, but at a rate of 1/3 Only "bell-bell-bell" combinations will be aligned to the right.

  Although not particularly shown, when a bell (middle bell + lower right bell) is won, a combination of “bell-bell-bell” is arranged on the winning line LN regardless of the stop order of the reels and the operation timing. To be controlled.

  Also, all roles (middle bell + lower right bell + upper bell 1 + upper bell 2 + upper bell 3 + upper bell 4 + upper bell 5 + upper bell 6 + upper bell 7 + upper bell 8 + middle watermelon + right lower watermelon + upper watermelon + lower cherry + middle (Cherry + 1 hand + right-up bell + right-up rivebe) is selected, the “bell-bell-bell” combination is controlled to rise to the right regardless of the reel stop order and operation timing. The

  In this embodiment, as shown in FIG. 19, it is controlled to one of the normal gaming state, internal 1, internal 2, RB, BB (RB), and in the normal gaming state, any of RT 0 to 4 Controlled.

  Normal / RT0 is normal / RT1 when a promotion replay wins (when either one of the replays GR1 to GR6 is elected and a stop operation is performed in the order in which the promotion replay wins), normal / RT1 or normal / RT2 Shifts when the game is completed due to the consumption of the specified number of games. Regardless of the number of games after the transition to normal / RT0, the normal / RT0 shifts to the normal / RT1 by winning the fall replay or stopping the transition, or to the normal / RT2 by winning the special replay It ends when the special role is elected and moves to the inside 1 or inside 2 inside.

  Normal / RT1 shifts when the transition is stopped at normal / RT0, normal / RT2, normal / RT3, normal / RT4, or when a fall replay wins at normal / RT0. The normal RT1 is such that the number of remaining RT games is subtracted for each game, and the normal number of RT remaining games is reduced to 0 by digesting the specified number of games (1000G in this embodiment).・ It will end when it shifts to RT0, or when the special role is elected and shifts to 1 inside or 2 inside.

  Normal / RT2 shifts when a special replay wins in normal / RT0 or normal / RT3. The normal RT 2 is such that the number of remaining RT games is subtracted for each game, and the normal number of RT remaining games is reduced to 0 by digesting the specified number of games (30G in this embodiment).・ Move to RT0, SP replay wins and move to normal ・ RT3, or move to stop and move to normal ・ RT1, or special role wins and becomes 1 in internal or 2 in internal It ends by migrating.

  Normal / RT3 shifts when SP replay wins in normal / RT2. Regardless of the number of games since the transition to normal / RT3, whether or not the normal / RT3 shifts to the normal / RT2 with the special replay winning, or the transition outcome stops and shifts to the normal / RT1 When the special role is elected and moves to the inside 1 or the inside 2, it ends.

  Normal / RT4 shifts to the end of BB (RB) and RB. Regardless of the number of games since the transition to the normal / RT4, the normal / RT4 stops the transition and moves to the RT1, or the special role is elected and moves to the internal 1 or the internal 2 To finish.

  The inside 1 shifts when BB1, BB3, RB2 among the special roles are won in the normal gaming state. Then, regardless of the number of games since the transition to the inside, the inside 1 finishes when the special role that triggered the transition to the inside 1 wins and shifts to BB (RB) or RB. .

  The inside 2 shifts when BB2, BB4, RB1 among special roles are won in the normal gaming state. Then, inside 2 ends regardless of the number of games since the transition to the inside, when the special combination that triggered the transition to the inside 2 wins and shifts to BB (RB) or RB. .

  RB shifts when RB1 or RB2 wins in 1 and 2 inside. And RB is complete | finished by digesting 12 games or winning 6 times.

  BB (RB) shifts when BB wins inside. Then, BB (RB) ends when the total number of medals paid out to BB (RB) exceeds the prescribed number, regardless of the number of games since the transition to BB (RB).

  Further, in the slot machine according to the present embodiment, when the gaming state is RT0 to 3, the sub-control unit 91 provides an assist time (hereinafter referred to as AT) that is a notification period in which a navigation effect that notifies the internal lottery result can be executed. The production state can be controlled.

  Here, the gaming state and the transition state of RT will be described. As shown in FIG. 19, when RB or BB (RB) ends, the routine proceeds to normal RT4.

  In normal / RT4, when the transition is stopped, the transition is made to RT1, and when the special role is elected, the transition is made to internal 1 or internal 2 according to the type of the special role won.

  In normal / RT4, if any of the left bells 1-4, middle bells 1-4, right bells 1-4 is won and the small role cannot be won, the transitional outcome will stop. Therefore, any of the left bell 1-4, the middle bell 1-4, the right bell 1-4 can be won and the small role can be won in the normal RT 4 which has been shifted to after the end of RB or BB (RB) If not, the process moves to normal RT1.

  Normally, in RT1, the special role is not won, the promotion replay is not won, the specified number of games (1000G) is consumed, or the promotion replay wins, and the normal role is transferred to RT0, and the special role is won Depending on the type of the special role that has been won, the game moves to the inside 1 or 2 inside.

  Usually ・ Replay GR1-6 wins in RT1, and the promotion replay wins when the stop order is correct. Therefore, in normal ・ RT1, replay GR1-6 wins and corrects in the order of stop. It will shift to RT0.

  In normal / RT0, if the fall replay wins, or if the transition is stopped, it moves to normal / RT1, and if the special replay wins, it moves to normal / RT2, and the special role is won. Depending on the type of the special role, it shifts to 1 inside or 2 inside.

  Usually, the replays GR11 to 16 are won at RT0, the promotion replay wins when the stopping order is correct, and the fall replay wins when the answer is incorrect. In addition, when the replays GR21 to 25 are elected in normal / RT0 and the stop order is correct, the special replay is won, and if the answer is incorrect, the fall replay is won. In addition, in the case of normal / RT0, when any one of the left bells 1 to 4, the middle bells 1 to 4 and the right bells 1 to 4 is won and the small role cannot be won, the transitional outcome stops. Therefore, in normal / RT0, the replay GRs 21 to 25 are elected and the stop order is correct, so that the transition is made to normal / RT2 and the replay GRs 11 to 16 are elected and the stop order is incorrect or the left bell 1 -4, middle bell 1 to 4, right bell 1 to 4 are elected, and if it is not possible to win a small role, it will shift to normal · RT1.

  Normally, in RT2, the special role is not won, SP replay is not won, and the regular game number (30G) is used to move to normal RT0, and SP replay is won to move to normal RT3, When the special role is elected, it shifts to 1 inside or 2 inside depending on the kind of the special role won.

  In normal / RT2, the replay GRs 31 to 36 are won, and the SP replay wins when the stop order is correct. Further, in the normal / RT2, when any of the left bell 1 to 4, the middle bell 1 to 4 and the right bell 1 to 4 is won and the small role cannot be won, the transitional outcome stops. For this reason, in normal / RT2, the replays GR31 to 36 are elected, and when the stopping order is correct, the routine proceeds to normal / RT3, and any of the left bell 1 to 4, the middle bell 1 to 4, and the right bell 1 to 4 Will be transferred to normal / RT1 if the winning combination is not successful.

  In normal / RT3, when the special replay wins, it moves to RT2, and when the transition roll stops, it moves to normal / RT1, and the special role is elected. Transition to Medium 1 or Internal 2

  In normal / RT3, the replay GRs 31 to 36 are elected, the SP replay or the normal replay is won when the stop order is correct, and the special replay is won if the answer is incorrect. Further, in the normal / RT3, when any one of the left bells 1 to 4, the middle bells 1 to 4 and the right bells 1 to 4 is won and the small role cannot be won, the transitional outcome is stopped. For this reason, in normal / RT3, the replay GRs 31 to 36 are elected, and the stop order becomes incorrect, so the routine proceeds to normal / RT2, and the left bell 1 to 4, the middle bell 1 to 4, the right bell 1 to 4 If either of them wins and the small combination cannot be won, the routine will shift to RT1.

  In the inside 1 and 2, the special role that triggers the transition to the inside wins a transition to RB or BB (RB).

  Next, various control contents executed by the sub-control unit 91 in the present embodiment will be described below with reference to FIGS.

  When the reset signal to the sub CPU 91a is input from the reset circuit 95, the sub control unit 91 performs the startup process (sub) shown in the flowcharts of FIGS.

  First, after the built-in device, peripheral IC, interrupt mode, stack pointer, etc. are initialized (Sn1), the general-purpose port setting corresponding to the general-purpose terminal connected to the CS signal line connected to the SRAM 99 is set as the output port. By setting (Sn2-1), after enabling the output of the chip select signal of the SRAM 99, access to the RAM 91c (work RAM) is permitted (Sn2-2). Next, it is determined whether or not the return command generated in Sa24a of the activation process (main) in FIGS. 8 to 10 is received from the main control unit 41 (Sn3). If the return command has not been received, it is determined whether or not the setting changing command generated in Sa27 of the startup process (main) of FIGS. 8 to 10 has been received from the main control unit 41 (Sn4). When a setting change command is received, a setting reception command flag indicating that the setting change command has been received is stored in a predetermined area of the RAM 91c (Sn5).

  When a return command is received or a setting changing command is received, it is determined whether or not a backup flag corresponding to the game history control module is set in the SRAM 99 (backup RAM) (Sn6-1). In this embodiment, in St0-5, St5, St10, St15 in the power interruption process (sub) of FIG. 26, a backup flag is set for each program module when a power interruption occurs. That is, in this embodiment, regarding the processing performed by the sub-control unit 91, the backup flag corresponds to the backup flag corresponding to the game history control module, the backup flag corresponding to the sound / LED control module, and the AT control module. There are four types of backup flags and backup flags corresponding to the image control module. In Sn6-1, the sub-control unit 91 first checks whether or not a backup flag corresponding to the game history control module is set.

  If the backup flag corresponding to the game history control module is not set, an initialization process for initializing all storage areas of the RAM 91c (work RAM) and SRAM 99 (backup RAM) is executed (Sn20). When the backup flag corresponding to the game history control module is set, the backup flag is cleared (Sn6-2). After clearing the backup flag, a checksum is calculated by obtaining an exclusive OR of data in an area where data used in the game history control module of the SRAM 99 (backup RAM) is stored (Sn6-3). Thereafter, it is determined whether or not the calculated checksum matches the backed-up checksum (Sn6-4). In this embodiment, in St0-4, St4, St9, and St14 in the power interruption process (sub) of FIG. 26, the checksum is also used for each program module when the power interruption occurs. Is generated by obtaining an exclusive OR of the data to be stored in the SRAM 99 (backup RAM). That is, in this embodiment, regarding the processing performed by the sub-control unit 91, the checksum includes a checksum calculated using data used in the game history control module and data used in the sound / LED control module. There are four types: a checksum calculated using the data, a checksum calculated using data used in the AT control module, and a checksum calculated using data used in the image control module . In Sn6-4, the sub-control unit 91 first confirms whether or not the checksum calculated using the data used in the game history control module matches that being backed up.

  If the checksums do not match, initialization processing for initializing all storage areas of the RAM 91c (work RAM) and SRAM 99 (backup RAM) is executed (Sn20). If the checksums match, it is determined whether or not a backup flag corresponding to the sound / LED control module is set in the SRAM 99 (backup RAM) (Sn6-5). If the backup flag corresponding to the AT control module is not set, initialization processing for initializing all storage areas of the RAM 91c (work RAM) and SRAM 99 (backup RAM) is executed (Sn20). If the backup flag corresponding to the sound / LED control module is set, the backup flag is cleared (Sn7). After clearing the backup flag corresponding to the sound / LED control module, the exclusive sum of the data of the SRAM 99 (backup RAM) in which the data used in the sound / LED control module is stored is obtained to calculate the checksum ( Sn8). Thereafter, it is determined whether or not the calculated checksum matches the backed-up checksum (Sn9). If the checksums do not match, initialization processing for initializing all storage areas of the RAM 91c (work RAM) and SRAM 99 (backup RAM) is executed (Sn20).

  If the checksums match, it is determined whether a backup flag corresponding to the AT control module is set in the SRAM 99 (backup RAM) (Sn10). If the backup flag corresponding to the AT control module is not set, initialization processing for initializing all storage areas of the RAM 91c (work RAM) and SRAM 99 (backup RAM) is executed (Sns20). If the backup flag corresponding to the AT control module is set, the backup flag is cleared (Sn11). After the backup flag corresponding to the AT control module is cleared, an exclusive OR of the data of the SRAM 99 (backup RAM) in which the data used in the AT control module is stored is obtained to calculate the checksum (Sn12). Thereafter, it is determined whether or not the calculated checksum matches the backed-up checksum (Sn13). If the checksums do not match, initialization processing for initializing all storage areas of the RAM 91c (work RAM) and SRAM 99 (backup RAM) is executed (Sn20).

  If the checksums match, it is determined whether a backup flag corresponding to the image control module is set in the SRAM 99 (backup RAM) (Sn14). When the backup flag corresponding to the image control module is not set, initialization processing for initializing all storage areas of the RAM 91c (work RAM) and SRAM 99 (backup RAM) is executed (Sn20). If the backup flag corresponding to the image control module is set, the backup flag is cleared (Sn15). After clearing the backup flag corresponding to the image control module, the exclusive sum of the data in the area of the SRAM 99 (backup RAM) where the data used by the image control module is stored is obtained to calculate the checksum (Sn16). Thereafter, it is determined whether or not the calculated checksum matches the backed-up checksum (Sn17). If the checksums do not match, initialization processing for initializing all storage areas of the RAM 91c (work RAM) and SRAM 99 (backup RAM) is executed (Sn20).

  If the checksums match, it is determined whether the setting change command reception flag is set (Sn18). If the command change flag during setting change is not set, a return process is executed (Sn19). On the other hand, if the setting change command reception flag is set, initialization processing for initializing all storage areas of the RAM 91c (work RAM) and SRAM 99 (backup RAM) is executed (Sn20). After the process of Sn19 or Sn20 is completed, the timer interrupt process (sub) shown in FIG. 24 is performed according to the timer interrupt.

  As described above, in the startup process (sub), the return process is performed on the condition that all checksums of the program modules match and the backup flags for the program modules are all set. It is possible to prevent the restoration process from being performed even though the module backup data is not accurate. As a result, even if backup data is created for each module, the restoration process can be performed reliably.

  FIG. 24 is a flowchart of timer interrupt processing (sub) executed by the CPU 91c at intervals of 1.12 seconds based on the count value of the internal clock.

  In the timer interrupt process (sub), first, the register in use is saved in the stack area (Sp1).

  Next, a power failure determination process is performed (Sp2). In the power failure determination process, it is determined whether or not a voltage drop signal is input from the power failure detection circuit 48. If a voltage drop signal is input, whether or not the voltage drop signal is input in the previous power failure determination process as well. If a voltage drop signal has been input in the previous power failure determination process, it is determined that a power failure has occurred, and a power interruption flag indicating that is set.

  After the power failure determination process in the step of Sp2, it is determined whether or not the power interruption flag is set (Sp3). If the power interruption flag is set, the process proceeds to a power interruption process (sub) described later. .

  If the power interruption flag is not set, command analysis processing is executed (Sp4). In the command analysis process, it is determined whether or not a command is stored in the command buffer. If the command is stored in the command buffer, the command is acquired from the command buffer. And the process according to the acquired command is performed.

  After the command analysis process is completed, the sound / LED control process is executed based on the sound / LED control module (Sp5). The sound / LED control process in the step of Sp5 is a process executed by the sub-control unit 91 according to the sound / LED control module. In the sound / LED control process, control related to the effect effect LED 52, the speakers 53, 54, and the reel LED 55 is performed according to the progress of the game.

  After the sound / LED control process is completed, the AT control process is executed based on the AT control module (Sp6). The AT control process in the step of Sp6 is a process executed by the sub control unit 91 according to the AT control module. In the AT control process, the sub control unit 91c determines whether or not a predetermined AT lottery condition is satisfied based on a command from the main control unit 41, and determines whether or not to control the AT when the AT lottery condition is satisfied. An AT lottery to determine whether or not.

  As the AT lottery conditions, for example, in RT0 to RT4, when cherries (weak cherry, strong cherry, middle cherries) or SP replay is established, when BB or RB is completed, it is set.

  When the sub-control unit 91c wins the AT lottery, the sub-control unit 91c sets an AT flag indicating that in a predetermined area of the RAM 91c. Then, it is determined whether or not the AT flag is set. If the AT flag is set, AT control is executed.

  When it is specified from the AT flag that it is AT, a navigation effect is executed when a winning combination corresponding to the gaming state is won. The navigation target combination is replay GR1 to 6 when it is normal · RT1, replay GR11 to 16 and replay GR21 to 25 when it is normal · RT0, and replay GR31 to 36 when it is normal · RT2. Further, in normal / RT0 to RT3, the push order bell is a common navigation target combination. As a navigation effect when winning replays GR1 to GR36, a push order for winning a promotion replay, special replay, or SP replay according to the winning situation is notified. For example, a message “left middle right!” Is displayed on the liquid crystal display 51 as a navigation effect when the replay GR1 is won. Regarding the other replays GR <b> 2 to 36, a message corresponding to the replay GR is displayed from the liquid crystal display 51.

  As described above, in the navigation effect in the present embodiment, a message reminiscent of an operation mode advantageous to the player is notified in the same mode regardless of the type of the navigation target role. For this reason, the player can operate in an operation mode that is advantageous to the player without being conscious of the type of the winning navigation target combination.

  In addition, the aspect of a navigation effect is not restricted to such an aspect, What kind of thing may be sufficient if a player is distinguishable according to a winning condition. In addition, the navigation effect is not limited to what is displayed on the liquid crystal display 51, and may be executed using the effect effect LED 52, the speakers 53 and 54, the reel LED 55, and the like.

  Then, by executing the navigation effect, it is possible to make the promotion replay winning, the special replay winning, the SP replay winning, the bell winning selected intentionally, and avoid the falling replay winning.

  In addition, as a navigation effect (a specific example will be described later with reference to FIGS. 39 and 40) when one of the push order bells is won, a push order for reliably winning a right-falling bell or a middle bell is notified. Is done. For example, when winning the left bell, the left reel is stopped as the first stop reel, so that the right falling bell can be reliably won, so “left!” For stopping the left reel as the first stop reel. Is displayed on the liquid crystal display 51. As for the middle bell and the right bell, a message corresponding to each bell is displayed from the liquid crystal display 51.

  After the AT control process is completed, the image control process is executed based on the image control module (Sp7). The image control process in the step of Sp7 is a process executed by the sub control unit 91 according to the image control module. In the image control process, for example, control related to display of various images displayed from the liquid crystal display 51 such as demonstration display and effect display is performed.

  After the image control process is completed, the game history control process is executed based on the game history control module (Sp8). The game history control process in the step of Sp8 is a process executed by the sub control unit 91 according to the game history control module. In the game history control process, a game history or the like corresponding to the result of the game or the effect is accumulated, and the accumulated game history is output so that it can be browsed, or externally output using a two-dimensional code or the like.

  FIG. 26 is a flowchart showing the control content of the power interruption process (sub) executed when the sub control unit 91 determines that the power interruption flag is set in the timer interrupt process (sub) described above.

  In the power interruption process (sub), first, the sub control unit 91 reads the backup data of the game history control module from the work RAM (St0-1). Next, predetermined data conversion is performed on the data read from the work RAM to create backup data (St0-2). Then, the sub control unit 91 stores the created backup data in the SRAM 99 (backup RAM) (St0-3). Next, the sub-control unit 91 calculates the exclusive OR of the backup data converted in St0-2, calculates the checksum of the backup data of the game history control module, and sets this in the SRAM 99 (backup RAM) ( St0-4). After setting the checksum data, the sub-control unit 91 sets a backup flag indicating that the backup has been executed in the SRAM 99 (backup RAM) (St0-5).

  Here, the data conversion process in step St0-2 will be described. In St1, the sub-control unit 91 reads 2 bytes (16 bits) of data from the work RAM which is an internal memory. In this embodiment, an SRAM 99 capable of only 8-bit bus access is connected as an external memory and used as a backup RAM. As already described, in this embodiment, the sub-control unit 91 can only perform 16-bit or 32-bit bus access to an external device such as an external memory. Then, even if the 16-bit data read from the work RAM is stored in the SRAM 99 (backup RAM) as it is, only the 8-bit data can be recognized on the SRAM 99 (backup RAM) side, so the upper 8 bits are lost, A situation occurs in which only lower 8-bit data can be stored in the SRAM 99 (backup RAM). Therefore, in the step of Sm2, the 16-bit data read in St0-1 is converted into two data by performing the following data conversion process.

  First, for the first conversion data, the 16-bit data read in St0-1 is masked with the mask value “00FF (H)” as it is, and only the lower 8 bits of the original data read in St0-1 are stored. The data set in the lower 8 bits is generated as it is. For the second conversion data, the 16-bit data read in St0-1 is shifted by 8 bits (therefore, the value in the upper 8 bits of the original data is moved to the lower 8 bits). The data after the shift processing is masked with the mask value “00FF (H)”, and data in which the upper 8 bits of the original data read in St0-1 are set to the lower 8 bits is generated. Then, by storing these two pieces of conversion data in the SRAM 99 (backup RAM) in the step St0-3, the upper and lower values of the original data read in St0-1 are divided into two data. The power can be backed up without missing.

  In the steps St2, St7, and St12, which will be described later, the same data conversion processing as that in the steps St0-2 described above is executed.

  Next, the sub-control unit 91 reads the backup data of the sound / LED control module from the work RAM (St1). Next, predetermined data conversion is performed on the data read from the work RAM to create backup data (St2). Then, the sub control unit 91 stores the created backup data in the SRAM 99 (backup RAM) (St3). Next, the sub-control unit 91 calculates the exclusive OR of the backup data converted in St2, calculates the checksum of the backup data of the sound / LED control module, and sets it in the SRAM 99 (backup RAM) (St4). ). After setting the checksum data, the sub-control unit 91 sets a backup flag indicating that the backup has been executed in the SRAM 99 (backup RAM) (St5).

  Next, the sub control unit 91 reads backup data of the AT control module from the work RAM (St6). Next, predetermined data conversion is performed on the data read from the work RAM to create backup data (St7). Then, the sub control unit 91 stores the created backup data in the SRAM 99 (backup RAM) (St8). Next, the sub-control unit 91 calculates the exclusive OR of the backup data converted in St7, calculates the checksum of the backup data of the AT control module, and sets this in the SRAM 99 (backup RAM) (St9). After the checksum data is set, the sub-control unit 91 sets a backup flag indicating that the backup has been executed in the SRAM 99 (backup RAM) (St10).

  Next, the sub control unit 91 reads the backup data of the image control module from the work RAM (St11). Next, predetermined data conversion is performed on the data read from the work RAM to create backup data (St12). Then, the sub control unit 91 stores the created backup data in the SRAM 99 (backup RAM) (St13). Next, the sub-control unit 91 calculates the exclusive OR of the backup data converted in St12, calculates the checksum of the data used in the reel rotation control module, and sets this in the SRAM 99 (backup RAM). (St14). After setting the checksum data, the sub-control unit 91 sets a backup flag indicating that the backup has been executed in the SRAM 99 (backup RAM) (St15).

  After setting the backup flag at St15, access to the RAM 91c is prohibited (St16), and the setting of the general-purpose port corresponding to the general-purpose terminal to which the CS signal line connected to the SRAM 99 is connected is set to the input port. (St17), the output function of the chip select signal to the SRAM 99 is forcibly disabled. Thereafter, the voltage decreases, the CPU 91a of the sub-control unit 91 stops and shifts to a standby state. And if a voltage falls in this standby state, it will be in an operation stop state internally. Therefore, the sub-control unit 91 reliably stops operation when power is interrupted.

  Here, a specific example when the backup data of each program module is stored in the SRAM 99 (backup RAM) will be described with reference to FIG.

  As described with reference to FIG. 26, among the four program modules of the game history control module, the sound / LED control module, the AT control module, and the image control module, first, the backup data of the game history control module is stored in the SRAM 99 (backup RAM). Store (St0-3). In the SRAM 99 (backup RAM), the start address specified when storing the backup data of the game history control module is set to “A5000”. Therefore, the sub-control unit 91 specifies “A5000” as the start address in step St0-3 and stores the backup data of the game history control module. Then, the process of St0-1 to St0-3 is repeated while incrementing the storage destination address of the SRAM 99 (backup RAM) until backup of all data for the game history control module stored in the work RAM is completed. Run.

  Next, after the backup data of the game history control module is stored, the backup data of the sound / LED control module is stored in the SRAM 99 (backup RAM) (St3). In the SRAM 99 (backup RAM), the start address designated when storing the backup data of the sound / LED control module is set to “A6000”. Therefore, in step St3, the sub-control unit 91 designates “A6000” as the start address and stores the sound / LED control module backup data. Then, the St1 to St3 processes are repeatedly executed while incrementing the storage destination address of the SRAM 99 (backup RAM) until backup of all data for the sound / LED control module stored in the work RAM is completed.

  Next, after the backup data of the sound / LED control module is stored, the backup data of the AT control module is stored in the SRAM 99 (backup RAM) (St8). In the SRAM 99 (backup RAM), the start address designated when storing data used in the AT control module is set to “A7000”. Therefore, the sub-control unit 91 specifies “A7000” as the start address and stores the backup data of the AT control module in step St8. Then, until the backup of all data for the AT control module stored in the work RAM is completed, the processing of St6 to St8 is repeatedly executed while incrementing the storage destination address of the SRAM 99 (backup RAM).

  Next, after the backup data of the AT control module is stored, the backup data of the image control module is stored in the SRAM 99 (backup RAM) (St13). In the SRAM 99 (backup RAM), the start address designated when storing the backup data of the image control module is set to “A8000”. Therefore, the sub-control unit 91 specifies “A8000” as the start address in step St13, and stores the backup data of the image control module. Then, until backup of all data for the image control module stored in the work RAM is completed, the processing of St11 to St13 is repeatedly executed while incrementing the storage destination address of the SRAM 99 (backup RAM).

  As described above, since backup data is stored for each program module, when only one of the program modules needs to be changed in another model, only that program module needs to be replaced, and the change of the presentation control program is facilitated. . Since the start address for storing the backup data of each program module is set for each program module, it is not necessary to maintain consistency for storing the backup data even if the model is changed. The backup data may be stored at the start address set in. For this reason, it is possible to simplify the program at the time of storing the backup data, and it is possible to reduce the man-hour for developing the program. Similarly, checksum data is also created for each program module, so even if the model is changed, there is no need to maintain consistency for storing checksum data, and the program for storing checksum data is simplified. Can reduce the man-hours for program development.

  In addition, a game history control module indirectly related to a player's profit, such as when it is possible to receive various benefits by, for example, storing game history on an external server etc. Since the data is stored in the SRAM 99 (backup RAM) in preference to other backup data, the backup data of the game history control module can be secured quickly, and it is effective in preventing loss of the player's profit. Is.

  Further, since the backup data of the AT control module related to the player's profit is stored in the SRAM 99 (backup RAM) in preference to the image control module, the backup data of the AT control module can be secured quickly, and the player's profit. It is effective in preventing the occurrence of loss.

  Next, referring to FIGS. 28 to 30, in Sm2, Sm7, Sm12, Sm17 of the power interruption process (main) in FIG. 14 and St0-2, St2, St7, St12 of the power interruption process (sub) in FIG. The data conversion to be executed will be specifically described.

  FIG. 28 is an explanatory diagram showing the contents of data in the backup RAM when data is transferred between the work RAM and the backup RAM with (A) the same bus width (B) and different bus widths. In the present embodiment, data is expanded in the work RAM for processing, and the data expanded in the work RAM is stored in the backup RAM as backup data. “(H)” indicates a hexadecimal number.

  The work RAM stores 16 pieces of 8-bit (1 byte) data at each address. For example, data “00”, “01”... “0F” are stored in addresses “0000h” to “000Fh”, respectively, and data “10” and “001Fh” are stored in addresses “0010h” to “001Fh”. 11 ”...“ 1F ”data is stored.

  As shown in FIG. 28 (A), a 8-bit bus accessible microprocessor can be used for external devices such as an external memory, and the external RAM backup RAM can be accessed with a bus width of 8 bits (1 byte). In this case, that is, when the accessible bus widths coincide with each other, when the backup data is transferred from the work RAM to the backup RAM, the 8-bit backup data is stored as it is. Does not happen. Specifically, for example, when the data stored in the work RAM at the address “0000h” is read in 8-bit units and the 8-bit backup data “00” is transferred to the backup RAM, the transferred backup data “00” is transferred. Is stored in “0000h” of the backup RAM. Similarly, when the 8-bit backup data “01” stored at the address “0001h” in the work RAM is transferred to the backup RAM, the transferred backup data “01” is stored in the backup RAM. Similarly, backup data stored at other addresses is also stored at corresponding addresses.

  On the other hand, as shown in FIG. 28B, as shown in this embodiment, a microprocessor capable of only 32-bit or 16-bit bus access to an external device such as an external memory is used. When the backup RAM can be accessed with a bus width of 8 bits (1 byte), that is, when the accessible bus widths do not match, data is read from the work RAM in units of 16 bits, and the backup RAM When the data is transferred to the data, the upper 8 bits of data transferred from the work RAM are lost, and the entire 16 bits cannot be transferred. Specifically, for example, when 16-bit backup data “0001” stored at addresses “0000h” and “0001h” in the work RAM is transferred to the backup RAM, the upper 8-bit data “01” is lost. Only the lower 8 bits of data “00” are stored in “0000h” of the backup RAM. Similarly, when the 16-bit backup data “0203” stored in the addresses “0002h” and “0003h” in the work RAM is transferred to the backup RAM, the upper 8-bit data “03” is lost and the lower 8-bit data is lost. Only data “02” is stored in “0002h” of the backup RAM. That is, the upper 8 bits of the 16-bit backup data are lost, and the backup data is stored only at even addresses in the backup RAM.

  Therefore, in order to prevent data loss even when the bus widths of the data buses of the work RAM and the backup RAM do not match, in the present invention, the power interruption processing (main) Sm2, Sm7, Data conversion is performed in Sm12, Sm17, and St0-2, St2, St7, and St12 of the power interruption process (sub) in FIG.

  First, the case where the bus width to be accessed on the microprocessor side does not match the bus width accessible on the backup RAM side and data in the upper 1 byte is lost will be described with reference to FIG. For example, data is stored from the work RAM to the backup RAM in Sm3, Sm8, Sm13, Sm18 in the power interruption process (main) in FIG. 14 and St0-3, St3, St8, St13 in the power interruption process (sub) in FIG. In this case, it is assumed that 16-bit backup data “1234” is transferred to the backup RAM. In this case, as described with reference to FIG. 28, the upper 8-bit data “34” is missing and stored. Therefore, when the restoration process is performed in Sa24 of FIG. 10 or Sn19 of FIG. 24, when the backup data is read from the backup RAM, the upper 8-bit data “34” is lost, and only the lower-order 1-byte data “12” is stored. Stored in work RAM. However, this cannot return to the state before the power interruption.

  Therefore, as shown in FIG. 29B, in this embodiment, when data is transferred from the work RAM to the backup RAM, the power interruption processing (main) Sm2, Sm7, Sm12, Sm17 and FIG. Data conversion is performed in St0-2, St2, St7, and St12 of the power interruption process (sub) in FIG.

  Specifically, for example, “1234 (H)” that is 16-bit data is converted into two data. For the first data, the data “1234 (H)” read from the work RAM is masked with the mask value “00FF (H)” as it is, and converted to “0034 (H)”. For the second data, the data read from the work RAM is shifted by 8 bits, masked with the mask value “00FF (H)”, and converted to “0012 (H)”. As a result, when 16-bit backup data “1234 (H)” is read from the work RAM and data conversion is performed, it is composed of two 16-bit data consisting of “0012 (H)” and “0034 (H)”. A total of 32 bits (4 bytes) of backup data is created. When each of the two 16-bit backup data is sequentially written in the backup RAM, as described above, the upper 8 bits of data “00” are lost, so the lower 8 of the one backup data “0012”. Bit data “12” is stored in the backup RAM. Similarly, “34”, which is lower byte data of the other backup data “0034”, is stored in the backup RAM. As a result, even when 16-bit backup data “1234” is transferred using a data bus having an 8-bit bus width, the data can be stored in the backup RAM without being lost.

  Also, the reverse data conversion process is performed when the return process is performed in Sa24 of FIG. 10 or Sn19 of FIG. Specifically, since only 8-bit data can be read from the backup RAM, the data “12 (H)” and the data “34 (H)” are sequentially read out and combined to form the data “1234 ( H) "is restored, and the restored data is stored in the work RAM.

  Next, referring to FIG. 30, data conversion is performed in Sm2, Sm7, Sm12, Sm17 in the power interruption process (main) in FIG. 14 and St0-2, St2, St7, St12 in the power interruption process (sub) in FIG. A data storage state in the backup RAM when the data is stored from the work RAM to the backup RAM will be described.

  As described above, for example, the 16-bit backup data “0001” stored in the addresses “0000h” and “0001h” in the work RAM is converted, and “0000” which is a total of 32-bit backup data. And “0001” are created. When this is transferred to the backup RAM, the upper 8-bit data “00” added at the time of conversion is lost, and only the lower 8-bit data “00” and “01” are stored in the backup RAM. If the upper 8 bits of data (data “00” added at the time of data conversion) is lost, no data is stored in the odd addresses “+ 0001h” and “+ 0003h”, so the lower 8 bits of the transferred 16-bit data “0000” The bit data “00” is stored in the even address “+ 0000h”, and the data “01” of the lower 8 bits of the 16-bit data “0001” transferred subsequently is stored in the even address “+ 0002h”. As described above, when data conversion is performed on other data and the data is transferred, the data is similarly stored at even addresses in the backup RAM.

  In the present embodiment, the main control unit 41 is connected to an SRAM 50 as an external memory, and this SRAM 50 is used as a backup RAM. Similarly, the sub-control unit 91 is connected to an SRAM 99 as an external memory, and this SRAM 99 is used as a backup RAM. As described above, when the external memory is used as the backup RAM instead of the built-in memory of the main control unit 41 or the sub control unit 91, the CPU side stores the RAM when the supply voltage is unstable like a power failure. Even if access to the memory is prohibited, a phenomenon may occur in which the chip select signal for specifying the RAM and the WR signal indicating the timing of writing to the RAM are erroneously output, and these signals coincide with each other by chance. In addition, there is a problem that data in the external memory is rewritten.

  With respect to this problem, in this embodiment, as shown in FIG. 31, taking the sub control unit 91 as an example, it is supplied to Vcc (I / O) of the sub control unit 91 and used for the operation of the I / O port 91d. A DC voltage of 3.3 V is generated by the first switching regulator IC 901 and supplied to the Vcc (CPU) of the sub-control unit 91 and a DC voltage of 1.15 V used for the operation of the CPU 91 a is generated by the second switching regulator IC 902. And the second switching regulator IC 902 is provided with a function of outputting a POWERGOOD signal when the output voltage from the second switching regulator IC 902 reaches a specified voltage value and the output is satisfactorily performed. The RMT2 terminal serving as an input unit for the output POWERGOOD signal is connected to the first switching regulator. Provided in the IC 901 and used for the operation of the CPU 91a by providing the first switching regulator IC 901 with a function for the first switching regulator IC 901 to start generating a direct current on condition that the POWERGOOD signal is input to the RMT2 terminal. By starting the supply of the 3.3V DC voltage used for the operation of the I / O port 91d after the supply of the 1.15V DC voltage is started first, A chip that designates an SRAM by operating the I / O port 91d in a state where the operation of the CPU 91a is unstable by supplying the 3.3V DC voltage before the DC voltage of 1.15V. Prevents the phenomenon that the select signal and the WR signal indicating the timing of writing to the SRAM are erroneously output. And, so as to prevent the data in the external memory will be rewritten.

  Specifically, as shown in FIG. 31, a first switching regulator IC 901 that generates DC 3.3 V and DC 1.0 V from a 12 V DC current supplied from the game control board 40 via a power supply line, A second switching regulator IC 902 that generates DC 1.15 V from a 12 V DC current supplied in parallel with the first switching regulator IC 901 is provided.

  Note that the voltage of the power supply line 12V is monitored by the power interruption detection circuit 98 as described above.

  DC1.0V is output from the Vout1 terminal of the first switching regulator IC 901, and DC3.3V is output from the Vout2 terminal. As shown in FIG. 31, this Vout2 terminal is also connected to the Vcc (I / O) terminal of the sub-control unit 91, the VDD terminal of the SRAM 99, and the Vcc I / O Vcc terminal of the VDP, and has a maximum current of 250 mA. Is consumed.

  Further, DC 1.15 V is output from the Vout terminal of the second switching regulator IC 902. As shown in FIG. 31, the Vout terminal is also connected to the Vcc (CPU) terminal of the sub-control unit 91 and the Vcc core Vcc terminal of the VDP, and a maximum current of 1400 mA is consumed.

  That is, the maximum load capacity (1400 mA) which is the maximum power consumption of 1.15 V supplied from the second switching regulator IC 902 is the maximum power consumption of 3.3 V supplied from the Vout2 terminal of the first switching regulator IC 901. When the power consumption of 1.15 V is larger than a certain maximum load capacity (250 mA), the voltage of 1.15 V supplied from the second switching regulator IC 902 during a power failure is the first switching regulator. There may be a case where the voltage drops before 3.3V supplied from the IC 901.

  Since the rated voltage to be supplied to the Vcc (CPU) terminal of the sub-control unit 91 is 1.2 V and the rated voltage to be supplied to the VDP core Vcc terminal is 1.1 V, in this embodiment, By connecting each of these terminals to the Vout terminal of the second switching regulator IC 902 and outputting 1.15 V, which is an intermediate voltage between 1.2 V and 1.1 V, from the Vout terminal, one switching regulator IC 902 is connected. By sharing the sub-control unit 91 and the VDP, the number of switching regulator ICs to be used is reduced and the cost is reduced.

  Further, as shown in FIG. 31, the second switching regulator IC 902 of this embodiment is provided with a POWERGOOD terminal, and has an output function of a POWERGOOD signal (hereinafter abbreviated as PG signal) from the POWERGOOD terminal. Yes.

  As shown in FIG. 32, the POWERGOOD signal starts to be output when the voltage of the 12V power supply line supplied to the second switching regulator IC 902 rises and the output DC voltage rises to 0.6V. At the same time, the output is stopped when the voltage of the power supply line decreases and the output DC voltage decreases to 0.6V. That is, in the second switching regulator IC 902, a comparison circuit that compares the output voltage with the specified voltage of 0.6V, and a POWERGOOD signal is output when the comparison voltage is higher than the specified voltage of 0.6V. A signal driving circuit is provided.

  Further, as shown in FIG. 31, the first switching regulator IC 901 of this embodiment is provided with an RMT2 terminal, and when input of a signal to the RMT2 terminal is started (OFF → ON), The oscillation of each voltage in the DC-DC conversion switching circuit is started in the order of 1.0 V → 3.3 V, and when the signal input to the RMT2 terminal is stopped (ON → OFF), the DC− A control circuit for stopping oscillation in the DC conversion switching circuit is provided.

  Here, the starting state (starting sequence) of each DC voltage and the output state of the PG signal will be described with reference to FIG.

  First, as the voltage of the power supply line increases, the voltage supplied to the first switching regulator IC 902 and the second switching regulator IC 902 connected to the power supply line increases.

  In a state where these supplied voltages are increasing, the second switching regulator IC 902 starts voltage generation by oscillation when the increased voltage reaches the operable voltage.

  On the other hand, even if the supplied voltage rises and reaches the operable voltage, the first switching regulator IC 901 does not start voltage generation due to oscillation because the input of the PG signal to the RMT 2 is in the OFF state.

  Next, the second switching regulator IC 902 starts outputting the PG signal when the generated output voltage rises as the supplied voltage rises and reaches a specified voltage of 0.6V. To do. Note that the output voltage from the second switching regulator IC 902 increases as the supplied voltage (power supply voltage) increases, and reaches 1.15V.

  In response to the start of output of the PG signal from the second switching regulator IC 902, the first switching regulator IC 901 first generates (outputs) a 1.0 V DC voltage by oscillation in the 1.0 V DC-DC conversion switching circuit. In response to the output voltage reaching 1.0 V, generation (output) of 3.3 V DC voltage by oscillation in the 3.3 V DC-DC conversion switching circuit is started.

  In other words, the 1.15V output used for the operation of the CPU 91a of the sub-control unit 91 is supplied before the 3.3V DC voltage used for the operation of the I / O port 91d. Since the CPU 91a that controls the operation of the O port 91d can start up before the I / O port 91d becomes operable and can control the I / O port 91d satisfactorily, the I / O port 91d Can be operated prior to the CPU 91a, so that it is possible to prevent the backup data from being rewritten due to erroneous output of the chip select signal or the WR signal.

  In this embodiment, the chip select signal and WR signal output to the SRAM 99 are prevented from being erroneously output from the sub-control unit 91, and the chip select signal and WR signal are input as described above. Also on the SRAM 99 side, as shown in FIG. 31, by prohibiting writing up to a predetermined voltage of 2.9 V, it is possible to reliably prevent the backup data from being rewritten.

  Next, the situation at the time of a power failure will be described. As shown in FIG. 32, when the voltage (power supply voltage) supplied from the power supply line reaches 9V, the voltage drop signal described above is output and the power interruption process (sub) is performed.

  In the first switching regulator IC 901 of this embodiment, when the power supply voltage drops to 6V, the output voltage starts to drop by 3.3V. That is, the minimum power supply voltage capable of outputting 3.3V is 6V, and when the voltage is lower than that, the output voltage is set so as to decrease as the power supply voltage decreases.

  Further, in the first switching regulator IC 901 of this embodiment, when the power supply voltage decreases to 5V, the output voltage of 1.30V starts to decrease. That is, the minimum power supply voltage capable of outputting 1.0 V is 5 V, and when it is lower than that, the output voltage is set so as to decrease as the power supply voltage decreases.

  In the second switching regulator IC 902 of this embodiment, when the power supply voltage decreases to 3.9 V, the output voltage starts to decrease. That is, the lowest power supply voltage capable of outputting 1.15 V is 3.9 V, and when the voltage is lower than 3.9 V, the output voltage is set to decrease as the power supply voltage decreases.

  Further, as described above, the second switching regulator IC 902 of the present embodiment stops the output of the PG signal (ON → OFF) when the output voltage becomes 0.6V.

  Thus, 3.3V used for the operation of the I / O port 91d starts to decrease at 6V, and 1.15V used for the operation of the CPU 91a starts to decrease at 3.9V. Thus, the I / O port 91d becomes inoperable first, and then the CPU 91a becomes inoperable, so that the CPU 91a becomes inoperable before the I / O port 91d, and the chip select signal and the WR signal are output. It is possible to prevent backup data from being accidentally output and rewritten.

  However, as described above, the driving voltage of the sub CPU 91a is also used for a VDP having a large amount of power consumption. Therefore, the speed at which the voltage decreases when the power is interrupted depends on the power usage state in the VDP. Hardware configuration in which the I / O port 91d stops operation earlier than the sub CPU 91a of the sub control unit 91, as described above, before 3.3V used for the operation of the / O port 91d Even if it is adopted, it has been confirmed that the operation of the sub CPU 91a stops before the I / O port 91d stops the operation. In such a case, a chip select signal for designating the SRAM 99, There remains a possibility that the WR signal indicating the timing of writing to the SRAM 99 will be output, and the data in the external memory may be rewritten. .

  For this reason, in this embodiment, after backup data is stored in the SRAM 99 in the event of a power failure, the setting of the I / O port 91d corresponding to the general-purpose terminal connected to the CS signal line connected to the SRAM 99 is set to the input port. As a result, the writing of data to the SRAM 99 is invalidated by software, and if the 1.15V used for the operation of the CPU 91a is lowered first, as shown in FIG. Even if only 1.15V drops and 3.3V does not drop due to some trouble, such as failure of the second switching regulator IC 902, 1.15V drops to 0.6V and PG In response to the stop of the signal output, the controller of the first switching regulator IC 901 causes the DC-D of 1.0V. Since the oscillation of the conversion switching circuit and the 3.3-V DC-DC conversion switching circuit is stopped and the voltage generation of 1.0 V and 3.3 V is stopped instantaneously, the operation of the CPU 91a is also difficult in terms of hardware. Since the I / O port 91 can operate after being stabilized or stopped, it is possible to more reliably prevent the data in the external memory (SRAM 99) from being rewritten.

  In the above description, the sub control unit 91 has been described as an example. Similarly, in the main control unit 41, the setting of the I / O port 41d is set to the input port, so that data writing to the SRAM 50 can be performed by software. In addition, the data in the external memory (SRAM 50) is rewritten at the time of start-up or power failure by generating a direct current and supplying it to the main control unit 41 and the SRAM 50 in the same manner as the configuration shown in FIG. It may be possible to prevent the occurrence of the problem more reliably.

  In this embodiment, the configuration in which the backup RAM is mounted on the same substrate as the main control unit 41 or the sub control unit 91 is described. However, the substrate is separate from the main control unit 91 or the sub control unit 91. Even in the configuration where the backup RAM is executed above, by forcibly disabling the function of outputting the chip select signal to the backup RAM as described above, in the unstable voltage state at the time of power failure Thus, it is possible to reliably prevent the data in the backup RAM from being rewritten.

  In this embodiment, the backup RAM is provided separately in both the main control unit 41 and the sub control unit 91, but only one of the main control unit 41 or the sub control unit 91 is provided with a backup RAM. If the microcomputer and at least the microcomputer backup are stored in the external memory, the output function of the chip select signal to the external memory for backup is forcibly disabled. Thus, the same effect as described above can be obtained.

  In the present embodiment, after the main control unit 41 and the sub control unit 91 are activated, after the setting of the built-in device and other built-in registers, before determining whether the backup data is normal, By setting the general-purpose port setting corresponding to the general-purpose terminal to which the CS signal line connected to the SRAM 50 or SRAM 99 is connected to the output port, the output of the chip select signal of the SRAM 50 or SRAM 99 is enabled. Since the function of outputting a chip select signal to the SRAM 50 or SRAM 99 is disabled until it is determined whether or not it can be restored based on the backup data stored in the SRAM 50 or SRAM 99, power supply is started. This prevents the SRAM 50 and SRAM 99 data from being rewritten in an unstable state after the operation. It can be.

  Further, according to the embodiment, not only the first DC voltage of 3.3V but also the start of generation of the third DC voltage of 1.0V is the second DC voltage of 1.15V. It can be controlled to output after the output starts.

  Further, according to the above-described embodiment, the third DC voltage lower than the first DC voltage of 3.3 V is included in the first switching regulator IC 901 which is the first DC voltage generation integrated circuit. 0V can be generated before 3.3V that is the first DC voltage.

  Further, according to the embodiment, since the PG signal that is the specified voltage output signal of the present invention is input, the oscillation of each DC-DC conversion switching circuit in the first switching regulator IC 901 is started. It can be prevented that the first DC voltage of 3.3 V is generated and output before the signal is input.

  Further, according to the embodiment, when the voltage of the power supply line, which is the power supply voltage at the time of power interruption, decreases, the first lower limit value of 6V is the second lower limit value of 3.9V. Therefore, the first DC voltage of 3.3V cannot be generated earlier than the second DC voltage of 1.15V, and the operation of the I / O port 91d serving as the external interface is disabled. Is stopped before the CPU 91a, so that it is possible to prevent a malfunction due to a malfunction of the I / O port 91d even when the power is interrupted.

  In addition, according to the embodiment, the voltage of the power supply line, which is the power supply voltage, is 3.3 V or the first DC voltage of the first switching regulator IC 901 or the second switching regulator IC 902 is the first DC voltage. 2. When the DC power voltage of 1.15V, which is the lower DC voltage of 6V, becomes 9V which is a power failure detection voltage higher than 3.9V, that is, the first DC voltage is 3.3V. Since the power interruption processing (backup) processing is executed in response to the input of the voltage drop signal (power failure detection signal) before the generation of the second DC voltage 1.15V becomes impossible, these first DC voltages It is possible to avoid that 3.3V and 1.15V which is the second DC voltage cannot be generated and the power interruption processing (backup) processing is not performed properly.

  Although the embodiments of the present invention have been described with reference to the drawings, the present invention is not limited to these embodiments, and modifications and additions within the scope of the present invention are included in the present invention. Needless to say.

  In the above embodiment, the slot machine for setting the bet number using medals and credits has been described as an example of the gaming machine. However, the present invention is not limited to this. For example, a gaming ball is used as a gaming medium. Applying the configuration shown in the above embodiment to a pachinko machine to be used, a slot machine that sets a bet number using a game ball, and a complete credit type slot machine that sets a bet number using only credits, The invention according to claim 1 can be realized. When a game ball is used as a game medium in the slot machine, for example, when one medal is made to correspond to five game balls, and 3 is set as the bet number in the above embodiment, 15 This is equivalent to setting the number of bets using one game ball.

  Note that the gaming machine of the present invention is not limited to one using only one type of a plurality of types of game media such as medals and game balls, and for example, a plurality of types of games such as medals and game balls. The medium may be used in combination. That is, it is possible to play a game by setting the number of bets using any one of a plurality of types of game media such as medals and game balls, and a plurality of types of game media such as medals and game balls when a winning occurs. Any of the slot machines that can pay out any of these is also included in the slot machine of the present invention.

  Specifically, even in a pachinko machine that uses game balls, there are a game control board (main board) and an effect control board as in the slot machine 1 described above, so these game control boards (main board) In addition, the effect control board has the same configuration as that of the slot machine, so that troubles at the time of start-up and power interruption can be solved even in the pachinko machine.

  In addition, unlike the slot machine, there are many pachinko machine effect control boards that do not have a configuration for storing backup data, but the present invention is applied even to those that do not store backup data. As a result, it becomes possible to prevent the I / O port of the control microcomputer mounted on the production control board from malfunctioning, so that these I / O ports malfunction and an abnormal sound is output, It is possible to prevent the occurrence of problems such as LEDs or lamps that are not originally lit.

  Further, in this embodiment, when the power supply is stopped, backup processing for storing backup data in the backup RAM is performed for each program module based on the data used in the program module (Sm3, Sm8, Sm13, Sm18 part, St0-3, St3, St8, and St13 part in FIG. 26), the start address is set so as to be stored in a different storage area for each program module, and from the storage area corresponding to the set start address The backup data is stored in the backup RAM (in Sm3, Sm8, Sm13, and Sm18 in FIG. 14, the part that stores the backup data at the start address shown in FIG. 15 and in St0-3, St3, St8, and St13 in FIG. Open Portion to store backup data address). Therefore, it is possible to complete the backup process for each function of the gaming machine, and it is possible to develop a program related to the backup process for each function, thus facilitating the program development and simplifying the program. As a result, the development man-hours for the program can be reduced. In addition, the backup process can be simplified. In addition, when performing backup processing with a program structure composed of a plurality of program modules, it becomes possible to perform backup processing for each program module in a common way without taking consistency for each model. Development man-hours can be reduced.

  In the above embodiment, each of the game control program and the effect control program has a program module structure. However, the present invention is not limited to this embodiment, and a game machine or a game control program in which only one of the programs is configured by a program module, A slot machine in which a program other than the production control program is configured by a program module, a gaming machine in which at least one of the game control program and the production control program and a program other than the game control program and the production control program are configured by a program module. You may apply the structure shown in said Example.

  In the above embodiment, the game control program is composed of four program modules: an internal lottery control module, an input / output control module, a reel rotation control module, and a payout control module. However, the present invention is not limited to this embodiment. A gaming machine having a game control program in a module structure with at least one program module of the above, or a gaming machine having a game control program in a module structure with a program module other than at least one of the four and the four program modules The configuration shown in the above embodiment may be applied.

  In the above embodiment, the effect control program is composed of four program modules: a game history control module, a sound / LED control module, an AT control module, and an image control module. However, the present invention is not limited to this embodiment. A gaming machine having a presentation control program in a module structure with at least one program module of the above, or a gaming machine having a presentation control program in a module structure with a program module other than at least one of the four and the four program modules The configuration shown in the above embodiment may be applied.

  In the above embodiment, in the power interruption process (main), the backup process is performed in the order of the internal lottery control module, the input / output control module, the reel rotation control module, and the payout control module. However, the backup process is not limited to this example. The configuration shown in the above embodiment may be applied to a gaming machine having a processing order different from that in the above embodiment.

  In the above embodiment, in the power interruption process (sub), the backup process is performed in the order of the game history control module, the sound / LED control module, the AT control module, and the image control module. However, the backup process is not limited to this example. The configuration shown in the above embodiment may be applied to a gaming machine having a processing order different from that in the above embodiment. As a modified example related to the order of backup processing, for example, a gaming machine that performs backup processing of a program module (AT control module in this embodiment) for performing processing related to game control with priority over backup processing of other program modules The configuration shown in the above embodiment may be applied. Specifically, in the above embodiment, in the power interruption process (sub), the backup process is performed in the order of the game history control module, the sound / LED control module, the AT control module, and the image control module. ), The backup process of the AT control module may be prioritized over the backup process of the game history control module, the sound / LED control module, and the image control module. That is, the AT control module backup processing may be performed with the highest priority over the backup processing of other program modules by performing the AT control module backup processing in the portion of St0-1 to St0-5 in FIG. . As a result, in the startup process (sub), the return process is not performed on condition that all backup data is normal, and only the function related to the program module whose backup data is normal is performed. Even if an unexpected power interruption occurs when backup processing related to other program modules is performed after the backup processing of the game is completed, it is possible to secure at least highly important backup data related to the interests of the player It becomes possible.

  In this embodiment, for each program module, check data for determining whether backup data is normal is created using data used in the program module (Sm4, Sm9, Sm14, Sm19 and St0-4, St4, St9, St14 in FIG. 26).

  Therefore, even if the program structure is composed of a plurality of program modules and the backup process is performed by a common method regardless of the model, the program development man-hours can be reduced.

  Further, in this embodiment, for each program module, it is determined whether backup data based on data used in the program module is normal, and it is determined that all backup data is normal. Based on the above, a return process is performed (the portions of Sa8, Sa12, Sa17, Sa21 in FIGS. 8 to 10 and the portions of Sn6-4, Sn9, Sn13, and Sn17 in FIGS. 22 to 23). Therefore, even if the start address is specified so that the start address of the data creation area of the backup data differs for each program module, the return process can be performed reliably.

  In the above embodiment, in the startup process (main) and the startup process (sub), the checksums of the program modules are all returned to the state before the power interruption on condition that the checksums match. Not limited, if there is a program module with a checksum that matches and a program module with a checksum that does not match, only the functions related to the program module with a matching checksum are restored to the state before power interruption, or all The configuration described in the above embodiment may be applied to a gaming machine that returns to the state before power interruption with respect to the function.

  In particular, as in the case of the game history control module of the above-described embodiment, when performing control of a game history that allows a privilege to be granted by external output, not only the game machine, checksums of other program modules If the checksums of the game history control modules match even if the backup data is not normal, that is, if the backup data is not normal, only the game history control module returns to the state before the power interruption, so Even if has been initialized, the game history that has been returned can be output to the outside so that a privilege that does not depend on the initialized contents of the production can be received. In the case of such a configuration, it is preferable to preferentially create and store the backup data of the game history control module at the time of power interruption, as in the above embodiment, so that other program modules can be Even if it is not backed up normally, there is an increased possibility that the game history control module has been backed up normally, the power interruption will not be performed normally, and other effects will be initialized as described above Even if it is done, the possibility that the game history module will return to the state before the power interruption is increased, and it is possible to receive benefits that do not depend on the initialized production contents by outputting the returned game history to the outside Increases nature.

  Also, in the case of controlling a game history such as a game history control module in which not only the gaming machine but also a bonus can be given by external output, only the game history control module is different from other program modules. For other program modules, the checksums of the other program modules are restored to the state before the power interruption while the checksums of the program modules are all matched. Regardless of whether or not they match, if the checksum of the game history control module matches, it may be configured to be able to return to the state before the power interruption, and with this configuration, a program other than the game history control module If the module is not normal, other effects will be initialized, If the checksum of the technique history control module is normal, it is possible to restore only the game history control module. By outputting the restored game history to the outside, it is possible to grant a privilege that does not depend on the initialized contents of the production. Can be received.

  Even in such a configuration, it is preferable to preferentially create and store the backup data of the game history control module at the time of power interruption, and this makes it possible for other program modules not to be backed up normally. Even if there is, the possibility that the game history control module will be backed up normally will increase, and even if the power interruption is not performed normally and other production contents are initialized as described above, the game history module Is likely to return to the state before the power interruption, and by outputting the returned game history to the outside, the possibility of receiving a privilege that does not depend on the initialized contents of the production increases.

  In this embodiment, the backup data is stored in the backup RAM by performing a common data conversion process regardless of which program module is used as the backup data (Sm2, Sm7,. (Sm12, Sm17 and St0-2, St2, St7, St12 in FIG. 26 perform data conversion shown in FIG. 28). Therefore, the number of program development steps can be reduced.

  In the above embodiment, data conversion for adding 8-bit data is performed. However, the present invention is not limited to this embodiment, and the configuration shown in the above embodiment is applied to a slot machine that performs data conversion processing by another method. It may be applied.

  In this embodiment, the program module performs backup processing of backup data based on data used in the AT control module in preference to an image control module other than the AT control module for performing processing related to AT (see FIG. 26, a part in which the process from St6 to St10 in FIG. Therefore, it is possible to reliably back up the program module having a high importance related to the player's profit.

  In the above embodiment, an example in which an AT control module is applied as a game control program module has been described. However, the present invention is not limited to this embodiment. For example, backup processing of a program module that performs processing related to RT is given priority. The configuration shown in the above embodiment may be applied to a gaming machine that performs backup processing of program modules related to games other than AT.

1 slot machine 2L, 2C, 2R reel 6 MAXBET switch 7 start switch 8L, 8C, 8R stop switch 41 main controller 41a CPU
41b ROM
41c RAM
91 Sub-control unit 91a CPU
91b ROM
91c RAM

Claims (1)

A gaming machine capable of performing a predetermined game,
A control microcomputer for performing control related to the game;
A first DC voltage generating integrated circuit that generates and outputs a first DC voltage used for the operation of the external interface in the control microcomputer from a predetermined power supply voltage;
An integrated circuit that is separate from the first DC voltage generating integrated circuit, and is used for operation of a central processing unit that performs operation control processing of the external interface in the control microcomputer; A second DC voltage generating integrated circuit that generates and outputs a lower second DC voltage from the power supply voltage;
With
The second DC voltage generation integrated circuit includes a signal output unit that outputs an output permission signal that permits output of the first DC voltage from the first DC voltage generation integrated circuit, and outputs the second DC voltage. The output of the output permission signal is stopped on the condition that the voltage has decreased to a predetermined specified voltage,
The first DC voltage generation integrated circuit has a signal input unit to which the output permission signal is input, and generates the first DC voltage when input of the output permission signal from the signal input unit is stopped. A gaming machine characterized by stopping.

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