JP2013118939A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine that prevents bias in combinations of a plurality of random number counter values by eliminating correlation among a plurality of random numbers generated by a random number generating means.SOLUTION: First and second counter values are updated on the basis of updating intervals Ta and Tb of the first and second counter values and total numbers Na and Nb of the first and second counter values satisfying: k=Na/Pb or k=Pa/Nb, and Pa≤Nb and Pb≤Na when the total number of the counter values of a first random number generating means for generating the first random number to be used for a lottery as to whether to generate a specific game state is Na; the counter value updating interval of the first random number generating means is Ta; the total number of the counter values of a second random number generating means for generating a second random number value to be used for determining a performance mode of the variable display is Nb; the counter value updating interval of the second random number generating means is Tb; the ratio of the updating interval Ta of the first counter value to the updating interval Tb of the second counter value (Ta/Tb) is k; Pa and Na are integers which are mutually coprime; and Pb and Nb are integers mutually coprime.

Description

  The present invention relates to a gaming machine that includes a random number generation unit that circulates and updates a counter value and uses the counter value generated by the random number generation unit as a random number for game control.

Conventionally, in a pachinko gaming machine as a gaming machine using a game ball, a winning opening called a start winning opening is provided in a game area on the game board, and a random number is calculated based on the winning of a hit ball to the starting winning opening. 2. Description of the Related Art Gaming machines that have been acquired and determined for winning and providing a predetermined profit (for example, so-called jackpot game) to players based on the winning result are widely used.
This type of gaming machine that uses random numbers for game control includes a plurality of random number counters that perform counting operations at a predetermined cycle as means for generating random numbers, and the counter values counted by these random number counters at arbitrary timings. There are those that acquire and use those counter values as random numbers.

  Specifically, a first random number generator (random number counter) of a cyclic update method that counts M counter values from 0 to M−1 with a clock signal of a predetermined cycle, and then returns to “0” and continues counting again. , A second random number generation means (random number counter) that counts N (M ≠ N) counter values from 0 to N−1 with a clock signal of a predetermined period, and then returns to “0” and continues counting again. Then, at the timing when the game ball wins a predetermined winning opening such as a start winning opening, both counter values by the first and second random number counters are acquired as random numbers, and the game control is performed using the acquired random numbers. Judgment (lottery) was performed (see, for example, Patent Document 1).

JP 2008-212731 A

  By the way, in the above-mentioned prior application invention, when the first random number generation means and the second random number generation means are activated simultaneously, the number of counts (ie, “M” times) during which the count value by the first random number generation means goes around, When the count operation of the least common multiple (LCM (M, N)) with the number of counts (that is, “N” times) during the cycle of the count value by the second random number generation means is performed, both counter values are Return to the state. That is, the first and second random number generation means perform a counting operation that synchronizes at a period corresponding to the least common multiple (LCM (M, N)).

  Therefore, if the least common multiple (LCM (M, N)) of the counter values of the first and second random number generation means is small, the counter values of the first and second random number generation means are synchronized in a relatively short cycle. . At this time, depending on the setting method of the number of counts (“M” and “N”) of the first and second random number generation means, it tends to be a combination of possible values of the counter values of the first and second random number generation means. Will occur. That is, there is a problem that the uniformity of the game is lowered due to combinations that do not occur or combinations that occur frequently.

  The present invention has been made in view of the above circumstances, and includes random number generation means for generating a plurality of random numbers used for game control, and a plurality of random number counter values so that there is no correlation between the plurality of generated random numbers. An object of the present invention is to provide a gaming machine capable of preventing the occurrence of bias in the combination of the above and ensuring the uniformity of the game.

In order to solve the above-mentioned problem, the invention described in claim 1
When a variable display game is executed by winning a game ball to the start area provided in the game area, and the variable display game is in a specific result mode, a special game state is provided that gives a player a game value, and In a gaming machine capable of generating a specific game state in which the progress of the game after the special game state ends is advantageous,
A display device capable of displaying images;
A display capable of expressing a plurality of types of symbols by executing the variable display game;
A game control device that controls the game in an integrated manner and controls at least the display;
A display control device for controlling a variable display using a decorative symbol in the display device in synchronization with a variable display game executed by the display device based on an instruction from the game control device;
The game control device includes:
A first counter value is circulated and updated to generate a first random value used for a lottery to determine whether or not to generate the specific gaming state when the execution result of the variable display game is in the specific result mode. First random number generating means for
A second random number generating unit that circulates and updates the second counter value, and generates a second random number value used to determine an effect mode of the variable display executed by the display device;
The total number required for one round of the first counter value updated by the first random number generating means is Na, the update interval of the first counter value is Ta, and the second counter value updated by the second random number generating means is required for one round. The total number is Nb, the update interval of the second counter value is Tb,
The ratio Ta / Tb between the update interval Ta of the first counter value and the update interval Tb of the second counter value is k,
When Pa is an integer that is relatively prime with Na, and Pb is an integer that is relatively prime with Nb,
The first and second random number generation means include
k = Na / Pb or k = Pa / Nb
And
Pa ≦ Nb, Pb ≦ Na
The first and second counter values are updated based on the total number Na and Nb of the first and second counter values satisfying the conditions and the update intervals Ta and Tb of the first and second counter values. To do.

  According to the first aspect of the present invention, the first counter value (big hit symbol random number) generated by the first random number generator and the second counter value (variation pattern random number) generated by the second random number generator. Since there is no correlation between them, there is no bias in the combination of possible values of the first counter value and the second counter value, so that the uniformity of the game can be ensured.

The invention according to claim 2 is the gaming machine according to claim 1,
The game control device includes:
An arithmetic processing unit that executes game control based on a predetermined game program;
The arithmetic processing unit includes:
An individual identification information storage unit for storing individual identification information that can be identified as the arithmetic processing device;
Individual information transmitting means for transmitting the individual identification information stored in the individual identification information storage unit to an external device outside the gaming machine,
Monitoring whether the second counter value has completed a cycle, and subjecting the individual identification information stored in the individual identification information storage unit to an external device outside the gaming machine on condition that the second counter value has completed a cycle It is characterized by transmitting.

According to the invention described in claim 2, since the individual identification information (chip ID) is transmitted to the outside of the gaming machine every time the second counter value makes a round, the second counter value is updated at an appropriate cycle. By monitoring whether or not there is a bias in the combination of random number counter values due to a malfunction of the program, etc., if a bias occurs, a reset is applied, etc. Thus, the uniformity of the game can be ensured by avoiding the bias.
Also, external devices outside the gaming machine, such as information collection terminals and management devices, periodically send them at a predetermined cycle based on the individual identification information (chip ID) transmitted each time the second counter value makes a round. By determining whether or not the random number generation circuit has been received, it is possible to monitor whether the random number generation circuit has been normally updated, and it becomes easy to find fraudulent acts such as board replacement and failures.

  According to the present invention, random number generating means for generating a plurality of random numbers used for game control is provided, and there is no correlation between the plurality of generated random numbers, and there is a bias in the combination of a plurality of random number counter values. This is advantageous in that it is possible to realize a gaming machine capable of preventing the above and ensuring the uniformity of the game.

It is a front view showing one embodiment of a gaming machine provided with a pachinko gaming machine to which the gaming machine according to the present invention is applied. It is a rear view which shows the structural example of the back surface of the game machine of embodiment. It is a front view showing an example of a game board in the gaming machine of the embodiment. It is a block diagram which shows the structural example of the control system provided in the back surface of the game machine of embodiment. It is a block diagram which shows the structural example of the microcomputer for games which comprises the game control apparatus of the control system of FIG. FIG. 6 is a block diagram illustrating a configuration example of a first random number generation circuit and a clock generator provided in the gaming microcomputer of FIG. 5. It is a flowchart which shows the first half part of the specific procedure of the random number update control performed by the random number update controller (update control means) of the 1st random number generation circuit of FIG. It is a flowchart which shows the latter half part of the specific procedure of the random number update control performed by the random number update controller (update control means) of the random number generation circuit of FIG. FIG. 6 is a block diagram showing a configuration example of a second random number generation circuit and a clock generator provided in the gaming microcomputer of FIG. 5. 10 is a timing chart showing the relationship between counter circuit update timing and counter value latch timing in the second random number generation circuit of FIG. 9; 10 is a flowchart showing a specific procedure of latch register holding control performed by a random number update controller of the second random number generation circuit of FIG. 9. 10 is a flowchart showing a specific procedure of latch data reading control performed by a random number update controller of the second random number generation circuit of FIG. 9. It is a flowchart which shows the first half part of an example of the specific procedure of a main process among the game controls performed by the game microcomputer of a game control apparatus. It is a flowchart which shows the second half part of an example of the specific procedure of a main process among the game controls performed by the game microcomputer of a game control apparatus. It is a flowchart which shows an example of the specific procedure of a timer interruption process among the game controls performed by the game microcomputer of a game control apparatus. It is a flowchart which shows an example of the specific procedure of the special figure game process performed during the timer interruption process of FIG. It is a flowchart which shows an example of the specific procedure of the start port SW2 monitoring process performed during the special figure game process of FIG. 16 is a flowchart showing an example of a specific procedure of a chip ID transmission process executed during the timer interrupt process of FIG. (A) is explanatory drawing which shows the relationship between the jackpot symbol random number value and jackpot random number value which are produced | generated in the conventional game control apparatus, (B) is 1st and 2nd in the game control apparatus of the Example of 1st invention. It is explanatory drawing which shows the relationship between the jackpot design random number value produced | generated by the random number generation circuit, and a jackpot random number value. In the game control device of the embodiment of the first invention, it is an explanatory diagram showing an example of the relationship between each random number, the winning symbol and the distribution contents when the jackpot symbol random number is set in the range of 0-9. FIG. 10 is an explanatory diagram showing an example of a variation pattern selection table when the range of variation pattern random numbers is set to 1 to 7 and the range of jackpot symbol random numbers is set to 0 to 9 in the game control apparatus of the first embodiment of the present invention. . It is explanatory drawing which shows an example of the relationship between the number of effective bits in the 2nd random number generation circuit (random number counter) of the game control apparatus of the Example of 1st invention, and the total number of the generated random numbers. (A) is explanatory drawing which shows the conditions in the case of determining the total number of two random numbers and update interval in 2nd invention of this application, (B) is "5" with the total number of two random numbers in 2nd Example. It is explanatory drawing which shows the relationship between the jackpot symbol random number value produced | generated by the 1st and 2nd random number generation circuit at the time of setting to "7", and a jackpot random number value. In the embodiment of the second invention, the jackpot symbol random number value generated by the first and second random number generation circuits when the total number of the two random numbers is “10” and “10” and the update interval Ta = 10 Tb, It is explanatory drawing which shows the relationship with a jackpot random value. In the embodiment of the second invention, the jackpot symbol disturbance generated by the first and second random number generation circuits when the total number of two random numbers is “10” and “5” and the update interval Ta = 2Tb / 5 It is explanatory drawing which shows the relationship between a numerical value and a big hit random number value. It is explanatory drawing which shows the relationship of each random number at the time of applying the Example of 2nd invention, and generating the big hit design random number and two types of fluctuation pattern random numbers 1 and the fluctuation pattern random number 2. FIG. An example of the variation pattern selection table used when the update process is performed under the same conditions as in FIG. 26 to generate the jackpot symbol random number, the variation pattern random number 1, and the variation pattern random number 2 and the result of the variation display game is out of place. It is explanatory drawing. 26 shows an example of a variation pattern selection table used when the big hit symbol random number, the variation pattern random number 1 and the variation pattern random number 2 are generated under the same conditions as in FIG. 26 and the result of the variation display game is a big hit. It is explanatory drawing. It is a flowchart which shows the second half part of the main process among the game controls performed by the game microcomputer of the game control apparatus of the Example of 3rd invention. It is a flowchart which shows an example of the specific procedure of the jackpot symbol random number update process performed during the main process of the Example of 3rd invention. It is a flowchart which shows an example of the procedure of the timer interruption process performed by the game microcomputer of the game control apparatus in 2nd Example of 3rd invention. It is a flowchart which shows the second half part of the main process among the game control performed by the game microcomputer of the game control apparatus in 2nd Example of 3rd invention.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.
FIG. 1 is a front view showing an entire gaming machine according to an embodiment of the present invention.
The gaming device of the present embodiment includes a card unit 70 into which a storage medium for storing a valuable value such as the number of gaming media (number of gaming balls) held by the player or the amount of money that can be converted to the gaming media, and the actual gaming media. And a gaming machine 10 capable of executing a game using the game balls as a prize ball and paying out a predetermined number of game balls as prize balls.
The gaming machine 10 includes a main body frame (outer frame) 11 and a front frame 12, and the front frame 12 is assembled to the main body frame (outer frame) 11 via a hinge 13 so as to be openable and closable. A game board 50 (see FIG. 3) is stored in a storage portion (not shown) formed on the front side of the front frame 12. A glass frame 15 having a cover glass (transparent member) that covers the front surface of the game board 50 is attached to the front frame 12.

Around the cover glass of the glass frame 15, there is provided a decorative member 16 provided with a light emitting device composed of a lamp, LED, or the like. An illumination unit 17 having a light emitting device is also provided above the glass frame 15. When these light-emitting devices emit light according to a predetermined mode, decorative light emission that enhances the effect of the game and light emission that indicates a game state are emitted.
Further, an error notification LED 18 is provided on the right side of the lighting unit 17 for notifying the hall clerk of the occurrence of an error in the gaming machine 10 and the opening of the front frame 12. A speaker 19 that emits sound (for example, sound effects) is provided on the lower left side of the glass frame 12.

  An opening / closing panel 20 and a fixed panel 30 are provided at the lower part of the front frame 12, and an upper plate 21 for supplying a game ball to a hitting ball launching device (not shown) is provided on the opening / closing panel 20. Are provided with a select switch 22 and an operation switch 23 for receiving an operation input from the player. Further, the fixed panel 30 is provided with an ashtray 31, a lower plate 32, an operation unit 33 of a ball striking device, and the like. Further, the lower tray 32 is provided with a lower tray ball removing mechanism 34 for discharging the game balls stored in the lower tray 32.

  In the gaming apparatus of this embodiment, the ball hitting device launches the gaming ball supplied from the upper plate 21 by the player turning the operation unit 33. Further, when the player operates the select switch 22, the contents of the effect of the variable display game on the display device 61 (see FIG. 3) provided in the center of the game board can be selected. Furthermore, when the player operates the operation switch 23, in the variable display game executed on the display device 61, an effect in which the player's operation is intervened can be performed.

A ball lending button 26 that is operated when a player borrows a game medium and a discharge button 27 that is operated to discharge a prepaid card from the card unit 70 are provided on the upper right portion of the upper plate 21. Between these buttons 26 and 27, a balance display unit 28 for displaying the balance of the prepaid card is provided.
A card insertion slot 71 into which a card such as a prepaid card or a membership card can be inserted is provided at the lower part of the card unit 70 disposed adjacent to the left side of the gaming machine 10. A card such as a prepaid card or a member card stores identification information of the card, member information of the owner (player) of the card, a balance, and the like.

When a card such as a prepaid card or a membership card is inserted into the card insertion slot 71, information stored in the card is read out by an internal card reader / writer. Of the read information, the card balance is displayed on the balance display section 28 of the gaming machine 10 and the balance display section 72 provided near the center of the card unit 70.
Above the balance display part 72, a bill insertion slot 73 into which a bill can be inserted is provided, and the amount of the bill inserted into the bill insertion slot 73 is stored as a balance on the card. An operation display unit 74 is provided above the bill insertion slot 73. The operation display unit 74 changes the emission color corresponding to the operation state of the card unit 70.

Next, the configuration of the back side of the gaming machine 10 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine 10 of the present embodiment.
A frame-like back mechanism board 40 having a substantially square opening at the center is attached to the back side of the gaming machine 10, specifically, the back of the front frame 12. A ball storage unit 41 that stores game balls replenished from a replenishment device (not shown) provided in the island facility and that causes the stored game balls to flow down is disposed above the back mechanism board 40. On the side of the back mechanism board 40 (the right side in FIG. 2), the ball discharge unit 42 that pays out the game balls flowing down from the ball storage unit 41 to the upper plate 21 and the lower plate 32 disposed in front of the game machine. Is arranged.

In the central portion of the back mechanism board 40, there are a game control device 100 that controls the game in an integrated manner, and an effect control device 150 that controls the effect of the variable display game based on the effect control command transmitted from the game control device 100. The game control device 100 is provided with an inspection device connection terminal 107 connected to the inspection device.
Under the back mechanism board 40, a payout control device 200 for controlling the operation of the ball discharge unit 42 based on data transmitted from the game control device 100, and a power supply device 160 are disposed. The payout control device 200 is provided with an inspection device connection terminal 217 connected to the inspection device and an error number display 43 that displays the type of error that has occurred in the payout control device 200 in numbers. A card unit connection terminal 170 for connecting the gaming machine 10 to the card unit 70 is provided on the right side of the power supply device 160.

Next, the game board 50 will be described with reference to FIG. FIG. 3 is a front view of the game board 50 of the present embodiment.
On the surface of the game board 50, a substantially circular game area 51 surrounded by guide rails 53 is formed. The game area 51 is constituted by resin side cases 52 and guide rails 53 provided at the four corners of the game board 50.
In the game area 51, a center case 60 provided with a display device 61 is disposed substantially at the center. The display device 61 is attached to a recess provided in the center case 60 at a position deeper than the front surface of the center case 60. That is, the center case 60 surrounds the display area of the display device 61 and is formed so as to protrude forward from the display surface of the display device 61.

The display device 61 is configured by a device having a display screen such as an LCD (Liquid Crystal Display) or a CRT (CRT). In the area (display area) where the image of the display screen can be displayed, a plurality of pieces of identification information (special symbols) and a character that produces a special figure variation display game are displayed. Although there is only one display screen, it can be considered that there are a plurality of (for example, three) variable display areas. In each variable display area, special symbols assigned as identification information are variablely displayed (variably displayed). A special figure variation display game is played. In addition, an image (for example, jackpot display, fanfare display, ending display, etc.) based on the progress of the game is displayed on the display screen.
A normal symbol starting gate 54 is provided on the left side of the center case 60. Three general winning openings 55 are arranged on the lower left side of the center case 60, and one general winning opening 55 is arranged on the lower right side of the center case 60. In addition, a start winning port 56 is provided below the center case 60, and a start winning device 57 including an ordinary variable winning device 57a that can be opened and closed is disposed immediately below the start winning port 56.

  Further, below the start winning device 57, a special variable winning device (large winning port) 58 that can be converted into a state in which a game ball is not accepted and a state in which it is easy to accept depending on the result of the variable display game of the display device 61 is disposed. The Also, on the upper right of the game board 50, a general map display 62 composed of a segment type display, a special map display 63, a light emission for displaying the number of unprocessed special map display games and the general map display game. A display unit 64 is provided. The universal symbol display 62 displays a universal symbol fluctuation display game that is performed when the game ball passes the normal symbol start gate 54. The special figure display 63 displays a special figure fluctuation display game that is performed when a game ball wins the start winning opening 56 or the start winning apparatus 57.

  In the gaming machine 10 of the present embodiment, a game is played by launching a game ball (pachinko ball) from a launching device (not shown) toward the game area 51. The launched game balls flow down the game area 51 while changing the rolling direction by means of direction changing members such as obstacle nails and windmills arranged in various places in the game area 51, and the normal symbol start gate 54 and the general winning opening 55 The winning prize opening 56, the starting prize winning device 57 or the special variable prize winning device 58 is won, or it flows into the out port 59 provided at the bottom of the gaming area 51 and is discharged from the gaming area.

  The start winning device 57 includes a state in which a game ball is likely to win a prize and a state in which a game ball is difficult to win by opening and closing the normal variation winning device 57a. Normally, the normal variation winning device 57a is in a closed state, and the starting winning device 57 is in a state where the game ball is not won or is difficult to win. When the game ball passes through the normal symbol starting gate 54, the normal symbol display game is executed on the general symbol display device 62. When the hit state occurs as a result of the general symbol variable display game, the normal variable prize winning device 57a is opened. It is converted into a state, and the start winning device 57 is in a state where the game ball is easy to win.

  The winning of a game ball in the general winning opening 55 is detected by general winning opening switches 55a to 55n (see FIG. 4) provided in the general winning opening 55. The winning of the game ball to the start winning opening 56 is detected by the special figure start switch 56a (see FIG. 4), and the winning of the game ball to the start winning apparatus 57 is detected by the special figure start switch 57b. The special symbol random number counter value extracted by the passing timing of the game ball is stored as a special symbol winning memory in the special symbol storage area (a part of the RAM) in the game control device 100 for a predetermined number of times (for example, up to four times). Remembered to the limit. The stored number of special symbol winning memories is displayed on the special symbol winning memory number display section (composite storage display section) of the light emitting display unit 64 and the display device 61. Based on the special symbol winning or the memory thereof, the game control device 100 performs a special diagram variation display game on the special diagram display 63 and also performs a decoration special diagram variation display game as an effect display on the display device 61.

When a game ball is won at the start winning opening 56 or the start winning device 57, the special symbol (identification information) composed of the numbers and the like is displayed on the left (first special symbol) and right (second) on the display device 61. Fluctuation display is started in the order of special symbol) and medium (third special symbol), and an image relating to the special symbol variation display game is displayed. That is, in the display device 61, a special symbol variation display game corresponding to the number of stored special symbol winning memories is performed, and various displays are produced to improve interest.
As a result of the special figure variation display game, when the winning to the starting winning opening 56 or the starting winning device 57 is made at a predetermined timing (specifically, when the winning random number at the time of winning detection is a winning value). A specific result mode (special result mode) is derived from the display symbol, and a big hit state is obtained. Specifically, the special symbol winning memory display unit of the display device 61 stops at a single-digit special symbol that is a winning symbol, and the display device 61 stops when three special symbols are aligned (big hit symbol). To do. In response to this, the special variable prize winning device 58 is easy to accept a game ball from a closed state in which a game ball is not accepted for a predetermined time by driving a built-in large prize opening solenoid 58b (see FIG. 4). It is converted to the open state, and a privilege that the player can acquire many prize balls is given.

  The winning of a game ball to the special variation winning device 58 is detected by a count switch 58a (see FIG. 4). The passing of the game ball to the normal symbol start gate 54 is detected by a normal diagram start switch 54a (see FIG. 4). The normal symbol random number counter value extracted by the passing timing of the game ball is stored in a normal symbol memory area (a part of the RAM) in the game control device 100 as a normal symbol winning memory a predetermined number of times (for example, up to four times). Remembered to the limit. Then, the number of memorized memorable winnings is displayed on the memorized memorized memorized number display unit (not shown) of the display device 61.

When there is a general-purpose winning memory, the game control device 100 starts a general-game variable display game on the general-purpose winning memory display section based on the general-purpose winning memory. That is, when the passage to the normal symbol start gate 54 is detected at a predetermined timing (specifically, when the common random number counter value at the time of passage detection is a winning value), the common symbol winning memory number display is performed. The normal symbol displayed on the part stops in the hit state and enters the hit state. At this time, the normal variation winning device 57a is converted so as to be opened for a predetermined time by driving the built-in power solenoid 57c (see FIG. 4), so that the game ball starting winning device 57 is supplied to the starting winning device 57. Winning is allowed. The opening time of the normal variation winning device 57a is, for example, 2.9 seconds in the probability variation state and the variation time shortened state, and 0.5 seconds in the normal gaming state so that the opening mode changes according to the gaming state. Can be controlled.
In this way, when a game ball wins the general winning opening 55, the start winning opening 56, 57, or the special variable winning device 58, the number of winning balls corresponding to the type of the winning winning port is controlled by the payout control device 200. From the dispensing unit 42 to the upper plate 21 or the lower plate 32 of the front frame 12.

FIG. 4 is a block diagram of the control system of the gaming device according to the present embodiment.
The gaming machine 10 includes a gaming control device 100 that controls the entire gaming machine. The gaming control device 100 includes a gaming microcomputer 110, an input I / F (Interface) 105, an output I / F (Interface) 106, and an inspection device. The game microcomputer 110 includes a connection terminal 107, and includes a CPU 111, a ROM (Read Only Memory) 112, and a RAM (Random Access Memory) 113.

  The CPU 111 is a main control device that controls the game in an integrated manner, and decodes (decodes) the instruction code of the program to generate a control signal inside the game control device 100, and an arithmetic operation that performs data operations. A logic unit, an accumulator that temporarily holds data to be operated are provided, and game control is executed according to a control program. The ROM 112 stores invariant information (program, fixed data, etc.) for game control. The RAM 113 is used as a work area that provides a work area for the CPU during game control.

The game control device 100 is provided with an inspection device connection terminal 107, and an identification number set in the game microcomputer (game microcomputer) 110 can be output from the inspection device connection terminal 107. Accordingly, when the inspection device is connected to the inspection device connection terminal 107, the inspection device can identify the gaming machine 10.
Further, an external information terminal 108 is connected to the game control device 100 via an output I / F 106, and information related to the gaming machine 10, a chip identification code (chip ID) of the gaming microcomputer 110, and the like are stored in the external information terminal 108. Accordingly, the information is output to a management device 300 such as an information collection device installed in a game store or a hall computer for internal management of the game hall.
Information from the payout control device 200 can also be output from the external information terminal 108 to the management device 300. The information from the gaming microcomputer 110 may be directly output to the management device 300 without going through the external information terminal 108.

  The game control device 100 includes various detection devices (special drawing start switches 56a and 57b, a general drawing start switch 54a, a count switch 58a, general winning opening switches 55a to 55n, an overflow switch 32a, a frame opening switch 12a, and a ball break switch 41a. ) Is input. The overflow switch 32a detects that a predetermined number or more of game balls are stored in the lower plate 32. The frame opening switch 12a detects that the front frame 12 is opened. The ball break switch 41a is disposed in the ball storage unit 41 and detects that the number of game balls stored in the ball storage unit 41 is equal to or less than a predetermined number.

Detection signals from the various detection devices input to the game control device 100 are input to the CPU 111 via the input I / F 105, and the CPU 111 performs various processes such as a big hit lottery based on these signals. In addition, the CPU 111, via the output I / F 106, emits a light emitting display unit 64, a general-purpose display 62, a special-purpose display 63, a general-purpose SOL (solenoid) 57c, a special winning opening SOL (solenoid) 58b, a payout control device. A command signal is transmitted to 200 and the effect control device 150 to control the game in an integrated manner.
Furthermore, the game control device 100 transmits a payout command signal to the payout control device 200 that controls the payout motor 42a of the ball payout unit 42, and also includes a change start command, a customer waiting demo command, a fanfare command, A probability information command, an error designation command, and the like are transmitted as an effect control command signal.

Next, the payout control device 200 and the effect control device 150 will be described. The effect control device 150 controls the error notification LED 18, the speaker 19, and the display device 61 based on various signals input from the game control device 100.
The payout control device 200 performs control for driving out the payout motor 42a of the payout unit 42 in accordance with the prize ball payout command signal from the game control device 100 so as to pay out the prize ball. In addition, the payout control device 200 drives the payout motor 42a of the payout unit 42 in accordance with the payout command signal transmitted from the game control device 100 based on the loan request signal from the card unit 70, and pays out the rental money. Control for.

The payout control device 200 includes a gaming microcomputer 210, an input I / F (Interface) 215, an output I / F (Interface) 216, and an inspection device connection terminal 217. The gaming microcomputer 210 includes a CPU 211, a ROM 212, and a RAM 213. Is provided.
The CPU 211 is a control device that comprehensively controls payout, and controls payout control. The ROM 212 stores invariant information (program, data, etc.) for payout control. The RAM 213 is used as a work area during payout control.
The CPU 211 receives signals from the payout ball detection switch 42b in the payout unit 42, the overflow switch 32a, the frame opening switch 12a as the fraud detection switch, the ball break switch 41a, and the error release switch 44 via the input I / F 215. Is done. Further, the CPU 211 outputs drive signals for the payout motor 42 a, the firing control device 180, the error number display 43 and the like in the payout unit 42 via the output I / F 216.

  The error release switch 44 is operated by the store clerk of the amusement store to cancel the error state when the cause of the error generated by the store clerk of the amusement store is resolved when an error occurs in the payout control device 200. It is a switch. The launch control device 180 controls a launch device for launching a game ball into the game area 51. The error number display 43 is disposed on the back side of the payout control device 200 and displays the type of error that has occurred in the payout control device 200 so as to be specified.

  Note that the game control device 100, the effect control device 150, and the payout control device 200 are connected to the power supply device 160. The power supply device 160 includes a backup power supply 161 and a RAM clear switch 162. The backup power supply 161 supplies power to the game control device 100, the effect control device 150, and the payout control device 200 even in the event of a power failure (it may not be supplied to the effect control device 150). The RAM clear switch 162 is a switch that forcibly initializes information stored in the RAM 113 in the game control device 100 and the RAM 213 in the payout control device 200.

  Further, when the ball lending button 26 provided on the gaming machine 10 is operated, the card unit 70 obtains the valuable value for the gaming ball lent from the valuable value stored in the card such as the prepaid card or the membership card. The value of the value obtained by the subtraction is displayed on the balance display unit 28 of the gaming machine 10. Further, when a discharge button 27 provided in the gaming machine 10 is operated, the card unit 70 is configured to discharge the card inserted in the card insertion slot 71.

FIG. 5 is a block diagram showing a more specific configuration of the gaming microcomputer (game arithmetic processing device) 110 that constitutes the gaming control device 100. Conventional gaming microcomputers generally have a random number generation circuit configured and connected as an external circuit, whereas the gaming microcomputer of this embodiment incorporates a random number generation circuit.
The gaming microcomputer 110 of this embodiment is divided into a game control block 110A for performing game control and a management block 110B for managing information. One element constituting each circuit block described below is provided on a semiconductor substrate. It is formed as a semiconductor integrated circuit (amusement chip).

  The game control block 110A includes a CPU core 111, a program ROM 112, a work RAM 113, an external bus interface 114, a bus switching circuit 115, a decryption / ROM writing circuit 116, a mirrored RAM 117, an interrupt controller 118 as an interrupt control circuit, and a boot block 119. , Reset interrupt control circuit 120, address decoder 121, output control circuit 122, clock generator 123, random number generation circuit 124 and HW parameter ROM 125, chip ID register 127 holding chip identification code (chip ID), external device The functional block such as the serial transmission / reception circuit 128 for transmitting / receiving data by the serial communication method is included. These functional blocks and the management block 110B are connected by a CPU bus 126.

  The CPU core 111 includes various registers such as an accumulator, an arithmetic / logic unit (ALU), an instruction register (IR), a decoder, a program counter (PC), a stack pointer (SP), a data bus connecting them, an address bus, and various controls. For example, a Z80 architecture. The CPU core 111 implements various functions necessary for controlling the gaming machine 10 by software by loading and executing the game control program stored in the program ROM 112.

  The work RAM 113 corresponds to the main memory of the CPU core 111, and is composed of a high-speed semiconductor device such as an S-RAM, for example. The work RAM 113 is used as a work area (work area) when executing processing based on the game program in the game block 110A. The work RAM 113 can be provided with a battery backup function using a dedicated terminal assigned to one of the terminal groups of the gaming microcomputer 110, and the stored contents even after the gaming machine 10 is turned off. Hold. In addition, the work RAM 113 is controlled so that the chip enable is prohibited and permitted by a protection circuit (not shown), and is read and written while the chip enable is prohibited (when power is not supplied to the gaming machine 10). None of this can be done.

  The external bus interface 114 is a circuit for performing input / output control of various signals such as a memory request signal, an input / output request signal, a memory write signal, a memory read signal, and a mode signal with an external device. The bus switching circuit 115 is a circuit that performs bus switching to enable input / output of address signals and data signals between an external bus (not shown) and the CPU bus 126 in the chip. For example, when the memory write signal WR is activated while the memory request signal MREQ or the input / output request signal IORQ is activated, an external data signal can be written to a predetermined external I / O, and the memory read signal RD is activated. Then, an external data signal can be taken in from a predetermined external I / O.

  The decryption / ROM writing circuit 116 decrypts data sent after being encrypted, generates a voltage necessary for writing to the electrically programmable program ROM 112 and the HW parameter ROM 125, and controls timing. Circuit. For example, when an external data signal is given from the outside while sequentially incrementing the external address signal while the mode signal MODE is active, it becomes a writing mode to the program ROM 112 and is made by a game machine manufacturer or a third party organization. A game program can be written. However, if the write end code is recorded in a predetermined area of the HW parameter ROM 125 described later after the game program has been written to the program ROM 112, the game program cannot be written to the program ROM 112 thereafter.

The mirrored RAM 117 stores information obtained by copying information stored in the user work area when the clock falls (if the CPU core is Z80, processing is executed when the clock rises, and thus the mirrored RAM 117 can move in synchronization. Not so).
The interrupt control circuit 118 is a circuit that makes an interrupt request to the CPU core 111 in response to an interrupt request signal from the outside, and sends a control signal to a circuit (for example, a random number generation circuit) inside the chip. is there. The reset interrupt control circuit 120 resets the CPU core 111 in response to a reset signal input from the outside, and generates a signal for setting various resources inside the gaming microcomputer 110 to an initial state. Circuit.

The boot block 119 includes a ROM for storing a boot program. When the system of the gaming microcomputer 110 is reset, the boot program starts up and performs a predetermined simple check. If the boot ROM is normal, the protection setting process is executed, and then the process is transferred to a predetermined address of the game program (a predetermined address in the address space of the CPU 111 (generally, the first address 0000h in the address space)).
The address decoder 121 decodes the address information of the CPU bus 126 and controls the output control circuit 122 according to the decoding result. The clock generator 123 generates an operation clock, a timer interrupt clock, a counter update clock, etc. supplied to each block in the gaming microcomputer 110 including the CPU core 111 based on the system clock MCLK supplied from the outside. Generate. In addition to the system clock MCLK, a random number update clock EXCLK may be received.

  The random number generation circuit 124 is a circuit for generating a random number used for determination of a big hit. The conventional gaming microcomputer has a built-in one that is configured as an external circuit and adds a specific function. It is a thing. In the present embodiment, the random number generation circuit 124 includes a first random number generation circuit that generates a jackpot symbol random number for determining a stop symbol when the result of the special symbol variation display game is a jackpot, and a special symbol variation. And a second random number generation circuit for generating a big hit random number for determining whether or not the result of the display game is a big hit. These random number generation circuits will be described in detail later with reference to FIGS.

The HW parameter ROM 125 is used to record the write end code for prohibiting program writing to the program ROM 112 and to set parameters specific to the user system (hardware). It is constituted by a memory (for example, EPROM, EEPROM, flash memory, etc.) that can be written to.
The chip ID register 127 holds a chip identification code (chip ID) read from an ID property memory 134 in a management block 110B described later. The serial transmission / reception circuit 129 has a function of transmitting / receiving data to / from an external device by a serial method. The chip ID held in the chip ID register 127 is also transmitted to the output interface 106 and the external device by the serial transmission / reception circuit 127. It is transmitted to the management apparatus 300 via the information terminal.

  The management block 110B includes a management program ROM 131, a management work RAM 132, a bus monitor circuit 133, an ID property memory 134, a management control circuit 135, an external communication control circuit 136, and a local bus 137 that connects these circuit blocks. In addition, the bus monitor circuit 133 is connected to both the local bus 137 and the CPU bus 126 of the game control block 110A, so that data can be transmitted to and received from the CPU core 111 via the CPU bus 126. ing.

  The management work RAM 132 is used as a storage area for temporarily storing information of the game control block 110A read via the bus monitor circuit 133. The bus monitor circuit 133 monitors the state of the CPU bus 126. When the CPU bus 126 is not used by the CPU core 111, the program ROM 112 and the user work of the game control block 110A are connected via the CPU bus 126 as necessary. The RAM 113 and the like are accessed, and necessary data (game program, contents of the user work RAM 113, etc.) are taken into the management block 113B.

  In the ID property memory 134, an identification code (a management unique ID and a chip ID) unique to the chip used for identification of the gaming microcomputer 110 and determination of legitimacy is written. The chip ID is a code that can be read via the buses 126 and 137 by the user program. The unique ID cannot be accessed by a user program and can be directly read by an inspection device or a management device (hall computer) outside the gaming machine via the bus 137 and the external communication control circuit 136. Thereby, the unique ID of the gaming machine can be monitored by the inspection device or the management device. Specifically, if the unique ID set in advance in the gaming machine does not match the unique ID read by the management device, the management device disables input / output of various signals. Then, it becomes impossible to input / output signals between the various devices connected to the game control device 100 (for example, the big winning opening solenoid 58b and the normal variation winning opening solenoid 57c) and the subordinate control device and the CPU core 111. However, it becomes clear that an abnormality has occurred in the gaming machine due to the fact that the player cannot operate or the decorative lamp does not light.

  In addition to the unique ID, information such as a game type code, a rank code, a manufacturer number, a model code, and an inspection number is written in the ID property memory 134. The game type code is information for distinguishing pachinko gaming machines, throttle machines, and the like, and is represented by, for example, “P” for pachinko gaming machines and “G” for throttle machines. The rank code is a model rank code of the gaming machine 1 (a code for distinguishing between the first type and the second type), a manufacturer number, or a manufacturer ID (or manufacturer code) for identifying the manufacturer of the gaming machine 1. is there. The model code is a product code of the gaming machine 1 set by the manufacturer. The inspection number (or verification code) is a number given to the gaming machine 1 that has passed the inspection by the third party organization.

  Further, the ID property memory 134 includes a ROM and a RAM, and the contents of the ROM are copied to the RAM. That is, the unique ID, game type code, rank code, manufacturer number, model code, and inspection number are stored in the ROM, and are copied to the RAM. The copy timing is performed when the gaming machine is turned on or when the gaming microcomputer 110 is reset, for example, in an initialization process executed by the management block 110B immediately after the system reset.

  The control circuit 135 controls the operation of the management block 110B and has a buffer memory. For example, the control circuit 135 monitors the operation of the CPU core 11 via the bus monitor circuit 133, and copies the contents stored in the user work RAM 113 of the game block 110A to the mirrored RAM 117 during non-operation. Further, the contents of the ID property memory 134 of the management block 110B are transferred to the outside in response to a request from the inspection apparatus, and the program in the user program ROM 112 is sent to the outside via the bus monitor circuit 133 in response to a program request. Or transfer. The buffer memory is used for timing adjustment at the time of transfer.

  The external communication control circuit 136 communicates with an information collection terminal device and an ID inspection device provided outside the gaming machine. For example, when an information collection terminal device is connected, in response to a request from the information collection terminal device, the storage contents of the management work RAM 132 and ID property memory 134 are transferred to the requesting information collection terminal device. When the ID inspection device is connected, at least information on the unique ID stored in the ID property memory 134 is transferred to the requesting ID inspection device in response to a request from the ID inspection device.

Next, the random number generation circuit 124 in the gaming microcomputer 110 according to the embodiment of the present invention will be described in detail. As described above, the random number generation circuit 124 includes the first random number generation circuit 124A that generates a jackpot symbol random number and the second random number generation circuit 124B that generates the jackpot random number.
FIG. 6 is a block diagram of the first random number generation circuit 124A. The first random number generation circuit (first random number generation means) 124A includes a random number update controller 608a, a first random number register group 608b, a second random number register group 608c, a third random number register group 608d, and a fourth random number register. A group 608e is formed.

The random number update controller (update control means) 608a performs arithmetic processing for generating random numbers used in the game control execution process, and generates a uniform random number using a counter method, a generator polynomial, or the like. A random number is generated using (for example, an M-sequence method or a congruence method). Further, the random number update controller 608a has an interrupt signal from the reset interrupt control circuit 120, a signal (CTC2, a CTC (Counter / Timer Circuit) circuit 232 as a signal generating means constituting the clock generator 123, and a frequency dividing circuit 231). φ
1) can be input.

  Although not particularly limited, the first random number generation circuit 124A according to the present embodiment receives the signal CTC2 from the CTC circuit 232 in the clock generator 123 and the random number update trigger register ( 608b3) is configured so that the random number can be updated. Further, as will be described later, the first random number generation circuit 124A can select either a counter method, that is, a mode for generating a random number by updating the counter value by −1 or a mode for generating an M-sequence random number. It is configured.

  The first random number register group 608b includes a CTC update permission register 608b1, a tap setting register 608b2, a random number update trigger register 608b3, a maximum value setting register (range information storage means) 608b4, a start value setting register 608b5, a round completion notification register 608b6, A random number counter (random number storage means) 608b7, a work area (update means) 608b8, a random number update notification register (update information storage means) 608b9, an update error notification register 608b10, a random number circuit reset register 608b11, and a random number counter 608b7 A circulation counter 608b12 that counts the number of times, a number counter 608b13 that counts the number of times the divided signal φ1 is input, and the like.

  Note that the second random number register group 608c, the third random number register group 608d, and the fourth random number register group 608e have the same configuration as the first random number register group 608b, and thus description thereof is omitted. By providing multiple random number registers, the jackpot symbol random number that determines the jackpot stop symbol, the variation pattern random number that determines the variation pattern in the special diagram variation display game, and whether or not to generate a hit in the normal variation display game It is possible to generate a plurality of random numbers used in the game control in parallel, such as a hit random number.

The CTC update permission register 608b1 sets whether or not the automatic update of the random number counter 608b7 is permitted / not permitted. If set to “permitted”, the random number counter is triggered by the signal CTC2 from the CTC circuit 232. 608b7 is updated.
The tap setting register 608b2 operates the random number counter 608b7 in the “counter mode” and is “0” when the power is turned on. At this time, the random number counter 608b7 does not operate. . Then, when a value other than “0” is written in the tap setting register 608b2, the random number counter 608b7 operates. In the case of the “random number mode”, the type of M-sequence recurrence formula is determined by the value written in the tap setting register 608 b 2. Therefore, the tap setting register 608b2 functions as activation information storage means for storing activation information indicating whether or not to start updating the random number value.

  The random number update trigger register 608b3 is a register that can be directly written from the CPU core 111. When the CPU core 111 writes a predetermined value by, for example, interrupt processing, the random number update controller 608a recognizes it and the counter value of the random number counter 608b7 Is configured to update. At this time, the random number counter 608b7 is updated regardless of whether the setting of the CTC update permission register 608b1 is “permitted” / “not permitted”. Accordingly, the random number update trigger register 608b3 functions as an update instruction storage unit that instructs to update the random number value.

  The maximum value setting register 608b4 sets the maximum value and mode of the random number counter 608b7. The maximum value is set to a value between 8 and 4095. The mode is set to either “random number mode” or “counter mode”. When the set maximum value is N, the random number counter 608b7 is updated in the range of 1 to N in the “random number mode”, and the random number counter 608b7 is updated in the range of 0 to N in the “counter mode”. Therefore, the maximum value setting register 608b4 functions as range information storage means for storing the update range information of the first random number generation circuit 124A.

  The start value setting register 608b5 sets the update start value (start value) of the random number counter 608b7. When the random number counter 608b7 makes a predetermined cycle once, this random number update controller 608a sets this start value in the random number counter 608b7. Specifically, for example, when a value larger than the maximum value N set in the maximum value setting register 608b4 is set as the start value S, the maximum value N when the random number counter 608b7 makes one round of a predetermined cycle. Is divided by the start value S, and the remainder value is set in the random number counter 608b7. Accordingly, the start value setting register 608b5 functions as a start value storage unit that stores the start value of the random number value, and the random number update controller 608a functions as a start value setting unit.

  The one-round completion notification register 608b6 notifies that the random number counter 608b7 has made a predetermined cycle once. When the CPU core 111 sets a start value in the start value setting register 608b5, it is set to ON and set to ON. After that, when the random number counter 608b7 makes a predetermined cycle once, it is set to OFF. Then, the circulation counter 608b12 counts the number of circulations of the random number counter 608b7.

  The random number counter 608b7 is composed of a 12th-order (12-bit) random number sequence, and until a predetermined value is written to the tap setting register 608b2, data can be set and the start value when the random number is turned on can be changed. it can. Therefore, the range of the random number counter 608b7 can take a value between 1 and 4095 in the “random number mode”, and can take a value between 0 and 4095 in the “counter mode”. Become. Further, in the “random number mode”, the same random number value is not generated until the counter value makes one round.

  The work area 608b8 functions as an update buffer for the random number counter 608b7. The random number is updated in the work area 608b8, and the updated value is stored in the random number counter 608b7. Accordingly, the work area 608b8 functions as a random number update unit, and the random number counter 608b7 functions as a random value storage unit. The work area 608b8 is a register that cannot be read from the CPU, thereby preventing an indeterminate value being updated from being erroneously taken into the CPU. When a power failure occurs, the value immediately before the power failure is held in the work area 608b8.

The value in the work area 608b8 is continuously updated until it reaches a value in the range indicated by the maximum value setting register 608b4 when the update of the random number is instructed by a signal from the CTC circuit 232 or writing in the random number update trigger register 608b3. While the value in the work area 608b8 is being updated, “0” is set in the random number counter 608b7 regardless of whether it is in the “random number mode” or the “counter mode”. Therefore, in the “random number mode”, if “0” that does not belong to the numerical value (1 to N) within the update range is set in the random number counter 608b7, it indicates that the random number counter 608b7 is being updated. In the “counter mode”, the count value is updated by the down-count method in the work area 608b8. The count value may be updated by an up-count method.

  The random number updating notification register 608b9 notifies that the random number is being updated, and is set to ON while the random number counter 608b7 is being updated by the CTC circuit 232 or the random number update trigger register 608b3 as a signal generating means. If it is not being updated, it is set to off. Therefore, the random number updating notification register 608b9 functions as an updating information storage unit that stores updating information indicating whether or not the random number value is being updated.

  In the update error notification register 608b10, when the value of the random number counter 608b7 is not updated, a value indicating an error is set by the random number update controller 608a, and when the CPU 111 reads the value of this register, a random number update error occurs. It is possible to know whether or not. Therefore, the update error notification register 608 b 10 functions as an abnormality information storage unit of the random number generation circuit 608. An update error, that is, whether or not the value of the work area 608b8 has been updated can be determined by the random number update controller 608a.

  The random number circuit reset register 608b11 is for resetting the random number generation circuit 608 from the outside when a random number update error occurs. When the CPU 111 writes a predetermined value in this register, the random number update controller 608a receives a reset command. It is determined that the circuit is in the reset state. The number counter 608b13 counts the number of times the divided signal φ1 is input.

The clock generator 123 includes a CTC circuit 232 and a frequency dividing circuit 231. The frequency dividing circuit 231 divides the original clock signal MCLK input from the outside (oscillation circuit), and the period of the original clock signal is 2 A clock signal φ 1 having a double cycle is generated and supplied to the random number controller 608 a as an operation clock, and a clock signal φ 2 having a longer cycle than the original clock signal MCLK is generated and input to the CTC circuit 232.
Based on the clock signal φ2 from the frequency dividing circuit 231, the CTC circuit 232 triggers a timer interrupt signal (CTC1) having a predetermined period (for example, 2 milliseconds) to the CPU 111 and a random number update trigger to be supplied to the random number controller 608a. A signal CTC2 to be applied is generated. Accordingly, the CTC circuit 232 functions as a signal generating means for giving a trigger for updating the random number. The CTC circuit 232 is configured so that the period of the generated signals CTC1 and CTC2 can be set freely.

Next, a control procedure in the first random number generation circuit 124A by the random number update controller 608a will be described.
FIG. 7 shows a flowchart of the first half of processing by the random number update controller, and FIG. 8 shows a flowchart of the second half of processing by the random number update controller.

  First, the random number update controller 608a initializes values stored in other storage areas and registers except for the values stored in the work area 608b8 based on the reset interrupt signal from the reset interrupt control circuit 120 ( Step S101). At this time, the value of the circulation counter 608b12 is set to “0”. Next, the value of the random number counter stored in the work area 608b8 is taken into the random number counter 608b7 (step S102). Subsequently, the change of the random number counter 608b7 is permitted (step S103), and the setting of the tap setting register 608b2 is awaited (step S104).

  Thereafter, the random number update controller 608a prohibits the change of the random number counter 608b7 (step S105), stores the value of the random number counter 608b7 at this time in the work area 608b8 (step S106), and sets the number counter 608b13 to “0”. (Step S107). Until the change of the random number counter 608b7 is prohibited, an arbitrary value can be written to the random number counter 608b7 by the CPU core 111 (FIG. 5).

  Next, it is determined whether or not a CTC signal (CTC2) is generated (detected) by the CTC circuit 232 (step S108). In the determination of whether or not the CTC signal is generated by the CTC circuit 232 (step S108), if the CTC signal is generated by the CTC circuit 232 (Yes), it is determined whether or not the CTC use mode is set. It is determined whether or not the permission register 608b1 is set to “permitted” (step S109).

  In the determination of whether or not the mode is the CTC use mode (step S109), if the mode is the CTC use mode (Yes), the process proceeds to step S111. On the other hand, if it is not in the CTC use mode in the determination of whether or not it is in the CTC use mode (step S109), that is, if the CTC update permission register 608b1 is set to “impossible” (No), the random number update trigger register 608b3 It is determined whether or not a specified value is written in (Step S110).

  In the determination of whether or not the CTC signal is generated by the CTC circuit 232 (step S108), if the CTC signal is not generated by the CTC circuit 232 (No), the specified value is written in the random number update trigger register 608b3. It is determined whether or not (step S110). In this determination (step S110), when the specified value is written in the random number update trigger register 608b3 (Yes), the process proceeds to step S111. On the other hand, if it is determined in step S110 that the specified value is not written in the random number update trigger register 608b3 (No), the process returns to step S108.

  Next, the random number updating notification register 608b9 is set to ON (step S111), the value of the random number counter 608b7 is set to “0” (step S112), and the frequency dividing signal φ1 is input from the frequency dividing circuit 231. (Step S113). Then, it is determined whether the mode set in the maximum value setting register 608b4 is the “random number mode” or the “counter mode” (step S114). In this determination (step S114), when the mode set in the maximum value setting register 608b4 is “counter mode”, it is determined whether or not the value of the work area 608b8 is larger than “0” (step S115).

  In the determination of whether or not the value of the work area 608b8 is greater than “0” (step S115), when the value of the work area 608b8 is “0” (No), the value of the work area 608b8 is set to the maximum value. (Step S116). On the other hand, if it is determined that the value of the work area 608b8 is greater than “0” (step S115) and the value of the work area 608b8 is greater than “0” (Yes), the value of the work area 608b8 is determined. Is decremented by 1 (step S117).

  Next, the value of the circulation counter 608b12 is incremented by 1 (step S118), and it is determined whether or not the value of the circulation counter is greater than or equal to the maximum value of the random number counter (step S119). If the value of the circulation counter is equal to or greater than the value added to the maximum value of the random number counter 608b7 (step S119; Yes), the value of the circulation counter is set to “0” (step S120). On the other hand, in the determination of whether or not the value of the circulation counter is equal to or larger than the value added to the maximum value of the random number counter 608b7 (step S119), the value of the circulation counter is not equal to or larger than the value added to the maximum value of the random number counter 608b7. In step S119; No, the process proceeds to step S134.

  Next, the start value setting register 608b5 acquires the start value for random number update and corrects it to be equal to or less than the maximum value (step S121). Specifically, at this time, if the acquired start value is larger than the maximum value, correction is performed with the remainder value when the maximum value is divided by the start value as the start value. Then, the start value is taken into the work area 608b8 (step S122), and the one-round completion notification register 608b6 is set to ON (step S123).

  Next, it is determined whether or not the value of the number counter 608b13 has reached a specified value (step S134). Here, the specified value (specified update time) is, for example, the specified value is “2” in the “counter mode”, the specified value is in the “random number mode”, and the maximum value is “17” or more. In the case of “20” and “random number mode” and the maximum value is “16” or less, the specified value is set to “200”. Data of these specified values (specified update times) is stored in advance in the ROM 112 of the gaming microcomputer 110.

  Therefore, when updating of the random number counter 608b7 is started, the random number is not updated every time the divided signal is input from the frequency dividing circuit 231 to the random number update controller 608a, but until the input divided signal is detected a predetermined number of times. Will not update the random number counter 608b7, and the number of detections will be fixed to a certain number. In other words, in the “counter mode”, in order to update the random number counter 608b7, it takes time for the frequency-divided signal to be generated twice (specified update time). In the case of the “random number mode”, when the maximum value of the random number counter is “17” or more, it takes time to generate the divided signal 20 times in order to update the random number counter 608b7. In the case of the “random number mode”, when the maximum value of the random number counter is “16” or less, it takes time to generate the divided signal 200 times in order to update the random number counter 608b7.

  In the determination of whether or not the value of the number counter 608b13 has reached the specified value (step S134), if the value of the number counter has not reached the specified value (No), the process waits for a frequency division signal (step s137). The counter value is incremented by 1 (step S138), and the process returns to step S134. On the other hand, if it is determined whether or not the value of the number counter has reached the specified value (step S134), if the value of the number counter reaches the specified value (Yes), the value of the work area 608b8 is set in the random number counter 608b7. (Step S135), the random number updating notification register 608b9 is set to OFF (Step S136), and the process returns to Step S107.

  Further, in determining whether the mode set in the maximum value setting register 608b4 is the “random number mode” or the “counter mode” (step S114), the mode set in the maximum value setting register 608b4 is the “random number mode”. In this case, the process proceeds to step S124. Then, the M-sequence random number is updated in the work area 608b8 (step S124), and it is determined whether or not the value based on the M-sequence random number in the work area 608b8 is larger than the maximum value (step S125).

  In this determination (step S125), when the value based on the M-sequence random number in the work area 608b8 is larger than the maximum value (Yes), it is determined whether or not a frequency-divided signal is detected (step S126). In this determination (step S126), when the frequency division signal is detected (Yes), the value of the number counter 608b13 is incremented by 1 (step S127), and the process returns to step S124. On the other hand, in the determination of whether or not the frequency-divided signal is detected (step S126), when the frequency-divided signal is not detected (No), the process returns to step S124.

  If the value based on the M-sequence random number in the work area 608b8 is not larger than the maximum value in the determination in step S125 (step S125; No), the value of the circulation counter 608b12 is incremented by 1 (step S128), and the circulation counter It is determined whether or not the value is greater than or equal to the maximum value (step S129). In this determination (step S129), when the value of the circulation counter is equal to or greater than the maximum value (Yes), the value of the circulation counter is set to “0” (step S130). On the other hand, in the determination of whether or not the value of the circulation counter is equal to or greater than the maximum value (step S129), if the value of the circulation counter is not equal to or greater than the maximum value (No), the process proceeds to step S134.

  Next, the start value setting register 608b5 acquires the start value and corrects it to be equal to or less than the maximum value (step S131). Specifically, at this time, since the acquired start value is larger than the maximum value, correction is performed using the remainder value when the maximum value is divided by the start value as the start value. Then, the start value is taken into the work area 608b8 (step S132), the one-round completion notification register 608b6 is set to ON (step S133), and the process proceeds to step S134. In this determination (step S134), if it is determined that the value of the number counter 608b13 has reached the specified value (Yes), the value of the work area 608b8 is set in the random number counter 608b7 as described above (step S135). ), The random number updating notification register 608b9 is set to OFF (step S136), and the process returns to step S107.

  Although not shown in FIGS. 7 and 8, the random number update controller 608a checks the value of the random number counter 608b7 after the random number update process, and determines that it is an update error if the update has not been performed. The update error notification register 608b10 is configured to set a value indicating that an error has occurred.

Next, a second random number generation circuit 124B constituting the random number generation circuit 124 built in the gaming microcomputer 110 of this embodiment will be described with reference to FIG.
The second random number generation circuit 124B is operated by a clock φ1 supplied from a frequency dividing circuit 231 that divides the system clock MCLK in the clock generator 123 and a signal CTC2 supplied from a CTC (counter / timer circuit) circuit 232. To do. The configuration of the clock generator 123 is the same as that of the clock generator 123 of FIG.

The second random number generation circuit 124B includes a random number update controller 240 that controls the entire random number generation circuit, a second random number initial value setting register 241 in which an initial value of the random number is set by the CPU core 111 via the CPU bus 126, A second random number circuit activation register 242 and a second random number counter 243 are provided.
When a predetermined value is set by the CPU core 111 in the second random number circuit activation register 242, the random number update controller 240 is configured to start control of random number generation. The second random number counter 243 is a binary counter, and the counting range is selected from a range of 8 bits (FFh) to 16 bits (FFFFh) by setting a predetermined value in the HW parameter ROM. It is configured to be able to. Similarly to the first random number generation circuit 124A, a maximum value setting register may be provided. When a plurality of types of random numbers are required, a plurality of second random number counters 243 can be provided, and a different initial value can be set for each random number counter in the second random number initial value setting register 241.

Furthermore, the second random number generation circuit 124B artificially generates three second random number latch registers 245, 247, and 249 that take in and hold the value of the second random number counter 243, and start winning detection signals. Second random number latch register trigger circuits 244, 246, and 248 for generating a trigger signal for latching the value of the second random number counter 243 to the latch registers. The second random number latch register trigger circuits 244, 246 and 248 can be constituted by registers. The second random number latch registers 245, 247, and 249 normally latch the value of the second random number counter 243 based on the latch signal generated by the random number update controller 240, but the CPU core 111 performs the second random number latch register trigger circuit 244. , 246, 248 also set a predetermined value, a latch trigger signal is generated, and the value of the second random number counter 243 is latched in the second random number latch registers 245, 247, 249.

  In this embodiment, as shown in FIG. 10, the second random number counter 243 is updated at the rising edge of the clock φ1 (signal CTC2 from the CTC circuit 232) divided by the frequency dividing circuit 231, while the clock φ1 ( By using the inversion signal of CTC2), that is, the clock / φ1 (or / CTC2) having a phase difference of 180 ° as the latch timing signal, the counter value is not latched at the timing when the value of the second random number counter 243 changes. ing.

  The random number update controller 240 receives the latch signals LAT0, LAT1, and LAT2 from the interrupt controller 118, and sets counters to the second random number latch registers 245, 247, and 249 based on the input of the latch signals LAT0, LAT1, and LAT2. A control signal for latching is generated. In this embodiment, the start winning detection signals DET0 and DET1 from the special drawing start switches 56a and 57b are input to the interrupt controller 118, and the value of the second random number counter 243 is changed to the second random number every time a start winning is detected. It is latched in one of the latch registers 245 and 247.

  Specifically, the interrupt controller 118 continuously outputs the start winning detection signal DET over 256 clocks (25.6 μs: when EXCLK or MCLK = 20 MHz is input) by the clock signal supplied to the second random number counter 243. A latch signal LAT is output to the random number update controller 240 at the detected timing. The random number update controller 240 does not latch the counter value at the timing when the latch signal LAT is input, but instead of the second random number latch registers 245, 247, and 249 at the rising edge of the clock signal immediately after the latch signal LAT is input. The counter value is latched in one of the corresponding registers.

  Although not particularly limited, in this embodiment, the signal of the start port switch 1 is input to DET0 (LAT0), and when the signal is input, the counter value is latched in the second random number latch register 245. . A signal of the start port switch 2 is input to DET1 (LAT1), and when the signal is input, the counter value is latched in the second random number latch register 247. Of the three inputs of the interrupt controller 118, one DET2 (LAT2) and the second random number latch register 249 are provided to support a gaming machine in which three start winning holes are provided in the gaming area. In the gaming machine of the embodiment, it is treated as a spare.

  Instead of the interrupt controller, a control register writable from the outside may be provided, and a counter value latch signal may be generated in response to the writing to the control register. When a control register is provided, a predetermined bit of the control register is set by the start winning detection signals DET0 and DET1, and an interrupt signal is input to the interrupt controller 118. The interrupt controller 118 performs the same control as described above. You may comprise so that it may perform.

Further, the second random number generation circuit 124B initializes the second random number generation circuit 124B and the second random number status register 250 for informing the CPU core 111 of the internal state of the second random number generation circuit 124B. 2 random number circuit initialization register 251 is provided. The second random number status register 250 is provided with a latch permission flag that permits or prohibits the latching of the counter value to the second random number latch registers 245, 247, and 249, and the counter value is latched by setting this flag. Can be disabled by clearing the flag.

  In this embodiment, the latch permission flag is provided corresponding to each of the second random number latch registers 245, 247, and 249, and is configured to be able to control permission / prohibition of latch for each register. The second random number status register 250 is rewritten by the random number update controller 240 so that the CPU core 111 can only read and cannot write. As a result, it is possible to prevent an illegal act of rewriting the program and causing the CPU to acquire an illegal random number value.

  FIG. 11 shows a procedure for holding the counter value in the latch register (latch control) by the random number update controller 240. In this control, first, it is determined whether any of the latch signals LAT0, LAT1, and LAT2 is input (step S141). If any of the latch signals LAT0, LAT1, and LAT2 is input, It is determined whether the latch permission flag of the two random number status register 250 is set (step S142). If there is no latch signal input or if there is a latch signal and the latch permission flag is not set, the control is terminated, and if it is determined in step S142 that the latch permission flag is set, the second random number counter The counter value is read from 243 and stored in the corresponding second random number latch register (any one of 245, 247, 249) (steps S143, S144). Subsequently, the corresponding latch permission flag of the second random number status register 250 is set to a prohibited state, and the control is terminated (step S145).

  FIG. 12 shows a control procedure when the random number update controller 240 reads latch data. In this control, first, it is determined whether or not the CPU core 111 has read data in the second random number latch register (any one of 245, 247, and 249) (step S151), and data (counter value) is read. In this case, the data in the second random number latch register is cleared, the corresponding latch permission flag in the second random number status register 250 is set to the permitted state, and the control is terminated (steps S152 and S153). When the data in the second random number latch register is read and then cleared and the latch permission flag is set to the permitted state, so that the counter value is no longer latched into the second random number latch register due to a malfunction such as a circuit failure. In addition, there is no possibility of acquiring the acquired counter value in duplicate. As a result, when the value held in the second random number latch register immediately before corresponds to the big hit, it is possible to prevent the big hit from occurring.

  In this embodiment, the counter value latched in the second random number latch registers 245 and 247 by the random number update controller 240 is performed by external start winning detection signals DET0 and DET1. On the other hand, when the start winning detection signal DET0 or DET1 is input to the microcomputer, the CPU core 111, when a predetermined condition is satisfied by the program processing, data (counter value) of the second random number latch register 245 or 247 Is read as a random value for jackpot determination. The latch permission flag of the second random number status register 250 is set to the latch prohibited state until the value of the counter is latched in the second random number latch register and is read by the CPU.

  Therefore, by performing the control as described above, even if there is noise on the latch signals LAT0, LAT1, and LAT2 input to the random number update controller 240, the counter value of the second random number counter 243 is erroneously set to the second value. It is not latched (overwritten) in the random number latch register, and the CPU does not read an incorrect counter value (random number value). The data (second random number) read by the CPU core 111 is stored in a predetermined area of the RAM 113 in the gaming microcomputer 110.

  In addition, in a conventional game control circuit in which a random number generation circuit is connected as an external circuit, if a player gives a latch signal at a timing different from the original start winning detection signal by an unauthorized operation, an incorrect counter value (disturbance) In this embodiment, even if the start winning detection signals DET0 and DET1 are illegally input and the counter value is latched in the latch register, the latch data is not read by the CPU. The counter value is latched in the latch register by the start winning detection signals DET0 and DET1 that are normally generated and read by the CPU. As a result, it is difficult to acquire an erroneous random number value due to fraud, and the counter value latched based on the start winning can be reliably used in the game control.

Next, game control executed by the game microcomputer (hereinafter referred to as game microcomputer) 110 of the game control apparatus 100 will be described.
The control process by the gaming microcomputer 110 mainly includes a main process shown in FIGS. 13 and 14 and a timer interrupt process shown in FIG. 15 performed every predetermined time period (for example, every 2 msec).

  The main process is started when the power is turned on. In this main process, as shown in FIG. 13, first, an interrupt prohibition process (step S1) is performed, and then an interrupt vector setting process (step S1) for setting a jump destination vector address to be executed when an interrupt occurs. S2), a stack pointer setting process (step S3) for setting a stack pointer that is the start address of an area in which a value of a register or the like is saved when an interrupt occurs, and an interrupt mode setting process (step S4) for setting an interrupt processing mode. )I do.

  Next, access to a readable / writable RWM (read / write memory) such as RAM or EEPROM is permitted, and all output ports are set to OFF (no output) (steps S5 and S6). Thereafter, the chip ID is acquired from the chip ID register 127 (FIG. 5) in the gaming microcomputer 111 (step S7), and the chip ID is set in the transmission buffer for transmission to the management device 300 (step S8). The chip ID set in the transmission buffer is sequentially transmitted to the management apparatus 300 by the serial transmission / reception circuit 127 via the output interface 106 and the external information terminal. Subsequently, it is determined whether or not the backup memory clear switch 162 in the power supply device 160 is turned on (step S9). If the clear switch is off, in step S10, after checking the data in the power failure check area in the RWM, check the code for checking whether or not the power failure is restored and the normality / abnormality of the data called a checksum. (Steps S11 and S12).

  If it is determined in step S11 that the power failure has been restored and it is determined in step S12 that the checksum is normal, in step S13, an initial value at the time of power failure recovery is set in the readable / writable RWM, and the state of the game frame is set. The memory area in which such data is stored is cleared, a power failure recovery command is transmitted to another control device (steps S14 and S15), and the process proceeds to step S19 in FIG. On the other hand, if it is determined in step S11 that the power failure has not been recovered or the checksum is determined to be abnormal in step S12, the read / writeable RWM being used is cleared in step S16. Then, after saving the initial value at power-on in the RWM, processing for transmitting a power-on command to other control devices (steps S17 and S18) is performed, and the process proceeds to step S19 in FIG.

  If it is determined in step S9 that the clear switch is ON, the process jumps to step S16 to clear the read / write RWM being used, save the initial value at power-on in the RWM, and so on. Processing for transmitting a power-on command to the control device (steps S17 and S18) is performed, and the process proceeds to step S19 in FIG.

  In step S19, an interrupt timer is started, and in the next step S20, the random number generation circuit is started to start the random number generation circuit 124. Specifically, in the first random number generation circuit 124A (see FIG. 6), setting in the CTC update permission register 608b1, setting of the maximum value and mode in the maximum value setting register 608b4 in the case of soft random number processing, tap setting register The CPU 111 sets a code (designated value) for starting the random number generation circuit to 608b2. In the second random number generation circuit 124B (see FIG. 9), a code for starting the circuit is set in the second random number circuit start register 242, and the second random number generation circuit 124B is started.

  Thereafter, the interruption is temporarily prohibited (step S21), and an initial value for breaking the temporal regularity of the random number by updating the initial value of the random number such as the jackpot symbol determination random number generated by the first random number generation circuit 124A. A value random number update process (step S22) is performed. Then, an interrupt is permitted (step S23), and a process of checking data in the power failure inspection area (step S24) is performed. Then, a determination is made as to whether or not a power failure has occurred (step S25). If no power failure has occurred (No), the process returns to the process for prohibiting the interruption (step S21), and steps S22 to S25 are performed. Repeat the process.

  On the other hand, if it is determined in step S25 that a power failure has occurred (Yes), processing for temporarily prohibiting interruption (step S26), processing for turning off all output ports (step S27), and clearing the power failure inspection area The process (step S28) to perform is performed. After that, the process of saving the power failure recovery inspection area check data in the power failure recovery inspection area (step S29) and the process of calculating the checksum when the RWM is turned off (step S30) are performed, and access to the RWM is prohibited. After performing the process (step S31) to be performed, it waits for the power supply of the gaming machine to be cut off. In this way, the check data is saved in the power failure recovery inspection area and the checksum at the time of power shutdown is calculated, so that whether or not the information stored in the RWM before the power shutdown is correctly backed up can be checked. This can be determined when the power is turned on again.

  Next, the timer interrupt process in FIG. 15 will be described. This timer interrupt processing is started, for example, every 2 ms when the periodic timer interrupt signal CTC1 generated by the CTC circuit 232 in the clock generator 123 is input to the CPU core 111. When a timer interrupt occurs in the gaming microcomputer 110, the timer interrupt process of FIG. 15 is started.

  When the timer interrupt process is started, a register saving process (step S40) is first performed in which a value held in a predetermined register is transferred to the RAM. Next, an input process (step S41) is performed in which inputs from various sensors (special drawing start switches 56a and 57b, universal drawing start switch 54a, frame opening switch 12a, ball break switch 41a, etc.) are taken. Then, based on the output data set in various processes, an output process (step S42) for performing drive control of an actuator such as a solenoid (large winning opening SOL58b, ordinary electric power SOL57b) or the like is performed. As for the input from the switch for detecting winning and passing of the game ball, the input port is read every 2 ms in the input process of step S41, the state where the chattering is removed is analyzed, and the level state of the switch is 0. When it changes from 1 to 1, the switch is turned on.

  Further, in the input processing of step S41, as a method of eliminating chattering for the switch input when acquiring the input port state, the switch port state is read from the input port for each interrupt and the switch port state to be analyzed is extracted. If the continuous data for two interrupts match, the state is set to a normal port state. Then, the state is determined as the level state and the level state is updated. If the data does not match, the previous level state is continued. Further, the rising edge is updated according to the change of the level state. At this time, the updated rising edge is stored in the RAM. The above processing is performed in all the switches that detect winning and passing of game balls.

  Next, a command transmission process (step S43) and a random number update process (step S44) for outputting commands set in the transmission buffer in various processes to the effect control device 150, the payout control device 200, and the like are performed. In this random number update process (step S44), an update command (write of a predetermined value) is performed to the random number update trigger register 608b3 provided in the first random number generation circuit 124A (FIG. 6). Accordingly, the random number update process (step S44) also constitutes a part of the random number update means. On the other hand, once activated, the second random number generation circuit 124B (FIG. 9) is updated by the random number update controller 240 without receiving an update command from the CPU.

  It should be noted that the jackpot symbol random number for determining the jackpot symbol of the special figure fluctuation display game generated by the first random number generation circuit 124A and the fluctuation pattern random number for determining the fluctuation pattern in the special figure fluctuation display game are determined. This step does not include the acquisition of the big hit determination random number for determining the hit / miss of the special figure variation display game generated by the second random number generation circuit 124B. The big hit determination random number, the fluctuation pattern random number, and the big hit determination random number are fetched in a start port SW2 monitoring process (FIG. 16) of the special figure game process described later. In addition, the acquisition of the hit random number for determining the hit error of the usual figure change display game generated by the first random number generation circuit 124A is executed in the later-described usual figure game process (step S47).

  Next, a special drawing start switch 56a, 57b, an ordinary drawing start switch 54a, a winning opening switch 55a ... 55n, a winning opening switch for monitoring whether there is a normal signal input from the count switch 58a, and monitoring errors. / An error monitoring process (step S45) is performed. Also, a special figure game process (step S46) for performing a process related to the special figure fluctuation display game, a normal figure game process for carrying out a process related to the general figure fluctuation display game, such as taking in a random number of hits in the normal figure fluctuation display game and determining whether or not to win (Step S47) is performed. Details of the special game process (step S46) will be described later with reference to FIG.

  Next, a segment LED editing process (step S48) that is provided in the gaming machine 10 and drives the segment LED that displays various information related to the game to display desired contents is performed. Then, external information editing processing (step S49) for setting a signal to be output to the external management device in the output buffer, and chip ID transmission processing (step S50) for transmitting the chip ID to the management device or the like are performed. Subsequently, a process of declaring the end of the interrupt (step S51) is performed, a process of restoring the saved register data (step S52), a process of permitting the interrupt (step S53), and a timer interrupt The process ends. Details of the chip ID transmission process (step S50) will be described later with reference to FIG.

Next, details of the special figure game process (step S46) in the timer interrupt process of FIG. 15 will be described with reference to FIG.
As shown in FIG. 16, in the special figure game process, first, monitoring of the winning (special drawing start SW1, SW2) to the normal variable winning device 57 having the start winning opening 56 and the second starting winning opening, and winning detection. The start port switch monitoring process (step S361) for acquiring and storing various random number values based on the above is executed. The start port switch monitoring process includes a start port SW1 monitoring process (start port switch 1 monitoring process) for monitoring the winning of the start winning port 56 and a start port SW2 monitoring process (starting) for monitoring the winning to the normal variation winning device 57. Mouth switch 2 monitoring process). Thereafter, a count switch monitoring process (step S362) for monitoring the input from the count switch 58a in the special variable winning device 58 and counting the number of inputs is executed.

  Next, it is determined whether or not the game process timer set in each process relating to the execution of the special figure variation display game has expired (step S363). If it is determined that the game process timer has not timed up (No), the special figure variation control process (step S375) relating to the control of the special figure variation display game is performed and the special figure game process is terminated. In addition, in the determination of whether or not the game processing timer has expired (step S363), if it is determined that the game processing timer has expired (Yes), the game provided for reasonably progressing the game A game branching process (step S364) for selecting a process to be executed next based on the process number is performed.

  In the game branching process (step S364), when it is determined that the game process number is “0”, the special symbol variation start is monitored, the special symbol variation start setting, the effect setting, or the special graphic routine processing A special figure routine process (step S365) for setting information necessary for performing the process is performed. Further, in the game branching process (step S364), when it is determined that the game process number is “1”, the special figure first half fluctuation start process (step for setting information related to the first half fluctuation time of the special figure fluctuation display game) S366) is performed.

  Here, the first half variation time is a period from the start of the special figure variation display game to the occurrence of the reach state. On the other hand, in the game branching process (step S364), when it is determined that the game process number is “2”, the special figure latter half fluctuation start process (step S367) is performed. In this special chart second half fluctuation start process, information related to the second half fluctuation time, which is a period from the occurrence of the reach state of the special figure fluctuation display game to the end of the special figure fluctuation display game, is set. Then, a variation start command corresponding to the variation pattern is determined based on a variation pattern selection table to be described later, and the determined variation start command is set in the transmission buffer for transmission to the effect control device.

  Also, in the game branching process (step S364), when it is determined that the game process number is “3”, the updating of the symbol and the symbol during the variation of the decorative special symbol variation display game executed on the display device 61 are temporarily performed. A special figure changing process (step S368) for performing control such as changing again after stopping is performed. Also, in the game branching process (step S364), when it is determined that the game process number is “4”, a special figure display process (step for setting a final symbol stop timing in the special figure variation game) S369) is performed.

Further, in the game branching process (step S364), when it is determined that the game process number is “5”, the sound effect in the special gaming state (big hit), the light emission drive of the lighting unit 17, a predetermined interval (for example, 1 second) A fanfare / interval process (step S370) is performed for performing a plurality of opening operation processes of the special variable winning device 58 (large winning opening) sandwiching the.
Further, in the game branching process (step S364), when it is determined that the game process number is “6”, a special winning opening opening process (step S371) is performed. In the special prize opening opening process (step S371), if the special gaming state is not the final round, information necessary for performing the fanfare / interval processing (step S370) is set, and the special gaming state is the final round. If there is, the setting of the command for the special game state end screen and the setting of information necessary for performing the next big winning opening remaining ball process (step S372) are performed.

Further, in the game branching process (step S364), when it is determined that the game process number is “7”, all the game balls remaining in the big prize opening after the big prize opening is closed are detected by the count switch 58a. The winning ball remaining ball processing (step S372) for setting the time until the time is performed. Further, in the game branching process (step S364), when it is determined that the game process number is “8”, the special game state is terminated and the special figure routine process (step S365) is performed. A jackpot ending process (step S373) for setting necessary information is performed.
Furthermore, after performing each of the above-described processes based on the game process number, the table data saving process (step S374) for saving various set data is performed, and then a process such as updating the game process timer is performed. A control process (step S375) is performed to end the special figure game process.

Next, details of the start port SW2 monitoring process (start port 2 monitoring process) executed in the start port switch monitoring process (step S361) during the special figure game process of FIG. 16 will be described with reference to FIG.
In the start port SW2 monitoring process (start port switch 2 monitoring process), first, it is determined whether or not the normal variation winning device 57 is in operation, that is, the open state in which the normal variation winning device 57 is activated and the game ball can be won. It is determined whether or not (step S611). In this determination, when the normal variation winning device is in operation (Yes), the process jumps to step S613 to determine whether the start port switch 2 (57b) is on. If it is determined in step S611 that the normally variable winning device is not in operation (No), it is determined in the next step whether or not the number of illegal winnings is an upper limit (step S612).

In the determination of the start port switch in step S613, the presence or absence of the rising edge corresponding to the start port switch stored in the RAM in the input process in step S41 of FIG. ", It is determined that the switch state is ON, and when the updated rising edge is" NONE ", it is determined that the switch state is OFF.
The normally variable winning device 57 cannot win game balls in the closed state, and can win game balls only in the open state. Therefore, when a game ball wins in a closed state, it is a case where some abnormality or fraud occurs, and when there is a game ball won in such a closed state, the number is counted as an illegal winning number. ing.

Then, in determining whether or not the number of illegal winnings is an upper limit value (step S612), it is determined whether or not the number of illegal winnings counted in this way is equal to or greater than a predetermined upper limit value. In this determination, when the number of illegal winnings is the upper limit (Yes), the start port SW monitoring process is terminated. That is, in this case, the start memory is not generated. If it is determined in step S612 that the number of illegal winnings is not the upper limit (No), it is determined in step S613 whether the start port switch 2 (57b) is on.
If it is determined in step S613 that the start port switch 2 is not on, the start port SW2 monitoring process is terminated. On the other hand, if it is determined in step S613 that the start port switch 2 is on, the process proceeds to step S614, and a start port signal output count update process for updating the number of winning game balls to the normal variation winning device 57 ( Step S614) is performed.

  Next, it is determined whether or not the starting memory number is the upper limit value (step S615). If the starting memory number is not the upper limit value (No) in this determination, the starting memory number is determined in the next step S616. After incrementing (+1), the value of the second random number latch register (245, 247, 249) in the second random number generation circuit 124B is acquired as a big hit random value and stored in a predetermined area of the RAM (113) (step S617) )I do.

  After step S617, the gaming microcomputer 110 refers to the random number updating notification register 608b9 of the first random number generation circuit 124A (step S618), and determines whether or not the random number is being updated (step S619). If it is determined in step S619 that the random number is being updated (Yes), the process returns to step S618. This is because in the case of the M-sequence random number update process, it takes time to update, so that the random number is updated. If it is determined in step S619 that the random number is being updated (No), the value of the random number counter 608b7 of the first random number generation circuit 124A is acquired and stored in the RAM as a jackpot symbol random number (step S620), the fluctuation pattern random number is acquired and stored in the RAM. The storing process (step S621) is performed. Further, a process (step S622) of setting a decoration special figure start memory number command to be transmitted to the effect control device 150 in the transmission circuit is executed, and the start port SW2 monitoring process is ended.

  If it is determined in step S615 that the start memory number is the upper limit value (Yes), that is, if no more start memory can be stored, the process proceeds to step S623 and the second random number generation circuit 124B The value of the second random number latch register (245, 247, 249) is acquired, that is, read only, and the start port SW2 monitoring process is terminated. Even when the starting memory number is the upper limit value, by acquiring the value of the latch register (245, 247, 249), the next time the starting winning is detected, the random number counter 243 detects the latch register (245, 247, 249) can be incorporated into the counter value. This is because the second random number generation circuit 124B cannot acquire the next counter value unless the random number value is read from the latch register.

Further, in the start port switch monitoring process (step S361) of FIG. 16, the start port SW1 monitoring process (start port switch 1 monitoring process) is executed following the above-described start port switch 2 monitoring process. The start port switch 1 monitoring process is substantially the same as the start port switch 2 monitoring process.
The difference between the start port switch 2 monitoring process and the start port switch 1 monitoring process is that, in the start port switch 1 monitoring process, whether or not the normal variation winning device 57 in step S611 of the start port switch 2 monitoring process in FIG. In step 613, the start port switch 1 (56a) is turned on instead of the start port switch 2 (57b). It can be determined whether or not there is.

Next, details of the chip ID transmission process (step S50) in the timer interrupt process of FIG. 15 will be described with reference to FIG.
As shown in FIG. 18, in the chip ID transmission process, first, a fluctuation pattern random number stored in the RAM 113 (FIG. 4) is acquired (step S501). Then, it is determined whether or not the acquired random number is coincident with the start value, that is, whether or not the random value has been completed (step S502). If it is determined in step S502 that the start value does not match (No), the chip ID transmission process is exited. The determination may be made using a big hit random number or a stop symbol random number instead of the fluctuation pattern random number. Further, the variation pattern random number is not limited to the one generated by the random number counter of the first random number generation circuit 124A. For example, the counter value stored in the RAM 113 is incremented by +1 for each timer interrupt in step S44 of FIG. It may be a random number to be updated.

  On the other hand, if it is determined in step S502 that the variation pattern random number matches the start value (Yes), the process proceeds to step S503, and the chip ID held in the chip ID register 127 (FIG. 5) in the gaming microcomputer 110 is reached. To get. Then, in order to transmit the chip ID to the management apparatus 300, the chip ID is set in the transmission buffer (step S502), and the processing exits from the chip ID transmission process. In addition, when the values of the random number counter 608b7 of the first random number generation circuit 124A coincide with the values of the random number counter 243 of the second random number generation circuit 124B instead of the coincidence determination with the start value (when the combination of two random numbers makes a round) In addition, the chip ID may be transmitted.

The management device 300 monitors whether the random number generation circuit of the gaming microcomputer 110 has been normally updated by determining whether the chip ID is periodically transmitted at a predetermined cycle by the chip ID transmission. This makes it easier to detect fraudulent acts such as board replacement and failures. In addition, when the bias occurs, the uniformity of the game can be ensured by applying a reset or the like so as not to be biased.
Furthermore, since the variation pattern random number has a wider range of random numbers than other random numbers such as jackpot random numbers, by sending the chip ID when the variation pattern random number makes a round as described above, the chip ID It can be avoided that the transmission cycle becomes too short and the burden on the CPU increases.

(First invention)
Next, with reference to FIG. 19, how to generate a jackpot random number value and a jackpot symbol random number value according to the first invention in the game control device of the embodiment including the first random number generation circuit 124A and the second random number generation circuit 124B will be described. explain. The same applies to the case of generating a hit random number value (hereinafter referred to as a random number value per universal figure) or a fluctuation pattern random number value and a big hit symbol random number value for the normal figure fluctuation display game instead of the big hit random number value. Therefore, the method of generating the jackpot random number value and the jackpot symbol random number value will be mainly described below, and the generation of the random symbol value per common symbol or the variation pattern random number value and the jackpot symbol random value will be supplementarily described.

In conventional gaming machines, the generation of jackpot random numbers and jackpot symbol random numbers in the game control device determines the occurrence probability of each, and the random number according to the probability and the counter circuit (number of bits of the binary counter) to be used The update range was set, and the correlation of each random number was not considered.
Therefore, for example, when the range of the jackpot random number is set to 1 to 4, the range of the jackpot symbol random number is set to 0 to 9, and a random number is generated using a counter operating with the same clock, a round of two types of random numbers is performed. Assuming that the number of updates required for each is M and N, the combination of the two types of random numbers returns to the initial state when a count operation corresponding to the least common multiple of M and N is performed. Therefore, when the possible range of two random values is set as described above, as can be seen from FIG. 19A, the initial state (for example, 1, 0) is set to once every 20 updates. It appears relatively frequently and (2,0) (4,0) (6,0) (8,0) (1,1) (1,3) (1,5) (1,7) ... As described above, since some of them do not appear, there is a problem that the randomness combination is biased and the uniformity of the game is lowered.

  Therefore, in this embodiment, the total number of jackpot random numbers (second counter value) is a number that does not include “2” or “5” as a prime factor when factoring, and the jackpot symbol random number (first counter value) is In the factorization, the prime factors are set to include numbers “2” and “5”. Specifically, for example, as shown in FIG. 19B, the range of the jackpot random number is set to 1 to 7, and the range of the jackpot symbol random number is set to 0 to 9. That is, the total number of jackpot random numbers is “7” that does not include “2” or “5” as a prime factor, and the total number of jackpot symbol random numbers is “10” that includes “2” and “5” as prime factors. It can be said that “7” is a number that does not include “2” and “5” as prime factors.

  By performing the setting as described above, since the combination of random numbers that has appeared once does not appear again (70 times) from the initial state (for example, 1, 0) until all the combinations of random numbers appear, It is possible to prevent the game uniformity from deteriorating due to the combination of the jackpot symbol random numbers. The total number of random numbers per ordinary figure or the total number of fluctuation pattern random numbers is a number that does not include “2” and / or “5” as prime factors, and the total number of jackpot symbol random numbers is a number that includes “2” and “5” as prime factors. Even in such a case, it is possible to prevent a bias from occurring in the combination of the random numbers per ordinary figure or the variation pattern random numbers and the jackpot symbol random numbers.

The total number of jackpot random numbers is not limited to “7” and does not include “2” or “5” as prime factors, that is, “3” “7” “11” “13” “17” “19”. ... May be a number represented by multiplication of several prime factors. The total number of jackpot symbol random numbers is not limited to “10”, and it is preferable to include “2” or “5” as a prime factor.
Further, in order to increase the least common multiple, the total number of the two types of random numbers is not included in the same prime factor. Here, the total number of jackpot symbol random numbers including “2” or “5” as a prime factor is based on accurate distribution based on a percentage (for example, an appearance rate that is not a fraction such as 40% or 15%) or a lottery. It is because it is easy to do. Specifically, the total number of jackpot symbol random numbers is a number including only “2” as a prime factor (2, 2 × 2, 2 × 2 × 2...), Or a number including only “5” as a prime factor (5, 5 × 5, 5 × 5 × 5..., Or a number including only “2” and “5” as prime factors (2 × 5, 2 × 5 × 2, 2 × 5 × 5, 2 × 5 × 2 × 2... It is better to decide as follows.

In FIG. 20, the range of the jackpot symbol random number is “0000” to “1001” (decimal numbers “0” to “9”), and ten types of numbers “0” to “9” are used as the jackpot symbol, for example. In this case, the relationship between the jackpot symbol random number, the jackpot symbol, and the distribution contents is shown.
In FIG. 20, “round number: 15R, low probability (100 times shorter)” means that the special variable winning device 58 is released 15 times in the generated big hit game, and the special figure changes after the big hit game ends. This means that the probability state in the display game becomes a low probability, and a specific game state in which the time-short control is executed 100 times when the variation time of the special figure variation display game is shorter than normal is generated.

In addition, “the number of rounds: 15R, high probability (short time ∞ times)” means that the special variable winning device 58 is released 15 times in the generated jackpot game, and after the jackpot game is over, the probability in the special figure variable display game This means that a specific gaming state occurs in which the state is highly probable and time-saving control is executed until the next big hit occurs.
That is, a lottery is performed as to whether or not to generate a specific gaming state in which the game progress after the end of the special gaming state is advantageous based on the jackpot symbol random number (first random number value). Accordingly, the first random number generation circuit 124A that generates the jackpot symbol random number (first random number value) circulates and updates the first counter value, and is specified when the execution result of the variable display game becomes a specific result mode. It can be said that it is a first random number generation means for generating a first random number value used for lottery of whether or not to generate a gaming state.

By setting and distributing the jackpot symbol random number range as shown in FIG. 20, the probability state after the jackpot game is 40% low and 60% high, making it easy to sort and draw based on percentage. I understand that. As a result, more accurate notification is possible when, for example, the probability is notified to the player. Further, by performing the above sort, the jackpot symbol random number can be regarded as a random number for determining whether or not to generate a probability variation state.
In the above embodiment, the relationship between the jackpot random number and the jackpot symbol random number has been described. However, each random number is generated under the above-described conditions in the relationship between the jackpot random number and the jackpot symbol random number, and the random number per random symbol or the variation pattern random number is generated. Each random number may be generated so that the above-described condition is satisfied in relation to the jackpot symbol random number.

In FIG. 21, the range of the variation pattern random number is set to 1 to 7 and the range of the big hit symbol random number is set to 0 to 9, that is, the total number of the variation pattern random numbers does not include “2” and “5” as prime factors “7”. The example of the variation pattern selection table in the case where the jackpot symbol random number is set to “10” including “2” and “5” as prime factors is shown.
Of these, FIG. 21A is a variation pattern selection table used when the result of the variation display game is out of place, and FIG. 21B is a variation pattern selection used when the result of the variation display game is a big hit. It is a table. As shown in FIG. 21B, when the result of the fluctuation display game is a big hit, the fluctuation pattern is selected according to the combination of the big hit symbol random number and the fluctuation pattern random number.

The total number of fluctuation pattern random numbers is set not to include “2” and “5” as prime factors, and the big hit symbol random number is set to include “2” and “5” as prime factors. When a variation pattern is selected using a table, the combination of the jackpot symbol and the variation pattern is biased, and the occurrence rate of a specific variation pattern in the variation display game that is a jackpot due to the random number generation method Can be prevented from decreasing.
That is, the variation pattern as the effect pattern using the selection table is determined by the variation pattern random number (second random number value). Accordingly, the first random number generation circuit 124A that generates the fluctuation pattern random number (second random number value) circulates and updates the second counter value, and is used to determine the effect pattern of the fluctuation display executed by the display device. It can also be said that the second random number generation means for generating the second random number value to be generated.

FIG. 22 shows the relationship between the number of effective bits of the random number counter 243 and the range of random numbers that can be generated in the second random number generation circuit 124B of FIG.
Assuming that the number of effective bits of the binary counter as a random number generation circuit is n, the counter can count 2n (1 is a positive integer) of 2n-1. By the way, mathematically, a number (3, 7, 15, 31,...) Corresponding to “2n−1” in a decimal number is obtained by multiplying one prime factor not including “2” or two or more prime factors. It is known to be represented. Further, as shown in FIG. 22, when the effective bit number n of the counter is a multiple of 2 (4, 8, 12, 16,...), The number “2n−1” is set to “5” as a prime factor. Including.

  Therefore, as described in the above embodiment, when the big random number not including “2” or “5” as a prime factor is generated by the second random number generation circuit 124B, the effective bit number n of the random number counter 243 is set to 2. A number other than a multiple (2, 3, 5, 6, 7, 9, 10, 11, 13, 14 or 15 in FIG. 22) is set, and the counter value in the range of “1” to “2n−1” is set. If generated, the big hit random number not including “2” and “5” as prime factors can be generated without providing the maximum value setting register 608b4 unlike the first random number generation circuit 124A of FIG. The number of effective bits is stored as an HW parameter in the user program ROM, and is set when starting the user program. The random number generation circuit may be provided with a valid bit setting register and set in the user program.

By the way, in the field of random number generation circuits, the counter value is conventionally started from “1” instead of “0” in M-sequence random numbers, and “0” is not taken as the initial value of the counter. It is not difficult to implement the counter in hardware.
In the above embodiment, the jackpot symbol random number (or random symbol per block, fluctuation pattern random number) is generated by the first random number generation circuit 124A updated by the timer interrupt process (step S44 in FIG. 15). In the above description, the second random number generation circuit 124B that can update the counter value by the M-sequence method using the generator polynomial that is updated without depending on the timer interrupt process has been described. May be generated by a random number generation circuit similar to the first random number generation circuit 124A that is updated in Step 1, or a big hit random number and a big hit symbol random number are generated not by a random number generation circuit but by program processing by a timer interrupt, that is, on a RAM It is also possible to provide a counter area and update the random number by software.
Note that updating of the counter value by the second random number generation circuit is not limited to the M-sequence method, and a count-up method or a count-down method may be employed.

From the above description, in the present application, in the present application, when the variable display game is executed by winning a game ball in the starting area (56, 57) provided in the game area, and the variable display game becomes a specific result mode, In a gaming machine capable of generating a special gaming state that gives a player a gaming value and generating a specific gaming state in which the progress of the game after the special gaming state is advantageous,
A display device (61) capable of displaying an image;
A display (63) capable of expressing a plurality of types of symbols by executing the variable display game;
A game control device (100) for controlling the game in an integrated manner and at least controlling the display;
A display control device (150) for controlling a variable display using decorative symbols in the display device in synchronization with a variable display game executed by the display device based on an instruction from the game control device; Prepared,
The game control device includes:
A first counter value is circulated and updated to generate a first random value used for a lottery to determine whether or not to generate the specific gaming state when the execution result of the variable display game is in the specific result mode. First random number generating means for
A second random number generating unit that circulates and updates the second counter value, and generates a second random number value used to determine an effect pattern of the variable display executed by the display device;
The total number required for one cycle of the first counter value updated by the first random number generation means is a number including both “2” and “5” as prime factors,
It is understood that the total number required for one cycle of the second counter value updated by the second random number generation means includes an invention in which neither “2” nor “5” is included as a prime factor. .

  According to the invention as described above, since the total number of the first counter values and the total number of the second counter values are numbers that do not include a common prime factor, the possible values of the counter values of the first and second random number counters Since there is no bias in the combination, the uniformity of the variable display game can be ensured. In addition, since the total number of the first counter values updated by the first random number generation means is a number including “2” and “5” as prime factors, sorting and lottery using the first counter to generate a specific gaming state When performing the above, it is possible to perform accurate sorting and lottery based on the percentage.

  Further, the second random number generation means updates the counter value by an M-sequence method using a generator polynomial, and can set 1 to 2n−1 (n: integer) as the update range of the second counter value. You may do it. Thereby, it is possible to prevent the second counter value from being biased by updating the second counter value by the M-sequence method. In addition, by setting 1 to 2n-1 (n: integer) as the update range of the second counter value, it is possible to set a number that does not include “2” as a prime factor as the total number of the second counter value. The number including “5” as a prime factor can be reduced, and the number not including “2” and “5” as a prime factor can be set as the total number of second counter values.

(Second invention)
The second invention uses a random number generation circuit similar to the first random number generation circuit 124A updated in the timer interrupt process, for example, when the big hit random number and the big hit symbol random number are updated by the timer interruption. The present invention provides a random number generation method capable of updating random numbers so that there is no bias in the combination. The embodiment of the second invention has the same configuration as the gaming machine of the embodiment of the first invention described above, and includes a control device having the same configuration and function. That is, the hardware of the second embodiment may be the same as that of the first embodiment described above.

In the second invention, as shown in FIG. 23A, for example, the total number of random numbers 1 (first counter value) used as a jackpot symbol random number is Na, for example, a jackpot random number (or a random number per universal symbol, a variation pattern random number). ), The total number of random numbers 2 (second counter values) used as Nb is Nb, the update interval of random numbers 1 is Ta (ms: milliseconds), the update interval of random numbers 2 is Tb (ms), and Pa is relatively prime with Na. When an integer (where Pa ≦ Nb) or “1” and Pb is an integer that is relatively prime with Nb (where Pb ≦ Na) or “1”,
Tb = kta
k = Na / Pb or Pa / Nb
Na, Nb, Ta, Tb, k are determined so as to satisfy the above. Here, the integers that are prime to each other mean integers that are not divisible by each other and that do not include a common prime factor.

  For example, when Na = 5 and Nb = 7, it is necessary to select Pa from 1, 2, 3, 7 and Pb from 1, 2, 3, 5 from the above conditions, and k = Na / Pb or Pa / Nb, k can be 5/1, 5/2, 5/3, 5/5; 1/7, 2/7, 3/7, 7/7. obtain. Here, if Pa = 7 and Pb = 5 are selected, k = 1 may be set from k = Na / Pb (= Pa / Nb), and therefore Ta = Tb.

FIG. 23B shows the relationship between the jackpot random number (or random number per variation, random pattern random number) and the jackpot symbol random number when the update processing is performed after setting as described above. The update intervals Ta and Tb of the random numbers are set to 2 ms from Ta = Tb.
From FIG. 23B, in the case of this embodiment, since the combination of random numbers that has appeared once does not reappear during the period from the initial state (for example, 0, 0) until all the combinations of random numbers appear (35 times). It can be seen that the uniformity of the game can be prevented from decreasing.

  On the other hand, for example, when Na = 10 and Nb = 10, the prime factors of “10” are “2” and “5”. Therefore, from the above conditions, Pa is 1, 3, 7, or 9, and Pb is also 1, 3, 7 and 9 need to be selected, but k = Na / Pb or Pa / Nb, so k is 10/1, 10/3, 10/7, 10/9; Any of 1/10, 3/10, 7/10, and 9/10 can be taken. Here, if Pa = 1 is selected, it is sufficient to set k = 1/10 from k = Pa / Nb, and therefore Ta = 10 Tb.

FIG. 24 shows the relationship between the jackpot symbol random number and the jackpot random number (or random number per regular symbol, variation pattern random number) when the setting process is performed as described above and the update process is performed. When the update interval of each random number is Tb = 1 ms, Ta becomes 10 ms from Ta = 10 Tb.
From FIG. 24, in the initial state (for example, 0, 0), the frequency of appearance of the big hit random number is reduced as once every 100 times, and all possible combinations of two types of random numbers are once every 100 times. It appears that the uniformity of the game is improved.

  For example, when Na = 10 and Nb = 5, since the prime factor of “10” and “5” is “5”, Pa is 1, 2, 3, 4, 6, 7, 8 from the above condition. , 9, Pb must be selected from 1, 2, 3 and 4, but k = Na / Pb or Pa / Nb, so k = 1/10, 2/10, Any of 3/10, 4/10, 6/10, 7/10, 8/10, 9/10; 5/1, 5/2, 5/3, and 5/4 can be taken. Thus, for example, if Pb = 4 is selected, k = 10/4 = 5/2 from k = Na / Pb, so that 5Ta = 2Tb may be set.

FIG. 25 shows the relationship between the jackpot symbol random number and the jackpot random number (or random number per regular symbol, variation pattern random number) when the setting process is performed as described above and the update process is performed. Assuming that Ta = 2 ms for the update interval of each random number, Tb is 5 ms from 5Ta = 2Tb. In other words, if the big hit symbol random number is updated once every 2 ms, the big hit random number (or random number per regular symbol, variation pattern random number) may be updated once every 5 ms.
From FIG. 25, in the case of this embodiment, since the combination of random numbers that appears once does not appear (50 times) from the initial state (for example, 0, 0) until all random number combinations appear, It can be seen that it is possible to prevent the appearance from decreasing.

  As described above, when k takes an appropriate value other than “1”, that is, when the update interval of the jackpot symbol random number and the update interval of the jackpot random number (or random numbers per block, random pattern random number) are set to different values Even if the total number Na of jackpot symbol random numbers and the total number Nb of jackpot random numbers (or random numbers per block, random pattern random numbers) include a common prime factor (“5” in the example of FIG. 25), the jackpot symbol It is possible to make the initial state appear at a frequency of once in the number corresponding to the product of the total number of random numbers and the total number of jackpot random numbers (or random numbers per variation, random pattern random numbers). Note that the jackpot random number (or random number per regular figure, variation pattern random number) and the jackpot symbol random number may be generated not by a random number generation circuit but by a program process using a timer interrupt. That is, it is possible to provide a counter area on the RAM and update the random number by software.

In the present embodiment, the relationship between the jackpot random number or the regular hit random number or variation pattern random number and the jackpot symbol random number has been described. However, the relationship between the jackpot random number and the jackpot symbol random number should satisfy the above-described condition. Each random number may be generated, and each random number may be generated so that the above-described condition is satisfied in relation to the random number per regular figure or the variation pattern random number and the big hit symbol random number.
Also, two types of variation pattern random numbers are prepared for the jackpot symbol random number, the variation pattern is selected by a combination of the variation pattern random number 1 and the variation pattern random number 2, and the relationship between the variation pattern random number 1 and the jackpot symbol random number is Each random number may be generated (updated) so that the above-described conditions are satisfied and the relationship between the variation pattern random number 2 and the jackpot symbol random number satisfies the above-described condition.

FIG. 26 shows the relationship between each random number when the update process is performed under the above conditions to generate a jackpot symbol random number and two types of variation pattern random number 1 and variation pattern random number 2. In this embodiment, the range of the jackpot symbol random number (random number 1) is set to 0 to 4 and the update interval is set to 2 ms, while the range of the fluctuation pattern random number 1 (random number 2) is set to 0 to 6 and the update interval is set to 2 ms. The range of the fluctuation pattern random number 2 (random number 3) is 0 to 2, and the update interval is set to 2 ms.
That is, in this case, the total number required for one round of the jackpot symbol random number (random number 1) is “5”, the total number required for one round of the fluctuation pattern random number 1 (random number 2) is “7”, and the round of the fluctuation pattern random number 1 (random number 2). The total number required for “3” is “3”, and the total number of each random number is in the relation of integers that are relatively prime. Here, the update intervals Ta, Tb, and Tc of the random numbers are the same, that is, Ta = Tb = Tc (= 2 ms). Therefore, the conditions described in FIG. 23A are satisfied. As a result, each combination of random numbers makes a round with 105 (= 5 × 7 × 3) updates, and it can be seen that there is no bias in the generated random number combinations.

  FIG. 27 is a variation pattern selection table used when the update process is performed under the conditions of FIG. 26 to generate a jackpot symbol random number, variation pattern random number 1 and variation pattern random number 2, and the result of the variation display game is out of place. 28 shows a variation pattern selection table used when the result of the variation display game is a big hit under the same conditions. As shown in FIG. 27, when the result of the variation display game is out of place, the variation pattern is selected according to the combination of the variation pattern random number 1 and the variation pattern random number 2, and as shown in FIG. When the result is a big hit, the variation pattern is selected according to the combination of the big hit symbol random number and the variation pattern random number 1 and the variation pattern random number 2.

In FIG. 27, when the variation pattern random number 1 is 0 and the variation pattern random number 2 is 0, the variation pattern group 1 is selected, and the variation pattern 1 belonging to the variation pattern group 1 is selected. Show.
In FIG. 28, when the jackpot symbol random number is 1, the variation pattern random number 1 is 0, and the variation pattern random number 2 is 0, the variation pattern group 15 is selected, and the variation pattern 43 belonging to the variation pattern group 15 is selected. Is selected.
Similarly to the variation pattern selection table at the time of deviation in FIG. 27, there are three types for each variation pattern group, such as variation patterns 22 to 24 for variation pattern group 8 and variation patterns 25 to 27 for variation pattern group 9. It belongs to the fluctuation pattern.
The game control device 100 according to the embodiment determines a variation start command corresponding to the variation pattern selected by the variation pattern selection table of FIGS. A variable display game is played.

From the above description, in the present application, in the present application, when the variable display game is executed by winning a game ball in the starting area (56, 57) provided in the game area, and the variable display game becomes a specific result mode, In a gaming machine capable of generating a special gaming state that gives a player a gaming value and generating a specific gaming state in which the progress of the game after the special gaming state is advantageous,
A display device (61) capable of displaying an image;
A display (63) capable of expressing a plurality of types of symbols by executing the variable display game;
A game control device (100) for controlling the game in an integrated manner and at least controlling the display;
A display control device (150) for controlling a variable display using decorative symbols in the display device in synchronization with a variable display game executed by the display device based on an instruction from the game control device; Prepared,
The game control device includes:
A first counter value is circulated and updated to generate a first random value used for a lottery to determine whether or not to generate the specific gaming state when the execution result of the variable display game is in the specific result mode. First random number generating means for
A second random number generating unit that circulates and updates the second counter value, and generates a second random number value used to determine an effect mode of the variable display executed by the display device;
The total number required for one round of the first counter value updated by the first random number generating means is Na, the update interval of the first counter value is Ta, and the second counter value updated by the second random number generating means is required for one round. The total number is Nb, the update interval of the second counter value is Tb,
The ratio Ta / Tb between the update interval Ta of the first counter value and the update interval Tb of the second counter value is k,
When Pa is an integer that is relatively prime with Na, and Pb is an integer that is relatively prime with Nb,
The first and second random number generation means include
k = Na / Pb or k = Pa / Nb
And
Pa ≦ Nb, Pb ≦ Na
The first and second counter values are updated based on the total number Na and Nb of the first and second counter values satisfying the above and the update intervals Ta and Tb of the first and second counter values. It can be seen that is included.

  According to the invention as described above, between the first counter value (big hit symbol random number) generated by the first random number generator and the second counter value (variation pattern random number) generated by the second random number generator. Since the correlation is lost and there is no bias in the combination of values that the first counter value and the second counter value can take, the uniformity of the game can be ensured.

In the second aspect of the invention, when the update intervals Ta and Tb are Ta = Tb, the total number of first counter values updated by the first random number generation means and the second random number generation means The total number of second counter values to be updated may be a number that does not include a common prime factor.
Thereby, the least common multiple of the total number of the first counter values and the total number of the second counter values is equal to the number obtained by multiplying the total number of the first counter values and the total number of the second counter values, and the number of times corresponding to the least common multiple. Can be generated as a combination of the first counter value and the second counter value, and all possible combinations of values of the first counter value and the second counter value can be generated. Can be secured.

Also in the second invention, as in the first invention, the total number of first counter values updated by the first random number generation means is a number including 2 or 5 as a prime factor, and the second random number generation The total number of second counter values updated by the means may be a number that does not include 2 or 5 as a prime factor.
Thereby, when performing distribution and lottery using the first counter, accurate distribution and lottery based on a percentage (for example, 40%, 15%, etc.) can be performed. Further, since the total number of the second counter values updated by the second random number generation means is a number that does not include “2” or “5” as a prime factor, the total number of the first counter values and the total number of the second counter values Are numbers that do not include common prime factors.

(Third invention)
Next, an embodiment of the third invention will be described with reference to FIGS. 29 and 30. FIG.
In the first embodiment of the third invention, instead of the initial value random number update processing executed in step S22 of the main processing in the embodiment of the first invention shown in FIG. The random number stored in the design random number area provided in is directly updated.

  FIG. 30 shows an example of a detailed procedure of the jackpot symbol random number update process. In FIG. 14, the interrupt prohibition and interrupt permission provided before and after step S22 are provided in the jackpot symbol random number update process of FIG. 30 in the third embodiment. This is because the time for executing the processing by the timer interruption is not compressed by shortening the interruption prohibition period as much as possible.

  In the jackpot symbol random number update process of this embodiment, as shown in FIG. 30, first, the process of setting the address of the symbol random number area provided in the RAM 113 is performed (step S201). A prime number such as is set (step S202). The number of repetitions of addition is not limited to “3”, but a very large value should be avoided. This is because if a large value is used, it takes a long time to update the random number, and interrupt processing is under pressure.

  After setting the number of repetitions for addition in step S202, the interrupt is prohibited (step S203), and then a process of adding “1” to the value of the symbol random number area for which the address is set in step S201 is performed (step S204). . In this process, data is read from the RAM 113, added by the CPU arithmetic unit, the result is stored in the accumulator, and is not stored in the symbol random number area at the original address position of the RAM 113, but the value in the RAM is directly updated ( +1). For example, such a new instruction can be provided in the CPU.

  After performing the process of adding “1” to the value of the symbol random number area in the above step S204, the addition repetition number set in step S202 is subtracted (−1) (step S205). Then, it is determined whether or not the number of repetitions is “0” in the next step S206 (step S206). If it is determined that the number of repetitions is not “0” (No), the process returns to step S204 and the above process is repeated. On the other hand, if it is determined in step S206 that the number of repetitions has become “0” (Yes), the process proceeds to step S207, the interrupt prohibited in step S203 is permitted, and the big hit symbol random number update process is terminated.

  As in the big hit symbol random number update process of this embodiment, by directly updating the random number value stored in the RAM, the value changes due to noise while the data is read from the RAM. Can be avoided, and an accurate random number can be updated. Also, by repeatedly executing the big hit symbol random number update process in the main process, the remaining time until the next timer interrupt is changed every time, so the number of executions of the big hit symbol random number update process changes and is generated accordingly Random numbers are more random. Furthermore, by setting the number of repetitions of addition as in step S202, it is possible to make it difficult to perform fraud compared to a method of adding a fixed value.

(Second embodiment)
Next, a second embodiment of the third invention will be described with reference to FIGS.
In the first embodiment, a big hit symbol random number update process is provided in the main process, and the random number is updated by adding a prime number to the value stored in the symbol random number area in the RAM 113. When “0” is set as the value to be performed, that is, “0” is set as the number of repetitions to be added, the value of the symbol random number area is set to −1 in step S205, so that the value of the symbol random number area is FF, 16 bits when the repetition number is 8 bits In this case, it becomes FFFF, and the time until it becomes “Yes” in the determination in the next step S206 becomes very long.

Therefore, for example, if the fraudulent setting of “0” is made as the number of additional repetitions in step S202 at the timing of updating to the jackpot symbol random number 4 to 6 (see FIG. 20 the highest game value is given) By repeating steps S204 to S206 many times while interrupts are prohibited, the execution time of the timer interrupt process is shortened, and all processes cannot be completed within the interrupt time. There is a risk that it will not be done. Therefore, in the second embodiment, as shown in FIG. 31, a process for monitoring the interrupt process is provided in the timer interrupt process to avoid the above-described fraud.

  The difference between the timer interrupt process of this embodiment shown in FIG. 31 and the timer interrupt process of the embodiment of the first invention shown in FIG. 15 is that in the timer interrupt process of this embodiment, steps S40 and S41 in FIG. In the meantime, a process for determining whether or not the interrupt process monitoring flag is on (step S40a), and a process for turning on the interrupt process monitoring flag when the interrupt process monitoring flag is not on (No) (step S40b), The process of declaring the end of the interrupt (step S40c), the process of permitting the interrupt (step S40d), and the process of permitting the interrupt following step S52 of FIG. 15 (step S53) are deleted. Instead, a process of turning off the interrupt process monitoring flag (step S54) is provided.

  In the timer interrupt process of the present embodiment shown in FIG. 31, if the process proceeds to the middle of steps S41 to S52, the time given to one interrupt process has passed, and the next timer interrupt is entered. Suppose you come. Then, since the process for turning off the interrupt process monitoring flag in step S54 is not executed, it is determined that the interrupt process monitoring flag is turned on in step S40a when the next timer interrupt process is executed (Yes). Then, the process proceeds to step S55, where interrupts are prohibited. Thereafter, the process jumps to step S41 of the main process of FIG. 32 according to symbol B, and access of the RWM (read / write memory) is prohibited.

Therefore, for example, at the timing of updating to the jackpot symbol random number 4 to 6 (see FIG. 20 the highest game value is given), fraud is set such that “0” is set as the additional repetition number in step S202. By repeating steps S204 to S206 many times while interrupts are prohibited, the execution time of the timer interrupt process is shortened, and all processes cannot be completed within the interrupt time. It is possible to prevent a situation that is not done.

As described above, in the present application, the first random number generation unit that circulates and updates the first counter value with the predetermined number as the update range, and the second random number generator that circulates and updates the second counter value with the predetermined number as the update range. The random number generator and the game program control the game centrally, acquire the first and second counter values updated by the first and second random number generators at an arbitrary timing, and And a game control means for performing game control using the second counter value as a random number,
The game control means executes an interrupt routine that is started at a predetermined cycle and a main routine having a loop process that is repeatedly executed during the remaining time of the interrupt routine, and the first random number generation means is the interrupt routine. In the main routine for executing the loop processing in the remaining time, the first counter value is updated by adding a predetermined prime value to the first counter value.

  According to the invention as described above, the first counter value is updated by adding a predetermined prime value to the first counter value in the main routine that executes loop processing with the remaining time of the interrupt routine. Therefore, since the update cycle in which the first counter circulates changes without being determined, the first counter value generated by the first random number generation means and the second counter value generated by the second random number generation means It is possible to prevent the game from becoming less uniform due to the occurrence of a bias in the combination of values that can be taken by the first counter value and the second counter value.

  In the third aspect of the invention, work area data storage means for storing data necessary as a work area for predetermined arithmetic processing including game control by the game program, the game control means includes the first counter value, The game program stores data necessary for predetermined arithmetic processing including game control and can store data even after the power is turned off. The first random number generation unit receives the first counter value from the storage unit. Without adding the accumulator to the accumulator, and includes a predetermined arithmetic process for adding a predetermined prime value to the first counter value stored in the storage means, and prior to the start of the predetermined arithmetic process, Execution may be prohibited, and execution of the interrupt routine may be permitted after completion of the arithmetic processing.

Thereby, it is possible to prevent an incorrect value from being stored in the storage means due to noise or the like. That is, since it is not necessary to read out to the register or the like and perform an operation, the value acquired from the storage means and the value written to the storage means are changed to an arbitrary value due to noise or the like, and an incorrect value is set as the first counter value. Can be prevented.
Also in the third invention, as in the first invention, the total number of first counter values updated by the first random number generation means is a number including 2 or 5 as a prime factor, and the second random number generation The total number of second counter values updated by the means may be a number that does not include 2 or 5 as a prime factor.

  Furthermore, in the third invention, a gaming machine capable of giving a predetermined game value in connection with winning of a game ball at a winning opening, wherein the predetermined game value includes a special game state and the special game state. A probability variation state in which the probability of occurrence of the special gaming state is high after the end of the determination, whether to generate the special gaming state is determined based on the second counter value, The determination as to whether or not to generate the probability variation state may be performed based on the first counter value.

Although the invention made by the present inventor has been specifically described based on the embodiments, the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is shown not by the above description of the invention but by the scope of claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims.
In the embodiment, a method of updating various random numbers such as a big hit random number, a normal hit random number, a variation pattern random number, a big hit symbol random number by the first random number generation circuit 124A or the second random number generation circuit 124B is shown as an example. However, any update method may be adopted as long as the update conditions described above are satisfied. For example, in step S44 of FIG. 15 executed by the user program, the counter value stored in the RAM 113 may be a random number that is updated by +1 for each timer interruption.
In the first embodiment, the big hit symbol random number or the like is generated by the first random number generation circuit 124A updated in the timer interrupt process (step S44 in FIG. 15), and the big hit random number is not updated in the timer interrupt process. What is generated by the random number generation circuit 124B, and in the third embodiment, the big hit symbol random number is generated not by the random number generation circuit but by the main processing by the program. That is, the counter area is provided on the RAM and the random number is generated by software. Although the description has been given of the configuration configured to perform the update, it is also possible to generate a random number for determining per hit, a random number for selecting a variation pattern, and a big hit random number by the main processing by the program. In this case, the random number update process in step S44 of FIG. 31 is not necessary.

  Furthermore, in the above-described embodiment, the present invention is mainly applied to a pachinko gaming machine in which a game ball as a game medium is lent by a card unit, but the present invention is not limited to such a pachinko gaming machine, The present invention can also be applied to game machines such as arrange ball game machines, sparrow ball game machines, and slot machines.

DESCRIPTION OF SYMBOLS 10 Game machine 50 Game board 54 Normal symbol start gate 55 General winning opening control device 56 Starting winning port 57 Starting winning device 58 Special variable winning device 59 Out port 61 Display device 63 Special figure display device 100 Game control device 110 Game microcomputer (Game control means)
113 RAM (data storage means)
124A first random number generation circuit (first random number generation means, second random number generation means)
124B Second random number generation circuit 150 Production control device

Claims (2)

When a variable display game is executed by winning a game ball to the start area provided in the game area, and the variable display game is in a specific result mode, a special game state is provided that gives a player a game value, and In a gaming machine capable of generating a specific game state in which the progress of the game after the special game state ends is advantageous,
A display device capable of displaying images;
A display capable of expressing a plurality of types of symbols by executing the variable display game;
A game control device that controls the game in an integrated manner and controls at least the display;
A display control device for controlling a variable display using a decorative symbol in the display device in synchronization with a variable display game executed by the display device based on an instruction from the game control device;
The game control device includes:
A first counter value is circulated and updated to generate a first random value used for a lottery to determine whether or not to generate the specific gaming state when the execution result of the variable display game is in the specific result mode. First random number generating means for
A second random number generating unit that circulates and updates the second counter value, and generates a second random number value used to determine an effect mode of the variable display executed by the display device;
The total number required for one round of the first counter value updated by the first random number generating means is Na, the update interval of the first counter value is Ta, and the second counter value updated by the second random number generating means is required for one round. The total number is Nb, the update interval of the second counter value is Tb,
The ratio Ta / Tb between the update interval Ta of the first counter value and the update interval Tb of the second counter value is k,
When Pa is an integer that is relatively prime with Na, and Pb is an integer that is relatively prime with Nb,
The first and second random number generation means include
k = Na / Pb or k = Pa / Nb
And
Pa ≦ Nb, Pb ≦ Na
The first and second counter values are updated based on the total number Na and Nb of the first and second counter values satisfying the conditions and the update intervals Ta and Tb of the first and second counter values. To play. The game control device includes:
An arithmetic processing unit that executes game control based on a predetermined game program;
The arithmetic processing unit includes:
An individual identification information storage unit for storing individual identification information that can be identified as the arithmetic processing device;
Individual information transmitting means for transmitting the individual identification information stored in the individual identification information storage unit to an external device outside the gaming machine,
Monitoring whether the second counter value has completed a cycle, and subjecting the individual identification information stored in the individual identification information storage unit to an external device outside the gaming machine on condition that the second counter value has completed a cycle The game machine according to claim 1, wherein the game machine is transmitted.