JP2013118311A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance of a semiconductor device.SOLUTION: A semiconductor device manufacturing method comprises: forming a metal-containing film 4 containing metal such as hafnium in a state where a part of an insulation film 3 such as a silicon oxide film formed on a semiconductor substrate 1 is covered with a hard mask pattern 10 composed of a mask film 9 such as a titanium nitride film, and performing an annealing treatment on the metal-containing film 4; and separately forming MISFETs by adding metal to an insulation film 3 at MISFET formation regions AN1 and AP1 at which MISFETs each having a larger threshold voltage are to be formed, and by not adding metal to the insulation film 3 at MISFET formation regions AN2 and AP2 at which MISFETs each having a smaller threshold voltage are to be formed.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to a method for manufacturing a semiconductor device having a MISFET.

  In SoC (System on a Chip) and MCU (Micro Controller Unit), a transistor formed with a minimum dimension called a core transistor is used, and a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is used as the core transistor. ing. With respect to the core transistor composed of the MISFET, a plurality of types of MISFETs having different threshold voltages (Vth) are required according to a request for circuit design.

  As a method for adjusting the threshold voltage (Vth), there is a method of adjusting the impurity concentration on the surface of the semiconductor substrate (substrate surface) by channel implantation or halo implantation. In this method, in order to reduce the threshold voltage (Vth), it is necessary to reduce the impurity concentration on the substrate surface. However, the short channel effect is likely to appear by reducing the impurity concentration on the substrate surface, and if the gate length is shortened to about 45 nm, the MISFET may be difficult to operate normally. On the other hand, in order to increase the threshold voltage (Vth), it is necessary to increase the impurity concentration on the substrate surface. Although the short channel effect is easily suppressed by increasing the impurity concentration on the substrate surface, GIDL (Gate Induced Drain Leakage) increases and the standby leakage current (off leakage current) increases. As described above, it is difficult to adjust the threshold voltage (Vth) while suppressing the appearance of the short channel effect or the increase in off-leakage current only by adjusting the impurity concentration on the substrate surface by channel implantation or halo implantation.

  On the other hand, in a MISFET having a silicon oxynitride (SiON) film as a gate insulating film and a polysilicon film as a gate electrode, hafnium (Hf) is added to the interface between the silicon oxynitride (SiON) film and the polysilicon film. Thus, a technique for adjusting the threshold voltage (Vth) by changing the work function of the gate electrode is known.

  Japanese Patent Laid-Open No. 2002-110812 (Patent Document 1) discloses that in a semiconductor device having a gate insulating film having two types of film thicknesses so as to correspond to a plurality of types of power supply voltages, one of the gate insulating films is a silicon oxide film. A technique is described in which the other is a laminate of a high-dielectric film containing a metal such as hafnium (Hf) and a silicon oxide film.

  Japanese Patent Laying-Open No. 2007-142007 (Patent Document 2) discloses that in a semiconductor device having a first MISFET constituting an analog circuit and a second MISFET constituting a digital circuit, only the gate insulating film of the second MISFET is a silicon oxynitride film. And a high dielectric film formed on a silicon oxynitride film and containing a metal such as hafnium (Hf).

  Japanese Patent Laying-Open No. 2005-223289 (Patent Document 3) discloses a semiconductor device in which a gate insulating film made of a silicon oxynitride film and a hafnium silicate film is formed on an n-type well region in a region constituting an internal circuit of a semiconductor device. Describes a technique in which a gate insulating film made of a silicon oxide film, a nitride layer, and a silicon nitride film is formed on an n-type well region in a region constituting the input / output circuit.

In Japanese Patent Laid-Open No. 2011-048772 (Patent Document 4), a hafnium oxide (HfO ₂ ) film and an aluminum (Al) -containing layer are formed on an interface layer made of a silicon oxide film, and nitriding is performed only in the p-type MISFET formation region A technique is described in which after a mask film made of titanium (TiN) is formed, a lanthanum (La) containing layer is formed and heat treatment is performed. In the technique described in Patent Document 4, by performing the heat treatment, n-type MISFET formation region in a hafnium oxide (HfO ₂₎ to diffuse the La and Al in the film, hafnium oxide in the p-type MISFET formation region _(HfO 2) Al is diffused in the film.

  According to the technique described above, the threshold voltage (Vth) can be adjusted without changing the impurity concentration on the substrate surface. Therefore, the threshold voltage (Vth) can be reduced while suppressing the appearance of the short channel effect or the increase in off-leakage current. Different types of MISFETs can be formed.

JP 2002-110812 A JP 2007-142007 A JP 2005-223289 A JP 2011-048772 A

  According to the study of the present inventor, the following has been found.

  As described above, the gate insulating film in one MISFET is made of a silicon oxide film, and the gate insulating film in the other MISFET is a stack of a high dielectric film containing a metal such as hafnium (Hf) and a silicon oxide film. The body is an effective method for making different MISFETs having different threshold voltages (Vth). However, it has been found that when MISFETs having different threshold voltages (Vth) are separately produced by the conventional manufacturing process of a semiconductor device, the performance of the semiconductor device is likely to deteriorate.

  In a conventional semiconductor device manufacturing process, patterning is performed using a photoresist pattern as an etching mask when different gate insulating films having different metal contents such as hafnium (Hf) are formed. However, for a semiconductor device such as an SRAM (Static Random Access Memory) of 32 nm node or less, for example, patterning is performed with high shape accuracy in the n-type MISFET formation region and the p-type MISFET formation region in the step of forming a pattern with a photoresist pattern. This decrease in shape accuracy deteriorates the performance of the semiconductor device. In addition, diffusion of organic substances or the like contained in the photoresist pattern into the gate insulating film, or damage to the gate insulating film due to plasma when the photoresist pattern is removed deteriorates the performance of the semiconductor device.

  An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In a method for manufacturing a semiconductor device according to a typical embodiment, a part of an insulating film such as a silicon oxide film formed on a semiconductor substrate is covered with a mask film such as a titanium nitride film, and a metal such as hafnium is used. Is formed and annealed, so that a metal is added to the gate insulating film of the MISFET having a large threshold voltage and a metal is not added to the gate insulating film of the MISFET having a small threshold voltage.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the representative embodiment, the performance of the semiconductor device can be improved.

2 is a main-portion cross-sectional view of the semiconductor device of First Embodiment; FIG. FIG. 6 is a manufacturing process flow chart showing a part of the manufacturing process of the semiconductor device of the first embodiment. FIG. 6 is a manufacturing process flow chart showing a part of the manufacturing process of the semiconductor device of the first embodiment. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. It is a manufacturing process flowchart which shows a part of manufacturing process of the semiconductor device of a comparative example. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. FIG. 10 is a manufacturing process flow chart showing a part of the manufacturing process of the semiconductor device of the second embodiment. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
<Semiconductor device>
A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The semiconductor device of the present embodiment is a semiconductor device having a MISFET as a semiconductor element.

  FIG. 1 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment.

  As shown in FIG. 1, the MISFET provided in the semiconductor device of the present embodiment is formed on a semiconductor substrate 1. The semiconductor substrate 1 is, for example, a single crystal silicon substrate. On the main surface of the semiconductor substrate 1, an element isolation region 2 and MISFET formation regions (active regions) AN1, AP1, AN2, and AP2 are defined. The MISFET formation regions AN1, AP1, AN2, and AP2 are regions partitioned by the element isolation region 2. The MISFET formation region AN1 is a region (n-type MISFET formation region AN1) where an n-channel type MISFET QN1 is formed. The MISFET formation region AP1 is a region where the p-channel type MISFET QP1 is formed (p-type MISFET formation region AP1). The MISFET formation region AN2 is a region (n-type MISFET formation region AN2) in which an n-channel type MISFET QN2 is formed. The MISFET formation region AP2 is a region where the p-channel MISFET QP2 is formed (p-type MISFET formation region AP2). The threshold voltage (Vth) of the n-channel type MISFET QN2 formed in the MISFET formation region AN2 is smaller than the threshold voltage (Vth) of the n-channel type MISFET QN1 formed in the MISFET formation region AN1. The threshold voltage (Vth) of the p-channel type MISFET QP2 formed in the MISFET formation region AP2 is smaller than the threshold voltage (Vth) of the p-channel type MISFET QP1 formed in the MISFET formation region AP1.

  In the present specification, when the magnitude of the threshold voltage (Vth) is compared, the magnitude of the absolute value of the threshold voltage (Vth) is compared. Further, in FIG. 1, for the sake of easy understanding, the MISFET formation regions AN1, AP1, AN2, and AP2 are shown adjacent to each other, but the actual positional relationship between the MISFET formation regions AN1, AP1, AN2, and AP2 is shown. Can be changed as needed.

  A p-type well region PW is formed in the semiconductor substrate 1 in the n-type MISFET formation regions AN1 and AN2. An n-type well region NW is formed in the semiconductor substrate 1 in the p-type MISFET formation regions AP1 and AP2.

  First, a specific configuration of the n-channel MISFET QN1 having a large threshold voltage (Vth) formed in the n-type MISFET formation region AN1 will be described.

  The n-channel type MISFET QN1 has a gate electrode GE formed on the semiconductor substrate 1. The gate electrode GE is formed on the p-type well region PW formed in the semiconductor substrate 1 in the n-type MISFET formation region AN1. Further, the n-channel type MISFET QN1 includes a gate insulating film GI1 formed between the gate electrode GE and the semiconductor substrate 1. That is, the n-channel type MISFET QN1 includes a gate insulating film GI1 formed on the semiconductor substrate 1 and a gate electrode GE formed on the gate insulating film GI1.

  As the gate electrode GE, for example, a conductor film made of polycrystalline silicon (doped polysilicon) in which impurities are introduced to achieve low resistivity is used. Alternatively, as the gate electrode GE, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), or tantalum nitride carbide (TaCN) ) Is used. Alternatively, a MIPS (Metal Inserted Poly-silicon Stack) structure which is a laminated structure of a conductive film made of a material other than polycrystalline silicon and a conductive film made of polycrystalline silicon may be used.

  The gate insulating film GI1 contains silicon, oxygen, and metal. The gate insulating film GI1 includes an insulating film 3 made of, for example, silicon oxide (SiO), and a metal-containing insulating film formed on the insulating film 3 by diffusing a metal such as hafnium (Hf) into the insulating film 3. 3a. For example, a metal-containing film 4 containing a metal such as hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), etc. on the insulating film 3 made of silicon oxide (SiO) (see FIG. 13 described later). ), The insulating film 3 and the metal-containing film 4 are reacted by annealing, and then the unreacted metal-containing film 4 is removed, so that a portion of the insulating film 3 opposite to the semiconductor substrate 1 is formed. A metal-containing insulating film 3a is formed. During the annealing process, the metal contained in the metal-containing film 4 diffuses into the insulating film 3 from the interface between the metal-containing film 4 and the insulating film 3, so that the side of the insulating film 3 opposite to the semiconductor substrate 1. The portion becomes the metal-containing insulating film 3a. In the metal-containing insulating film 3a, the concentration of metal such as hafnium (Hf) decreases from the gate electrode GE side to the semiconductor substrate 1 side.

  Over the side wall of the gate electrode GE, a side wall spacer SW is formed as a side wall insulating film. In the n-type MISFET formation region AN1, source / drain regions SD are formed on both sides of the gate electrode GE on which the sidewall spacer SW is formed. In the n-type MISFET formation region AN1, the source / drain region SD is an n-type semiconductor region in which an n-type impurity such as phosphorus (P) or arsenic (As) is diffused.

  In the n-type MISFET formation region AN1, an extension region EX and a source / drain region SD having a higher impurity concentration than that are formed in the semiconductor substrate 1, thereby providing a source / drain having an LDD (Lightly doped Drain) structure. A region is formed.

  A metal silicide layer such as a cobalt silicide layer or a nickel silicide layer can be formed on the source / drain region SD and the gate electrode GE by using a salicide (Self Aligned Silicide) technique.

  Next, a specific configuration of the p-channel MISFET QP1 formed in the p-type MISFET formation region AP1 and having a large threshold voltage (Vth) will be described.

  The p-channel type MISFET QP <b> 1 has a gate electrode GE formed on the semiconductor substrate 1. The gate electrode GE is formed on the n-type well region NW formed in the semiconductor substrate 1 in the p-type MISFET formation region AP1. The p-channel type MISFET QP1 has a gate insulating film GI1 formed between the gate electrode GE and the semiconductor substrate 1. That is, the p-channel type MISFET QP1 has a gate insulating film GI1 formed on the semiconductor substrate 1 and a gate electrode GE formed on the gate insulating film GI1.

  As the gate electrode GE, the same material as that of the gate electrode GE of the n-channel type MISFET QN1 can be used.

  Similarly to the gate insulating film GI1 of the n-channel type MISFET QN1, the gate insulating film GI1 contains silicon, oxygen, and metal, and includes an insulating film 3 made of, for example, silicon oxide (SiO), and hafnium (Hf), for example. The metal diffuses into the insulating film 3, thereby having the metal-containing insulating film 3 a formed on the insulating film 3.

  Over the side wall of the gate electrode GE, a side wall spacer SW is formed as a side wall insulating film. In the p-type MISFET formation region AP1, source / drain regions SD are formed on both sides of the gate electrode GE on which the sidewall spacer SW is formed. In the p-type MISFET formation region AP1, the source / drain region SD is a p-type semiconductor region in which a p-type impurity such as boron (B) is diffused.

  Also in the p-type MISFET formation region AP1, the extension region EX is formed in the semiconductor substrate 1, and the source / drain region SD having the LDD structure is formed. Furthermore, in the p-type MISFET formation region AP1, a metal silicide layer can be formed on the source / drain region SD and the gate electrode GE by using a salicide technique.

  Next, a specific configuration of the n-channel MISFET QN2 having a small threshold voltage (Vth) formed in the n-type MISFET formation region AN2 will be described.

  The n-channel type MISFET QN2 has a gate electrode GE formed on the semiconductor substrate 1. The gate electrode GE is formed on the p-type well region PW formed in the semiconductor substrate 1 in the n-type MISFET formation region AN2. Further, the n-channel type MISFET QN2 has a gate insulating film GI2 formed between the gate electrode GE and the semiconductor substrate 1. That is, the n-channel type MISFET QN2 has a gate insulating film GI2 formed on the semiconductor substrate 1 and a gate electrode GE formed on the gate insulating film GI2.

  As the gate electrode GE, the same material as that of the gate electrode GE of the n-channel type MISFET QN1 can be used.

  The gate insulating film GI2 contains silicon and oxygen. The gate insulating film GI2 includes an insulating film 3 made of, for example, silicon oxide (SiO). Unlike the gate insulating film GI1 of the n-channel type MISFET QN1, the gate insulating film GI2 does not contain a metal such as hafnium (Hf). Thus, the threshold voltage (Vth) of the n-channel type MISFET QN2 can be made smaller than the threshold voltage (Vth) of the n-channel type MISFET QN1 without changing the impurity concentration of the channel region. Further, by reducing the threshold voltage (Vth) without changing the impurity concentration of the channel region, it is possible to prevent the transistor characteristics of the MISFET having a short channel length from deteriorating, and without reducing the performance of the semiconductor device. (Vth) can be arbitrarily adjusted.

  Hereinafter, an example in which the gate insulating film GI2 does not contain, for example, a metal made of hafnium (Hf) will be described. However, the gate insulating film GI2 is made of a metal (for example, hafnium (Hf)) in the gate insulating film GI2. The concentration should be lower than the concentration of the metal in the gate insulating film GI1. Therefore, for example, by making the insulating film 3 itself contain silicon, oxygen, and metal, a metal such as hafnium (Hf) is smaller than the concentration in the gate insulating film GI1 as the gate insulating film GI2. You may use what is contained with a density | concentration.

  Over the side wall of the gate electrode GE, a side wall spacer SW is formed as a side wall insulating film. In the n-type MISFET formation region AN2, source / drain regions SD are formed on both sides of the gate electrode GE on which the sidewall spacer SW is formed. In the n-type MISFET formation region AN2, the source / drain region SD is an n-type semiconductor region in which an n-type impurity such as phosphorus (P) or arsenic (As) is diffused.

  Further, also in the n-type MISFET formation region AN2, the extension region EX is formed in the semiconductor substrate 1, and the source / drain region SD having the LDD structure is formed. Furthermore, in the n-type MISFET formation region AN2, a metal silicide layer can be formed on the source / drain region SD and the gate electrode GE by using a salicide technique.

  Next, a specific configuration of the p-channel MISFET QP2 formed in the p-type MISFET formation region AP2 and having a small threshold voltage (Vth) will be described.

  The p-channel type MISFET QP <b> 2 has a gate electrode GE formed on the semiconductor substrate 1. The gate electrode GE is formed on the n-type well region NW formed in the semiconductor substrate 1 in the p-type MISFET formation region AP2. The p-channel type MISFET QP2 has a gate insulating film GI2 formed between the gate electrode GE and the semiconductor substrate 1. That is, the p-channel type MISFET QP2 has a gate insulating film GI2 formed on the semiconductor substrate 1 and a gate electrode GE formed on the gate insulating film GI2.

  As the gate electrode GE, the same material as the gate electrode GE of the n-channel type MISFET QN2 can be used.

  Similarly to the gate insulating film GI2 of the n-channel type MISFET QN2, the gate insulating film GI2 includes silicon and oxygen, and includes the insulating film 3 made of, for example, silicon oxide (SiO). Unlike the gate insulating film GI1 of the p-channel type MISFET QP1, the gate insulating film GI2 does not contain a metal such as hafnium (Hf). Thus, the threshold voltage (Vth) of the p-channel type MISFET QP2 can be made smaller than the threshold voltage (Vth) of the p-channel type MISFET QP1 without changing the impurity concentration of the channel region. Further, by reducing the threshold voltage (Vth) without changing the impurity concentration of the channel region, it is possible to prevent the transistor characteristics of the MISFET having a short channel length from deteriorating, and without reducing the performance of the semiconductor device. (Vth) can be arbitrarily adjusted.

  Similar to the gate insulating film GI2 of the MISFET QN2, as the gate insulating film GI2 of the MISFET QP2, a film containing a metal such as hafnium (Hf) at a concentration lower than the concentration in the gate insulating film GI1 may be used.

  Over the side wall of the gate electrode GE, a side wall spacer SW is formed as a side wall insulating film. In the p-type MISFET formation region AP2, source / drain regions SD are formed on both sides of the gate electrode GE on which the sidewall spacer SW is formed. In the p-type MISFET formation region AP2, the source / drain region SD is a p-type semiconductor region in which a p-type impurity such as boron (B) is diffused.

  Further, also in the p-type MISFET formation region AP2, the extension region EX is formed in the semiconductor substrate 1, and the source / drain region SD having the LDD structure is formed. Further, in the p-type MISFET formation region AP2, a metal silicide layer can be formed on the source / drain region SD and the gate electrode GE by using a salicide technique.

  In the example described with reference to FIG. 1, the insulating film 3 in the MISFETs QN1, QP1, QN2, and QP2 has the same film thickness and is displayed as a single-layer film for easy understanding. . However, in order to create a plurality of types of MISFETs such as a MISFET as a core transistor and a MISFET as an I / O (Input / Output) transistor, for example, between a plurality of regions such as a core transistor formation region and an I / O transistor formation region. Thus, the insulating film 3 may have different thicknesses, or may be a stack of a plurality of layers having different numbers of layers. Furthermore, for example, the insulating film 3 may have different compositions such as the presence or absence of nitridation between a plurality of regions such as a core transistor formation region and an I / O transistor formation region.

  In the element isolation region 2, an element isolation groove 2a is formed in the main surface of the semiconductor substrate 1, and an insulating film 2b is embedded in the formed element isolation groove 2a. The insulating film 2b includes an n-channel MISFET QN1 formed in the n-type MISFET formation region AN1, a p-channel MISFET QP1 formed in the p-type MISFET formation region AP1, and an n-channel type formed in the n-type MISFET formation region AN2. The MISFET QN2 and the p-channel MISFET QP2 formed in the p-type MISFET formation region AP2 are separated from each other. The insulating film 2b is preferably made of a silicon oxide film. The insulating film 2b is formed by, for example, an STI (Shallow Trench Isolation) method as will be described later.

  An interlayer insulating film 5 is formed on the entire main surface (front surface) of the semiconductor substrate 1 so as to cover the gate electrodes GE, the side wall spacers SW, and the source / drain regions SD of the MISFETs QN1, QP1, QN2, and QP2. ing. The interlayer insulating film 5 is made of, for example, a single film of a silicon oxide film or a laminated film of a silicon nitride film and a thicker silicon oxide film (the silicon nitride film is on the lower layer side), and the upper surface of the interlayer insulating film 5 Is flattened so that the heights thereof substantially coincide in the MISFET formation regions AN1, AP1, AN2, and AP2.

  A contact hole CNT is formed in the interlayer insulating film 5, and a conductive plug PG is formed in the contact hole CNT. The contact hole CNT and the plug PG filling the contact hole CNT are formed on the source / drain regions SD of the MISFET formation regions AN1, AP1, AN2, and AP2, the gate electrode GE, and the like. The bottom of the plug PG is electrically connected to the source / drain region SD and the gate electrode GE formed in the MISFET formation regions AN1, AP1, AN2, and AP2.

  An insulating film 6 made of, for example, a silicon oxide film is formed on the interlayer insulating film 5 in which the plug PG is embedded, and the first layer wiring is formed in a wiring groove (opening) formed in the insulating film 6. The wiring M1 is formed. The wiring M1 is electrically connected to the source / drain region SD, the gate electrode GE, and the like formed in the MISFET formation regions AN1, AP1, AN2, and AP2 through the plug PG.

  The wiring M1 is formed by a damascene technique (here, a single damascene technique), but may be formed by a patterned conductor film (for example, a tungsten wiring or an aluminum wiring) as another form.

<Manufacturing process of semiconductor device>
A manufacturing process of the semiconductor device of the present embodiment will be described with reference to the drawings. 2 and 3 are manufacturing process flow charts showing a part of the manufacturing process of the semiconductor device of the first embodiment. 4 to 22 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of First Embodiment.

  First, as shown in FIG. 4, the semiconductor substrate 1 is prepared (step S11 in FIG. 2). In step S11, a semiconductor substrate 1 made of p-type single crystal silicon (Si) having a specific resistance of, for example, about 1 to 10 Ωcm is prepared.

  Next, as shown in FIG. 5, an element isolation groove 2a is formed in the element isolation region 2 (step S12 in FIG. 2). In step S12, the semiconductor substrate 1 is dry-etched to form an element isolation trench 2a having a depth of, for example, about 300 nm in the semiconductor substrate 1.

  In step S12, an insulating film (not shown) made of silicon oxide and an insulating film (not shown) made of silicon nitride are sequentially formed on the entire main surface (front surface) of the semiconductor substrate 1, and then a photoresist. The element isolation trench 2a can be formed by dry etching using a pattern (not shown) as an etching mask.

  Next, as shown in FIG. 6, an insulating film 2b is formed in the element isolation region 2 (step S13 in FIG. 2). In this step S13, an insulating film 2b is formed on the entire main surface (front surface) of the semiconductor substrate 1 so as to fill the element isolation trench 2a, and the insulating film 2b embedded in the element isolation trench 2a is baked. Then, the insulating film 2b is polished by a CMP (Chemical Mechanical Polishing) method. The insulating film 2b is made of, for example, a silicon oxide film, and is formed by, for example, a plasma CVD (Chemical Vapor Deposition) method. The heat treatment can be performed by heat-treating the semiconductor substrate 1 at about 400 to 1200 ° C., for example.

  Before forming the insulating film 2b, a thin insulating film (not shown) made of, for example, silicon nitride is formed on the entire main surface (front surface) of the semiconductor substrate 1 including the inside of the element isolation trench 2a. You may make it prevent that the side wall of the element isolation groove | channel 2a is oxidized by the above-mentioned heat processing.

  In addition, after polishing by the CMP method, a treatment for reducing the step between the insulating film 2b embedded in the element isolation trench 2a and the semiconductor substrate 1 is performed. FIG. 6 shows a case where the height position of the upper surface of the insulating film 2b in the element isolation trench 2a is substantially equal to the height position of the upper surface of the semiconductor substrate 1 and the level difference is reduced.

  Thus, as shown in FIG. 6, in the element isolation region 2, the insulating film 2b is formed by the STI method. In the semiconductor substrate 1, MISFET formation regions (active regions) AN 1, AP 1, AN 2, and AP 2 are defined (defined) by the element isolation region 2. In the MISFET formation regions AN1, AP1, AN2, and AP2, various semiconductor elements (for example, MISFETs QN1, QP1, QN2, and QP2, which will be described later) are formed in the following steps.

  Next, as shown in FIG. 7, a step of forming a well region over a predetermined depth from the upper surface of the semiconductor substrate 1 is performed (step S14 in FIG. 2). In step S14, the process of forming the well region is repeated twice. The first time forms a p-type well region PW containing a p-type impurity (for example, boron) in the semiconductor substrate 1, and the second time forms an n-type impurity (for example, phosphorus or arsenic) in the semiconductor substrate 1. And the like are formed.

The p-type well region PW can be formed, for example, by introducing a p-type impurity into the semiconductor substrate 1 using an ion implantation method. First, after applying a photoresist layer on the entire main surface (front surface) of the semiconductor substrate 1, the photoresist layer is exposed and developed so as to have openings in the MISFET formation regions AN1 and AN2. A resist pattern (not shown) is formed. Then, using the formed photoresist pattern as a mask, for example, boron (B) is ion-implanted at a concentration of 5 × 10 ^{12 to} 5 × 10 ¹³ / cm ² , and the impurity concentration (impurity concentration) is A p-type well region PW of 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ is formed. Thereafter, the photoresist pattern is removed.

The n-type well region NW can be formed, for example, by introducing an n-type impurity into the semiconductor substrate 1 using an ion implantation method. First, after applying a photoresist layer over the entire main surface (front surface) of the semiconductor substrate 1, the photoresist layer is exposed and developed so as to have openings in the MISFET formation regions AP1 and AP2. A resist pattern (not shown) is formed. Then, using the formed photoresist pattern as a mask, phosphorus (P) or arsenic (As) is ion-implanted at a concentration of 5 × 10 ^{12 to} 5 × 10 ¹³ / cm ² , for example, and the impurity concentration ( An n-type well region NW having an impurity concentration of 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ is formed. Thereafter, the photoresist pattern is removed.

  Next, as shown in FIG. 8, the insulating film 3 is formed on the semiconductor substrate 1 (step S15 in FIG. 2). In this step S15, the insulating film 3 made of, for example, silicon oxide having a thickness of about 2 nm is formed on the entire main surface (front surface) of the semiconductor substrate 1 by, for example, thermal oxidation.

  Next, as shown in FIG. 9, a mask film 9 is formed on the semiconductor substrate 1 (step S16 in FIG. 2). In this step S16, for example, the mask film 9 having a thickness of about 10 to 50 nm is formed by sputtering (PVD (Physical Vapor Deposition)), thermal CVD, or the like. In the later process (step S18 in FIG. 2), the mask film 9 is partially etched in the MISFET formation regions AN1 and AP1 by dry etching. In the later process (step S20 in FIG. 2), the MISFET formation is performed. The metal-containing film 4 (see FIG. 13) is prevented from being formed on the insulating film 3 in the regions AN2 and AP2. Further, all of the mask film 9 is removed by wet etching in a later process (step S22 in FIG. 2). Therefore, a film made of titanium nitride (TiN) or tantalum nitride (TaN) is preferably used as the mask film 9. By using the materials described above, the mask film 9 can be easily formed, and when the mask film 9 is partially removed, the metal film 4 can be easily removed. This is because the state in which the insulating film 3 is covered with the mask film 9 can be maintained in the MISFET formation regions AN2 and AP2, and when the entire mask film 9 is subsequently removed, it can be easily removed.

  Next, as shown in FIG. 10, a photoresist pattern PR1 is formed on the semiconductor substrate 1 (step S17 in FIG. 2). In this step S17, a photoresist layer is applied to the entire main surface (front surface) of the semiconductor substrate 1, and then the photoresist layer is exposed and developed to have openings in the MISFET formation regions AN1 and AP1. Next, a photoresist pattern PR1 is formed.

  Next, as shown in FIG. 11, the mask film 9 is dry-etched using the photoresist pattern PR1 as an etching mask (step S18 in FIG. 2). In this step S18, the mask film 9 is removed by dry etching using the photoresist pattern PR1 having openings in the MISFET formation regions AN1 and AP1 as an etching mask, whereby the mask film 9 is removed in the MISFET formation regions AN1 and AP1. The film 3 is exposed.

  Next, as shown in FIG. 12, the photoresist pattern PR1 is removed (step S19 in FIG. 2). In this step S19, the photoresist pattern PR1 is removed by performing, for example, an ashing process and a cleaning process using a processing solution such as an SPM (Sulfuric Acid-Hydrogen Peroxide Mixture) solution. Thereby, the hard mask pattern 10 including the mask film 9 is formed so that the MISFET formation regions AN1 and AP1 have openings and the insulating film 3 is covered with the MISFET formation regions AN2 and AP2. That is, the hard mask pattern 10 made of the mask film 9 is formed so that the insulating film 3 is exposed in the MISFET forming regions AN1 and AP1, and the insulating film 3 is covered in the MISFET forming regions AN2 and AP2.

  Next, as shown in FIG. 13, a metal-containing film 4 is formed (deposited) on the semiconductor substrate 1 (step S20 in FIG. 2). In this step S20, with the insulating film 3 in the MISFET formation regions AN2 and AP2 covered with the hard mask pattern 10 (mask film 9), the entire main surface (front surface) of the semiconductor substrate 1 is, for example, ALD (Atomic Layer Deposition). : Atomic layer deposition), for example, the metal-containing film 4 having a thickness of about 1 nm is formed. As a result, in the MISFET formation regions AN1 and AP1, for example, a metal-containing film 4 having a thickness of about 1 nm is formed on the upper surface of the insulating film 3 made of silicon oxide having a thickness of about 2 nm, for example. In the MISFET formation regions AN2 and AP2, a metal-containing film 4 having a thickness of, for example, about 1 nm is formed on the upper surface and side surfaces of the hard mask pattern 10 (mask film 9) made of, for example, titanium nitride (TiN).

  As the metal-containing film 4, for example, a film containing a metal such as hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), or the like is used. Thereby, the threshold voltage (Vth) can be adjusted without changing the impurity concentration of the channel region.

  Next, as shown in FIG. 14, the semiconductor substrate 1 is annealed (heat treated) (step S21 in FIG. 2). In this step S21, the semiconductor substrate 1 is subjected to an annealing process such as RTA (Rapid Thermal Anneal). Thereby, in the MISFET formation regions AN1 and AP1, the insulating film 3 and the metal-containing film 4 react, and the metal contained in the metal-containing film 4 is transferred from the interface between the metal-containing film 4 and the insulating film 3 to the insulating film 3. By diffusing inside, the portion of the insulating film 3 opposite to the semiconductor substrate 1 becomes the metal-containing insulating film 3a. In the metal-containing insulating film 3a, the concentration of metal such as hafnium (Hf) decreases from the metal-containing film 4 side toward the semiconductor substrate 1 side.

  In addition, it is preferable to perform annealing treatment on the conditions of temperature 600-1000 degreeC, for example in nitrogen atmosphere. When the temperature is lower than 600 ° C., the metal contained in the metal-containing film 4 may not be sufficiently diffused into the insulating film 3. When the temperature exceeds 1000 ° C., the semiconductor substrate 1 including the insulating film 3 and the metal-containing film 4 may be altered.

  When the metal contained in the metal-containing film 4 is hafnium (Hf), the metal-containing insulating film 3a is one of hafnium oxide (HfO), hafnium oxynitride (HfON), and silicon-containing hafnium oxynitride (HfSiON). It consists of more than seeds.

  If step S21 is not performed, when the hard mask pattern 10 (mask film 9) is removed in the subsequent process (step S22), the metal-containing film 4 in the MISFET formation region AN1 and AP1 is also removed, and the MISFET QN1. In addition, the metal contained in the metal-containing film 4 cannot be added to the gate insulating film GI1 of QP1. Therefore, by performing step S21, the metal contained in the metal-containing film 4 can be reliably added to the gate insulating film GI1 of the MISFETs QN1 and QP1.

  After performing step S21, the unreacted metal-containing film 4 remains on the metal-containing insulating film 3a in the MISFET formation regions AN1 and AP1 that are not covered with the hard mask pattern 10 (mask film 9). In the MISFET formation regions AN2 and AP2 covered with the hard mask pattern 10 (mask film 9), the metal-containing film 4 remains on the upper surface and side surfaces of the hard mask pattern 10 (mask film 9). Although illustration is omitted, a part of the metal-containing film 4 may react with the hard mask pattern 10 (mask film 9) on the top and side surfaces of the hard mask pattern 10 (mask film 9).

  Next, as shown in FIG. 15, wet etching is performed (step S22 in FIG. 2). In this step S22, the hard mask pattern 10 (mask film 9) is removed by wet etching. When the hard mask pattern 10 (mask film 9) is made of, for example, titanium nitride (TiN) or tantalum nitride (TaN), an SPM solution is suitably used as a chemical solution (etching solution) for wet etching. In the MISFET formation regions AN2 and AP2 that were covered with the hard mask pattern 10 (mask film 9) until immediately before step S22, the hard mask pattern 10 (mask film 9) is the upper surface of the hard mask pattern 10 (mask film 9) and By removing together with the metal-containing film 4 formed on the side surface, the insulating film 3 is exposed. On the other hand, in the MISFET formation regions AN1 and AP1 that have not been covered with the hard mask pattern 10 (mask film 9) before step S22, the metal-containing film 4 is removed by removing an unreacted portion. The insulating film 3a is exposed.

  As described above, after the insulating film 3 is formed on the semiconductor substrate 1 by the process of step S15, the processes of steps S16 to S22 are performed to form the MISFET formation regions AN1 and AP1 on the semiconductor substrate 1. An insulating film 11 including the insulating film 3 and the metal-containing insulating film 3a formed on the insulating film 3 is formed. In the MISFET formation regions AN2 and AP2, an insulating film 12 made only of the insulating film 3 formed on the semiconductor substrate 1 is formed. That is, the metal-containing insulating film 3a can be selectively formed in the MISFET formation regions AN1 and AP1 using the hard mask pattern 10 (mask film 9). Alternatively, in the MISFET formation regions AN1 and AP1, the insulating film 3 and the metal-containing insulating film 3a may not be clearly separated. At this time, by performing the processes up to step S22, the insulating film 11 to which the metal is added is formed in the MISFET formation regions AN1 and AP1, and the insulating film to which the metal is not added in the MISFET formation regions AN2 and AP2. 12 is formed.

  As will be described in detail later, in the present embodiment, when the metal-containing insulating film 3a is formed in the MISFET formation regions AN1 and AP1, the metal-containing film 4 and the metal-containing insulating film 3a are in contact with the resist pattern. There is no. Further, when the resist pattern is removed, the metal-containing insulating film 3a is not damaged by ashing. Therefore, the reliability of the gate insulating film can be ensured.

  Next, as shown in FIG. 16, a conductive film 13 for a gate electrode is formed on the semiconductor substrate 1 (step S23 in FIG. 3). In this step S23, the conductor film 13 for the gate electrode is formed on the entire main surface (front surface) of the semiconductor substrate 1. As the conductor film 13 for the gate electrode, for example, a conductor film made of polycrystalline silicon (doped polysilicon) can be used.

  Next, as shown in FIG. 17, a photoresist layer PR2 is formed by applying a photoresist layer on the entire main surface (front surface) of the semiconductor substrate 1 and then exposing and developing (see FIG. 3). Step S24).

  Next, the gate electrode GE and the gate insulating films GI1 and GI2 are formed (Step S25 in FIG. 3). In this step S25, the conductor film 13, the metal-containing insulating film 3a, and the insulating film 3 are etched by dry etching using the photoresist pattern PR2 as an etching mask. That is, the conductor film 13 and the insulating film 11 are etched in the MISFET formation regions AN1 and AP1, and the conductor film 13 and the insulating film 12 are etched in the MISFET formation regions AN2 and AP2. As a result, as shown in FIG. 18, patterned gate electrode GE and gate insulating film GI1 are formed in MISFET formation regions AN1 and AP1. On the other hand, in the MISFET formation regions AN2 and AP2, the patterned gate electrode GE and gate insulating film GI2 are formed. Thereafter, the photoresist pattern PR2 is removed. FIG. 18 shows a stage (state) where the photoresist pattern PR2 is removed. The gate insulating film GI1 includes an insulating film 3 formed on the semiconductor substrate 1 and a metal-containing insulating film 3a formed on the insulating film 3. The gate insulating film GI <b> 2 is composed only of the insulating film 3 formed on the semiconductor substrate 1.

  Next, as shown in FIG. 19, the extension region EX is formed (step S26 in FIG. 3). In this step S26, first, in the MISFET formation regions AN1 and AN2, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into regions on both sides of the gate electrode GE of the p-type well region PW. The n-type extension region EX is formed. In the MISFET formation regions AP1 and AP2, p-type extension regions EX are formed by ion-implanting p-type impurities such as boron (B) into the regions on both sides of the gate electrode GE in the n-type well region NW. . Since the gate electrode GE can function as an ion implantation blocking mask during this ion implantation, the extension region EX is formed in alignment (self-alignment) with a region immediately below the gate electrode GE.

  Next, as shown in FIG. 20, a sidewall spacer SW made of, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof is formed as a sidewall insulating film on the sidewall of the gate electrode GE (FIG. 3). Step S27). In this step S27, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof is deposited on the entire main surface (front surface) of the semiconductor substrate 1, and the silicon oxide film, the silicon nitride film, or the laminated film is RIE. Sidewall spacers SW are formed by anisotropic etching using a (Reactive Ion Etching) method or the like.

  Next, the source / drain region SD is formed (step S28 in FIG. 3). In this step S28, in the MISFET formation regions AN1 and AN2, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into regions on both sides of the gate electrode GE and the sidewall spacer SW in the p-type well region PW. As a result, n-type source / drain regions SD are formed. In the MISFET formation regions AP1 and AP2, a p-type source is formed by ion-implanting a p-type impurity such as boron (B) into the regions on both sides of the gate electrode GE and the sidewall spacer SW in the n-type well region NW. -Drain region SD is formed. During this ion implantation, the gate electrode GE and the sidewall spacer SW on the side wall thereof can function as an ion implantation blocking mask, so that the source / drain region SD is aligned with the region immediately below the gate electrode GE (self Formed). After the ion implantation for forming the source / drain regions SD, an annealing process for activating the introduced impurities is performed. This annealing process can be performed, for example, by a flash lamp annealing process at about 1050 ° C.

  Thus, as shown in FIG. 21, the semiconductor region functioning as the source or drain of the LDD structure is formed by the pair of the extension region EX and the source / drain region SD formed on one side of the gate electrode GE. It is formed. The source / drain region SD has a higher impurity concentration and a deeper depth (junction depth) than the extension region EX. Then, each of the MISFETs QN1, QP1, QN2, and QP2 is formed in each of the MISFET formation regions AN1, AP1, AN2, and AP2.

  Each of the MISFETs QN1 and QP1 formed in each of the MISFET formation regions AN1 and AP1 has a gate insulating film GI1 including the insulating film 3 and the metal-containing insulating film 3a formed on the insulating film 3. Each of the MISFETs QN2 and QP2 formed in each of the MISFET formation regions AN2 and AP2 has a gate insulating film GI2 made of only the insulating film 3. The gate insulating film GI1 contains a metal such as hafnium (Hf), and the gate insulating film GI2 does not contain a metal such as hafnium (Hf). Therefore, an n-channel MISFET QN1 having a large threshold voltage (Vth) is formed in the n-type MISFET formation region AN1, and an n-channel MISFET QN2 having a small threshold voltage (Vth) is formed in the n-type MISFET formation region AN2. . Further, a p-channel type MISFET QP1 having a large threshold voltage (Vth) is formed in the p-type MISFET formation region AP1, and a p-channel type MISFET QP2 having a small threshold voltage (Vth) is formed in the p-type MISFET formation region AP2. .

  After step S28 and before step S29 described later, a low-resistance metal silicide layer made of cobalt silicide, nickel silicide, or the like is formed on the surfaces of the gate electrode GE and the source / drain regions SD by the salicide technique. Also good.

  Next, as shown in FIG. 22, the interlayer insulating film 5 and the plug PG are formed (step S29 in FIG. 3).

  In this step S29, first, the interlayer insulating film 5 is formed on the entire main surface (front surface) of the semiconductor substrate 1. That is, the interlayer insulating film 5 is formed on the entire main surface (front surface) of the semiconductor substrate 1 so as to cover the gate electrode GE and the sidewall spacer SW. The interlayer insulating film 5 is made of, for example, a single film of a silicon oxide film or a laminated film of a silicon nitride film and a thicker silicon oxide film. Thereafter, the upper surface of the interlayer insulating film 5 is flattened by polishing the surface (upper surface) of the interlayer insulating film 5 by CMP or the like. Even if unevenness is formed on the surface of the interlayer insulating film 5 due to the base step, by polishing the surface of the interlayer insulating film 5 by the CMP method, an interlayer insulating film having a flattened surface can be obtained. Can do.

  Next, the interlayer insulating film 5 is dry-etched using a photoresist pattern (not shown) formed on the interlayer insulating film 5 as an etching mask, thereby forming contact holes CNT in the interlayer insulating film 5. At the bottom of the contact hole CNT, a part of the main surface of the semiconductor substrate 1, for example, a part of the gate electrode GE and a part of the source / drain region SD are exposed.

  Next, a conductive plug PG made of tungsten (W) or the like is formed in the contact hole CNT. In order to form the plug PG, for example, a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof) is formed on the interlayer insulating film 5 including the inside of the contact hole CNT by a plasma CVD method or the like. . Then, a main conductor film made of a tungsten film or the like is formed by CVD or the like so as to fill the contact hole CNT on the barrier conductor film, and unnecessary main conductor films and barrier conductor films on the interlayer insulating film 5 are formed by CMP. Alternatively, the plug PG can be formed by removing by an etch-back method or the like. In FIG. 22, for simplification of the drawing, the plug PG shows the main conductor film and the barrier conductor film integrally. The plug PG is in electrical contact with the gate electrode GE or the source / drain region SD at the bottom.

  Next, the insulating film 6 is formed on the interlayer insulating film 5 in which the plug PG is embedded. The insulating film 6 can also be formed of a stacked film of a plurality of insulating films.

  Next, the wiring M1 which is the first layer wiring is formed by the single damascene method (step S30 in FIG. 3). In step S30, specifically, the wiring M1 can be formed as follows. First, after forming a wiring groove in a predetermined region of the insulating film 6 by dry etching (plasma dry etching) using a photoresist pattern (not shown) as a mask, the insulating film 6 including the bottom and side walls of the wiring groove is formed. A barrier conductor film (for example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like) is formed. Subsequently, a copper seed layer is formed on the barrier conductor film by a CVD method or a sputtering method, and a copper plating film is further formed on the seed layer by using an electrolytic plating method. Embed the inside. Then, the main conductor film (copper plating film and seed layer) and the barrier conductor film in the region other than the wiring groove are removed by polishing by CMP, thereby filling the wiring groove and using copper as the main conductive material. A layer wiring M1 is formed. As a result, as shown in FIG. 1, a semiconductor device having a structure in which the layers up to the first layer wiring M1 are formed is manufactured. In FIG. 1, for simplification of the drawing, the wiring M1 is shown by integrating a barrier conductor film, a seed layer, and a copper plating film.

  The wiring M1 is electrically connected to the gate electrode GE or the source / drain region SD through the plug PG. Thereafter, a second layer wiring is formed by a dual damascene method, but illustration and description thereof are omitted here.

<Patterning of metal-containing insulating film by photoresist pattern>
A manufacturing process of the semiconductor device of the comparative example will be described with reference to the drawings. FIG. 23 is a manufacturing process flow chart showing a part of the manufacturing process of the semiconductor device of the comparative example. 24 to 29 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the comparative example.

  The manufacturing process of the semiconductor device of the comparative example is to manufacture a semiconductor device similar to the semiconductor device of the first embodiment.

  In the manufacturing process of the semiconductor device of the comparative example, a photoresist pattern is used as a mask for patterning the metal-containing insulating film, not a hard mask pattern made of a mask film.

  In the semiconductor device manufacturing process of the comparative example, steps S11 to S15 in FIG. 23 are the same as steps S11 to S15 in FIG. 2 in the semiconductor device manufacturing process of the first embodiment. Description of the process is omitted.

  After the steps S11 to S15 are performed and the insulating film 3 is formed, the metal-containing film 4 is formed on the semiconductor substrate 1 as shown in FIG. (Deposition) (step S116 in FIG. 23). In step S116, the metal-containing film 4 having a thickness of, for example, about 1 nm is formed on the entire main surface (front surface) of the semiconductor substrate 1 by, for example, the ALD method.

  Next, as shown in FIG. 25, the semiconductor substrate 1 is annealed (step S117 in FIG. 23). In step S117, the semiconductor substrate 1 is subjected to an annealing process such as RTA. As a result, the insulating film 3 and the metal-containing film 4 react, and the metal contained in the metal-containing film 4 diffuses into the insulating film 3 from the interface between the metal-containing film 4 and the insulating film 3, thereby insulating the metal. A portion of the film 3 opposite to the semiconductor substrate 1 becomes the metal-containing insulating film 3a.

  Next, as shown in FIG. 26, wet etching is performed (step S118 in FIG. 23). In step S118, the metal-containing insulating film 3a is exposed by removing the unreacted portion of the metal-containing film 4 by wet etching using, for example, an SPM solution.

  Next, as shown in FIG. 27, a photoresist pattern PR101 is formed on the semiconductor substrate 1 (step S119 in FIG. 23). In this step S119, after applying a photoresist layer on the entire main surface (front surface) of the semiconductor substrate 1, the photoresist layer is exposed and developed to have openings in the MISFET formation regions AN2 and AP2. Next, a photoresist pattern PR101 is formed.

  Next, as shown in FIG. 28, the metal-containing insulating film 3a is dry-etched using the photoresist pattern PR101 as an etching mask (step S120 in FIG. 23). In this step S120, the metal-containing insulating film 3a is dry-etched using the photoresist pattern PR101 having openings in the MISFET forming regions AN2 and AP2 as an etching mask, so that the metal-containing insulating film 3a is formed in the MISFET forming regions AN2 and AP2. This is removed and the insulating film 3 is exposed.

  Next, as shown in FIG. 29, the photoresist pattern PR101 is removed (step S121 in FIG. 23). In step S121, the photoresist pattern PR101 is removed by performing, for example, an ashing process and a cleaning process using a processing solution such as an SPM solution. Thereby, the metal-containing insulating film 3a is exposed in the MISFET formation regions AN1 and AP1. That is, the metal-containing insulating film 3a is patterned using the photoresist pattern PR101.

  Thereafter, similarly to the manufacturing process of the semiconductor device of the first embodiment, the semiconductor device having the same structure as that of the first embodiment is manufactured by performing steps S23 to S30 of FIG.

  However, according to the analysis by the present inventor, it has been found that the performance of the semiconductor device is likely to deteriorate in the semiconductor device manufactured by the manufacturing process of the semiconductor device of the comparative example.

  When patterning is performed using a photoresist pattern as an etching mask, the shape accuracy of the formed pattern becomes worse as the line width of the photoresist pattern becomes finer. Therefore, for example, in a semiconductor device such as an SRAM of 32 nm node or less, it is difficult to perform patterning with high shape accuracy in the n-type MISFET formation region or the p-type MISFET formation region. It has been found that it is difficult to obtain desired characteristics in transistor characteristics such as voltage (Vth).

  In the manufacturing process of the semiconductor device of the comparative example, the photoresist pattern PR101 is in direct contact with the metal-containing insulating film 3a. For this reason, it has been found that the gate insulating film of the MISFET is likely to be deteriorated due to diffusion of the organic substance or the like contained in the photoresist pattern PR101 into the metal-containing insulating film 3a.

  In the manufacturing process of the semiconductor device of the comparative example, the metal-containing insulating film 3a or the insulating film 3 is exposed to plasma when the photoresist pattern PR101 is removed by ashing. For this reason, it has been found that the reliability of the gate insulating film of the MISFET is likely to be lowered when the metal-containing insulating film 3a or the insulating film 3 is damaged by the plasma.

<Main features and effects of the present embodiment>
Therefore, in this embodiment, the metal-containing insulating film is patterned using a hard mask pattern instead of the photoresist pattern.

  That is, in the present embodiment, after the hard mask pattern 10 is formed on the insulating film 3, the metal-containing film 4 is formed, and the insulating film 3 and the metal-containing film 4 are reacted by an annealing process. By removing the reactive metal-containing film 4 and the hard mask pattern 10, a pattern including a region where the metal-containing insulating film 3a is formed and a region where the metal-containing insulating film 3a is not formed is formed.

  When patterning using a hard mask pattern as an etching mask, even if the line width of the hard mask pattern is reduced, the shape accuracy of the formed pattern is better than when patterning is performed using a photoresist pattern as an etching mask. For this reason, for example, a semiconductor device such as an SRAM having a node of 32 nm or less can be patterned with high shape accuracy in the n-type MISFET formation region or the p-type MISFET formation region. For example, a desired transistor characteristic such as a threshold voltage (Vth) can be obtained. Easy to get characteristics.

  Further, in the manufacturing process of the semiconductor device of the present embodiment, the photoresist pattern PR1 is not in direct contact with the metal-containing insulating film 3a. Therefore, it is possible to prevent the gate insulating film of the MISFET from being deteriorated due to diffusion into the metal-containing insulating film 3a such as an organic substance contained in the photoresist pattern PR1.

  In the manufacturing process of the semiconductor device according to the present embodiment, the metal-containing insulating film 3a or the insulating film 3 is not exposed to plasma when the photoresist pattern PR1 is removed by ashing. Therefore, damage to the metal-containing insulating film 3a and the insulating film 3 due to plasma can be reduced, and the reliability of the gate insulating film of the MISFET can be improved.

  Thus, in the manufacturing process of the semiconductor device of the present embodiment, MISFETs QN1 and QP1 having the gate insulating film GI1 including the metal-containing insulating film 3a, and MISFET QN2 having the gate insulating film GI2 not including the metal-containing insulating film 3a. And QP2 can be easily created. In MISFETs QN1 and QP1, the threshold voltage (Vth) can be increased without changing the impurity concentration in the channel region, and in MISFETs QN2 and QP2, the threshold voltage (Vth) can be reduced without changing the impurity concentration in the channel region. it can. Therefore, it is possible to form a plurality of types of MISFETs having different threshold voltages (Vth) while suppressing the short channel effect.

  Further, even when an analog circuit is formed in addition to a logic circuit such as SoC or MCU, if MISFETs QN1 and QP1 are used as MISFETs constituting a digital circuit and MISFETs QN2 and QP2 are used as MISFETs constituting an analog circuit, a semiconductor device Performance can be improved.

  In an analog circuit, a MISFET having a small threshold voltage (Vth) may be used to operate the MISFET with a voltage about 70% of the power supply voltage (Vdd). However, the threshold voltage (Vth) constituting the analog circuit is small. When hafnium (Hf) is added to the MISFET, the noise characteristics are deteriorated and the performance of the semiconductor device may be deteriorated. However, in the present embodiment, hafnium (Hf) is added to MISFETs QN1 and QP1, but hafnium (Hf) is not added to MISFETs QN2 and QP2, so that the threshold voltage (Vth) is increased in the logic circuit. In the analog circuit, the threshold voltage (Vth) can be reduced and the noise characteristics can be improved.

  Even when the MISFET is embedded in a logic circuit as a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type memory, the MISFETs QN1 and QP1 are used as the MISFETs constituting the logic circuit, and the MISFET QN2 as the MISFET constituting the MONOS type memory. When QP2 is used, the performance of the semiconductor device can be improved.

  When hafnium (Hf) is added to a MISFET formed as a MONOS type memory, the impurity concentration in the channel region is not reduced in order to compensate for the increase in threshold voltage (Vth) due to the addition of hafnium (Hf). must not. When the impurity concentration of the channel region is reduced, the electric field at the PN junction in the source / drain region SD is reduced, the amount of hot carriers required for the memory write operation and erase operation is reduced, and the write speed and erase speed are reduced. There is a risk. However, in the present embodiment, hafnium (Hf) is not added in MISFETs QN2 and QP2, and the threshold voltage (Vth) is originally small, so that the impurity concentration in the channel region is reduced to reduce the threshold voltage (Vth). There is no need. Accordingly, the MISFETs QN2 and QP2 having the increased threshold voltage (Vth) and the MISFETs QN2 and QP2 having the decreased threshold voltage (Vth) are mixedly mounted, and the generation of hot carriers can be suppressed from decreasing in the MISFETs QN2 and QP2. The memory writing speed and erasing speed can be improved.

(Embodiment 2)
In the manufacturing process of the semiconductor device of the first embodiment, when the hard mask pattern is formed, the mask film is completely removed by dry etching in the region where the mask film is exposed, and then the photoresist pattern is removed. On the other hand, in the manufacturing process of the semiconductor device of the second embodiment, in the region where the mask film is exposed, after the mask film is etched halfway by dry etching, the photoresist pattern is removed and then remains. The mask film is completely removed by wet etching.

  Note that the manufacturing process of the semiconductor device of the present embodiment is to manufacture a semiconductor device similar to the semiconductor device of the first embodiment, and the description of the semiconductor device is omitted.

  Next, the manufacturing process of the semiconductor device of this embodiment will be described with reference to the drawings. FIG. 30 is a manufacturing process flow chart showing a part of the manufacturing process of the semiconductor device of Second Embodiment. 31 to 33 are fragmentary cross-sectional views of the semiconductor device of the second embodiment during the manufacturing steps thereof.

  In the manufacturing process of the semiconductor device of the second embodiment, each of the processes of steps S31 to S37 in FIG. 30 is the same as each of the processes of steps S11 to S17 of FIG. 2 in the manufacturing process of the semiconductor device of the first embodiment. The description of these steps is omitted. As in the first embodiment, a film made of titanium nitride (TiN) or tantalum nitride (TaN) is preferably used as the mask film 9.

  After the steps S31 to S37 are performed to form the photoresist pattern PR1 (see FIG. 10), in the manufacturing process of the semiconductor device of the second embodiment, the photoresist pattern PR1 is formed as shown in FIG. The mask film 9 is dry-etched as an etching mask (step S38 in FIG. 30). In this step S38, the mask film 9 is etched halfway by dry etching using the photoresist pattern PR1 having openings in the MISFET formation regions AN1 and AP1 as an etching mask. Therefore, after step S38 is performed, the mask film 9 is not completely removed and remains on the insulating film 3 in the MISFET formation regions AN1 and AP1. That is, the semiconductor substrate 1 is covered with the mask film 9 over the entire main surface (front surface), and the insulating film 3 is not exposed even in the MISFET formation regions AN1 and AP1.

  The thickness for leaving the mask film 9 in the MISFET formation regions AN1 and AP1 is preferably such that the insulating film 3 in the MISFET formation regions AN1 and AP1 is not exposed to plasma in step S38 and the subsequent process (step S39). Say it. Although depending on the conditions of the subsequent process (step S39), the thickness T1 of the mask film 9 in the MISFET formation region AN1 and AP1 after step S38 can be set to about 1 to 5 nm, for example. Further, the thickness T1 of the mask film 9 in the MISFET formation regions AN1 and AP1 is smaller than the thickness T2 of the mask film 9 in the MISFET formation regions AN2 and AP2.

  Next, as shown in FIG. 32, the photoresist pattern PR1 is removed (step S39 in FIG. 30). In this step S39, the photoresist pattern PR1 is removed, for example, by performing an ashing process. Even after step S39 is performed, the semiconductor substrate 1 is covered with the mask film 9 over the entire main surface (front surface). However, as described above, the thickness T1 of the mask film 9 in the MISFET formation regions AN1 and AP1 is smaller than the thickness T2 of the mask film 9 in the MISFET formation regions AN2 and AP2.

  Next, as shown in FIG. 33, the mask film 9 is wet-etched (step S40 in FIG. 2). In this step S40, the mask film 9 is completely removed in the MISFET formation regions AN1 and AP1, and the mask surface 9 is left in the MISFET formation regions AN2 and AP2 over the entire main surface (front surface) of the semiconductor substrate 1. The film 9 is wet etched. Thus, after step S40 is performed, the hard mask pattern 10 made of the mask film 9 is formed so that the insulating film 3 is exposed in the MISFET formation regions AN1 and AP1 and the insulating film 3 is covered in the MISFET formation regions AN2 and AP2. Is formed. The thickness of the hard mask pattern 10 (mask film 9) in the MISFET formation regions AN2 and AP2 is T3 smaller than the thickness T2 before performing Step S40.

  As the etching solution in step S40, an aqueous hydrogen peroxide solution is preferably used. The etching rate of the mask film 9 when the aqueous hydrogen peroxide solution is used as the etching solution is smaller than the etching rate of the mask film 9 when the SPM solution is used as the etching solution. Therefore, by using an aqueous hydrogen peroxide solution as an etchant, the wet etching conditions are such that the mask film 9 is completely removed in the MISFET formation regions AN1 and AP1, and the mask film 9 remains in the MISFET formation regions AN2 and AP2. It can be adjusted easily.

  That is, in the second embodiment, damage to the insulating film 3 when removing the mask film 9 in the MISFET formation region AN1 and AP1 is smaller than that in the first embodiment. Therefore, the reliability of the gate insulating film GI1 (insulating film 11, metal-containing insulating film 3a, and insulating film 3) can be improved finally.

  Thereafter, the metal-containing film 4 is formed (deposited) on the semiconductor substrate 1 (step S41 in FIG. 30), the semiconductor substrate 1 is annealed (step S42 in FIG. 30), and wet etching is performed (step S43 in FIG. 30). ). Thereby, in the same way as described with reference to FIG. 15 in the first embodiment, in the MISFET formation regions AN1 and AP1, the insulating film 3 formed on the semiconductor substrate 1 and the metal formed on the insulating film 3 are formed. An insulating film 11 made of the containing insulating film 3a is formed, and an insulating film 12 made only of the insulating film 3 formed on the semiconductor substrate 1 is formed in the MISFET formation regions AN2 and AP2. That is, the metal-containing insulating film 3a can be selectively formed in the MISFET formation regions AN1 and AP1 using the hard mask pattern 10 (mask film 9).

  Alternatively, in the MISFET formation regions AN1 and AP1, the insulating film 3 and the metal-containing insulating film 3a may not be clearly separated. At this time, by performing the processes up to step S43, the insulating film 11 to which the metal is added is formed in the MISFET formation regions AN1 and AP1, and the insulating film to which the metal is not added in the MISFET formation regions AN2 and AP2. 12 is formed.

  30 are the same as steps S20 to S22 of FIG. 2 in the semiconductor device manufacturing process of the first embodiment, and the details of these processes are as follows. Description is omitted.

  Thereafter, similarly to the manufacturing process of the semiconductor device of the first embodiment, the semiconductor device having the same structure as that of the first embodiment is manufactured by performing steps S23 to S30 of FIG. That is, an n-channel MISFET QN1 having a large threshold voltage (Vth) is formed in the n-type MISFET formation region AN1, and an n-channel MISFET QN2 having a small threshold voltage (Vth) is formed in the n-type MISFET formation region AN2. . Further, a p-channel type MISFET QP1 having a large threshold voltage (Vth) is formed in the p-type MISFET formation region AP1, and a p-channel type MISFET QP2 having a small threshold voltage (Vth) is formed in the p-type MISFET formation region AP2. .

  Also in the manufacturing process of the semiconductor device of the present embodiment, since the shape accuracy of the pattern to be formed is better than in the case of using the photoresist pattern as in the manufacturing process of the semiconductor device of the first embodiment, the n-type MISFET formation is performed. Patterning can be performed with high shape accuracy in the region or the p-type MISFET formation region. Further, since the photoresist pattern is not in direct contact with the metal-containing insulating film 3a, it is possible to prevent the MISFET gate insulating film from being altered. Further, when the photoresist pattern PR1 is removed by the ashing process, damage to the metal-containing insulating film 3a and the insulating film 3 due to plasma can be reduced, and the reliability of the gate insulating film of the MISFET can be improved. .

  In addition, the semiconductor device manufactured by the manufacturing process of the semiconductor device of the present embodiment is also similar to the semiconductor device manufactured by the manufacturing process of the semiconductor device of the first embodiment, while suppressing the short channel effect and the threshold voltage. A plurality of types of MISFETs having different (Vth) can be formed. Further, when MISFETs QN2 and QP2 are used as MISFETs constituting the analog circuit, the analog circuit can reduce a threshold voltage (Vth) and improve noise characteristics, and MISFETs QN2 and QP2 are used as MISFETs constituting the MONOS type memory. Thus, the writing speed and erasing speed of the memory can be improved.

  In addition to the effects described above, in the manufacturing process of the semiconductor device of the present embodiment, after the mask film 9 is etched halfway by dry etching in the region where the mask film 9 is exposed, the photoresist pattern PR1 is removed, Thereafter, the remaining mask film 9 is completely removed by wet etching. Therefore, when the mask film 9 is dry-etched and when the photoresist pattern PR1 is subjected to an ashing process, damage caused by exposure of the insulating film 3 to plasma can be reduced. As a result, the reliability of the gate insulating film of the MISFET can be further improved as compared with the first embodiment, and the transistor characteristics of the MISFET can be further improved as compared with the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment and the second embodiment, the manufacturing process of the semiconductor device of the present invention is performed by using a MISFET and a threshold voltage having a large threshold voltage (Vth) for both an n-channel MISFET and a p-channel MISFET. The example applied to the manufacturing process of the semiconductor device in which two types of MISFETs made of MISFETs with small (Vth) are formed has been described. However, the present invention is not limited to the example applied to the manufacturing process of a semiconductor device including both n-channel type and p-channel type MISFETs. For example, one of the n-channel type and the p-channel type MISFETs. The present invention can also be applied to a manufacturing process of a semiconductor device having only the above.

  The present invention is effective when applied to a method of manufacturing a semiconductor device.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 2a Element isolation groove 2b 3, 6, 11, 12 Insulating film 3a Metal containing insulating film 4 Metal containing film 5 Interlayer insulating film 9 Mask film 10 Hard mask pattern 13 Conductor films AN1, AN2, AP1, AP2 MISFET formation region CNT Contact hole EX Extension region GE Gate electrode GI1, GI2 Gate insulating film M1 Wiring NW n-type well region PG Plug PR1, PR2 Photoresist pattern PW p-type well region QN1, QN2, QP1, QP2 MISFET
SD Source / drain region SW Side wall spacer

Claims (7)

A first MISFET and a second MISFET formed on a semiconductor substrate;
The first MISFET has a first gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the first gate insulating film,
The second MISFET is a method of manufacturing a semiconductor device having a second gate insulating film formed on the semiconductor substrate and a second gate electrode formed on the second gate insulating film,
(A) preparing the semiconductor substrate;
(B) after the step (a), forming a first film containing silicon and oxygen on the semiconductor substrate;
(C) a step of forming a mask film on the first film after the step (b);
(D) After the step (c), the first film is exposed in the first region where the first MISFET is formed, and the first film is covered in the second region where the second MISFET is formed. Patterning the mask film,
(E) after the step (d), forming a second film containing a metal on the first film exposed in the first region;
(F) After the step (e), adding the metal contained in the second film to the first film in the first region by heat treatment;
(G) After the step (f), a step of removing the second film and the mask film;
(H) After the step (g), a step of forming a conductor film on the semiconductor substrate;
(I) After the step (h), by patterning the conductor film and the first film, the first gate electrode made of the conductor film and the metal in the first region Forming the first gate insulating film made of the added first film, and forming the second gate electrode made of the conductive film in the second region, and the first not added with the metal. Forming the second gate insulating film made of the film of
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device according to claim 1,
The step (d)
(J) After the step (c), forming a photoresist pattern so that the mask film is exposed in the first region and the mask film is covered in the second region;
(K) After the step (j), using the photoresist pattern as a mask, etching the mask film in the first region halfway;
(L) a step of removing the photoresist pattern after the step (k);
(M) After the step (l), by etching the mask film in the first region and the mask film in the second region, the mask film is removed in the first region and the first region is removed. Exposing the film and leaving the mask film so as to cover the first film in the second region;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device according to claim 2,
In the step (k), the mask film is etched by dry etching,
In the step (m), the mask film in the first region and the mask film in the second region are etched by wet etching. A method of manufacturing a semiconductor device according to claim 2,
In the step (l), the photoresist pattern is removed by an ashing process. A method of manufacturing a semiconductor device according to claim 2,
A method of manufacturing a semiconductor device, wherein the thickness of the mask film etched in the step (m) is thinner than the thickness of the mask film etched in the step (k). A method of manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the metal is hafnium. A method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the mask film is made of titanium nitride or tantalum nitride.

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