JP2013118242A - Crystal fault detection method and silicon carbide semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of detecting a fault formed inside a SiC epitaxial layer without breaking a substrate; and provide a manufacturing method of a SiC semiconductor device using the crystal fault detection method.SOLUTION: A crystal fault detection method comprises: (a) a step of preparing a SiC substrate 1 on which a SiC drift layer 2 is formed on a surface; (b) a step of forming a C-rich layer 4 on a surface of the SiC drift layer 2 by annealing the SiC substrate 1; (c) a step of removing the C-rich layer 4 by dry etching after the step (b); and (d) a step of inspecting a fault on the surface of the SiC drift layer 2 after the step (c).

Description

  The present invention relates to a method for detecting crystal defects in a silicon carbide substrate and a method for manufacturing a silicon carbide semiconductor device.

  Semiconductor elements using silicon carbide (SiC) are promising as next-generation switching elements that can achieve high breakdown voltage, low loss, and high heat resistance, and are expected to be applied to power semiconductor devices such as inverters. However, many problems to be solved remain in the SiC semiconductor device, and one of them is improvement in yield. Since the SiC crystal growth technology is still under development, many crystal defects exist in the substrate, and these crystal defects become device killer defects that deteriorate the characteristics of the semiconductor device, which is a major factor that hinders the yield. ing.

  In order to improve the yield, it is necessary to select (screen) a substrate having few crystal defects before the wafer process. In addition, in order to improve the substrate quality of SiC, it is necessary to conduct a correlation survey between various defects and device characteristics, identify which types of defects become device killer defects, and feed back to the substrate / epitaxial manufacturer It becomes.

  As a method for detecting a defect in a substrate, for example, Patent Document 1 discloses a method in which an image of a defect-free area on a substrate that has been photographed in advance is compared with an inspection image, and a mismatched portion is detected as a defect.

  A SiC substrate used for a power device generally has a configuration in which an epitaxial layer is formed on a SiC bulk. It is known that in a SiC bulk, there exists a screw dislocation having a hollow structure called a micropipe, and the micropipe becomes a device killer defect that deteriorates element characteristics. When epitaxial growth is performed in a bulk in which micropipes are present, the micropipes are inherited to the surface of the epitaxial layer, so that the defects can be detected by a conventional defect detection method as described in Patent Document 1.

  However, some micropipes are plugged during epitaxial growth and do not appear on the surface of the epitaxial layer. Such a micropipe cannot be detected by the defect detection method described in Patent Document 1 although it becomes a device killer defect.

  As a method for solving this problem, Patent Document 2 discloses defects that cannot be observed on the surface of the SiC epitaxial layer by performing anisotropic dry etching using SF6 as a gas source after alkali etching the surface of the SiC epitaxial layer. Is disclosed.

  For example, Patent Document 3 discloses a technique for quickly etching a SiC substrate by performing ion implantation on a portion of the SiC substrate to be removed and then performing heat treatment.

JP 2005-321237 A JP 2008-28178 A JP 2000-12509 A

  However, since alkali etching is generally a destructive inspection and causes a large damage to the SiC substrate, there is a problem that the SiC substrate inspected by the method of Patent Document 2 cannot be used for a device. In addition, if SF6 gas is used in the dry etching process after alkali etching, it takes time and throughput is reduced. Since SF6 gas has a high greenhouse effect, its use for device mass production flow has a large environmental impact. There is a problem of giving.

  Moreover, in patent document 3, in order to improve an etching rate, since ion implantation is implemented to the etching location before heat processing, a process will increase. In addition, a step of forming a mask necessary for selective ion implantation is required, which increases the manufacturing cost and lowers the throughput.

  In view of the above problems, the present invention provides a method for detecting defects formed inside an SiC epitaxial layer without destroying the substrate by a simple process, and a method for manufacturing an SiC semiconductor device using the crystal defect detection method. The purpose is to provide.

  In the crystal defect detection method of the present invention, (a) a step of preparing a SiC substrate having an epitaxial layer formed on the surface, and (b) a step of annealing the SiC substrate to form a C-rich layer on the surface of the epitaxial layer And (c) after step (b), a step of removing the C-rich layer by dry etching, and (d) after step (c), a step of inspecting defects on the surface of the epitaxial layer.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes (a) a step of preparing an SiC substrate having an epitaxial layer formed on the surface thereof, and (b) a predetermined step for forming predetermined element components of each chip in the epitaxial layer. (C) After step (b), the SiC substrate is annealed to form a C-rich layer on the surface of the epitaxial layer, and (d) step (c) is followed by dry processing. A step of removing the C-rich layer by etching, a step of (e) inspecting defects on the surface of the epitaxial layer after the step (d), and (f) after the step (e), in the inspection result of the step (e). And a step of screening each chip.

  In the crystal defect detection method of the present invention, (a) a step of preparing a SiC substrate having an epitaxial layer formed on the surface, and (b) a step of annealing the SiC substrate to form a C-rich layer on the surface of the epitaxial layer And (c) a step of removing the C-rich layer by dry etching after step (b), and a step of (d) inspecting defects on the surface of the epitaxial layer after step (c). Without destroying the substrate by the process, it is possible to expose and inspect the defects blocked inside the epitaxial layer.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes (a) a step of preparing a SiC substrate having an epitaxial layer formed on the surface thereof, and (b) a method for forming predetermined element components of each chip in the epitaxial layer. (C) After step (b), after the step (b), the SiC substrate is annealed to form a C-rich layer on the surface of the epitaxial layer, and (d) after step (c) A step of removing the C-rich layer by dry etching, a step of (e) inspecting defects on the surface of the epitaxial layer after the step (d), and (f) an inspection of step (e) after the step (e). And a step of screening each chip based on the result, so that the defect blocked in the epitaxial layer can be exposed and inspected without destroying the substrate by a simple process. Further, by performing the defect detection inspection in the device manufacturing process, the cost and throughput of the characteristic evaluation test after the device manufacturing process can be improved.

3 is a flowchart showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view for explaining the crystal defect method according to the first embodiment. FIG. 3 is a cross-sectional view for explaining the crystal defect method according to the first embodiment. FIG. 3 is a cross-sectional view for explaining the crystal defect method according to the first embodiment. 5 is a flowchart showing a method for manufacturing a silicon carbide semiconductor device according to a second embodiment. 7 is a cross-sectional view for explaining a crystal defect method according to Embodiment 2. FIG. 7 is a cross-sectional view for explaining a crystal defect method according to Embodiment 2. FIG. 7 is a cross-sectional view for explaining a crystal defect method according to Embodiment 2. FIG. 7 is a cross-sectional view for explaining a crystal defect method according to Embodiment 2. FIG. 7 is a cross-sectional view for explaining a crystal defect method according to Embodiment 2. FIG. 7 is a cross-sectional view for explaining a crystal defect method according to Embodiment 2. FIG. 7 is a cross-sectional view for explaining a crystal defect method according to Embodiment 2. FIG. 7 is a cross-sectional view for explaining a crystal defect method according to Embodiment 2. FIG.

(Embodiment 1)
FIG. 1 is a flowchart showing the steps of the crystal defect detection method according to the first embodiment, and FIGS. 2 to 4 are cross-sectional views of the SiC epitaxial wafer to which the crystal defect detection method according to the first embodiment is applied. Hereinafter, the crystal defect detection method according to the first embodiment will be described with reference to FIG. 1 and FIGS.

  First, an n-type SiC drift layer 2 is epitaxially grown on an n-type SiC substrate 1 to prepare a SiC epitaxial wafer (step S1 in FIG. 1, FIG. 2). Here, the thickness of the SiC drift layer 2 is formed to be about 1 to 3 μm thicker than the thickness required to secure a desired withstand voltage at the time of device fabrication. This SiC epitaxial wafer becomes an inspection object. The SiC substrate 1 and the SiC drift layer 2 have micropipe defects 3 that are closed during the epitaxial growth of the SiC drift layer 2, and various defects are present near the surface of the SiC drift layer 2. .

  Next, a first defect inspection for detecting defects on the surface of the SiC drift layer 2 is performed (step S2 in FIG. 1). In the first defect inspection, for example, an image of the surface of the SiC drift layer 2 is photographed by a CCD, and the defect is detected by comparing it with a defect-free image of the SiC substrate surface photographed in advance.

  Thereafter, a high temperature annealing process is performed on the SiC epitaxial wafer (step S3 in FIG. 1, FIG. 3). Thereby, Si evaporates from the surface of the SiC drift layer 2 and the C rich layer 4 is formed. Here, it is desirable to perform the annealing process at 1600 ° C. or more and less than 2000 ° C. If it is less than 1600 ° C., Si does not evaporate, and it becomes difficult to etch the SiC drift layer 2 in a later step. Further, if annealing is performed at 2000 ° C. or higher, the SiC epitaxial wafer may be damaged due to stress, or a new defect may be generated due to lattice distortion, which may deteriorate the wafer quality.

Next, for example, an etching process is performed using a gas having high reactivity with C, such as O ₂ gas, to remove the C rich layer 4 from the surface of the SiC drift layer 2 (steps S4 and 4 in FIG. 1). Through this step, the micropipe defect 3 that has been blocked inside the SiC drift layer 2 in the stage of FIG. 2 is exposed on the surface of the SiC drift layer 2. Note that it is possible to provide contrast to defects that are difficult to detect optically by high-temperature annealing and etching that removes the C-rich layer 4.

  Thereafter, a second defect inspection for inspecting defects on the surface of the SiC drift layer 2 is performed (step S5 in FIG. 1). A second defect inspection is performed using the same method as the first defect inspection. In the second defect inspection, it is possible to detect a defect originally blocked in the etching growth process of the SiC drift layer 2 or a defect with low contrast on the surface of the SiC drift layer 2.

  Next, the difference between the defect position information acquired in the first and second defect inspection is obtained, and the defect newly detected in the second defect inspection is extracted. Then, the chip including the extracted defect is regarded as a defective chip after the device creation process is completed, and is excluded from the device characteristic evaluation target. The defect detected in the first defect inspection does not necessarily cause a device failure, whereas the defect detected for the first time in the second defect inspection, that is, the micropipe defect 3 is highly likely to cause a device failure. In the crystal defect detection method according to the present embodiment, by obtaining the difference between the mapping data of the first defect inspection and the second defect inspection, only the chip including the micropipe defect 3 is surely excluded from the device characteristic evaluation target.

  Therefore, since the number of chips on which the device characteristic evaluation is performed is reduced, the cost of the device characteristic evaluation is suppressed and the throughput is improved.

<Effect>
In the crystal defect detection method of the present embodiment, (a) a step of preparing a SiC substrate (SiC epitaxial wafer) having a SiC drift layer 2 (epitaxial layer) formed on the surface, and (b) annealing the SiC epitaxial wafer. A step of forming the C-rich layer 4 on the surface of the SiC drift layer 2, a step (c) of removing the C-rich layer 4 by dry etching after the step (b), and a step (d) of the step (c). Thereafter, a step of inspecting defects on the surface of the SiC drift layer 2 is provided, so that the defects blocked during the epitaxial growth of the SiC drift layer 2 can be exposed and detected without destroying the SiC substrate 1.

  Further, the crystal defect detection method of the present embodiment includes (e) a step of inspecting defects on the surface of the SiC drift layer 2 (epitaxial layer) between steps (a) and (b), and a step (f) ( e) and a step of comparing the inspection results of step (d). Since the defect newly detected in the step (d) is a micropipe defect blocked in the SiC drift layer 2 at the time of the step (a), it is possible to detect a defect that leads to such a device failure.

  Further, in the crystal defect detection method of the present embodiment, step (b) is a step of annealing the SiC epitaxial wafer (SiC substrate) at 1600 ° C. or more and less than 2000 ° C., so that stress is not applied to the SiC epitaxial wafer. Si can be evaporated from the SiC drift layer 2.

In the crystal defect detection method of the present embodiment, step (c) is a step of performing dry etching using O ₂ gas. Since the O ₂ gas has high reactivity with C, the C rich layer 4 can be efficiently removed.

  In the crystal defect detection method according to the present embodiment, the steps (d) and (e) are performed by taking an image of the surface of the SiC drift layer 2 (epitaxial layer) and acquiring the defect-free image of the surface of the SiC substrate in advance. It is possible to detect defects on the surface of the SiC drift layer 2 by comparing with the photographed image.

  Alternatively, in the crystal defect detection method of the present embodiment, in steps (d) and (e), the laser light irradiated on the surface of SiC drift layer 2 (epitaxial layer) is scattered on the substrate surface, and the scattered light is detected. Thus, it is possible to detect defects on the surface of the SiC drift layer 2.

(Embodiment 2)
In the crystal defect detection method of the first embodiment, the defect inspection is performed before the device creation process. However, the crystal defect detection may be performed during the device creation process.

  FIG. 5 is a flowchart showing a device creation process incorporating crystal defect detection, and FIGS. 6 to 12 are cross-sectional views showing manufacturing steps of a Schottky barrier diode as an example of the device. Hereinafter, the crystal defect detection method of the second embodiment will be described with reference to FIGS. 5 and 6 to 12.

  First, an SiC epitaxial wafer is prepared (Step S1 in FIG. 5, FIG. 6). The SiC epitaxial wafer is formed by epitaxially growing an n-type SiC drift layer 2 having a thickness of 5 to 25 μm on an n-type SiC substrate 1 having a thickness of 300 to 400 μm. Here, the SiC drift layer 2 is formed to be thicker by about 1 to 3 μm than the thickness required to secure a desired breakdown voltage at the time of device creation in consideration of etching in a later process.

  The SiC epitaxial wafer is a target for defect inspection. The SiC substrate 1 and the SiC drift layer 2 have micropipe defects 3 that are blocked during the epitaxial growth of the SiC drift layer 2, and various defects also exist near the surface of the SiC drift layer 2.

  Next, a first defect inspection is performed to detect defects on the surface of SiC drift layer 2 (step S12 in FIG. 5). In the first defect inspection, for example, an image of the surface of the SiC drift layer 2 is taken with a CCD, and the defect is detected by comparing it with a defect-free image of the surface of the SiC substrate acquired in advance.

  Next, a photoresist is applied on the surface of SiC drift layer 2. Then, each process of heating, pattern transfer by photolithography, and development with an alkaline developer is sequentially performed to form a resist pattern 5 having openings in the formation regions of the alignment mark 7 and the guard ring 8 (see FIG. 8) (see FIG. 8). 7).

  Then, reactive ion etching (RIE) is performed using the resist pattern 5 as a mask, and a recess 6 and an alignment mark 7 having a depth of about 0.3 to 0.6 μm are formed simultaneously (FIG. 8).

  Next, using the resist pattern 5 as a mask, p-type impurity Al ions are implanted into the SiC drift layer 2 to form a guard ring 8 (FIG. 9).

  Thereafter, the resist pattern 5 is removed by dry etching, for example.

  Then, the Al ions implanted into the SiC drift layer 2 are activated by performing high-temperature annealing at 1600 ° C. or more and less than 2000 ° C. At this time, Si evaporates from the surface of the SiC drift layer 2, and the C rich layer 4 is formed on the SiC drift layer 2 (FIG. 10). Note that if annealing is performed at a temperature lower than 1600 ° C., Si does not evaporate, and it becomes difficult to etch the SiC drift layer 2 in a later step. Further, if annealing is performed at 2000 ° C. or higher, the SiC epitaxial wafer may be damaged due to stress, or a new defect may be generated due to lattice distortion, which may deteriorate the wafer quality.

  Then, the C rich layer 4 is removed from the surface of the SiC drift layer 2 by performing an etching process using a gas highly reactive with C as a source. As a result, defects that have been blocked in SiC drift layer 2 are exposed on the surface of SiC drift layer 2.

  And the 2nd defect inspection for detecting the defect of the SiC drift layer 2 surface is implemented. The defect inspection method here is the same as the first defect inspection.

  Subsequently, a Ni layer 9 having a thickness of about 500 to 800 nm is formed on the back surface of the SiC substrate 1 using a sputtering method. Then, RTA (Rapid Thermal Annealing) at about 1000 ° C. is performed for about 5 minutes. As a result, a Ni silicide layer 10 is formed at the interface between the SiC substrate 1 and the Ni layer 9 (FIG. 11).

  Further, a Ti layer 11 having a thickness of about 100 to 300 nm is formed on the surface of the SiC drift layer 2 including a part of the guard ring 8 by using a sputtering method, and a thickness of 4.5 to 5 is further formed on the Ti layer 11. A 5 μm Al layer 12 is formed to form an anode electrode (FIG. 12). In order to stabilize the height φB of the Schottky barrier (difference between the metal work function and the electron affinity of the semiconductor), a heat treatment at about 600 ° C. may be performed after the Ti layer 11 is formed.

  Finally, an Au layer 13 having a thickness of about 100 to 300 nm is formed on the lower surface of the Ni layer 9 by a sputtering method to form a Schottky barrier diode having a structure shown in FIG. This completes the device creation process (step S13 in FIG. 5).

  Next, chip screening is performed (step S14 in FIG. 5). Here, the difference between the defect position information acquired in the first and second defect inspections is obtained, and the defect newly detected in the second defect inspection is extracted. Then, the chip including the extracted defect is regarded as a defective chip and excluded from device characteristic evaluation. Since the defect detected for the first time in the second defect inspection is a micropipe defect and is likely to cause a device failure, the cost and throughput of the device characteristic evaluation test can be improved by screening a chip including the defect. I can do it.

<Effect>
The method for manufacturing a silicon carbide semiconductor device of the present embodiment includes: (a) preparing a SiC epitaxial wafer (SiC substrate) having a SiC drift layer 2 (epitaxial layer) formed on the surface; and (b) SiC drift layer 2. (C) After the step (b), the SiC epitaxial wafer is annealed after the step (c) to form a predetermined element component of each chip, and the surface of the SiC drift layer 2 is C-rich. A step of forming the layer 4; (d) a step of removing the C-rich layer 4 by dry etching after the step (c); and (e) an inspection of defects on the surface of the epitaxial layer after the step (d). And (f) a step of screening each chip based on the inspection result of step (e) after step (e). Device characteristics after the device fabrication process are performed by performing defect inspection in steps (c) and (d) during the device fabrication process, and excluding defective chips from the device property evaluation test based on the defect inspection in step (e). The cost and throughput of the evaluation test can be improved.

  In addition, the method for manufacturing the silicon carbide semiconductor device according to the present embodiment includes a Ti layer 11, an Al layer 12 (first main electrode) provided on the surface of the SiC epitaxial wafer (SiC substrate), and a back surface of the SiC epitaxial wafer. The silicon carbide semiconductor device includes a Ni silicide layer 10 and a Ni layer 9 (second main electrode), and a main current flows in a thickness direction of the SiC epitaxial wafer. By incorporating a defect inspection step into the manufacturing process of such a vertical silicon carbide semiconductor device, the cost and throughput of a device characteristic evaluation test after the manufacturing process can be improved.

  The method for manufacturing the silicon carbide semiconductor device of the present embodiment further includes (g) a step of inspecting the surface of SiC drift layer 2 (epitaxial layer) between step (b) and step (c). The step (f) is a step of comparing the inspection results of the step (g) and the step (e) and excluding the chip including the defect detected for the first time in the step (e) from the device characteristic evaluation target. Since the defect detected for the first time in the step (e) is a micropipe defect blocked in the SiC drift layer 2 at the time of the step (a), such a defect leading to the device defect is excluded from the device characteristic evaluation test. I can do it.

  In the method for manufacturing the silicon carbide semiconductor device of the present embodiment, step (b) is a step of forming a guard ring (impurity region) in the surface layer of SiC drift layer 2 (epitaxial layer). By performing defect inspection after the guard ring forming step, the cost and throughput of the device characteristic evaluation test after the manufacturing process can be improved.

  In the method for manufacturing the silicon carbide semiconductor device of the present embodiment, since step (c) is a step of annealing the SiC substrate at 1600 ° C. or more and less than 2000 ° C., stress is applied to the SiC substrate (SiC epitaxial wafer). Si can be evaporated from the SiC drift layer 2 without giving.

In the method for manufacturing the silicon carbide semiconductor device of the present embodiment, step (d) is a step of performing dry etching using O ₂ gas. Since O ₂ gas is highly reactive with C, the C-rich layer can be removed efficiently.

  Further, in the method for manufacturing the silicon carbide semiconductor device of the present embodiment, in step (e), an image of the surface of SiC drift layer 2 (epitaxial layer) is photographed, and the defect-free image of the SiC substrate surface obtained in advance and the photographing are performed. By comparing with the image, it is possible to detect defects on the surface of the SiC drift layer 2.

  Or in the manufacturing method of the silicon carbide semiconductor device of this Embodiment, a process (e) scatters the laser beam irradiated to the SiC drift layer 2 (epitaxial layer) surface on the substrate surface, and detects scattered light. It is possible to detect defects on the surface of the SiC drift layer 2.

  Further, in the method for manufacturing the silicon carbide semiconductor device of the present embodiment, the step (g) takes an image of the surface of the SiC drift layer 2 (epitaxial layer), and obtains a defect-free image of the surface of the SiC substrate acquired in advance. By comparing with the image, it is possible to detect defects on the surface of the SiC drift layer 2.

  Alternatively, in the method for manufacturing the silicon carbide semiconductor device of the present embodiment, in step (g), the laser light irradiated on the surface of SiC drift layer 2 (epitaxial layer) is scattered on the substrate surface, and the scattered light is detected. It is possible to detect defects on the surface of the SiC drift layer 2.

  1 SiC substrate, 2 SiC drift layer, 3 micropipe defect, 4 C rich layer, 5 resist pattern, 6 alignment mark, 7 recess, 8 guard ring, 9 Ni layer, 10 Ni silicide layer, 11 Ti layer, 12 Al layer 13 Au layer.

Claims (16)

(A) preparing a SiC substrate having an epitaxial layer formed on the surface;
(B) annealing the SiC substrate to form a C-rich layer on the surface of the epitaxial layer;
(C) after the step (b), removing the C-rich layer by dry etching;
(D) after the step (c), inspecting the surface of the epitaxial layer for defects;
A crystal defect detection method comprising: (E) Inspecting defects on the surface of the epitaxial layer between the steps (a) and (b);
(F) a step of comparing the inspection results of the step (e) and the step (d);
The crystal defect detection method according to claim 1, comprising: The step (b) is a step of annealing the SiC substrate at 1600 ° C. or more and less than 2000 ° C.,
The crystal defect detection method according to claim 1 or 2. The step (c) is a step of performing dry etching using O ₂ gas.
The crystal defect detection method according to claim 1. In the step (d) and the step (e), an image of the surface of the epitaxial layer is taken, and a defect-free image on the surface of the SiC substrate obtained in advance is compared with the taken image to thereby detect defects on the surface of the epitaxial layer. Is a step of detecting
The crystal defect detection method according to claim 2. The step (d) and the step (e) are methods of detecting defects by scattering the laser light irradiated on the surface of the epitaxial layer on the substrate surface and detecting the scattered light.
The crystal defect detection method according to claim 2. (A) preparing a SiC substrate having an epitaxial layer formed on the surface;
(B) performing a predetermined process for forming a predetermined element component of each chip in the epitaxial layer;
(C) after the step (b), annealing the SiC substrate to form a C-rich layer on the surface of the epitaxial layer;
(D) after the step (c), removing the C-rich layer by dry etching;
(E) after the step (d), inspecting the surface of the epitaxial layer for defects;
(F) After the step (e), screening each chip based on the inspection result of the step (e);
A method for manufacturing a silicon carbide semiconductor device comprising: The silicon carbide semiconductor device is
A first main electrode provided on the surface of the SiC substrate;
A second main electrode provided on the back surface of the SiC substrate,
A main current flows in the thickness direction of the SiC substrate;
A method for manufacturing a silicon carbide semiconductor device according to claim 7. (G) Further comprising a step of inspecting a defect on the surface of the epitaxial layer between the step (b) and the step (c),
The step (f) is a step of comparing the inspection results of the step (g) and the step (e) and excluding the chip including the defect detected for the first time in the step (e) from the device characteristic evaluation target. is there,
A method for manufacturing a silicon carbide semiconductor device according to claim 7 or 8. The step (b) is a step of forming an impurity region in the surface layer of the epitaxial layer.
The manufacturing method of the silicon carbide semiconductor device in any one of Claims 7-9. The step (c) is a step of annealing the SiC substrate at 1600 ° C. or more and less than 2000 ° C.,
The manufacturing method of the silicon carbide semiconductor device in any one of Claims 7-10. The step (d) is a step of performing dry etching using O ₂ gas.
The manufacturing method of the silicon carbide semiconductor device in any one of Claims 7-11. The step (e) is a step of detecting a defect on the surface of the epitaxial layer by taking an image of the surface of the epitaxial layer and comparing the photographed image with a defect-free image of the SiC substrate surface acquired in advance. ,
The manufacturing method of the silicon carbide semiconductor device in any one of Claims 7-12. The step (g) is a step of detecting a defect on the surface of the epitaxial layer by taking an image of the surface of the epitaxial layer and comparing the photographed image with a defect-free image of the surface of the SiC substrate obtained in advance. ,
A method for manufacturing a silicon carbide semiconductor device according to claim 9. The step (e) is a step of detecting defects on the surface of the epitaxial layer by scattering the laser light irradiated on the surface of the epitaxial layer on the surface of the substrate and detecting the scattered light.
The manufacturing method of the silicon carbide semiconductor device in any one of Claims 7-12. The step (g) is a step of detecting defects on the surface of the epitaxial layer by scattering the laser light applied to the surface of the epitaxial layer on the surface of the substrate and detecting the scattered light.
A method for manufacturing a silicon carbide semiconductor device according to claim 9.

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