JP2013114483A - Digital signal processor system and interruption processing method in digital signal processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a DSP cannot process an external interruption on a DSP card.SOLUTION: According to one embodiment, a digital signal processor system 10 includes an interruption control unit 18 for outputting a notice of interruption generation by input of a plurality of interruption requests that are generated on a first data bus 16 or second data buses 20 and 26 and have different generation causes, a first DSP 21 for executing a signal processing operation, and a second DSP 22 for performing determination processing of selecting an external interruption request of the highest priority by respective priority orders and external interruption processing corresponding to the external interruption request. The second DSP 22 repeats the determination processing and the external interruption processing within one period, and ends the processing of the external interruption request of the highest priority among one or more asynchronous external interruption requests in a plurality of other periods in each of the other periods.

Description

  One embodiment relates to a digital signal processor system (DSP) and an interrupt processing method in the digital signal processor system.

  A CPU used in a personal computer has a large usable memory capacity. The CPU performs interrupt processing by basic software (hereinafter referred to as OS). A technique for realizing a high-speed interrupt response for a CPU is known (see, for example, Patent Documents 1 and 2).

  Since the DSP has various functions specialized for signal processing, many signal processing functions that have been conventionally configured by hardware are converted into software. Usually, since the DSP can use fewer memory resources than the CPU, the DSP cannot use the OS or execute complicated processing like the CPU. For this reason, the signal processing performed by the DSP allocates fixed signal processing such as digital filter processing and FFT processing to each DSP, and the DSP is connected to each other using dedicated high-speed communication. Processing or a round robin DSP configuration is used (see, for example, Patent Document 3 [FIGS. 14 and 15]).

  In the signal processing system, the system components perform processing in synchronization with the timing of the entire system. The DSP card needs to perform response control for a wide variety of interrupts. The DSP has all necessary devices including an interrupt controller, and can process internal interrupts that occur in its own IC. However, the field of application of arithmetic processing by DSP is expanding. Along with this expansion, a data bus having a known standard such as a VME bus or a PCI bus is wired to the DSP card, for example, an interrupt from another DSP card via the VME bus via an IC having a bus protocol conversion function, or a PCI There has been proposed a signal processing system in which a DSP receives and processes an interrupt from a CPU via a bus (see, for example, Patent Document 4).

  Since the DSP has a small memory capacity, a simple DSP is assigned a fixed process, and necessary processes are realized in units of a DSP card in which a plurality of DSPs are collected. Therefore, the interrupt source on the DSP card is the DSPIC itself, and there is no interrupt source from outside the DSPIC.

Japanese Patent Laid-Open No. 7-6038 JP 2000-284773 A JP 2009-020573 A JP 2010-244174 A

  However, in a DSP card wired with a PCI bus or the like, it is necessary for the DSP on the DSP card to process an external interrupt from an interrupt source other than the DSP. When a plurality of external interrupt requests that are asynchronous with each other are input from the PCI bus to the DSP card, the DSP card also receives an interrupt requiring a high-speed response from the PCI bus from a serial communication device (UART) on the external bus. Interrupts that do not require a fast response are handled at the same level. For this reason, the DSP card cannot make an appropriate interrupt response to asynchronous and multiple interrupts.

  In order to solve such a problem, according to one embodiment, a first data bus, a plurality of second data buses respectively connected to the first data bus via a bus interface, and the first data bus Alternatively, an interrupt generation notification is output by inputting one or more interrupt requests having interrupt factors of a plurality of interrupt requests that are generated on the second data bus and having different generation factors, and the first data bus and the plurality of interrupt requests are output. An interrupt control unit connected to the second data bus, and at least one first DSP for performing signal processing operations on the data by generating a reception interrupt of the data to be processed output from the interrupt control unit; A determination process for selecting an external interrupt request having the highest priority among a plurality of external interrupt requests from outside the DSP by the notification from the interrupt control unit according to each priority order; And a second DSP that performs external interrupt processing by executing the interrupt handler corresponding to the external interrupt request, and the second DSP repeats the determination processing and the external interrupt processing within one period, A digital signal processor system is provided in which processing of the highest priority external interrupt request among one or more asynchronous external interrupt requests is terminated in each of these other periods. .

  According to another embodiment, (a) a plurality of different generation factors that are generated on a first data bus or a plurality of second data buses connected to the first data bus via a bus interface. An interrupt generation notification is output by inputting one or more interrupt requests having an interrupt request interrupt factor, and (b) the second DSP on the second data bus is outside the DSP by the notification within one period. Determination processing for selecting the highest priority external interrupt request among the plurality of external interrupt requests from each priority, and external interrupt processing by execution of the interrupt handler corresponding to the external interrupt request (C) the second DSP performs processing of the highest priority external interrupt request among one or more asynchronous external interrupt requests in a plurality of other periods. Interrupt processing method in a digital signal processor system, characterized in that to end for each other period is provided.

1 is a block diagram of a digital signal processor system according to an embodiment. It is a figure which shows the connection relationship between multiple types of interrupt factors, the interrupt control part, and 2nd DSP in the digital signal processor system which concerns on embodiment. It is a flowchart for demonstrating the starting process by 2nd DSP used for the digital signal processor system which concerns on embodiment. It is a flowchart for demonstrating the external interruption process by the digital signal processor system which concerns on embodiment. It is a figure which shows an example of the time chart of the external interruption process by the digital signal processor system which concerns on embodiment. It is a figure which shows an example of the register group used for the determination process which the digital signal processor system which concerns on embodiment performs.

  Hereinafter, a digital signal processor according to an embodiment and an interrupt processing method in the digital signal processor will be described with reference to FIGS. In the drawings, the same portions are denoted by the same reference numerals, and redundant description is omitted.

  A digital signal processor system according to an embodiment is a signal processing system for received signals that periodically arrive from a radar apparatus, and is executed by a plurality of DSP cards each equipped with a plurality of DSPs. An interrupt processing method in a digital signal processor system according to an embodiment is an external interrupt reception processing method in a signal processing system. This external interrupt reception processing method has a plurality of types of interrupt request signals that are generated asynchronously, such as a reception completion interrupt from a radar device, a debug display data transmission completion interrupt, and a transmission / reception interrupt from a host device such as a CPU board. Is received by the DSP on the DSP card and processed by interrupt control.

  FIG. 1 is a block diagram of a signal processing system. The signal processing system 10 includes a radar device 11 that outputs a received signal of a radar wave for each basic period, an A / D converter 12 that performs A / D (analog to digital) conversion on the received signal from the radar device 11, and The M DSP cards 13 that perform signal processing operations on the received digital signals from the A / D converter 12 according to the DSP program, the VME bus 14 that connects these DSP cards 13, and the VME bus 14 are connected. And a CPU card 15 for controlling the operation of each DSP card 13.

  The radar apparatus 11 outputs a reception signal repeatedly for every basic period of, for example, 50 μsec to 10 msec. One basic period is substantially equal to the time required for the radar apparatus to perform transmission and reception once. The A / D converter 12 outputs a digital bit string from the received analog signal, flows at a high speed, and sends a large number of serial bit strings to the DSP card 13.

  Each of the plurality of DSP cards 13 is assigned a calculation time according to the basic period, and each signal processing operation is completed within each calculation time. These DSP cards 13 execute signal processing operations without dropping even one bit of the received data string.

  The first DSP card 13 includes a PCI bus 16 (first data bus), a bus protocol conversion function unit 19 (bus interface) connected to the PCI bus 16, and a bus protocol conversion function unit connected to the PCI bus 16, respectively. One or more interrupt requests having a plurality of interrupt factors that are generated on the PCI bus 16 or the data bus 26 and different from the data buses 20 and 26 (a plurality of second data buses) connected via the bus 19 An external interrupt control device 18 (interrupt control unit) that outputs a notification of occurrence of an interrupt by input, a plurality of DSPs 21 (first DSPs) on the data bus 20, and is also connected to the data bus 20 and mainly performs external interrupt processing. DSP 22 (second DSP) to be executed.

  Further, the DSP card 13 is a general-purpose serial communication device 25 for sending the execution results of the internal programs of the DSPs 21 and 22 from the DSPs 21 and 22 to the personal computer 24 via the signal line 23, and the serial communication device 25 and the bus protocol conversion function. Another data bus 26 (second data bus) that accommodates the unit 19 and the external interrupt control device 18, and a flash ROM 27 that holds a startup program for the DSPs 21 and 22 via the data bus 26. The external interrupt refers to an interrupt request from outside the DSP that is different from the internal interrupt generated inside the DSPs 21 and 22.

  A plurality of types of interrupt generation sources are physically arranged on the PCI bus 16 and the data bus 20. As an interrupt generation source, the DSP card 13 includes the serial communication device 25 that generates an interrupt when input / output of serial data is completed, and a high-speed serial communication device that generates an interrupt when reception of received data from the A / D converter 12 is completed. 28 and a PCI-VME bridge device 29 that generates an interrupt when transmission / reception of signals between the CPU card 15 and the DSP card 13 is completed.

  The serial communication device 25 is an IC having a UART (Universal Asynchronous Receiver Transmitter) function. The serial communication device 25 outputs a character string of a print sentence embedded in the source code of the DSP program executed by the DSPs 21 and 22. The serial communication device 25 transmits a low-speed serial bit string through the RS-232C interface of the personal computer 24 or the like.

  The high-speed serial communication device 28 writes the received data to the volatile external storage device 30 when an interrupt request is issued or immediately after that. When the high-speed serial communication device 28 receives a predetermined number of bit strings, it outputs a single reception completion interrupt. Of the plurality of external interrupt requests generated on the DSP card 13, the DSP card 13 treats the received data from the high-speed serial communication device 28 as the most important data, and accumulates the received data without causing bit dropping. Like to do. With the reception completion interrupt output from the high-speed serial communication device 28, the DSP 21 group performs a single signal processing operation. The processing timing on the DSP card is adjusted so that the external interrupt interval for the received data matches one basic period on the radar device 11 side.

  The PCI-VME bridge device 29 generates a transfer interrupt between the VME bus 14 and the DSP card 13. The PCI-VME bridge device 29 receives a control signal for operation control sent from the CPU 31 on the CPU card 15 to the DSP card 13. On the other hand, the bus protocol conversion function unit 19 transfers data from the DSP card 13 to the CPU card 15.

  The DSP card 13 may include a utility program watchdog timer, a temperature sensor, a power supply monitoring sensor, and the like provided in the bus protocol conversion function unit 19 as other interrupt generation sources. The temperature sensor raises an interrupt when the ambient temperature exceeds the upper limit. The power supply monitoring sensor raises an interrupt when the power supply voltage value falls below the threshold value.

  The external interrupt control device 18 has a terminal 33 for interrupt generation notification. When the external interrupt control device 18 receives one or more interrupt requests having an interrupt factor, the external interrupt control device 18 notifies an interrupt occurrence from the terminal 33. The function of the external interrupt control device 18 is realized by an FPGA.

  FIG. 2 is a diagram showing a connection relationship among a plurality of, for example, 32 types of interrupt factors, the external interrupt control device 18 and the DSP 22 in the digital signal processor system according to the embodiment. The above described symbols represent the same elements. INT0 to INT31 represent external interrupt request signal names by a plurality of interrupt generation sources outside the DSP. For example, INT0 to INT3 are for the PCI bus 16. INT4 to INT10 are for the VME bus 14. INT11 to INT31 are used for interruption from the serial communication device 25, timer interruption, temperature sensor, power supply monitoring sensor, and the like. In the example shown in the figure, the external interrupt control device 18 can input up to 32 types of external interrupt requests. When there is an input from any interrupt generation source, the external interrupt control device 18 notifies the DSP 22 of the occurrence of an external interrupt.

  The external interrupt control device 18 has an interrupt mask register 34 inside, and the interrupt mask register 34 can control whether or not an interrupt response is possible. The external interrupt control device 18 has an interrupt status register 35 inside. The interrupt status register 35 allows the external interrupt control unit 18 to specify the interrupt factor and notify the DSP 22 of the interrupt generation source. The external interrupt control device 18 has an interrupt EOI (End Of Interrupt) register 36 for identifying whether or not the interrupt processing is completed, and the interrupt EOI register 36 terminates the interrupt processing for each interrupt generation source. With these interrupt mask register 34, interrupt status register 35, and interrupt EOI register 36, the external interrupt control device 18 can notify the DSP 22 of the OR results of a plurality of external interrupt input signals.

  The interrupt mask register 34, the interrupt status register 35, and the interrupt EOI register 36 have the same bit allocation pattern. For example, the registers 34 to 36 (the interrupt mask register 34, the interrupt status register 35, and the interrupt EOI register 36) use 32-bit hardware registers each representing an interrupt generation source. LSB is INT0 and MSB is assigned to represent INT31. A bit value high indicates an interrupt request is present and a bit value low indicates no interrupt request.

  Using these registers 34 to 36, the external interrupt control device 18 takes in the value of the terminal group 37 to which 32 signals are input in parallel.

  The DSPs 21 and 22 are each provided with a terminal 38. The terminal 38 is a terminal provided in advance in the IC according to manufacturer specifications. When the external interrupt control device 18 uses the terminal 38 of one DSPIC as an input terminal for external interrupt, the DSP 22 is enabled for external interrupt processing.

  The bus protocol conversion function unit 19 in FIG. 1 transfers data after converting the protocol between the PCI bus 16 and the data buses 20, 26, and 42 having different bus widths and data transfer units according to the protocols of these buses. To do. When the DSP card 13 transfers the value data or control data to the CPU card 15, the DMA controller 32 in the bus protocol conversion function unit 19 reads the value data or control data from the external storage device 30, and the read data is stored in the CPU card. 15 is transferred. The data bus 20 is an internal bus that accommodates N DSPs 21 and 22 in total. The data bus 26 is an internal bus that accommodates the serial communication device 25. The external storage device 30 is a large-capacity memory such as a page memory. The data bus 42 is an internal bus.

  The DSP 21 for signal processing operation executes signal processing operation on this data by generating a reception interrupt of the data to be processed output from the external interrupt control device 18. The DSP 21 has an internal memory 40 having a small-capacity storage area and a DMA controller 41 for DMA transfer of data. The internal memory 40 stores programs and data. The DMA controller 41 loads the execution file from the flash ROM 27 into the internal memory 40 and executes it. The DMA controller 41 writes necessary results out of the execution results to the external storage device 30.

  The DSP 22 for external interrupt processing also includes an internal memory 40 and a DMA controller 41. The DSP 22 executes a determination process and an external interrupt process while these DSPs 21 are calculating. The determination process refers to a process of selecting an external interrupt request having the highest priority among the one or more types of external interrupt requests based on a priority signal according to a notification signal from the terminal 38.

  Since the DSP card 13 includes a plurality of N DSPs 21 and 22, one or a plurality of DSPs 21 and 22 to be booted exist. The configuration of each of the second to M-th DSP cards 13 is the same as the configuration of the first DSP card 13.

  Regarding the structure, the signal processing system 10 is incorporated in a box-shaped chassis. The signal processing system 10 is inserted into a chassis, a backplane in which a VME bus 14 is wired on the inner surface of the chassis, a plurality of slots arranged on the backplane, and a leftmost slot. The CPU card 15 and the M DSP cards 13 inserted into slots other than the slot into which the CPU card 15 is inserted, respectively. A PCI bus expansion connector is provided on each DSP card 13, and a plurality of types of internal bus lines are wired on the card substrate.

  When the signal processing system 10 having the above-described configuration is activated, each DMA controller 41 of the DSP 21 and DSP 22 on the first DSP card 13 transfers the program to the internal memory 40. The DSP 21 functions as a slave DSP and the DSP 22 functions as a master DSP (hereinafter, the DSP 22 may be referred to as a master DSP 22 and each DSP 21 may be referred to as a slave DSP 21).

  A flowchart of the boot procedure in the DSP card 13 is shown in FIG. FIG. 3 is a flowchart for explaining start-up processing by the master DSP 22 used in the digital signal processor system according to the embodiment.

  In step A1, power is turned on to the master DSP 22. In step A <b> 2, the master DSP 22 loads a program from the flash ROM 27 into the internal memory 40. In step A3, the master DSP 22 sets the interrupt mask register 34 to receive an external interrupt based on predetermined information. Alternatively, the external interrupt control device 18 cancels and sets a necessary mask.

  Of the interrupt request signals INT0 to INT31, for example, the signal processing system 10 uses INT0, INT4, INT11, INT14, and the like. The external interrupt controller 18 cancels the masking of the bits of the interrupt mask register 34 corresponding to these INT0 and the like. FIG. 6A is a diagram showing a mask example of the interrupt mask register 34. The external interrupt control device 18 releases the mask of INT0 among INT0 to INT3 assigned to the PCI bus 16 for the high-speed serial communication device 28. The external interrupt control device 18 cancels the mask of INT4 among INT4 to INT10 for the PCI-VME bridge device 29 and cancels the mask of INT11 for the serial communication device 25. The external interrupt control device 18 may assign interrupt bits from timer interrupts, temperature sensors, and power supply monitoring sensors to INT14 to INT17, for example, and cancel the mask of these bits.

  In step A4, the master DSP 22 executes arithmetic processing together with the slave DSP 21. Each slave DSP 21 starts arithmetic processing of DSP software assigned in accordance with a program calculation instruction. For example, each slave DSP 21 executes operations such as digital filter processing and FFT processing.

  During execution of this arithmetic processing, in step A5, the master DSP 22 determines whether or not an end command has been received from the CPU 31 as the host device. While the master DSP 22 does not receive an end command in step A5, the master DSP 22 continues the arithmetic processing through the NO route (step A4). In step A5, when the master DSP 22 receives the termination command, the YES route is passed, and in step A6, the master DSP 22 performs termination processing. After starting the program from the flash ROM 27, the master DSP 22 executes arithmetic processing and is ready to perform interrupt processing in conjunction with the generation of an external interrupt.

  Next, external interrupt processing in the master DSP 22 is shown in FIGS. FIG. 4 is a flowchart for explaining external interrupt processing by the master DSP 22. FIG. 5 is a diagram showing an example of a time chart of external interrupt processing by the master DSP 22. FIG. 5 illustrates an example in which interrupts (external interrupt requests) 1, 2, and 3 are generated in the DSP card 13. The interrupt priority is interrupt 1> interrupt 2> interrupt 3. As a specific example, interrupt 1 represents a reception completion interrupt of the high-speed serial communication device 28 as shown in (2) of FIG. Interrupt 2 represents a transfer interrupt from the CPU 31 to the PCI-VME bridge device 29 as indicated by (1) in FIG. Interrupt 3 represents a transmission completion interrupt of the serial communication device 25 as indicated by (5) in FIG.

  In step B1, as shown in (3) of FIG. 1, the external interrupt control unit 18 receives the generation of an external interrupt. In step B1, the master DSP 22 is notified of an external interrupt signal from the external interrupt control device 18 via the terminal 38, as indicated by (4) in FIG. The master DSP 22 executes external interrupt processing in subsequent steps B2 to B4. First, in step B2, the master DSP 22 reads the interrupt status register 35. At the start of this read process, the interrupt generation state of the DSP card 13 is in the state shown in FIG. As shown in FIG. 5A, it is assumed that interrupt 1 and interrupt 3 occur at time t0.

  In step B3, the master DSP 22 reads the value of the bit number “0” at the beginning of the for statement in which the bit number of the interrupt status register 35 is set to the repetition variable i. FIG. 6B shows an example of the interrupt status register 35 and the interrupt EOI register 36. The master DSP 22 reads 1 of the bit number “0” of the interrupt status register 35.

  In step B4, the master DSP 22 determines whether the bit value is 1. When it is 1, the master DSP 22 passes through the YES route, and in step B5, the master DSP 22 executes an interrupt process for the bit number “0”. As shown in FIG. 5B, the master DSP 22 performs external interrupt processing between time t1 and time t2.

  In step B5, the master DSP 22 performs an interrupt process. The master DSP 22 executes a user handler (interrupt handler) 1. As shown in FIG. 5C, the user handler 1 corresponding to the bit number “0” is executed between time t3 and time t4. From time t3 to time t4 is the time required to complete the task by the user handler 1. In step B5, as shown in FIG. 6B, the external interrupt controller 18 writes 1 to the bit position of the interrupt EOI register 36.

  After execution of the user handler 1, in step B6, the master DSP 22 executes interrupt termination processing corresponding to the interrupt 1. As shown in FIG. 6C, the external interrupt control device 18 writes 0 in the corresponding bit of the interrupt EOI register 36 and 0 in the corresponding bit of the interrupt status register 35. The external interrupt control unit 18 once finishes the external interrupt process. Since the master DSP 22 performs processing in ascending order of interrupt factors, the processing corresponding to the interrupt 1 having the highest priority can be reliably performed.

  The master DSP 22 ends the processing of the interrupt 1 of the high-speed serial communication device 28 to be processed with the highest priority by the time t4. Interrupt 2 occurs between time t3 and time t4. The interrupt 2 is handled by the external interrupt control device 18 and the interrupt 2 is written in the interrupt status register 35 (FIG. 6C). Since external interrupts 2 and 3 are occurring at time t4, the master DSP 22 executes the external interrupt process again. In FIG. 4, the master DSP 22 reads the interrupt status register 35 from the LSB again (step B2). The bit number “0” of the interrupt status register 35 has been processed and cleared. In the for statement of i = 0, 1, 2, 3 of bit (i), the master DSP 22 reads that the bit values of the bit numbers i of the interrupt status register 35 are low, and passes through the NO route. The repetition variable i is incremented by one (step B3, step B4, step B7).

  For i = 4, the master DSP 22 reads the bit value of the bit number “4” (step B3, step B4), passes the YES route, and in step B5, the master DSP 22 is between time t5 and time t6 (FIG. 5 ( b)), interrupt processing for bit number “4” is executed. The master DSP 22 executes the user handler (interrupt handler) 2 (FIG. 5 (d)). The task of the user handler 2 continues until time t8. The master DSP 22 executes the interrupt end process for interrupt 2 (step B6). As shown in FIG. 6D, the external interrupt control device 18 writes 0 in each bit number “4” of the interrupt EOI register 36 and the interrupt status register 35. The master DSP 22 once finishes the external interrupt process. Thus, although interrupt 3 has risen at time t0, and interrupt 3 has risen before interrupt 2, interrupt 2 that has entered later takes priority over interrupt 3 at time t4. Is done. Since the master DSP 22 performs the processing in the order of the priority of the interrupt factor, the processing corresponding to the interrupt 2 is preferentially processed regardless of the order between the interrupts 2 and 3 entering the time series.

  The master DSP 22 finishes the processing of interrupt 1 and interrupt 2 by time t8. Subsequently, the master DSP 22 performs processing corresponding to the interrupt 3. The master DSP 22 reads the interrupt status register 35 from the LSB again (step B2). As shown in FIG. 6D, the bit numbers “0” and “4” of the interrupt status register 35 have been processed and cleared. In the for statement from i = 0 to 10 in bit (i), the master DSP 22 reads the bit value of bit number i (step B3, step B4, step B7). For i = 11, the master DSP 22 reads the bit value of the interrupt status register 35 (step B3, step B4). In step B5, between time t9 and time t10, the master DSP 22 executes an interrupt process for the bit number “11” (FIG. 5B). Until time t12, the master DSP 22 executes the user handler (interrupt handler) 3 (FIG. 5 (e)). Subsequently, the master DSP 22 executes an interrupt end process for the interrupt 3 (step B6). The external interrupt control device 18 clears the bit values of the bit number “11” of the interrupt EOI register 36 and the interrupt status register 35 (FIG. 6E). The master DSP 22 finishes all external interrupt processing. At time t12, all three EOIs are issued. The master DSP 22 shifts control to signal processing calculation (step A4 in FIG. 3).

  As for interrupt 3, the priority of interrupt 3 is lower than that of interrupts 1 and 2. As shown in (1) to (4) of FIG. 1, after the processing of the interrupts 1 and 2 is completed, the post-processing is performed as shown in (5). Interrupt 3 continues to wait until the end of execution of interrupt handlers 1 and 2 after interrupt 3 is raised. In the present embodiment, even if the data stored in the serial communication device 25 is lost in the worst case, it is divided as less important data, and the DSP card 13 continues to operate. Since the signal processing system 10 always processes interrupt requests from a high priority, even if interrupts 1 are generated continuously, the signal processing system 10 does not leak external interrupt processing of all interrupts 1. Can be executed. As described above, by performing the external interrupt process according to the priority, the DSP card 13 can prevent the external interrupt from being missed.

  In the digital signal processor system according to the conventional example, the DSP cannot process an external interrupt whose source is an interrupt source other than the DSP on the DSP card. When a plurality of asynchronous external interrupt requests are generated in the DSP card, this DSP card handles interrupts that require a high-speed response from the PCI bus or the like and interrupts that do not require a high-speed response from the UART or the like at the same level. ing. The DSP card cannot make an interrupt response at high speed when multiple types of interrupts occur.

  At present, due to advances in semiconductor technology, the memory capacity that can be used by the DSP has increased, and more complicated processing can be executed. Therefore, a signal processing system that replaces processing conventionally performed by a CPU with a DSP has emerged. ing. Accordingly, the DSP card supports a known standard bus, and a bus protocol conversion function IC that outputs an interrupt from the known standard bus is provided on the DSP card. An external interrupt generation source for the DSP has come to exist on the DSP card.

  In the digital signal processor system according to the conventional example, the DSP card handles the received data from the radar apparatus that the DSP card is not allowed to miss and the character string data for debugging which is not so important in the same line. Assuming that the DSP card processes all of the asynchronous interrupt requests with the same importance, the DSP card receives a reception interrupt from the radar device during an unimportant interrupt process, and the received data is within the basic period. There is a possibility that the process will not finish.

  On the other hand, according to the digital signal processor system and the interrupt processing method in the digital signal processor system according to the present embodiment, the DSP 22 can process an external interrupt on the DSP card 13. Even if the number of interrupt factor types increases, it is possible to reliably detect the occurrence of a high-priority external interrupt within each basic cycle and process a high-priority external interrupt. The DSP 22 returns to i = 0 and rotates the for statement from the LSB every time the execution of the interrupt handler ends within each basic cycle. The DSP 22 always determines whether or not there is a reception interrupt from the high-speed serial communication device 28 having a high priority. Since the DSP 22 executes the evaluation determination based on the priority every time the processing is performed, the DSP card 13 can perform an interrupt response at a high speed to a plurality of asynchronous external interrupts.

  The above-described embodiment is not limited to the embodiment as it is, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. For example, in FIG. 2, up to 32 types of external interrupt generation sources are registered, but the type and number of external interrupt generation sources can be variously changed. In the determination process for selecting an external interrupt request with a high priority, the priority order is repeatedly evaluated. In this iterative process, how to allocate the interrupt mask register 34, interrupt status register 35, and interrupt EOI register 36 in FIG. Is an example. Although the for statement has been described as an example showing the repetition structure of the program language, the repetition processing may be described in another language or another repetition structure. The digital signal according to the present embodiment can be applied to an embodiment in which the determination process is merely performed by changing the bit allocation method or using a plurality of registers having substantially the same function as the above three register groups. The superiority of the processor system is not lost.

  Although several embodiments have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Signal processing system (digital signal processor system) 11 ... Radar apparatus, 12 ... A / D converter, 13 ... DSP card, 14 ... VME bus, 15 ... CPU card, 16 ... PCI bus (1st data bus), 18 ... external interrupt control device (interrupt control unit), 19 ... bus protocol conversion function unit (bus interface), 20 ... data bus (second data bus), 21 ... DSP (first DSP), 22 ... DSP (second DSP) , 23 ... signal line, 24 ... personal computer, 25 ... serial communication device (interrupt control unit), 26 ... data bus (second data bus), 27 ... flash ROM, 28 ... high-speed serial communication device (interrupt generation source), 29 ... PCI-VME bridge device (interrupt generation source), 30 ... external storage device, 31 ... CPU, 32 ... DMA controller 33 ... terminal, 34 ... interrupt mask register, 35 ... interrupt status register, 36 ... interrupt EOI register, 37, 38, 39 ... terminal, 40 ... internal memory, 41 ... DMA controller, 42 ... data bus.

Claims (3)

A first data bus;
A plurality of second data buses each connected to the first data bus via a bus interface;
An interrupt generation notification is output by inputting one or more interrupt requests having interrupt factors of a plurality of interrupt requests that are generated on the first data bus or the second data bus and have different generation factors. An interrupt control unit connected to the data bus and the plurality of second data buses;
At least one first DSP that performs a signal processing operation on the data by generating a reception interrupt of the data to be processed output from the interrupt control unit;
A determination process for selecting an external interrupt request having the highest priority among a plurality of external interrupt requests from outside the DSP based on the notification from the interrupt control unit, and an interrupt corresponding to the external interrupt request A second DSP that performs external interrupt processing by executing a handler,
The second DSP repeats the determination process and the external interrupt process within one period, and processes the highest-priority external interrupt request among one or more asynchronous external interrupt requests in a plurality of other periods. A digital signal processor system characterized in that it terminates every other period of time.   The second DSP includes the one or more high-priority external interrupt requests when the external interrupt processing for the high-priority external interrupt request is completed within the period. 2. The digital signal processor system according to claim 1, wherein the determination processing for the asynchronous external interrupt request is performed again. One or more types of interrupt requests having interrupt factors for a plurality of interrupt requests that are generated on the first data bus or a plurality of second data buses connected to the first data bus via a bus interface, respectively. Will output a notification that an interrupt has occurred.
A determination process in which the second DSP on the second data bus selects an external interrupt request having the highest priority among a plurality of external interrupt requests from the outside of the DSP according to the notification within one period according to each priority order; The external interrupt processing by executing the interrupt handler corresponding to the external interrupt request is repeated until the period expires,
The second DSP terminates processing of the highest-priority external interrupt request for each of these other periods among one or more asynchronous external interrupt requests in a plurality of other periods. An interrupt processing method in a digital signal processor system.

Images