JP2013114366A - Quantum computer system, control method and program for quantum computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a quantum computer having both versatility and stability.SOLUTION: The quantum computer system includes: a quantum register composed of at least one or more qubit; a control gate which performs an operation of the quantum register; a quantum unit having a read gate for observing a state of the quantum register; a classic storage device; and a control device accessible to the classic storage device. The classic storage device stores a quantum microcode which is a sequence of operation instructions for the control gate or the read gate. The control device reads the quantum microcode from the classic storage device, and controls the control gate or the read gate.

Description

  The present invention relates to a quantum computer system, a control method of the quantum computer system, and a program, and more particularly, to a quantum computer system having a hybrid configuration of classical-quantum quantum algorithms.

  A problem that has been difficult to solve with a conventional computer (hereinafter referred to as a classical computer) is expected to be solved by a quantum computer that applies the principles of quantum mechanics. The quantum computer uses the superposition state, and can process each superposed state at once (quantum parallelism). For example, in a quantum computer configured with 2 qubits, parallel processing can be performed for each state of 00, 01, 10, and 11. By utilizing quantum parallelism, efficient algorithms using quantum computers have been discovered in several problems that classical computers were not good at. A well-known example is the Shor factorization algorithm described in Non-Patent Document 1, which can perform factorization more efficiently than a classical computer.

  In order to realize quantum computers, innovation is required in each layer of devices, architectures, and algorithms. For example, since a quantum computer device uses quantum mechanical effects, even a slight disturbance disturbs the state, and it is difficult to keep it operating stably. Regarding this problem, efforts to realize a device that operates more stably in the device layer are continuing, but in parallel, efforts in higher layers such as architecture and algorithms are also important. For example, Patent Document 1 attempts to solve this problem by quantum error correction. In addition, the elements (various unitary transformations) used to describe the quantum computer algorithm (hereinafter referred to as the quantum algorithm) do not necessarily correspond one-to-one with the components of the quantum circuit constituting the quantum computer. For this reason, a process corresponding to the logic synthesis in a classical computer is required.

  For example, Patent Document 1 discloses a quantum program conversion device that automatically converts a quantum language that is easy to handle by humans into an optimal quantum circuit corresponding to the quantum system of the quantum computer. That is, the invention of Patent Document 1 compiles and links an input quantum program by dividing it into a classical code and a quantum code. Because the gate used depends on the quantum computer system (difference in hardware), the class code and error correction library for each system are compiled from the quantum code. According to the invention of Patent Document 1, a quantum circuit can be automatically generated for an input quantum program without considering the difference in hardware (quantum system) of the quantum computer.

  Various studies have been made on devices for quantum computers. For example, a solid element using a semiconductor as described in Patent Document 2 is advantageous in practice, and this kind of device will be used in the future. It is thought that devices will be used.

  Patent Document 3 discloses a system and method for local programming of quantum processor elements. That is, a method for programming device parameters of each element (eg, superconducting flux qubit and superconducting charge qubit) in a quantum processor comprising a plurality of elements (programmable devices) and a memory administration system is disclosed. Has been.

JP 2006-331249 A Japanese Patent No. 4213892 Special table 2010-511946 gazette

P. W. Shor, Algorithms for quantum computation: discrete logics and factoring, Proc. 35th Annual IEEE Symposium on Foundations of Computer Science, pp. 124-134, 1994.

  In order to put a quantum computer into practical use, it is important to ensure versatility and stability. From the viewpoint of versatility, it is desirable that the quantum computer be capable of being used universally for a plurality of types of problems as well as being effective for a single type of problem. In terms of stability, the technology for fabricating quantum computer devices is still under development, and the operation of quantum register elements and the like may be unstable. Under such circumstances, it is desired to reduce the time and the number of steps required for the processing as much as possible in order to finish the processing while the element is stable. In other words, there is a demand for versatility that the sequence of the quantum circuit is optimized according to the items to be processed by the user and the type of data so that the processing can be performed in a short time when the element is stable. In addition, at the stage where a large-scale device can be realized in the future, the number of elements becomes enormous and the entire system may become unstable. Furthermore, regarding the failure of the element, various failure modes such as a temporary failure and a permanent failure must be considered.

  The invention of Patent Document 1 relates to a quantum program conversion device based on differences in quantum systems, but it is not disclosed that a user uses a quantum computer for a plurality of types of problems for general purposes. . For example, a general-purpose process by software for a process in which a user gives data to be processed to an application program of a quantum computer, and a specific qubit is read by swapping between a plurality of qubits constituting a quantum register. It is not disclosed how to do this. There is no description about the stability of the operation of the quantum register.

  The invention of Patent Document 2 relates to a device of a quantum computer, and there is no description of software of a quantum computer provided with this device, in particular, versatility and stability when used by a user.

  The invention of Patent Document 3 relates to control of a plurality of superconducting elements (programmable devices) of a quantum computer, and is a technique that allows the characteristics of each superconducting element to be set (programmed) from the outside. Patent Document 3 does not disclose how the entire quantum computer system is controlled by software utilizing the characteristics of the device. That is, there is no description about versatility and stability when a user uses a quantum computer.

  A main object of the present invention is to provide a highly versatile quantum computer system.

  The present invention includes a plurality of means for solving the above-described problems. For example, a quantum computer system includes a classical computer function unit capable of executing a classical program and a quantum computer function unit capable of executing a quantum program. The quantum computer function unit includes a quantum unit, a classical storage device, and a control device, and the classical storage device stores quantum microcode that is a sequence of operation instructions for the quantum unit, and the quantum microcode Is converted from the quantum program, the input data to be processed in the quantum unit and the intermediate data generated based on the classical program, and is converted into the quantum microcode by the control device. The quantum unit is controlled based on the described sequence.

  According to the present invention, a user can generate a program for causing a quantum computer to execute arbitrary processing, and a highly versatile quantum computer system can be realized.

It is a figure which shows the structural example of the quantum computer system which concerns on Example 1 of this invention. FIG. 3 is a diagram illustrating a configuration example of a normal temperature unit of the quantum computer system according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a low temperature part of the quantum computer system according to the first embodiment. 3 is a plan view illustrating a configuration example of a qubit and a control gate in Embodiment 1. FIG. 3 is a plan view illustrating a configuration example of a quantum register, a control gate, and a readout gate in Embodiment 1. FIG. It is a figure explaining the state of a qubit. It is a figure explaining application of the voltage pulse which performs operation with respect to a qubit. It is a figure explaining the other state of a qubit. FIG. 3 is an explanatory diagram illustrating an example of processing (preprocessing and main processing preparation) in the quantum computer system according to the first embodiment. FIG. 3 is an explanatory diagram illustrating an example of processing (main processing and post-processing) in the quantum computer system according to the first embodiment. It is a figure explaining the relationship between a quantum part and training processing. It is a flowchart which shows the example of the training process with respect to a quantum register by the execution manager. It is explanatory drawing which shows the example of the process (training phase process) in a quantum computer system. 4 is an explanatory diagram illustrating a data structure of hardware restriction information according to the first embodiment. FIG. 6 is an example of a flowchart illustrating processing of an execution manager according to the first exemplary embodiment. FIG. 3 is an explanatory diagram illustrating processing in the quantum compiler according to the first exemplary embodiment. It is an example of the block diagram of the normal temperature part of the quantum computer system which concerns on Example 2 of this invention. 6 is an example of a configuration diagram of a low temperature part of a quantum computer system according to Example 2. FIG. FIG. 10 is an explanatory diagram illustrating an example of processing (preprocessing) in the quantum computer system according to the second embodiment. It is explanatory drawing which shows the example of the process (this process preparation, training process, this process, and post-process) in the quantum computer system of Example 2. FIG.

  To give an example of an embodiment of the present invention, a quantum computer system observes a state of a quantum register composed of at least one qubit, a control gate for operating the quantum register, and the quantum register. A quantum unit having a read gate for reading, a classical memory device, and a control device accessible to the classical memory device, wherein the classical memory device is a sequence of operation instructions for the control gate or the read gate. A code is stored, and the control device reads the quantum microcode from the classical storage device and controls the control gate or the read gate.

Thus, the quantum computer can be programmed, thereby realizing the versatility that is one of the problems of the present invention. Further, by utilizing the fact that it is programmable, it is possible to dynamically cope with a problem such as a failure by changing the operation of the program, thereby improving the stability of the quantum computer. Therefore, the above means can provide a quantum computer system that can be used universally and stably.
Embodiments of the present invention will be described below with reference to the drawings.

A quantum computer system according to a first embodiment of the present invention will be described with reference to FIGS.
In this embodiment, an example of a quantum computer system 100 that can be used in a general and stable manner because the quantum computer is programmable will be described.

  FIG. 1 is a diagram illustrating a configuration example of a quantum computer system 100 according to the first embodiment of the present invention. The quantum computer system of the present invention, including the embodiments described later, has the functions of both a quantum computer and a classical computer. That is, the quantum computer system 100 is configured as a hybrid system of a quantum computer function unit having a quantum computer function and a classic computer function unit having a classic computer function.

  In general, there are many types of algorithms for quantum computers (hereinafter referred to as quantum algorithms) that can be classified into three stages: preprocessing by a classical computer, main processing by a quantum computer, and post-processing by a classical computer. For example, Shor's factorization algorithm (Non-Patent Document 1), which is a famous quantum algorithm, generates parameters for the main processing by preprocessing, performs the main processing using the parameters, and obtains the results obtained by the main processing. Is post-processed to obtain a factorization result. In this process, factoring is not performed directly, but the order is found. In the pre-processing, order finding parameters are generated in order to perform factorization using the order finding of this processing. In post-processing, factorization is performed based on the order found in this processing. The pre-processing and post-processing can be performed by the quantum computer, but the processing cannot be speeded up by utilizing the characteristics of the quantum computer. For this reason, pre-processing and post-processing are generally performed by a classical computer. Thus, many quantum algorithms have a classical-quantum hybrid configuration.

  Also in this embodiment, the classical computer function unit includes pre-processing and post-processing units, and the quantum computer function unit includes this processing unit.

  The quantum computer system 100 also includes a normal temperature unit 101 and a low temperature unit 102, and the normal temperature unit 101 and the low temperature unit 102 are connected by a transmission path 103 for communication. That is, the normal temperature unit 101 and the low temperature unit 102 can send and receive programs and data to and from each other via the transmission path 103.

  In general, many quantum computer devices require a low-temperature operating environment. For example, when the device described in Patent Document 2 is adopted as the quantum computer function unit, it is necessary to use the device after cooling to a very low temperature of 4.2K. As described above, since the classical computer function unit that is currently used is premised on normal temperature operation and the quantum computer function unit is premised on low temperature operation, it is necessary to separate the normal computer unit 101 and the low temperature unit 102 from each other. Will understand.

  Also in this embodiment, the classical computer function unit generally corresponds to the normal temperature unit 101 and the quantum computer function unit corresponds to the low temperature unit 102. However, the low temperature unit 102 of the present embodiment includes a micro control unit 301 which is a control device corresponding to a classical computer function unit as well as a quantum computer function unit.

  FIG. 2 is a diagram illustrating a configuration example of the room temperature unit 101 in the quantum computer system 100 of the present embodiment. The hardware configuration of the room temperature unit 101 is basically the same as the hardware configuration of a classic computer that is generally used at present. The room temperature unit 101 includes a main storage device 201, a CPU 202, and an I / O adapter 203. The main storage device 201 holds an application program 210, system software 220, and line time information 230. The CPU 202 executes the system software 220 and the classic object 231 held by the main storage device 201. The I / O adapter 203 communicates with the low temperature unit 102 via the transmission path 103 in response to a request from the CPU 202. In addition, although it is natural that the quantum computer system 100 according to the present embodiment also includes components such as an operating system that are generally provided in the current classical computer, a description thereof will be omitted.

  The application program 210 is a program prepared for each problem to be processed by the quantum computer system 100. As described above, the quantum algorithm includes a pre-processing and post-processing unit executed by the classical computer function unit, and a main processing unit executed by the quantum computer function unit. Correspondingly, the application program 210 is configured as a composite of the classical program 211 and the quantum program 212. The classic program 211 is a program described in a programming language such as C language, for example, and describes processing to be performed by the CPU 202 in pre-processing and post-processing. The quantum program 212 describes a process to be performed by the low temperature unit 102 in this process. The quantum program 212 can be described in a programming language like the classical program 211, or may be expressed as a unitary matrix or a quantum circuit.

  The system software 220 is a software group for causing the CPU 202 to perform control and operation necessary for operating the application program 210 on the CPU 220 and the low temperature unit 102. The system software 220 includes a classic compiler 221, a quantum compiler 222, and an execution manager 223. The classical compiler 221 is software for converting the classical program 211 into a classical object 231 that is a format executable on the CPU 202. You can think of it as synonymous with the processing system of programming languages that are currently in common use. The quantum compiler 222 is software for converting the quantum program 212 into quantum microcode 232 which is a format that can be executed on the low temperature unit 102. The execution manager 223 inputs the input data 233 to the application program 210 and obtains a processing result, so that overall control of necessary processing such as processing by the system software 220 and data transfer between the normal temperature unit 101 and the low temperature unit 102 is performed. It is software that performs.

  The runtime information 230 is data required when the application program 210 is executed, or data or code temporarily generated in the course of execution. The runtime information 230 includes a classic object 231, quantum microcode 232, input data 233, intermediate data 234, and observation data 235. As described above, the classic object 231 is a code that can be executed by the CPU 202 generated by the classic compiler 221. As described above, the quantum microcode 232 is a code that can be executed by the low temperature unit 102 generated by the quantum compiler 222. The input data 233 is data prepared by a user who uses the application program 210 and is data that the application program 210 wants to process. For example, in the example of factorization described above, the composite number to be factored becomes the input data 233. That is, the input data 233 is data to be processed using the quantum unit of the quantum computer function unit. The intermediate data 234 is data generated by preprocessing by the classical program 211. The observation data 235 is data generated by this process, and is transferred from the low temperature unit 102 that executes this process to the room temperature unit 101.

  FIG. 3 is an example of a configuration diagram of the low temperature part 102 of the quantum computer system 100 of the present embodiment. The low temperature unit 102 includes a micro control unit 301, an observation register 302, an I / O adapter 303, a quantum unit 310, and an instruction buffer 320.

  The I / O adapter 303 is connected to the transmission path 103, receives a data transfer request issued by the room temperature unit 101, stores the quantum microcode 321 in the instruction buffer 320, executes an instruction to the micro control unit 301, and the observation register 302 Acquire data from.

  The quantum unit 310 is a core part of the quantum computer function unit, and has a resource for executing processing described in the quantum microcode 321. The quantum unit 310 includes a control gate 311, a quantum register 312, and a read gate 313. The quantum register 312 has one or more qubits that can hold 0, 1, or a superposition state of 0 and 1. A qubit configuration method is described in Patent Document 2, for example.

  FIG. 4 shows an example of the configuration of the qubit block 400 constituting the quantum register 312 in the present embodiment. Here, the qubit 410 is configured as a double qubit in which two quantum dots 411 and 412 are connected. In addition, in order to control the height of the barrier potential, control gates 420, 421, 422, 430, 431, and 432 are attached to the qubit 410. It becomes a component (building block).

  FIG. 5 shows an example of the configuration of the quantum unit 310 in this embodiment. As described above, the quantum unit 310 includes the control gate 311, the quantum register 312, and the read gate 313. Among these, the quantum register 312 is realized by arranging one or more qubit blocks 400 as shown in FIG. In the example of FIG. 5, the quantum register is configured by arranging four qubit blocks 501, 502, 503, and 504 side by side. The control gate 311 is placed in each qubit block (control gates 420, 421, 422, 430, 431, and 432 in FIG. 4). Hereinafter, when the qubits 410 in the qubit blocks 501, 502, 503, and 504 are indicated, they are simply referred to as qubits 501, 502, 503, and 504. In addition, control gates 511, 512, 521, 522 are also placed around the quantum register 312 (qubit blocks 501, 502, 503, 504) as a control gate 311 for initializing each qubit. ing. The read gate 313 is realized as single-electron transistors 531 and 532 placed around the quantum register 312 (qubit blocks 501 and 502).

Hereinafter, it is assumed that the quantum register 312 is an N qubit quantum register having N qubits. This N qubit quantum register has the ability to express a superposition of 2 ^N states from 000... 000 (N is 0) to 111... 111 (N is 1). The control gate 311 is a gate for performing operations on one or a plurality of qubits in the quantum register 312. For example, when the qubit described in Patent Document 2 is adopted as the quantum register, the operation is performed by applying a voltage. Operations that can be performed by the control gate 311 include initialization (initializing the state of the qubit to 0 or 1), Hadamard transformation, control NOT, and the like. In response to an instruction from the micro control unit 301, the control gate performs a designated operation on a designated qubit in the quantum register 312. The read gate 313 is a gate for observing and reading the value of one or a plurality of qubits in the quantum register 312. In response to an instruction from the micro control unit 301, the read gate 313 observes the value of the quantum register 312 and stores the observation result in the observation register 302. At this time, the qubit to be observed is designated by the micro controller 301. With the observation, the observed qubit state converges to either 0 or 1 from the superposition of 0 and 1.

  The instruction buffer 320 holds the quantum microcode 321. This quantum microcode 321 is obtained by transferring the quantum microcode 232 of the room temperature unit 101 via the transmission path 103.

  The observation register 302 is a register that holds the observation result of the quantum register 312 as described above, and this observation register holds a storage element of the classical computer function unit, that is, a binary value of 0 or 1.

  The micro control unit 301 reads the quantum microcode 321 from the instruction buffer 320 and controls the control gate 311 and the read gate 313 based on the sequence described in the quantum microcode 321.

  The quantum microcode 321 is an operation sequence in which commands for controlling the control gate 311 and the read gate 313 are shown in time series. As an instruction, an operation instruction for driving the control gate 311 to operate on a qubit designated in the quantum register 312 and an observation by controlling the read gate 313 are performed, and the observation result is stored in the observation register 302. There is an observation order. The operation command and the observation command are described on the same time series, and the order relationship is maintained between the commands. This has the irreversible effect of converging the superposition state to 0 or 1 when the observation instruction is executed. Therefore, in the quantum algorithm that uses observation in the middle of processing, each operation instruction and the observation instruction are executed. This is because the order becomes important.

  The operation command includes an operation that operates on a single qubit and an operation that operates on a plurality of qubits. Each of them has a qubit number as an operand in order to specify a qubit to be operated. When the quantum register 312 having N qubits is designated as QR, for example, qubit numbers are designated as QR (1) and QR (3) in order to designate qubits in the QR. At this time, the control NOT command can be expressed as “CNOT control queue bit number, target queue bit number” as an operation command. When the qubit number 1 is the control qubit and the qubit number 3 is the target qubit, it is described as “CNOT QR (1), QR (3)”. Similarly, an operation such as Hadamard transformation is prepared as an operation command. The observation instruction is also an instruction using the qubit number of the qubit to be observed as an operand.

  The operation command and the observation command may be a combination of a plurality of controls of the control gate 311 and the read gate 313. For example, a swap instruction for exchanging a state between two qubits can be indicated as an instruction such as “SWAP QR (i), QR (j)” (i and j are qubit numbers), but the control gate 311 directly Even if the swap instruction is not supported, the micro control unit 301 may realize an operation equivalent to the swap instruction by a control NOT instruction or a combination of other instructions.

  As is obvious from the example of FIG. 5, the read gates (single-electron transistors 531 and 532) can read only the qubits 501 and 502, and the qubits 503 and 504 cannot be read. Therefore, a plurality of controls of the control gate 311 and the read gate 313 are combined using the above-described swap. When the qubit 503 is read, the swap is performed between the qubits 501 and 503, and when the qubit 504 is read, the qubit 502 is read. , 504 is required to be swapped.

  FIG. 6 shows an example of a state held by the qubit 410. The two quantum dots 411 and 412 constituting the qubit 410 are assigned to the base | 0> and the base | 1>, respectively. Here, it is assumed that the quantum dot 411 is | 0> and the quantum dot 412 is | 1>. In the example of FIG. 6, it is assumed that electrons are stored in the quantum dot 411 and the state held by the qubit 410 is | 0>. Conversely, if electrons are accumulated on the quantum dot 412 side, the state held by the qubit 410 is | 1>.

  As shown in FIG. 6, a superposition state is created by applying a Hadamard transform to a qubit having a state of | 0> or | 1>, and parallel processing based on the superposition state peculiar to the quantum computer. It can be performed.

  FIG. 7 shows an example of a control gate control method for performing Hadamard transform. The operation on the qubit 410 is performed by applying voltage pulses to the control gates 420, 421, 422, 430, 431, and 432, respectively. The operations that can be realized differ depending on the voltage pulse pattern (amplitude, time, phase relationship with other pulses) applied to each control gate. In the voltage pulse pattern example (Vpa, Vpb, Vpc, Vpd, Vpe, Vpf) of FIG. 7, a pulse acting in the direction of lowering the barrier potential height is applied to the control gates 420, 430.

  As a result, as shown in FIG. 8, the height of the barrier potential between the two quantum dots 411 and 412 decreases, and the state of | 0> and the state of | 1> come and go with a certain probability. . At this time, if the probability of | 0> is α and the probability of | 1> is β, the qubit 410 shown in FIG. 8 has a superposition state of α | 0> + β | 1>. . In this way, various types of operations can be performed by applying voltage pulses to the control gate.

  In the above example, the operation is performed on a single qubit. However, since a plurality of adjacent qubits influence each other on the height of the barrier potential, the control gates of a plurality of qubits can be simultaneously controlled. By applying voltage pulses, operations such as control NOT and swap can be realized. As can be seen from the above, operations for a plurality of qubits can be performed only between adjacent qubits among the plurality of qubits on the plane shown in FIG. For this reason, swapping may be required to perform a desired operation, as in the case of performing reading by the reading gate (single-electron transistors 531 and 532). For example, when it is desired to perform control NOT using the qubit 501 as the control bit and the qubit 504 as the operation bit, the qubits 502 and 504 are swapped, and the qubit 504 is held in the qubit 502 adjacent to the qubit 501. It is necessary to bring a state to do.

  9 and 10 are diagrams showing the relationship between programs or software in the quantum computer system 100. FIG. A user who intends to use the quantum computer system 100 prepares a classical program 211, a quantum program 212, and input data 233.

  In the quantum computer system 100, the process (function) until the program is executed and the result is obtained is the classical compilation phase (classical compilation function) S400 in FIG. 9, the preprocessing phase (preprocessing function) S410 in FIG. Main processing preparation phase (main processing preparation function) S420, main processing execution phase (main processing execution function) S500 in FIG. 10, and post processing phase (post processing function) S510 in FIG.

  In the classical compilation phase S400 of FIG. 9, the classical program 211 is compiled by the classical compiler 221 to obtain the classical object 231. This phase must be performed every time the classical program 211 is changed. The classical compilation phase S400 is the same as the phase in which a computer is generally used at present and a program is compiled to generate an execution format.

  In the preprocessing phase S410, the quantum object is preprocessed by executing the classic object 231. At this time, data and parameters to be processed are given as input data 233. With the input data 233 as an input, the classic object 231 is executed in pre-processing execution S411, and intermediate data 234 is obtained as a processing result. The preprocessing phase S410 needs to be performed every time the input data 233 is changed. For example, when processing a plurality of data and parameters, it is necessary to execute the preprocessing phase S410 each time. In the quantum algorithm that does not require preprocessing, the preprocessing phase S410 can be omitted.

  In this processing preparation phase S 420, the quantum program 212 responsible for this processing in the quantum algorithm is converted into quantum microcode 232 by the quantum compiler 222. Since the quantum microcode 232 needs to include data to be processed by the quantum program 212, the quantum compiler 222 receives the intermediate data 234 generated in the preprocessing phase S410 in addition to the quantum program 212. The generated quantum microcode 232 is transferred to the low temperature part 102 in the low temperature part transfer S421.

  Note that the quantum compiler 222 requires hardware function information 707 and hardware restriction information 708 at the time of compilation as described later. The hardware function information 707 is information determined when the quantum unit 310 is designed, and is prepared in advance. The hardware restriction information 708 is generated in a training phase (training function) S490 described later.

  The training phase S490 is hardware restriction information necessary for generating the quantum microcode 232 that avoids the aging of the quantum unit 310, the manufacturing failure, and the operation failure in the usage environment at that time. This is done to generate 708. Therefore, the training phase S490 is periodically executed at intervals sufficiently shorter than the temporal characteristics (occurrence frequency and change speed) of the change factors that can change the hardware characteristics as described above. Further, when a malfunction of hardware is suspected as a result of executing some processing, such as an incorrect result, training phase S490 is executed.

  In the process execution phase S500 of FIG. 10, this process is executed. The quantum microcode 321 transferred to the low-temperature unit 102 in the processing preparation phase S420 is executed in the quantum unit execution S501, and the processing result is obtained in the observation register 302. Information held in the observation register 302 is transferred to the room temperature unit 101 as a result of this processing in room temperature section transfer S502.

  In the post-processing phase S510, the quantum object is post-processed by executing the classical object 231 as in the pre-processing phase S410. In the post-processing, the execution result of this processing execution phase S500, that is, the observation data 235 transferred in the room temperature portion transfer S502 is used. Therefore, post-processing execution S511 executes the classic object 231 using the observation data 235 as input data. The execution result S512 of the post-processing execution S511 is an execution result finally obtained by executing the quantum algorithm.

  According to this embodiment, the quantum computer can be programmed, thereby realizing a highly versatile quantum computer system. That is, the quantum computer system of the present embodiment is configured as a hybrid system of a quantum computer function unit and a classic computer function unit, and the quantum computer function unit (low temperature unit 102) includes a quantum unit 310, a classical storage device (commands). A buffer 320) and a controller (microcontroller 301) capable of accessing the classical storage device and the quantum unit 310, the quantum unit 310 comprising a quantum register 312 comprising at least one qubit 410, and a quantum register And a read gate 313 for observing the state of the quantum register. The classical memory device stores quantum microcode 321 which is a sequence of operation instructions for the control gate or read gate, and the controller 301 reads the quantum microcode from the classical memory device and controls the control gate or read gate. On the other hand, the classical computer function unit (room temperature unit 101) includes an application program 210 and system software 220, and the system software includes a quantum compiler 222 that converts the quantum program 212 into quantum microcode. As described above, the quantum compiler 222 that generates the quantum microcode 321 incorporating the input data is provided as a hardware configuration of the room temperature unit 101. Therefore, it is possible to easily generate a program that executes a series of sequences using not only the room temperature part 101 but also all the elements of the quantum part 310 of the low temperature part 102. The execution result finally obtained by executing the quantum algorithm in the quantum computer function unit in the low temperature part is output as observation data to the room temperature part. As a result, it is possible to realize a highly versatile quantum computer system that can be used not only for a single type of problem but also for a plurality of types of problems.

  Each of the quantum computer function unit and the classical computer function unit has a program for causing the computer to realize a predetermined function. By executing this program on the computer, the above-described processing functions are realized on the computer. Is done. The program describing this processing function can be recorded on a computer-readable recording medium.

  Next, the training phase S490 that is executed using the fact that the quantum part is programmable as described above will be described. In order to limit the use of unstable elements (qubits) and improve the stability of the quantum computer system, the quantum computer system is operated in advance in the training phase S490, and the operations of the elements constituting the quantum unit 310 are performed. Hardware restriction information 708 for restricting the use of elements that may be unstable is obtained.

  FIG. 11 is a diagram illustrating the relationship between the quantum unit and the training process. The quantum unit 310 includes a quantum register 312 composed of N qubits (qubit numbers 0 to (N−1)) arranged inside the control gate 311. Assume that each qubit is an element whose operation is unstable due to a problem in manufacturing technology. In this training phase S490, information on such qubits is extracted in advance and registered as hardware restriction information 708.

  FIG. 12 is a flowchart showing a training operation for updating the hardware restriction information 708. FIG. 13 is a diagram illustrating an example of the operation in the training phase S490 for executing the training operation in the quantum computer system. This training operation is for detecting the failure status of the quantum register 312 and updating the hardware restriction information 708. The training operation can also be performed in the same manner as the quantum program execution process shown in FIGS. For example, even for a qubit located at a position away from the read gate inside the quantum register 312 like the qubit of number X in FIG. 11, the state is read using the above-described swap. Hereinafter, the flowchart of FIG. 12 and the operation of FIG. 13 will be described in correspondence.

  In step S491 in FIG. 12, quantum microcode for training is executed. There are various modes of operation of the quantum microcode for training. For example, there is a method of generating a specific state for the quantum register 312, reading it, and checking it. For example, if it is initialized to 0, it can be expected to observe 0. If a superposition state of 0 and 1 is generated, it can be expected to observe with the probability according to the probability of each of 0 and 1.

  Step S491 in the training phase corresponds to the transfer of the training microcode 4901 of FIG. 13 to the low temperature unit 102 in the low temperature part transfer S4921 and the execution in the quantum part execution S4922.

  Next, observation is performed in step S492, and in step S493, the observation data is compared with the expected value, and the difference between them is inspected. In the inspection using the superposition state, the inspection cannot be performed only by one observation, and the determination is made by repeating the steps S491 to S493 several times and viewing the statistics of the observation results. Step S492 of FIG. 12 corresponds to that the observation result stored in the observation register 4902 in FIG. 13 is transferred to the room temperature unit 101 by room temperature portion transfer S4923, and step S493 corresponds to the observation result processing S4924.

  Based on the inspection result, hardware restriction information 708 is generated in step S494, and the training is completed. Step S494 corresponds to the generation of the hardware restriction information 708 in the hardware restriction information generation S4925 in FIG.

  FIG. 14 shows an example of the configuration of the hardware control information 708. The hardware configuration information 708 in FIG. 14 has a tabular data structure and includes columns indicating availability, status, and error rate. When the quantum register 312 is composed of N qubits, it is composed of N rows from 0 to N−1 in order to store hardware restriction information for each qubit. The availability indicates whether or not the qubit is available as a result of training. For example, 0 is unavailable and 1 is available. The quantum compiler 222 refers to this information to determine whether the qubit can be used. The status and error rate are for detailed analysis of failure factors and prediction of future failures. The error rate records the qubit error rate, that is, the rate at which the observed data and the expected value are different. The status records, for example, no abnormality (000), the error rate is increasing, but it is still usable (001), and the error rate exceeds the limit value so that it cannot be used (010).

  In each of the phases S400, S410, S420, S500, and S510 shown in FIGS. 9 and 10, the classical compilation phase S400 only needs to be executed once to obtain the classical object 231 unless the classical program 211 is changed. The classic program 211 has a change factor such as an algorithm change or a bug fix, but it is common that none of them is as frequent as it is performed every execution. On the other hand, since the preprocessing phase S410 and later depend on the input data 233, it is necessary to re-execute every time the input data 233 is changed. Therefore, the execution manager 223 of the system software 220 performs the phases S410, S420, S500, and S510 shown in FIGS. 9 and 10 as necessary, and manages the entire execution process in order to execute the quantum algorithm normally. To do. The execution manager 223 is activated by an instruction from a user that instructs the start of execution of the quantum algorithm.

FIG. 15 is a flowchart illustrating an example of the operation of the execution manager 223.
In step S601, it is checked whether the intermediate data 234 exists and whether the input data 233 has been changed. The absence of the intermediate data 234 means that the preprocessing has not yet been performed, and the preprocessing phase S410 needs to be executed, and thus the process proceeds to step S602. Also, if there is a change in the input data 233, even if the intermediate data 234 exists, it corresponds to the old input data 233 before the change, so the preprocessing phase S410 is executed again to execute the intermediate data 234 must be updated. Therefore, it progresses to step S602 similarly. Only when the input data 233 is not changed and the corresponding intermediate data 234 has already been generated, the preprocessing phase S410 can be omitted. Therefore, at this time, the preprocessing phase S410 is omitted and the process proceeds to step S603.

In step S602, the above-described preprocessing phase S410 is executed, and the process proceeds to step S603.
In step S603, it is checked whether the quantum microcode 232 exists and whether the intermediate data 234 has been changed. If the quantum microcode 232 does not exist, the process transitions to step S604 in order to execute the processing preparation phase S420 and generate the quantum microcode 232. In addition, even if the quantum microcode 232 exists, if the intermediate data 234 is changed, the quantum microcode 232 depends on the intermediate data 234, so that this processing preparation phase S420 is executed again. The process proceeds to step S604. Although the idea is the same as in step S601, if the quantum microcode 232 already exists and the intermediate data 234 is not changed, the process preparation phase S604 is omitted and the process execution phase S605 is entered. move on.

In step S604, the process preparation phase S420 described above is executed, and the process proceeds to step S604.
In step S605, the process execution phase S500 described above is executed, and the process proceeds to step S605.

In step S606, it is checked whether or not the number of executions of this process execution phase S500 has reached the prescribed number. If not, the process returns to step S605 to execute this process execution phase S500 again. If the number of executions is satisfied, the process proceeds to step S607. The number of executions is defined by input data 233 or intermediate data 234.
In step S607, the post-processing phase S510 described above is executed, and the process proceeds to step S608.

  In step S608, the execution result S512 obtained in the post-processing phase S510 is inspected, and the process ends if the process is successful. If the processing has failed such as an incorrect execution result is obtained, the process returns to the top of the flowchart of FIG. 15 to execute again. At this time, the input data 233 is changed in step S609 as necessary. The input data 233 is changed by a user operation or execution of the classic object 231. That is, the classic object 231 plays a role of changing the input data 233 at the time of re-execution as part of the pre-processing or post-processing.

  FIG. 16 is a diagram illustrating the relationship between the operation of the quantum compiler 222 and the input and output. The quantum compiler 222 receives the quantum program 212 and the intermediate data 234 as input and generates a quantum microcode 232. This generation function, that is, the processing (S701 to S706) performed in the quantum compiler 222 of FIG. 16 is referred to as compilation. Hardware function information 707 and hardware restriction information 708 are also used as inputs during the compilation process.

  The hardware function information 707 is information that defines a function of the low-temperature unit 102 that is a quantum computer function unit in the quantum computer system 100. Specifically, it is shown as a restriction in generating the quantum microcode 232. For example, information that a CNOT instruction is available is recorded. Also, constraints on operands are specified. For example, when the CNOT instruction can be applied only between adjacent qubits on the quantum register 312, if the qubits QR (i) and QR (i + 1) on the quantum register QR are adjacent qubits, the operand of the CNOT instruction Describes a constraint that QR (i), QR (i + 1) must be satisfied. The quantum compiler 222 generates the quantum microcode 232 based on the constraints defined by the hardware function information 707.

  The hardware restriction information 708 is information indicating a failure caused by manufacturing variation or failure of the quantum unit 310. Among the components constituting the quantum unit 310, the quantum register 312 is particularly susceptible to disturbance, and the failure probability of the entire quantum register 312 increases as the number of qubits increases. On the other hand, as described in the background art, quantum error correction technology is used, but when there is a qubit that is constantly broken, not only the quantum error correction technology but also at the program stage. By avoiding and using the qubit, it can be expected that the qubit can be used more stably. Therefore, the quantum compiler 222 generates the quantum microcode 232 so that the failure qubit indicated by the hardware restriction information 708 is not used.

  The hardware function information 707 is information that can be determined at the time of design because it is determined by the specifications of the low temperature part 102. On the other hand, the hardware restriction information 708 is affected by variations and deterioration during manufacture of the quantum unit 310, the operating environment, and the like, so that the restriction changes during operation of the quantum computer system 100. That is, a means for updating the hardware restriction information 708 during operation is required. For this purpose, the training phase S490 described above is used.

  Among the compilations performed by the quantum compiler 222, the lexical analysis S701, the syntax analysis S702, and the semantic analysis S703 are the same as the compiler used in the conventional classical computer, and thus the description thereof is omitted. A general compiler of a conventional classical computer performs code generation and optimization after lexical analysis, syntax analysis, and semantic analysis of an input program (source code). In contrast, the quantum compiler 222 performs a process of data embedding S704 after the semantic analysis S703.

  Data embedding S704 is an intermediate language (intermediate format) inside the quantum compiler 222 obtained as a result of the semantic analysis S703, and applies the data shown in the intermediate data 234 to the variable input to the quantum program 212. I do. By this processing, variables to be input at the time of execution are input at the time of compiling with the quantum compiler 212.

  In the code generation S705, the quantum microcode S705 is generated from the intermediate language after the data embedding S704 is completed. At this time, by referring to the hardware function information 707, restrictions on available instructions and operands are acquired. The processing expressed in the intermediate language is expressed by a combination of available instructions shown in the hardware function information 707. In order to satisfy the constraints of the operand, a swap instruction for exchanging the states held by the two qubits in the quantum register 312 is added.

  In the code generation S705, the quantum microcode S705 is generated in consideration of not only the hardware function information 707 but also the restrictions indicated in the hardware restriction information 708. Since the hardware restriction information 708 indicates an unusable qubit, a swap instruction or the like is added so as to perform processing while avoiding this qubit.

  Finally, the quantum microcode generated by the code generation S705 in the optimization S706 is optimized, and the quantum microcode 232 is output as a compilation result.

  According to the present embodiment, it is possible to generate a program for executing a series of sequences using the classical computer function unit and the quantum computer function unit, thereby realizing a highly versatile quantum computer system. Further, by utilizing the fact that it is programmable, it is possible to increase the stability by executing a training phase in advance and dynamically responding to a problem such as a failure by changing the operation of the program. As a result, a quantum computer system that can be used universally and stably can be provided.

Next, a quantum computer system according to Embodiment 2 of the present invention will be described with reference to FIGS.
In this embodiment, another embodiment of the quantum computer system 100 that can be used for general purpose and stably by being programmable will be described. In the second embodiment, the entire configuration of the quantum computer system including the classical computer function unit and the quantum computer function unit is the same as that of the first embodiment shown in FIG. 1, but the configurations of the normal temperature unit 101 and the low temperature unit 102 are different. The description of the components having the same reference numerals as those in the drawings described in the first embodiment and the same functions is omitted.

  In configuring the quantum computer system 100, both ends of the transmission path 103 have a significant temperature difference. Therefore, there is a possibility that the latency and throughput of the transmission path 103 are not necessarily good. On the other hand, since the quantum microcode 232 can be said to be a high-level description of the quantum program 212 written into lower-level operation instructions and observation instructions, the code length is longer than that of the original program. become. In the case where the performance that can withstand transmission of such a long quantum microcode cannot be realized by the transmission path 103, in this embodiment, an embodiment of the quantum computer system 100 that reduces the performance requirements required for the transmission path 103 is described. Show.

  In this embodiment, the quantum computer system 100 of FIG. 1 uses a configuration in which the normal temperature part 100 is replaced with a normal temperature part 1001 shown in FIG. 17 and the low temperature part 102 is replaced with a low temperature part 1101 shown in FIG. Accordingly, the operations of the preprocessing phase S410 and the main processing preparation phase S420 described in FIG. 9 and the main processing execution phase S500 described in FIG. Each will be described below.

  FIG. 17 is an example of a configuration diagram illustrating the configuration of the room temperature unit 1001 in the second embodiment. Compared with the normal temperature unit 100 of the first embodiment, the normal temperature unit 1001 of the second embodiment is characterized in that the quantum compiler 222 is not provided. Further, since the quantum compiler 222 is not provided, the quantum microcode 232 generated by the quantum compiler 222 is not provided.

  FIG. 18 is an example of a configuration diagram illustrating the configuration of the low temperature section 1101 in the second embodiment. Compared with the low temperature unit 102 of the first embodiment, the micro control unit 301 is replaced with a CPU 1102. Accordingly, the instruction buffer 320 attached to the microcontroller 301 in the first embodiment is changed to the main storage device 1130 of the CPU 1102 in the second embodiment. The main storage device 1130 includes intermediate data 1131, a quantum program 1132, a quantum compiler 1133, and quantum microcode 1134. The intermediate data 1131 and the quantum program 1132 are obtained by transmitting the intermediate data 234 and the quantum program 212 of the room temperature unit 1001 via the transmission path 103. That is, in the first embodiment, the transmission path 103 transmits the quantum microcode 321, but in this embodiment, the transmission path 103 transmits the intermediate data 1131 and the quantum program 1132. If the sizes of the intermediate data 1131 and the quantum program 1132 are smaller than the quantum microcode 1134, the load on the transmission path 103 can be reduced as compared with the first embodiment.

  The CPU 1102 executes the quantum compiler 1133, and generates the quantum microcode 1134 using the intermediate data 1131 and the quantum program 1132 as inputs of the compiler. Further, the quantum unit 310 is controlled based on the generated quantum microcode 1134. Therefore, the compilation and control of the quantum unit 310 can be pipelined, and the capacity of the main memory 1130 for storing the quantum microcode 1134 can be reduced.

  FIG. 19 is a diagram illustrating an example of the operation of the preprocessing S phase 1200 according to the second embodiment. In the first embodiment, the quantum microcode 232 is generated in the processing preparation phase S420 of FIG. 9, and then the low temperature part transfer S421 is performed. On the other hand, in this embodiment, as shown in the preprocessing phase S1200 of FIG. 19, when the intermediate data 234 can be generated, the intermediate data 234 and the quantum program 212 are transferred to the low temperature part 1101 by the low temperature part transfer S1201. .

  FIG. 20 is a diagram illustrating an example of operations of the main process preparation phase S1300 and the main process execution phase S1310 according to the second embodiment. In the first embodiment, the processing preparation phase S420 is executed in the room temperature unit 101. In the second embodiment, the processing preparation phase S1300 is executed by the CPU 1102 of the low temperature unit 1101. In the processing preparation phase S1300, the quantum program 1132 responsible for the processing in the quantum algorithm is converted into the quantum microcode 1134 by the quantum compiler 1133. Since the quantum microcode 1134 needs to include data to be processed by the quantum program 1132, the quantum compiler 1133 receives the intermediate data 1131 in addition to the quantum program 1132. The intermediate data 1131 and the quantum program 1132 required by the quantum compiler 1133 are those transferred from the normal temperature part 1001 to the low temperature part 1101 by the low temperature part transfer 1201 of the preprocessing phase 1200 described above. Further, as in the first embodiment, the quantum compiler 1133 requires the hardware function information 707 and the hardware restriction information 708 at the time of compilation. The hardware restriction information 708 is generated in the training phase S490.

  In the second embodiment, since the quantum compiler 1133 is in the low-temperature unit 102, the processing corresponding to the low-temperature unit transfer S4921 and the quantum unit execution S4922 in the training phase S490 illustrated in FIG. Processing corresponding to the result processing S4924 and the hardware restriction information generation S4925 can be performed on the CPU 1102 in the low temperature unit 102. In this case, the training phase S490 can be executed at an interval shorter than that in the first embodiment, so that it is possible to improve the ability to follow changes in hardware characteristics.

  According to this embodiment, the quantum computer can be programmed, thereby realizing a highly versatile quantum computer system. That is, the quantum computer system of the present embodiment is configured as a hybrid system of a quantum computer functional unit and a classical computer functional unit, and the quantum computer functional unit (low temperature unit 1101) includes the quantum unit 310, the classical storage device (main memory). Storage unit 1130) and a control unit (CPU 1102) capable of accessing this classical storage unit, and quantum unit 310 includes quantum register 312 composed of at least one qubit 410 and control for operating the quantum register It has a gate 311 and a read gate 313 for observing the state of the quantum register. The classical storage device stores the quantum compiler 1133 that converts the quantum program 1132 into the quantum microcode 1134 and the quantum microcode 1134 that is a sequence of operation instructions for the control gate or the read gate, and the control device 1102 includes the classical storage device. The quantum microcode is read out from the control gate or the control gate or readout gate is controlled. On the other hand, the classical computer function unit (normal temperature unit 1001) includes an application program 210 and system software 220. As described above, the low-temperature unit 1101 includes a quantum compiler 1133 that generates quantum microcode 1134 incorporating input data. Therefore, it is possible to easily generate a program that executes a series of sequences using not only the room temperature part 101 but also all the elements of the quantum part 310 of the low temperature part 102. The execution result finally obtained by executing the quantum algorithm in the quantum computer function unit in the low temperature part is output as observation data to the room temperature part. As a result, it is possible to realize a highly versatile quantum computer system that can be used not only for a single type of problem but also for a plurality of types of problems.

  According to the present embodiment, it is possible to generate a program for executing a series of sequences using the classical computer function unit and the quantum computer function unit, thereby realizing a highly versatile quantum computer system. Further, by utilizing the fact that it is programmable, it is possible to increase the stability by executing a training phase in advance and dynamically responding to a problem such as a failure by changing the operation of the program. As a result, a quantum computer system that can be used universally and stably can be provided. In addition, it is possible to improve followability to changes in hardware characteristics.

  Note that the quantum computer function unit described in each of the above embodiments may be based on other hardware such as nuclear magnetic resonance, quantum optics, and superconducting magnetic flux.

DESCRIPTION OF SYMBOLS 100 Quantum computer system 101 Normal temperature part 102 Low temperature part 103 Transmission path 201 Main memory 202 CPU
203 I / O adapter 210 Application program 211 Classical program 212 Quantum program 220 System software 221 Classical compiler 222 Quantum compiler 223 Execution manager 230 Runtime information 231 Classical object 232 Quantum microcode 233 Input data 234 Intermediate data 235 Observation data 301 Micro controller 302 Observation register 303 I / O adapter 310 Quantum unit 311 Control gate 312 Quantum register 313 Read gate 320 Instruction buffer 321 Quantum microcode 400 Qubit block 410 Qubit 411, 412 Quantum dot 420, 421, 422, 430, 431, 432 Control Gates 501, 502, 503, 504 Qubit blocks 511, 512, 5 21, 522 Control gate 531, 532 Single-electron transistor S400 Classical compilation phase S410 Preprocessing phase S411 Preprocessing execution S420 Main processing preparation phase S421 Low-temperature part transfer S490 Training phase S500 Main processing execution phase S501 Quantum part execution S502 After normal temperature part transfer S510 Processing phase S511 Post-processing execution S512 Execution result S701 Lexical analysis S702 Syntax analysis S703 Semantic analysis S704 Data embedding S705 Code generation S706 Optimization 707 Hardware function information 708 Hardware restriction information 1001 Normal temperature part 1101 Low temperature part 1102 CPU
1130 Main memory 1131 Intermediate data 1132 Quantum program 1133 Quantum compiler 1134 Quantum microcode S1200 Preprocessing phase S1201 Low temperature part transfer S1300 Main process preparation phase S1310 Main process execution phase 4901 Training microcode 4902 Observation register S4921 Low temperature part transfer S4922 Quantum part Execution S4923 Normal temperature part transfer S4924 Observation result process S4925 Generation of hardware restriction information.

Claims (20)

A classical computer function unit capable of executing classical programs and a quantum computer function unit capable of executing quantum programs are provided.
The quantum computer function unit includes a quantum unit, a classical storage device, and a control device,
The classical storage device stores quantum microcode which is a sequence of operation instructions for the quantum unit, and the quantum microcode includes the quantum program, input data to be processed in the quantum unit, and the classical program. Converted from the intermediate data generated based on
The quantum computer system, wherein the control unit controls the quantum unit based on a sequence described in the quantum microcode. In claim 1,
The quantum part is
A quantum register composed of at least one qubit;
A control gate that operates on the quantum register;
A readout gate for observing the state of the quantum register;
The classical storage device stores the quantum microcode that is converted from the quantum program and is a sequence of operation instructions for the control gate or the read gate,
The quantum computer system, wherein the control device reads the quantum microcode from the classical memory device and controls the control gate or the read gate. In claim 2,
A quantum compiler for converting the quantum program into the quantum microcode;
The quantum compiler system outputs the input data embedded in the quantum microcode. In claim 3,
A quantum computer system, wherein the classical computer function unit includes the quantum compiler. In claim 3,
A quantum computer system, wherein the quantum computer function unit includes the quantum compiler. In claim 3,
Hardware function information that defines the functions of the quantum computer function unit such as the types and restrictions of operations that can be realized by the control device controlling the control gate or the read gate;
The quantum computer system, wherein the quantum compiler generates the quantum microcode satisfying a constraint defined by the hardware function information. In claim 3,
It has hardware restriction information for storing information such as availability and error rate for each of the qubits constituting the quantum register,
The quantum computer system, wherein the quantum compiler generates the quantum microcode using only qubits that can be used in the hardware restriction information. In claim 7,
The hardware configuration information includes information indicating availability, status, and error rate for each of the N qubits constituting the quantum register,
The error rate is a record of an error rate in which the observation data and the expected value of the qubit are different,
2. The quantum computer system according to claim 1, wherein the status is a record of an error rate state of each qubit. In claim 8,
Having a quantum program for training that determines whether or not the qubit is available or measures an error rate;
A quantum computer system that executes the training quantum program and updates the hardware restriction information. In claim 3,
The qubit in the quantum register can be operated only between the qubits arranged adjacent to each other,
The control gate has a swap operation to exchange a state between the adjacently arranged qubits;
The quantum computer system, wherein the quantum compiler inserts the swap operation into the quantum microcode. In claim 3,
2. The quantum computer system according to claim 1, wherein the quantum register has one or more qubits capable of holding a superposed state of 0, 1, or 0 and 1. In claim 3,
The quantum algorithm of the quantum computer system includes at least four stages of a preprocessing phase, a main processing preparation phase, a main processing phase, and a postprocessing phase,
In the preprocessing phase, with the input data as input, the classical object is executed, and intermediate data is generated as a processing result,
In the main processing preparation phase, the intermediate data is input, and the quantum program responsible for the main processing is converted into quantum microcode by the quantum compiler to generate quantum microcode,
In the main processing phase, the quantum microcode is executed in the quantum unit, and a processing result is acquired in an observation register.
In a post-processing phase, the classical computer is executed using the observed data as input data, and an execution result is obtained. In claim 12,
The quantum computer system is composed of a normal temperature part, a low temperature part, and a transmission path for performing communication between the normal temperature part and the low temperature part,
The pre-processing phase, the training phase, the main processing preparation phase and the post-processing phase are executed by the classic computer function unit operating in the room temperature unit,
According to the training phase, the quantum computer system is operated, the operation of the elements constituting the quantum unit is inspected, and hardware restriction information for restricting the use of elements that may be unstable is obtained,
The quantum computer system characterized in that the processing phase is executed by the quantum computer function unit operating in the low temperature unit. In claim 12,
The quantum computer system is composed of a normal temperature part, a low temperature part, and a transmission path for performing communication between the normal temperature part and the low temperature part,
The pre-processing phase and the post-processing phase are executed by the classic computer function unit operating in the normal temperature unit,
The training phase, the main processing preparation phase, and the main processing phase are executed by the quantum computer function unit operating in the low temperature unit,
According to the training phase, the quantum computer system is operated, the operation of the elements constituting the quantum unit is inspected, and hardware restriction information for restricting use of elements that may be unstable is obtained. Quantum computer system. A method for controlling a quantum computer system, comprising:
The quantum computer system includes a classical computer function unit capable of executing a classical program and a quantum computer function unit capable of executing a quantum program,
The quantum computer function unit includes a quantum unit, a classical storage device, and a control device,
Converting the quantum program, input data to be processed in the quantum unit and intermediate data generated based on the classical program to generate quantum microcode,
Storing the quantum microcode in the classical memory device;
A control method for a quantum computer system, wherein the control unit controls the quantum unit based on a sequence described in the quantum microcode. In claim 15,
The quantum part is
A quantum register composed of at least one qubit;
A control gate that operates on the quantum register;
A readout gate for observing the state of the quantum register;
A quantum computer system, wherein the control device reads the quantum microcode, which is a sequence of operation instructions for the control gate or the read gate, from the classical memory device and controls the control gate or the read gate. Control method. In claim 15,
A quantum compiler for converting the quantum program into the quantum microcode;
A quantum computer system control method, wherein the quantum compiler embeds the input data in the quantum microcode and outputs the embedded data. A quantum computer system program configured as a combination of a classical program and a quantum program,
The quantum computer system includes a classical computer function unit and a quantum computer function unit,
The classical computer function unit includes a CPU capable of executing the classical program,
The quantum computer function unit includes a quantum unit, a classical storage device, and a control device,
In the classic computer function section,
Using the classic program and input data as input, realizing the function of executing the classic program and generating intermediate data,
In the quantum computer function unit,
A function for obtaining observation data by causing the quantum unit to execute quantum microcode converted from the quantum program and the intermediate data;
A program for realizing the function of transferring the observation data to the classical computer function unit. In claim 18,
The quantum computer function unit includes a quantum compiler that converts the quantum program into the quantum microcode.
The quantum unit includes, as resources for executing processing described in the quantum microcode, a quantum register including at least one qubit, a control gate, and a read gate,
In the quantum computer system,
The quantum compiler has the input of the quantum program and input data to be processed by the quantum program, and the output of the input data embedded in the quantum microcode.
A function of storing the quantum microcode, which is a sequence of operation instructions for the control gate or the read gate, in the classical storage device;
A program for reading the quantum microcode from the classical memory device and realizing the function of controlling the control gate or the read gate. In claim 18,
The quantum computer system includes:
Hardware function information that defines functions of the quantum computer function unit such as types of operations and restrictions that can be realized by controlling the control gate or the read gate by the control device;
Hardware restriction information for storing information such as availability and error rate for each of the qubits constituting the quantum register;
In the quantum computer system,
A program for realizing a function in which the quantum compiler generates the quantum microcode using only qubits that satisfy the constraints defined by the hardware function information and can be used in the hardware restriction information.

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