JP2013114296A - Design method of dummy pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design method of a dummy PT capable of reducing parasitic resistance of a wiring PT.SOLUTION: The design method includes the steps of: reducing a notch PT 2 by a specified value Δx1 in prescribed directions respectively to generate a reduced diagram 4; enlarging the reduced diagram 4 by the specified value Δx1 in the prescribed directions to generate a dummy PT 5; extracting the outline thereof to generate a rectangular diagram 6; reducing the rectangular diagram 6 by the specified value Δx1 in the prescribed directions to generate a reduced diagram 7; logically subtracting the reduced diagram 7 from the dummy PT 5 to generate a notch diagram 8 and a rectangular diagram 9; extracting the notch diagram 8; generating a rectangular diagram 21 from the outline of the notch diagram 8; comparing the notch diagram 8 and the rectangular diagram 21 to extract end sides 22 of a notch 3 of the notch diagram 8; extracting a side 23 extending in a direction orthogonal to the prescribed directions; generating a rectangular diagram 24 from the side 23; logically subtracting the rectangular diagram 24 from the notch diagram 8 to generate a rectangular diagram 25; deleting the notch diagram 8 from the notch diagram 8 and the rectangular diagram 9; logically adding the rectangular diagram 9 and the rectangular diagram 25 to generate first and second via arrangement regions 26, 27; and arranging vias 28 in each of the via arrangement regions 26, 27.

Description

  The present invention relates to a method for designing a dummy pattern in a semiconductor integrated circuit device having a multilayer wiring structure.

A semiconductor integrated circuit device usually has a multilayer wiring structure in which a plurality of metal wiring layers and a plurality of insulating layers are alternately stacked.
In a semiconductor integrated circuit device having such a multilayer wiring structure, a region in which a plurality of metal wiring layers are stacked and a region in which a plurality of metal wiring layers are not stacked are mixed depending on the difference in area and arrangement density of the metal wiring pattern. Variation in thickness occurs in the part.
When the variation in thickness is large, the thickness of the insulating layer and the metal wiring layer at the stepped portion is reduced. Since the insulation is deteriorated in the portion where the thickness of the insulating layer is thin, a short circuit failure may occur between the metal wiring layers in the stacking direction. In the portion where the thickness of the metal wiring layer is thin, the metal wiring pattern of the portion may be disconnected.
Therefore, the surface of the insulating layer formed on the metal wiring layer is planarized by using, for example, a CMP (Chemical Mechanical Polishing) method.

  However, if the level difference on the surface of the insulating layer formed on the metal wiring layer is large, the polishing time until flattening becomes longer, which may cause the productivity to deteriorate or expose the lower metal wiring layer. May end up. If the upper metal wiring layer is formed on the planarized insulating film with the lower metal wiring layer exposed, a short circuit may occur at the exposed portion of the upper metal wiring layer and the lower metal wiring layer. is there.

  Therefore, by providing a dummy pattern unrelated to the circuit configuration in the metal wiring layer, variation in the arrangement density of the metal wiring pattern in the metal wiring layer is reduced by the dummy pattern (for example, Patent Document 1). .

JP 9-115905 A

  A dummy pattern as disclosed in Patent Document 1 is generally formed in a region where a metal wiring pattern is not formed by a CAD (Computer Aided Design) process using DRC (design rule check). The data is uniformly generated for the purpose of reducing the variation of the density.

By the way, with the development of semiconductor process miniaturization technology, the density and scale of semiconductor integrated circuits are increasing. As a result, the metal wiring pattern tends to have a narrow line width and a long wiring length, and the parasitic resistance of the metal wiring pattern has a great influence on the delay of the circuit, which is one of the factors that cause the circuit to malfunction. It has become.
In addition, the effect of the parasitic resistance of the metal wiring pattern for the power supply wiring, combined with the current flowing through the power supply wiring, causes a drop in the voltage supplied to each circuit. This drop in voltage is referred to as an IR drop, and this IR drop may cause a timing delay, causing the semiconductor integrated circuit device to malfunction. In order to operate the circuit stably, it is desirable to reduce the parasitic resistance by increasing the line widths of the power supply wiring and the GND wiring as much as possible. However, if the line widths of the power supply wiring and the GND wiring are increased, the chip area increases, and the chip cost increases according to the chip area.

  Therefore, the present invention provides a dummy pattern design method capable of suppressing malfunction due to parasitic resistance of a metal wiring pattern of a semiconductor integrated circuit device while suppressing an increase in chip area. An object of the present invention is to provide a method for designing a dummy pattern having a shape.

In order to solve the above problems, the present invention provides the following dummy pattern design method.
Connected to the wiring pattern (1) via the via (28) to the second wiring layer arranged in the stacking direction of the first wiring layer having the wiring pattern (1) including the pattern extending in one direction. In the dummy pattern design method for generating a dummy pattern (5) to be generated, a dummy pattern generation pattern (2) having a notch (3) at a corner in a region corresponding to the wiring pattern (1) is generated. A dummy pattern generating pattern generating step, and the dummy pattern generating pattern (2) is reduced by a predetermined value (Δx1) in each of the one direction and the opposite direction to the one direction, and the first reduced figure (4 ) And a first reduced figure (4) enlarged in the one direction and the opposite direction by the predetermined value (Δx1), respectively, A dummy pattern generating step for generating 5), and a first rectangular figure (6) for extracting an outer shape of the dummy pattern (5) and generating an outer side of the dummy pattern (5) as one side. A second rectangular figure generation step of generating a second reduced figure (7) by reducing the first rectangular figure (6) by the predetermined value (Δx1) in the one direction and the opposite direction, respectively. A reduced graphic generation step, logically subtracting the second reduced graphic (7) from the dummy pattern (5), a notched graphic (8) having a notch (3) at a corner, and a second A notch figure and a rectangle figure generation step for generating a rectangle figure (9), respectively, and the notch figure having no rectangle shape among the notch figure (8) and the second rectangle figure (9) Notch figure extraction to extract (8) A third rectangular figure generating step for extracting an outer shape of the cutout figure (8) and generating a third rectangular figure (21) having an outer peripheral side of the cutout figure as one side; A first notch edge extraction step for comparing the notch figure (8) with the third rectangular figure (21) and extracting each edge (22) of the notch (3); Of the sides (22), a second notch edge extraction step for further extracting a side (23) extending in a direction orthogonal to the one direction, and a side extending in a direction orthogonal to the one direction ( A fourth rectangular figure generating step for generating a fourth rectangular figure (24) having one side as one side and extending in the one direction and having a side longer than the predetermined value as the other side; and the notch A fifth rectangular figure is obtained by logically subtracting the fourth rectangular figure (24) from the figure (8). Of the fifth rectangular figure generation step for generating (25) and the cutout figure (8) and the second rectangular figure (9) generated in the cutout figure and rectangular figure generation step, A notch figure deletion step for deleting the notch figure (8), the second rectangular figure (9) left in the notch figure deletion step, and the fifth rectangle figure generation step generated in the fifth rectangle figure generation step. A via placement area generating step for logically adding the rectangular figure (25) and generating a first via placement area (27) and a second via placement area (26) that are spaced apart from each other; A via cell generation step of generating a via cell in which the via (28) is arranged in the first via arrangement region (27) and a via cell in which the via (28) is arranged in the second via arrangement region (26); including A method of designing a dummy pattern characterized and.

  According to the present invention, in particular, in a dummy pattern design method in which corners have cutout shapes, it is possible to suppress malfunction due to parasitic resistance of a metal wiring pattern of a semiconductor integrated circuit device while suppressing an increase in chip area. There is an effect that becomes possible.

1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. It is a typical plane perspective view for demonstrating 1st Embodiment of the design method of the dummy pattern of this invention. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. 1 is a schematic plan view for explaining a first embodiment of a dummy pattern designing method of the present invention; FIG. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention. It is a typical plane perspective view for demonstrating 2nd Embodiment of the design method of the dummy pattern of this invention.

  The preferred embodiments of the present invention will be described with reference to FIGS.

<First Embodiment>
A first embodiment of a dummy pattern designing method according to the present invention will be described with reference to FIGS.

First, “first metal wiring layer data” of a first metal wiring layer composed of a plurality of metal wiring patterns is created.
The “first metal wiring layer data” includes, for example, data of the metal wiring pattern 1 shown in FIG.

  Next, “second metal wiring layer data” of the second metal wiring layer positioned in the stacking direction with respect to the first metal wiring layer is created.

In general, CAD (Computer Aided Design) that performs automatic wiring processing is often ruled so that wiring is performed only in a predetermined direction in a predetermined metal wiring layer. This wiring method is a method for efficiently wiring while suppressing occurrence of a metal wiring short-circuit between metal wiring layers between stacked layers. For example, the first metal wiring layer is wired only in the X direction, the second metal wiring layer is wired only in the Y direction, and the metal wiring pattern of the first metal wiring layer and the metal wiring pattern of the second metal wiring layer are In many cases, there is a dead space having no metal wiring pattern other than the three-dimensionally intersecting part or the part where the via is overlapped.
In this dead space, a dummy pattern is generally generated uniformly by CAD processing for the purpose of reducing variation in the density of the metal wiring pattern.

  In the first embodiment, when the region corresponding to the metal wiring pattern 1 in the second metal wiring layer is a dead space without the metal wiring pattern, the dummy pattern is not generated uniformly as in the prior art. Instead, a dummy pattern is generated based on the shape of the metal wiring pattern 1.

However, in actuality, due to the influence of the shape and arrangement of other metal wiring patterns, it may not be possible to generate a basic dummy pattern generation pattern having the same shape as the metal wiring pattern 1, for example, as shown in FIG. As shown, a dummy pattern generating pattern 2 having a notch 3 at a corner is generated.
However, since the conventional via arrangement rule according to the DRC rule cannot cope with the dummy pattern generating pattern 2 having the notch 3 at the corner, a DRC error may occur.

  Therefore, a method for designing a dummy pattern in the first embodiment will be described below.

As shown in FIG. 3, the dummy pattern generating pattern 2 in the second metal wiring layer is reduced by Δx1 (for example, 4.01 μm) in the X direction (left and right direction in FIG. 16).
As a result of the reduction, a figure whose width in the X direction is smaller than “2 × Δx1” (for example, 8.00 μm) disappears.
For example, the dummy pattern generation pattern 2 in FIG. 2 becomes a reduced figure 4 in FIG. 3 by reduction in the X direction.

As shown in FIG. 4, the reduced figure 4 is similarly enlarged by Δx1 in the X direction (left and right direction in FIG. 4).
By the enlargement in the X direction, the reduced figure 4 in FIG. 3 becomes the enlarged figure 5 in FIG.
This enlarged figure 5 becomes a dummy pattern 5 corresponding to the metal wiring pattern 1 of the first metal wiring layer in the second metal wiring layer.

In general, in the via placement rule according to the DRC rule, the number of via rows and the number of columns are determined so that the maximum number of vias can be placed in a rectangular area. Therefore, the via arrangement area is required to be rectangular in principle.
Therefore, a method for generating a via cell that connects the metal wiring pattern 1 of the first metal wiring layer and the dummy pattern 5 of the second metal wiring layer in the stacking direction will be described below as a first embodiment.

  The external shape of the dummy pattern 5 shown in FIG. 4 is extracted, and a rectangular figure 6 having one side of the outer periphery of the dummy pattern 5 is generated (see FIG. 5).

  As shown in FIG. 6, the rectangular figure 6 is similarly reduced by Δx1 in the X direction (left and right direction in FIG. 6) to obtain a reduced figure 7.

  By performing logical subtraction of the reduced figure 7 shown in FIG. 6 from the dummy pattern (enlarged figure) 5 shown in FIG. 4, the notch figure 8 having the notch 3 and the rectangular figure 9 shown in FIG. 7 are generated.

  As shown in FIG. 8, a graphic having no rectangular shape is extracted from the generated cutout graphic 8 and rectangular graphic 9. In FIG. 8, a cutout graphic 8 having no rectangular shape is extracted.

  The external shape of the notch figure 8 shown in FIG. 8 is extracted, and the rectangular figure 21 which makes the edge | side of the outer periphery of the notch figure 8 one side is produced | generated (refer FIG. 9).

  8 is compared with the outer shape of the rectangular figure 21 in FIG. 9 to extract each end 22 of the notch 3 (see FIG. 10).

  As shown in FIG. 11, the X end side 23 extending in the Y direction (vertical direction in FIG. 11) is further extracted.

  As shown in FIG. 12, a rectangular figure 24 is generated which has the X end side 23 as one side and extends in the Y direction and has the Y side longer than the above-described Δx1 as the other side.

  A rectangular figure 25 shown in FIG. 13 is generated by logically subtracting the rectangular figure 24 shown in FIG. 12 from the cutout figure 8 shown in FIG.

  A graphic having no rectangular shape is extracted from the cut graphic 8 having the cutout 3 and the rectangular graphic 9 shown in FIG. In FIG. 14, the rectangular figure 9 is left by logically subtracting the notch figure 8 shown in FIG. 8 from the notch figure 8 having the notch 3 and the rectangular figure 9 shown in FIG.

  By performing a logical addition of the rectangular figure 25 in FIG. 13 and the rectangular figure 9 in FIG. 14, via arrangement areas 26 and 27 shown in FIG. 15 are generated.

  As shown in FIG. 16, via cells are generated so that the maximum number of vias 28 are arranged in the via arrangement regions 26 and 27 based on the via arrangement rule according to the DRC rule.

FIG. 17 shows a metal wiring pattern 1 of the first metal wiring layer, a dummy pattern 5 of the second metal wiring layer, and a via 28 that electrically connects the metal wiring pattern 1 and the dummy pattern 5 in the stacking direction. A positional relationship in the stacking direction is schematically shown.
For example, when the current flows from the right side to the left side in FIG. 17, the current flows through the metal wiring pattern 1 of the first metal wiring layer and also flows through the via 28 to the dummy pattern 5 of the second metal wiring layer. Since the cross-sectional area of the metal wiring pattern through which a current flows substantially becomes the same as that of the state in which the current increases, the metal wiring pattern resistance can be reduced.

  By the above-described procedure, in particular, in a method for designing a dummy pattern having a cutout shape at a corner, it is possible to suppress a malfunction due to a parasitic resistance of a metal wiring pattern of a semiconductor integrated circuit device while suppressing an increase in chip area. It becomes possible.

  In addition, in the second metal wiring layer described above, in addition to the dummy pattern 5 in which the corner has a cutout shape, when the dummy pattern in which the corner does not have a cutout shape is arranged, the corner is cut out. The process of FIGS. 8-15 can be abbreviate | omitted about the dummy pattern which does not have a notch shape.

  Further, according to the above-described procedure, an optimal via arrangement region is generated and arranged according to the shape of the dummy pattern, particularly the notch shape of the dummy pattern, and the via arrangement according to the DRC rule is arranged in this via arrangement region. Since the via placement is performed based on the rule, the occurrence of a DRC error can be prevented.

  Further, according to the above-described procedure, when there are a plurality of via arrangement regions having the same size and the same shape, one generated via cell can be used in common, so that the number of via layout data can be reduced.

<Second Embodiment>
A second embodiment of the dummy pattern designing method according to the present invention will be described with reference to FIGS.
In order to make the explanation easy to understand, the same reference numerals are given to the same components as those in the first embodiment.

First, “first metal wiring layer data” of a first metal wiring layer composed of a plurality of metal wiring patterns is created.
The “first metal wiring layer data” includes, for example, data of the metal wiring pattern 1 shown in FIG.

  Next, “second metal wiring layer data” of the second metal wiring layer positioned in the stacking direction with respect to the first metal wiring layer is created.

In general, CAD (Computer Aided Design) that performs automatic wiring processing is often ruled so that wiring is performed only in a predetermined direction in a predetermined metal wiring layer. This wiring method is a method for efficiently wiring while suppressing the occurrence of a wiring short-circuit between metal wiring layers between layers. For example, the first metal wiring layer is wired only in the X direction, the second metal wiring layer is wired only in the Y direction, and the metal wiring pattern of the first metal wiring layer and the metal wiring pattern of the second metal wiring layer are In many cases, there is a dead space having no metal wiring pattern other than the three-dimensionally intersecting part or the part where the via is overlapped.
In this dead space, a dummy pattern is generally generated uniformly by CAD processing for the purpose of reducing variation in the density of the metal wiring pattern.

  In the second embodiment, when the region corresponding to the metal wiring pattern 1 in the second metal wiring layer is a dead space without the metal wiring pattern, the dummy pattern is not generated uniformly as in the prior art. Instead, a dummy pattern is generated based on the shape of the metal wiring pattern 1.

However, in actuality, due to the influence of the shape and arrangement of other metal wiring patterns, it may not be possible to generate a dummy pattern generation pattern that is the same shape as the metal wiring pattern 1. For example, FIG. As shown, a dummy pattern generating pattern 2 having a notch 3 at a corner is generated.
However, since the conventional via arrangement rule according to the DRC rule cannot cope with the dummy pattern generating pattern 2 having the notch 3 at the corner, a DRC error may occur.

  Therefore, a dummy pattern design method in the second embodiment will be described below.

As shown in FIG. 20, the dummy pattern generation pattern 2 in the second metal wiring layer is reduced by Δx1 (for example, 4.01 μm) in the X direction (left and right direction in FIG. 3).
As a result of the reduction, a figure whose width in the X direction is smaller than “2 × Δx1” (for example, 8.00 μm) disappears.
For example, the dummy pattern generation pattern 2 in FIG. 19 becomes a reduced figure 4 in FIG. 20 by reduction in the X direction.

As shown in FIG. 21, the reduced graphic 4 is similarly enlarged by Δx1 in the X direction (left and right direction in FIG. 21).
By the enlargement in the X direction, the reduced figure 4 in FIG. 20 becomes the enlarged figure 5 in FIG.
This enlarged figure 5 becomes a dummy pattern 5 corresponding to the metal wiring pattern 1 of the first metal wiring layer in the second metal wiring layer.

In general, in the via placement rule according to the DRC rule, the number of via rows and the number of columns are determined so that the maximum number of vias can be placed in a rectangular area. Therefore, the via arrangement area is required to be rectangular in principle.
Therefore, a method of generating a via cell that connects the metal wiring pattern 1 of the first metal wiring layer and the dummy pattern 5 of the second metal wiring layer in the stacking direction will be described below as a second embodiment.

  The external shape of the dummy pattern 5 shown in FIG. 21 is extracted, and a rectangular figure 6 having one side of the outer periphery of the dummy pattern 5 is generated (see FIG. 22).

  As shown in FIG. 23, the rectangular figure 6 is similarly reduced by Δx1 in the X direction (left and right direction in FIG. 23) to obtain a reduced figure 7.

  A logical pattern of the reduced graphic 7 shown in FIG. 23 is logically subtracted from the dummy pattern (enlarged graphic) 5 shown in FIG. 21 to generate a cutout graphic 8 and a rectangular graphic 9 shown in FIG.

  As shown in FIG. 25, a graphic having no rectangular shape is extracted from the generated cutout graphic 8 and rectangular graphic 9. In FIG. 25, a notched figure 8 having no rectangular shape is extracted.

  A rectangular figure 10 shown in FIG. 26 is generated by logically subtracting the notch figure 8 shown in FIG. 25 from the dummy pattern (enlarged figure) 5 shown in FIG.

  The rectangular figure 10 shown in FIG. 26 is similarly reduced by Δx1 in the X direction (left and right direction in FIG. 26) to obtain a reduced figure 11 shown in FIG.

  By logically subtracting the reduced graphic 11 shown in FIG. 27 from the rectangular graphic 10 shown in FIG. 26, via placement areas 12 and 13 shown in FIG. 28 are generated.

  As shown in FIG. 29, via cells are generated so that the maximum number of vias 14 are arranged in the via arrangement regions 12 and 13 based on the via arrangement rule in accordance with the DRC rule.

FIG. 30 shows a metal wiring pattern 1 of the first metal wiring layer, a dummy pattern 5 of the second metal wiring layer, and a via 14 that electrically connects the metal wiring pattern 1 and the dummy pattern 5 in the stacking direction. A positional relationship in the stacking direction is schematically shown.
For example, when the current flows from the right side to the left side in FIG. 30, the current flows through the metal wiring pattern 1 of the first metal wiring layer and also flows through the via 14 to the dummy pattern 5 of the second metal wiring layer. Since the cross-sectional area of the metal wiring pattern through which a current flows substantially becomes the same as that of the state in which the current increases, the metal wiring pattern resistance can be reduced.

  In addition, in the second metal wiring layer described above, in addition to the dummy pattern 5 in which the corner has a cutout shape, when the dummy pattern in which the corner does not have a cutout shape is arranged, the corner is cut out. The process of FIGS. 25-28 can be abbreviate | omitted about the dummy pattern which does not have a notch shape.

  By the above-described procedure, in particular, in a method for designing a dummy pattern having a cutout shape at a corner, it is possible to suppress a malfunction due to a parasitic resistance of a metal wiring pattern of a semiconductor integrated circuit device while suppressing an increase in chip area. It becomes possible.

  Further, according to the above-described procedure, an optimal via arrangement region is generated and arranged according to the shape of the dummy pattern, particularly the notch shape of the dummy pattern, and the via arrangement according to the DRC rule is arranged in this via arrangement region. Since the via placement is performed based on the rule, the occurrence of a DRC error can be prevented.

  Further, according to the above-described procedure, when there are a plurality of via arrangement regions having the same size and the same shape, one generated via cell can be used in common, so that the number of via layout data can be reduced.

  The embodiment of the present invention is not limited to the configuration and procedure described above, and it goes without saying that modifications may be made without departing from the scope of the present invention.

  In the first and second embodiments described above, the method of designing the dummy pattern extending in the X direction (each horizontal direction in FIGS. 1 to 30) has been described. The same process can be performed on the dummy pattern extending in the (direction) by changing the X direction to the Y direction.

  In the first and second embodiments described above, an example in which a dummy pattern is designed for a metal wiring pattern having a relatively small wiring width has been described. However, a relatively wide wiring width or a solid pattern is used. The present invention can also be applied when generating a dummy pattern for a power supply wiring or a GND wiring.

  In the first and second embodiments described above, the metal wiring layer has been described. However, the present invention is not limited to this. For example, the polysilicon wiring layers or the polysilicon wiring layer and the metal wiring layer are contact-connected. It can also be applied to the case (corresponding to via connection).

DESCRIPTION OF SYMBOLS 1 Metal wiring pattern 2 Dummy pattern generation pattern 3 Notch 4, 7, 11 Reduced figure 5 Dummy pattern (enlarged figure)
6, 9, 10, 21, 24, 25 Rectangular figure 8 Notched figure 12, 13, 26, 27 Via placement area 14, 28 Via 22 Each edge 23 X edge

Claims (1)

A dummy for generating a dummy pattern connected to the wiring pattern through a via on a second wiring layer arranged in the stacking direction of the first wiring layer having a wiring pattern including a pattern extending in one direction In the pattern design method,
A dummy pattern generating pattern generating step for generating a dummy pattern generating pattern having a notch at a corner in a region corresponding to the wiring pattern;
A first reduced graphic generation step of generating a first reduced graphic by reducing the dummy pattern generation pattern by a predetermined value in each of the one direction and the direction opposite to the one direction;
A dummy pattern generation step of generating a dummy pattern by expanding the first reduced figure by the predetermined value in the one direction and the opposite direction;
A first rectangular figure generating step for extracting a first outer shape of the dummy pattern and generating a first rectangular figure having an outer peripheral side of the dummy pattern as one side;
A second reduced graphic generation step of generating a second reduced graphic by reducing the first rectangular graphic by the predetermined value in the one direction and the reverse direction, respectively.
A notch figure and a rectangular figure generation step for logically subtracting the second reduced figure from the dummy pattern to generate a notch figure having a notch at a corner and a second rectangular figure, respectively,
A notch figure extraction step for extracting the notch figure having no rectangular shape from the notch figure and the second rectangular figure;
A third rectangular figure generation step of extracting a contour of the cutout figure and generating a third rectangular figure having an outer peripheral side of the cutout figure as one side;
A first notch edge extraction step for comparing each of the notched figure and the third rectangular figure to extract each edge of the notch;
A second notch edge extraction step of further extracting a side extending in a direction orthogonal to the one direction among the ends;
A fourth rectangular figure that generates a fourth rectangular figure that has a side extending in a direction orthogonal to the one direction as one side and a side longer than the predetermined value extending in the one direction as the other side. Generation step;
A fifth rectangular figure generation step of logically subtracting the fourth rectangular figure from the cutout figure to generate a fifth rectangular figure;
A notch graphic deletion step of deleting the notch graphic not having a rectangular shape among the notch graphic and the second rectangular graphic generated in the notch graphic and rectangular graphic generation step;
The second rectangular figure left in the cutout graphic deletion step and the fifth rectangular figure generated in the fifth rectangular figure generation step are logically added to be arranged apart from each other. A via placement region generating step for generating one via placement region and a second via placement region;
A via cell generating step for generating a via cell in which the via is arranged in the first via arrangement region and a via cell in which the via is arranged in the second via arrangement region;
A method for designing a dummy pattern, comprising: