JP2012146845A - Design method of dummy pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design method of a dummy pattern capable of suppressing operation failure which is caused by a parasitic resistance of a metal wiring pattern PT of a semiconductor integrated circuit device, while suppressing increase in chip area.SOLUTION: There are generated data in which a via PT is arranged in matrix, a first wiring layer data containing a first wiring PT, a second wiring data layer containing a second wiring PT having a region that overlaps with the first wiring PT, data which is over-sized by a first value with respect to the second wiring PT, graphic data in which an overlapping region with the oversize PT is erased from the first wiring PT, data in which a graphic is under-sized by a second value and the graphic that is the second value or less is erased, first dummy PT data in which the undersize PT is over-sized by the second value to restore original size, data in which a via PT in the region corresponding to the first dummy PT is extracted from a plurality of vias PT, second wiring layer data in which the second wiring PT is synthesized with the first dummy PT, and second dummy PT data for filling a gap of the second wiring layer.

Description

  The present invention relates to a method for designing a dummy pattern in a semiconductor integrated circuit device having a multilayer wiring structure.

A semiconductor integrated circuit device usually has a multilayer wiring structure in which a plurality of metal wiring layers and a plurality of insulating layers are alternately stacked.
In a semiconductor integrated circuit device having such a multilayer wiring structure, a region in which a plurality of metal wiring layers are stacked and a region in which a plurality of metal wiring layers are not stacked are mixed depending on the difference in area and arrangement density of the metal wiring pattern. Variation in thickness occurs in the part.
When the variation in thickness is large, the thickness of the insulating layer and the metal wiring layer at the stepped portion is reduced. Since the insulation is deteriorated in the portion where the thickness of the insulating layer is thin, a short circuit failure may occur between the metal wiring layers in the stacking direction. In the portion where the thickness of the metal wiring layer is thin, the metal wiring pattern of the portion may be disconnected.
Therefore, the surface of the insulating layer formed on the metal wiring layer is planarized by using, for example, a CMP (Chemical Mechanical Polishing) method.

  However, if the level difference on the surface of the insulating layer formed on the metal wiring layer is large, the polishing time until flattening becomes longer, which may cause the productivity to deteriorate or expose the lower metal wiring layer. May end up. When the upper metal wiring layer is formed on the planarized insulating film with the lower metal wiring layer exposed, a short circuit failure occurs at the portion where the upper metal wiring layer and the lower metal wiring layer are exposed. There is.

  Therefore, by providing a dummy pattern unrelated to the circuit configuration in the metal wiring layer, variation in the arrangement density of the metal wiring pattern in the metal wiring layer is reduced by the dummy pattern (for example, Patent Document 1). .

JP 9-115905 A

For example, as shown in FIG. 19, the dummy pattern 65 as disclosed in Patent Document 1 is generally an area where the metal wiring pattern 64 is not formed by CAD processing using DRC (design rule check). In addition, data is uniformly generated for the purpose of reducing variations in the density of the metal wiring pattern 64.
In FIG. 19, in order to facilitate comparison with FIGS. 8 and 18 described later, the metal wiring pattern 64 and dummy pattern of the second wiring layer 63 are formed on the metal wiring pattern 62 of the first wiring layer 61. 65 is shown as an arranged state. FIG. 19B is a schematic cross-sectional view corresponding to the cross-sectional view taken along the line CC in FIG.

By the way, with the development of semiconductor process miniaturization technology, the density and scale of semiconductor integrated circuits are increasing. As a result, the metal wiring pattern tends to have a narrow line width and a long wiring length, and the parasitic resistance of the metal wiring pattern has a great influence on the delay of the circuit, which is one of the factors that cause the circuit to malfunction. It has become.
In addition, the effect of the parasitic resistance of the metal wiring pattern for the power supply wiring, combined with the current flowing through the power supply wiring, causes a drop in the voltage supplied to each circuit. This drop in voltage is referred to as an IR drop, and this IR drop may cause a timing delay, causing the semiconductor integrated circuit device to malfunction. In order to operate the circuit stably, it is desirable to reduce the parasitic resistance by increasing the line widths of the power supply wiring and the GND wiring as much as possible. However, if the line widths of the power supply wiring and the GND wiring are increased, the chip area increases, and the chip cost increases according to the chip area.

  Therefore, an object of the present invention is to provide a dummy pattern design method capable of suppressing malfunction caused by parasitic resistance of a metal wiring pattern of a semiconductor integrated circuit device while suppressing an increase in chip area. .

In order to solve the above problems, the present invention provides the following dummy pattern design method.
1) creating pattern data in which a plurality of via patterns are arranged in a matrix; creating pattern data of a first wiring layer including a first wiring pattern; and laminating relation to the first wiring layer A step of creating pattern data of a second wiring layer including a second wiring pattern having an overlapping region in a stacking direction with respect to the first wiring pattern; and a first value over the second wiring pattern. Creating pattern data of the sized oversize pattern, creating pattern data of one or more figures from which the overlapping area with respect to the stacking direction with the oversize pattern is erased from the first wiring pattern; The one or more figures are undersized by a second value, and figures below the second value are erased. Creating pattern data of an undersize pattern, creating pattern data of a first dummy pattern in which the undersize pattern is oversized by the second value and returned to the original size, and A first via pattern extraction step of creating pattern data of an extracted via pattern obtained by extracting a via pattern in a region corresponding to the first dummy pattern from a via pattern; and the second wiring pattern and the first dummy pattern. Creating a synthesized pattern data of the synthesized second wiring layer; and creating pattern data of a second dummy pattern that fills a gap between the second wiring layer in which the second wiring pattern and the first dummy pattern are synthesized. A step, wherein the extracted via pattern and the first wiring pattern A method of designing a dummy pattern which is a pattern for connecting the first dummy patterns in the stacking direction.
2) After the first via pattern extracting step, creating pattern data of an undersized figure in which the first dummy pattern is undersized by a third value in the direction of the current flowing through the first wiring pattern; 1. The method for designing a dummy pattern according to 1), further comprising the step of: extracting a via pattern in an area corresponding to the undersized figure from the extracted via pattern and creating erased pattern data.

  According to the present invention, it is possible to suppress malfunction caused by parasitic resistance of a metal wiring pattern of a semiconductor integrated circuit device while suppressing an increase in chip area.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view for explaining Example 1 of a dummy pattern design method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view for explaining Example 1 of a dummy pattern design method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view for explaining Example 1 of a dummy pattern design method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view for explaining Example 1 of a dummy pattern design method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view for explaining Example 1 of a dummy pattern design method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view for explaining Example 1 of a dummy pattern design method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view for explaining Example 1 of a dummy pattern design method of the present invention. It is the typical top view and typical sectional view for explaining Example 1 of the design method of the dummy pattern of the present invention. It is a typical top view for demonstrating Example 2 of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating Example 2 of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating Example 2 of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating Example 2 of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating Example 2 of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating Example 2 of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating Example 2 of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating Example 2 of the design method of the dummy pattern of this invention. It is a typical top view for demonstrating Example 2 of the design method of the dummy pattern of this invention. It is the typical top view and typical sectional view for explaining Example 2 of the design method of the dummy pattern of the present invention. It is the typical top view and typical sectional view for explaining the conventional example of the design method of a dummy pattern.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS. 1 to 18 according to preferred embodiments 1 and 2. FIG.

[Example 1]
A first embodiment of the dummy pattern designing method of the present invention will be described with reference to FIGS.

As shown in FIG. 1, “dummy via pattern basic data” in which a plurality of dummy via patterns 1 having a predetermined shape are arranged in a matrix at equal intervals at a predetermined pitch is created.
In Example 1, the shape of the dummy via pattern 1 was a square having a side of 0.2 μm, and the pitch of the dummy via pattern 1 was 0.4 μm.

  As shown in FIG. 2, “first wiring layer data” of the first wiring layer 2 is created.

Similarly, as shown in FIG. 2, an oversized wiring in which the wiring pattern 5 of the second wiring layer 4 overlapping the wiring pattern 3 of the first wiring layer 2 in the stacking direction is oversized by a predetermined value. “Second wiring layer oversize data” of pattern 6 is created.
For example, when the minimum wiring pattern interval on the design rule is 0.2 μm, the wiring pattern 5 is oversized by 0.2 μm on one side so as to satisfy the design rule.
Note that the wiring pattern of the second wiring layer 4 that does not overlap with the wiring pattern 3 of the first wiring layer 2 is not oversized and remains in a predetermined size.

  In FIG. 2, in order to facilitate understanding of the positional relationship between the wiring pattern 3 of the first wiring layer 2, the wiring pattern 5 of the second wiring layer 4, and the oversized wiring pattern 6, The wiring layer 2 and the second wiring layer 4 are shown as being overlapped in the stacking direction.

  In FIG. 2, one wiring pattern 3 of the plurality of wiring patterns of the first wiring layer 2 and two wiring patterns 5 of the plurality of wiring patterns of the second wiring layer 4 are Although shown as an overlapped state, when a plurality of wiring patterns overlap each other in a plurality of locations in the first wiring layer 2 and the second wiring layer 4, a plurality of wirings overlapping each wiring pattern 3 Each pattern 5 is oversized by a predetermined value.

  As shown in FIG. 3, an area in which the overlapping area with the oversized wiring pattern 6 in the second wiring layer 4 is erased from the wiring pattern 3 in the first wiring layer 2 as a graphic 7.

As shown in FIG. 4, “dummy pattern undersize data” of the undersize dummy pattern 8 in which the figure 7 is undersized by a predetermined value is created.
For example, when the minimum wiring pattern width on the design rule is 0.2 μm, if the width of the wiring pattern 5 is undersized by 0.1 μm on one side, an area having a pattern width of 0.2 μm or less is erased from the figure 7.

As shown in FIG. 5, the undersize dummy pattern 8 is returned to the original size (the size before the undersize) to form a new dummy pattern 9.
Next, as shown in FIG. 5, the AND of the new dummy pattern 9 and the plurality of dummy via patterns 1 described above is taken, and as shown in FIG. 6, in the region corresponding to the new dummy pattern 9. “Dummy via pattern extraction data” of the extracted dummy via pattern 10 obtained by extracting the dummy via pattern 1 is created.

  As shown in FIG. 7, “first second wiring layer dummy pattern synthesis data” is created by synthesizing a new dummy pattern 9 with the wiring pattern 5 of the second wiring layer 4.

  In FIG. 7, in order to make the positional relationship between the wiring pattern 3 of the first wiring layer 2, the wiring pattern 5 of the second wiring layer 4, the dummy pattern 9, and the extracted dummy via pattern 10 easy to understand, The first wiring layer 2 and the second wiring layer 4 are shown as being connected by an extraction dummy via pattern 10.

As shown in FIG. 8, “second second wiring layer dummy pattern synthesis data” is created in which dummy patterns 12 that fill the gaps in the second wiring layer 4 are arranged in the same manner as the conventional method.
The above-described processing can be automatically processed by CAD using a DRC (design rule check) tool and a rule file.

  8A shows the positional relationship between the wiring pattern 3 of the first wiring layer 2, the wiring pattern 5 of the second wiring layer 4, the dummy patterns 9 and 12, and the extracted dummy via pattern 10. FIG. For ease of illustration, the first wiring layer 2 and the second wiring layer 4 are shown as being connected by the extraction dummy via pattern 10.

FIG. 8B shows a semiconductor having a multilayer wiring structure manufactured using the above-mentioned “first wiring layer data”, “dummy via pattern extraction data”, and “second second wiring layer dummy pattern synthesis data”. It is sectional drawing of an integrated circuit device, and respond | corresponds to sectional drawing in the AA line of Fig.8 (a).
That is, the metal wiring patterns 23 and 21 shown in FIG. 8B correspond to the wiring patterns 3 and 5 shown in FIG. 8A, respectively, and the metal dummy patterns 22 and 24 are the dummy patterns shown in FIG. 8A. The vias 13 corresponding to 12 and 9 and connecting the metal dummy pattern 24 and the metal wiring pattern 23 correspond to the extracted dummy via pattern 10 shown in FIG.

  According to the dummy pattern design method described above, the metal dummy pattern 24 is connected to the metal wiring pattern 23 through the via 13 as shown in FIG. When the current Ia flows, the current Ia flows through the metal wiring pattern 23 and also through the via 13 to the metal dummy pattern 24. Therefore, the parasitic resistance of the metal wiring pattern is reduced as compared with the case of the metal wiring pattern 23 alone. be able to.

  Further, according to the above-described dummy pattern design method, the dummy via pattern is extracted from the “dummy via pattern basic data” according to the position and shape of the dummy pattern. There is no need to design according to the type of integrated circuit device, and it can be made common.

[Example 2]
A second embodiment of the dummy pattern designing method of the present invention will be described with reference to FIGS.

As shown in FIG. 9, “dummy via pattern basic data” is created in which dummy via patterns 31 having a predetermined shape are arranged in a matrix at equal intervals at a predetermined pitch.
In Example 2, the shape of the dummy via pattern 31 was a square having a side of 0.2 μm, and the pitch of the dummy via pattern 31 was 0.4 μm.

  As shown in FIG. 10, “first wiring layer data” of the first wiring layer 32 is created.

Similarly, as shown in FIG. 10, an oversized wiring pattern 36 is obtained by oversizing the wiring pattern 35 of the second wiring layer 34 that overlaps the wiring pattern 33 of the first wiring layer 32 in the stacking direction by a predetermined value. The “second wiring layer oversize data” is created.
For example, when the minimum wiring pattern interval on the design rule is 0.2 μm, the wiring pattern 35 is oversized by 0.2 μm on one side so as to satisfy the design rule.
Note that the wiring pattern of the second wiring layer 34 that does not overlap with the wiring pattern 33 of the first wiring layer 32 is not oversized and is kept at a predetermined size.

  In FIG. 10, in order to facilitate understanding of the positional relationship between the wiring pattern 33 of the first wiring layer 32, the wiring pattern 35 of the second wiring layer 34, and the oversized wiring pattern 36, The wiring layer 32 and the second wiring layer 34 are shown as being overlapped in the stacking direction.

  In FIG. 10, one wiring pattern 33 of the plurality of wiring patterns of the first wiring layer 32 and two wiring patterns 35 of the plurality of wiring patterns of the second wiring layer 34 are formed. Although shown as an overlapped state, when a plurality of wiring patterns overlap each other in the first wiring layer 32 and the second wiring layer 34, the plurality of wiring patterns 35 overlapping each wiring pattern 33 are Each oversize by a predetermined value.

  As shown in FIG. 11, an area in which an overlapping area with the oversized wiring pattern 36 in the second wiring layer 34 is deleted from the wiring pattern 33 of the first wiring layer 32 as a graphic 37.

As shown in FIG. 12, “first dummy pattern undersize data” of the undersize dummy pattern 38 in which the figure 37 is undersized by a predetermined value is created.
For example, when the minimum wiring pattern width according to the design rule is 0.2 μm, if the width of the wiring pattern 35 is undersized by 0.1 μm on one side, an area having a pattern width of 0.2 μm or less is erased from the figure 37.

As shown in FIG. 13, the undersize dummy pattern 38 is returned to the original size (the size before the undersize) to form a new dummy pattern 39.
Next, as shown in FIG. 13, the AND of the new dummy pattern 39 and the plurality of dummy via patterns 31 is taken, and the dummy in the region corresponding to the new dummy pattern 39 is shown in FIG. “First dummy via pattern extraction data” of the extracted dummy via pattern 40 from which the via pattern 31 has been extracted is created.

As shown in FIG. 15, the “second dummy pattern” of the undersize dummy pattern 41 in which the dummy pattern 39 is undersized by a predetermined value with respect to the direction of the current flowing in the wiring pattern 33 that is laminated with the dummy pattern 39. Create undersize data.
In Example 2, the dummy pattern 39 was undersized by 0.6 μm on one side with respect to the direction of the current flowing in the wiring pattern 33.

  As shown in FIG. 16, the extracted dummy via pattern 40 in the region corresponding to the undersize dummy pattern 41 is further extracted from the “first dummy via pattern extraction data” and logically subtracted (erased) “second”. Dummy via pattern extraction data "is created.

  As shown in FIG. 17, “first second wiring layer dummy pattern synthesis data” is created by synthesizing the dummy pattern 39 with the wiring pattern 35 of the second wiring layer 34.

  In FIG. 17, the positional relationship between the wiring pattern 33 of the first wiring layer 32, the wiring pattern 35 and dummy pattern 39 of the second wiring layer 34, and the extracted dummy via pattern 43 remaining after the above logical subtraction. In order to facilitate understanding, the first wiring layer 32 and the second wiring layer 34 are shown as being connected by the extraction dummy via pattern 43.

As shown in FIG. 18, “second second wiring layer dummy pattern synthesis data” is created in which dummy patterns 44 that fill the gaps in the second wiring layer 34 are arranged in the same manner as the conventional method.
The above-described processing can be automatically processed by CAD using a DRC (design rule check) tool and a rule file.

  18A shows the positional relationship between the wiring pattern 33 of the first wiring layer 32, the wiring pattern 35 of the second wiring layer 34, the dummy patterns 39 and 44, and the extracted dummy via pattern 43. FIG. For simplicity, the first wiring layer 32 and the second wiring layer 34 are shown as being connected by the extraction dummy via pattern 43.

FIG. 18B shows a multilayer wiring structure produced using the above-described “first wiring layer data”, “second dummy via pattern extraction data”, and “second second wiring layer dummy pattern composite data”. FIG. 19 is a cross-sectional view of a semiconductor integrated circuit device having a cross-sectional view taken along line BB in FIG.
That is, the metal wiring patterns 53 and 52 shown in FIG. 18B correspond to the wiring patterns 33 and 35 shown in FIG. 18A, respectively, and the metal dummy patterns 54 and 56 are the dummy patterns shown in FIG. Corresponding to 44 and 39, the via 55 connecting the metal dummy pattern 56 and the metal wiring pattern 53 corresponds to the extracted dummy via pattern 43 shown in FIG.

  According to the dummy pattern design method described above, the metal dummy pattern 56 is connected to the metal wiring pattern 53 via the via 55 as shown in FIG. When the current Ib flows, the current Ib flows through the metal wiring pattern 53 and also through the via 55 to the metal dummy pattern 56, so that the parasitic resistance of the metal wiring pattern is reduced as compared with the case of the metal wiring pattern 53 alone. be able to.

  Further, according to the above-described dummy pattern design method, the dummy via pattern is extracted from the “dummy via pattern basic data” according to the position and shape of the dummy pattern. There is no need to design according to the type of integrated circuit device, and it can be made common.

  Further, according to the dummy pattern design method described above, the number of extracted dummy via patterns (see FIG. 18) can be made smaller than that in the first embodiment (see FIG. 8). Can be reduced.

  The embodiment of the present invention is not limited to the configuration and procedure described above, and it goes without saying that modifications may be made without departing from the scope of the present invention.

  For example, in the first and second embodiments, the case where the dummy pattern is designed in the second wiring layer has been described as an example, but the dummy pattern designing method according to the present invention is also applied to the first wiring layer. In addition, when there are three or more wiring layers, the dummy pattern design method according to the present invention can be applied to the third or more wiring layers.

1, 31_ dummy via pattern, 2, 32_1 first wiring layer, 3, 5, 33, 35_ wiring pattern, 4, 34_2 second wiring layer, 6, 36_ oversized wiring pattern, 7, 37_ figure, 38,41_undersize dummy pattern, 9,12,39,44_dummy pattern, 10,40,43_extraction dummy via pattern, 13_via, 21,23_metal wiring pattern, 22,24_metal dummy pattern

Claims (2)

Creating pattern data in which a plurality of via patterns are arranged in a matrix; and
Creating pattern data of a first wiring layer including a first wiring pattern;
Creating pattern data of a second wiring layer including a second wiring pattern that is in a stacking relationship with the first wiring layer and has an overlapping region in the stacking direction with respect to the first wiring pattern;
Creating pattern data of an oversized pattern that is oversized by a first value with respect to the second wiring pattern;
Creating pattern data of one or a plurality of figures from which the overlap region in the stacking direction with the oversize pattern is erased from the first wiring pattern;
Undersize the one or more figures by a second value and creating pattern data of an undersize pattern in which figures below the second value are erased;
Creating pattern data of a first dummy pattern in which the undersize pattern is oversized by the second value and returned to the original size;
A first via pattern extraction step of creating pattern data of an extracted via pattern obtained by extracting a via pattern in a region corresponding to the first dummy pattern from the plurality of via patterns;
Creating combined pattern data of a second wiring layer by combining the second wiring pattern and the first dummy pattern;
Creating pattern data of a second dummy pattern that fills a gap in a second wiring layer in which the second wiring pattern and the first dummy pattern are combined;
Have
The method for designing a dummy pattern, wherein the extracted via pattern is a pattern for connecting the first wiring pattern and the first dummy pattern in the stacking direction. After the first via pattern extraction step,
Creating pattern data of an undersized figure in which the first dummy pattern is undersized by a third value in the direction of the current flowing through the first wiring pattern;
From the extracted via pattern, creating a pattern data in which the via pattern in the region corresponding to the undersize figure is extracted and erased; and
The dummy pattern design method according to claim 1, further comprising: