JP2013106134A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce useless charge/discharge at recovery of power supply to circuit blocks of a semiconductor device.SOLUTION: A semiconductor device comprises: a first power source line supplying a first power source voltage; a second power source line supplying a second power source voltage higher than the first power source voltage; an upstream circuit block; a downstream circuit block operating based on an output signal from the upstream circuit block; and a power supply control circuit controlling supply of the first power source voltage and the second power source voltage to the upstream circuit block and the downstream circuit block. The power supply control circuit delays a supply start time of the first power source voltage to the downstream circuit block behind a supply start time of the first power source voltage to the upstream circuit block. Further, the power supply control circuit supplies the second power source voltage to both of the upstream circuit block and the downstream circuit block after the first power source voltage is supplied to the upstream circuit block and the downstream circuit block.

Description

  The present invention relates to a technique for controlling power supply to a circuit block in a semiconductor device.

  In the field of semiconductor devices, reduction of power consumption is an important issue. The power consumption is divided into power consumption in the active mode and power consumption in the standby mode. Among these, the power consumption in the standby mode mainly depends on the leakage current of the transistor.

  As a technique for reducing power consumption in the standby mode, “power gating” is known. Power gating is a technique for cutting off power supply to functional blocks that do not operate in the standby mode. For this purpose, a power switch is provided between the power gating target functional block and the power source. In the standby mode, the power switch is turned OFF, thereby cutting off the power supply to the functional block that is the target for power gating. As a result, the leakage current in the functional block is greatly reduced, and the power consumption in the standby mode is reduced.

  On the other hand, when the power supply to the functional block is resumed, the power switch is turned on. At this time, an in-rush current flows through the power gating circuit. Inrush current is undesirable because it causes power supply noise.

  Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2007-267162) discloses a technique for reducing inrush current. The semiconductor device described in Patent Document 1 includes a power supply control unit that controls connection between a circuit block group and a power supply line. The circuit block group includes a first circuit block and a second circuit block. The power supply control unit includes a first switch that controls connection between the first circuit block and the power supply line, a second switch that controls connection between the second circuit block and the power supply line, and a switch control circuit that controls these switches. Prepare. The switch control circuit controls the operation of the second switch based on an operation control signal instructing the operation start of the circuit block group and an output potential output via the first switch.

  According to the technique described in Patent Document 2 (Japanese Patent Laid-Open No. 8-227580), two pairs of a power supply line and a ground line are provided. Regarding the first power supply line-ground line pair, the electrical connection with the power supply line is interrupted when the power supply is interrupted. On the other hand, regarding the second power line-ground line pair, the electrical connection with the ground line is cut off when the power is cut off.

JP 2007-267162 A JP-A-8-227580

  As described above, the power consumption in the standby mode is reduced by cutting off the power supply to the circuit block. However, when returning from the standby mode to the active mode, it is necessary to charge and discharge the capacitance in the circuit block. Therefore, if the power supply is frequently interrupted / returned, the power consumption may increase due to the charge / discharge. It is desired to suppress useless charging / discharging that occurs when returning from the standby mode to the active mode.

  In one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes: a first power supply line that supplies a first power supply voltage; a second power supply line that supplies a second power supply voltage that is higher than the first power supply voltage; a front circuit block; and an output signal from the front circuit block. And a power supply control circuit that controls the supply of the first power supply voltage and the second power supply voltage to the front-stage circuit block and the rear-stage circuit block. The power supply control circuit delays the supply start timing of the first power supply voltage to the subsequent circuit block from the supply start timing of the first power supply voltage to the previous circuit block. Further, the power supply control circuit supplies the second power supply voltage to both the front circuit block and the rear circuit block after the first power supply voltage is supplied to the front circuit block and the rear circuit block.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to suppress useless charge / discharge at the time of the electric power supply return to the circuit block of a semiconductor device.

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to the first embodiment of the present invention. FIG. 2A shows an example of the delay circuit in the embodiment of the present invention. FIG. 2B shows another example of the delay circuit in the embodiment of the present invention. FIG. 3 is a timing chart showing the operation of the semiconductor device according to the first embodiment. FIG. 4 is a timing chart showing the operation in the comparative example. FIG. 5 is a timing chart for explaining the effect of the present invention. FIG. 6 is a block diagram showing a configuration of a semiconductor device according to the second embodiment of the present invention. FIG. 7 is a timing chart showing the operation of the semiconductor device according to the second embodiment. FIG. 8 is a plan view showing an example of the layout of the semiconductor device according to the second embodiment. FIG. 9A is a block diagram illustrating an example of a configuration for generating a switch control signal according to the second embodiment. FIG. 9B is a timing chart showing the operation of the configuration shown in FIG. 9A. FIG. 10A is a block diagram illustrating another example of a configuration for generating a switch control signal according to the second embodiment. FIG. 10B is a timing chart showing the operation of the configuration shown in FIG. 10A. FIG. 11 is a block diagram showing a modification of the semiconductor device according to the second embodiment. FIG. 12 is a block diagram showing a configuration of a semiconductor device according to the third embodiment of the present invention. FIG. 13 is a block diagram showing another configuration of the semiconductor device according to the third embodiment of the present invention. FIG. 14 is a plan view showing an example of the layout of the semiconductor device according to the third embodiment. FIG. 15 is a circuit diagram showing a configuration example of the first power supply voltage generation unit in the second and third embodiments of the present invention. FIG. 16A is a circuit diagram for explaining an operation of the first power supply voltage generation unit shown in FIG. FIG. 16B is a circuit diagram for explaining the operation of the first power supply voltage generation unit shown in FIG. FIG. 17 is a graph illustrating an operation of the first power supply voltage generation unit illustrated in FIG. FIG. 18 is a circuit diagram illustrating another configuration example of the first power supply voltage generation unit.

  Embodiments of the present invention will be described with reference to the accompanying drawings.

1. 1. First embodiment 1-1. Configuration FIG. 1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. The semiconductor device includes a power supply line 1 that supplies a power supply voltage VDD, a plurality of circuit blocks 10, and a power supply control circuit 100.

  The circuit block 10 is a functional block that provides a predetermined function. Typically, the circuit block 10 is a logic circuit including one or more logic gates. In the present embodiment, a plurality of circuit blocks 10 are linked to each other through signals. That is, when the two-stage circuit block 10 is considered, the subsequent-stage circuit block 10 operates based on the output signal output from the previous-stage circuit block 10.

  For example, in FIG. 1, the circuit block 10-1 receives an input signal IN, performs a predetermined logical operation based on the input signal IN, and outputs an output signal OUT1 indicating the operation result. The circuit block 10-2 receives the output signal OUT1 output from the circuit block 10-1 as an input signal, performs a predetermined logical operation based on the input signal, and outputs an output signal OUT2 indicating the calculation result. The circuit block 10-3 receives the output signal OUT2 output from the circuit block 10-2 as an input signal, and performs a predetermined logical operation based on the input signal. Thus, there is a signal flow in the order of the circuit blocks 10-1, 10-2, and 10-3.

  The power supply control circuit 100 is provided between the power supply line 1 and the plurality of circuit blocks 10 and controls the supply of the power supply voltage VDD from the power supply line 1 to the plurality of circuit blocks 10. More specifically, the power supply control circuit 100 includes a power distribution line PL and a first switch 110.

  The power distribution line PL is a line for distributing power to the plurality of circuit blocks 10. In FIG. 1, the power input terminal of the circuit block 10-1 is connected to the node N1 on the power distribution line PL, and the power supply voltage VDD is supplied from the node N1 to the circuit block 10-1. The power supply input terminal of the circuit block 10-2 is connected to the node N2 on the power distribution line PL, and the power supply voltage VDD is supplied from the node N2 to the circuit block 10-2. The power input terminal of the circuit block 10-3 is connected to the node N3 on the power distribution line PL, and the power supply voltage VDD is supplied from the node N3 to the circuit block 10-3.

  The first switch 110 is provided between the power supply line 1 and the starting node on the power distribution line PL. The first switch 110 is turned on / off in response to the switch control signal CON. ON / OFF control of the supply of the power supply voltage VDD from the power supply line 1 to the plurality of circuit blocks 10 from the power supply line 1 by turning ON / OFF the first switch 110 is performed. Can do. In the example of FIG. 1, the starting node coincides with the node N1, but is not limited thereto, and may be another location.

  The power supply control circuit 100 according to the present embodiment further has the following functions. That is, the power supply control circuit 100 also delays the supply start timing (application start timing) of the power supply voltage VDD in the same direction as the signal flow between the plurality of circuit blocks 10. For example, in FIG. 1, there is a signal flow in the order of the circuit blocks 10-1, 10-2, and 10-3 as described above. In this case, the power supply control circuit 100 delays the supply start timing to the subsequent circuit block 10-2 from the supply start timing to the previous circuit block 10-1, and further to the subsequent circuit block 10-3. The supply start timing is further delayed.

  For this purpose, the power supply control circuit 100 according to the present embodiment includes a delay circuit 150. The delay circuit 150 gives a delay larger than the delay in the normal signal wiring. For example, the delay circuit 150 is a resistance element as shown in FIG. 2A. This resistance element is a resistor (eg, polysilicon) different from normal signal wiring (eg, Al, Cu), and the resistance value per unit length is higher than that of normal signal wiring. Alternatively, the delay circuit 150 may be a PMOS transistor whose gate voltage is fixed to the ground voltage GND as shown in FIG. 2B. By using such a delay circuit 150, the power supply control circuit 100 delays the supply start timing of the power supply voltage VDD to the plurality of circuit blocks 10.

  In the example shown in FIG. 1, a delay circuit 150 is provided on the power distribution line PL between the node N1 and the node N2. Furthermore, the distance along the power distribution line PL is longer between the starting node and the node N2 than between the starting node and the node N1. In other words, on the power distribution line PL, the above-described starting node, node N1, delay circuit 150, and node N2 are arranged in this order. Accordingly, the supply start timing of the power supply voltage VDD is delayed at the node N2 than at the node N1, that is, the latter circuit block 10-2 is later than the preceding circuit block 10-1. The direction of delay of the power supply voltage VDD coincides with the direction of signal flow from the preceding circuit block 10-1 to the succeeding circuit block 10-2.

  Similarly, a delay circuit 150 is provided on the power distribution line PL between the node N2 and the node N3. Furthermore, the distance along the power distribution line PL is longer between the starting node and the node N3 than between the starting node and the node N2. In other words, on the power distribution line PL, the above-described start node, node N2, delay circuit 150, and node N3 are arranged in this order. Therefore, the supply start timing of the power supply voltage VDD is delayed at the node N3 than at the node N2, that is, the latter circuit block 10-3 is later than the preceding circuit block 10-2. The direction of delay of the power supply voltage VDD coincides with the direction of signal flow from the preceding circuit block 10-2 to the succeeding circuit block 10-3.

  The arrangement relationship between the delay circuit 150 and the nodes N1 to N3 is not limited to that shown in FIG. When considering the signal delay amount from the starting node by the delay circuit 150, the signal delay amount to the node N1 is the first delay amount, and the signal delay amount to the node N2 is the second delay amount larger than the first delay amount. Yes, it is sufficient if the signal delay amount to the node N3 is a third delay amount that is larger than the second delay amount. As long as this condition is satisfied, the nodes N1 to N3 may be connected in parallel to the origin node.

1-2. Operation FIG. 3 is a timing chart showing the operation of the semiconductor device according to the present embodiment. Here, a case will be described in which the circuit blocks 10-1 to 10-3 are returned from the standby state (OFF state in which the supply of the power supply VDD is cut off) to the active state (ON state in which the power supply VDD is supplied).

  At time t0, the switch control signal CON changes from the low level to the high level. Thereby, the first switch 110 is turned ON, and the power supply line 1 and the power distribution line PL are electrically connected. First, the voltage of the node N1 closest to the starting node starts to rise and reaches the power supply voltage VDD at time t1.

  Since the delay circuit 150 is interposed between the node N1 and the node N2, the voltage of the node N2 starts to rise later than the start of the rise of the voltage of the node N1. Preferably, the voltage at node N2 begins to rise after time t1. Then, at time t2 after a predetermined delay time Td from time t1, the voltage at the node N2 reaches the power supply voltage VDD.

  Further, since the delay circuit 150 is interposed between the node N2 and the node N3, the voltage of the node N3 starts to rise later than the start of the rise of the voltage of the node N2. Preferably, the voltage at node N3 begins to rise after time t2. Then, at time t3 after a predetermined delay time Td from time t2, the voltage at the node N3 reaches the power supply voltage VDD.

  As described above, when returning from the standby state, the power supply voltage VDD is supplied (applied) in the order of the nodes N1, N2, and N3. That is, the power supply voltage VDD is supplied (applied) in the order of the circuit blocks 10-1, 10-2, and 10-3.

1-3. Effects In order to describe the effects of the present embodiment, first, a comparative example will be described. In the comparative example, the delay circuit 150 as in the present embodiment is not used, and the power supply voltage VDD is supplied to the plurality of circuit blocks 10 “simultaneously”.

  FIG. 4 is a timing chart showing the operation in the comparative example. At time t0, the switch control signal CON changes from the low level to the high level, and the voltages of all the nodes N1 to N3 start to rise. During the voltage rise period in which the voltage at each node rises to the power supply voltage VDD, the output signal from each circuit block 10 is in an indefinite state, and when the voltage rise period ends, the voltage of the output signal from each circuit block 10 The level is finalized.

  Here, as an example, attention is focused on the operation of the circuit block 10-2 during the voltage rise period. During the voltage increase period, the input signal to the circuit block 10-2, that is, the output signal OUT1 from the preceding circuit block 10-1 is in an indefinite state. Since the input signal OUT1 to the circuit block 10-2 is in an undefined state, the output signal OUT2 of the circuit block 10-2 is also in an undefined state. Accordingly, the case shown in FIG. 4, that is, the case where the voltage of the output signal OUT2 once rises to an intermediate level (a level between the high level and the low level) and then settles (converges) to the low level. Can do. That is, there is a possibility that the voltage level of the output signal OUT2 fluctuates wastefully. This means generation of useless charge / discharge and useless power consumption.

  In the case of a CMOS logic circuit, when the input signal is at an intermediate level, both the PMOS transistor and the NMOS transistor are turned on, and a through current flows from the power supply terminal to the ground terminal. This also leads to an increase in power consumption.

  On the other hand, FIG. 5 is a timing chart showing the operation in the present embodiment. According to the present embodiment, the application start timing of the power supply voltage VDD to the node N2 (circuit block 10-2) is later than that to the node N1 (circuit block 10-1). Preferably, the application start timing of the power supply voltage VDD to the node N2 is after the voltage of the node N1 reaches the power supply voltage VDD and the voltage level of the output signal OUT1 of the circuit block 10-1 is determined. In this case, since the power supply voltage VDD is not supplied to the subsequent circuit block 10-2 during the period in which the output signal OUT1 of the previous circuit block 10-1 is in an indefinite state (intermediate level), the subsequent circuit block 10-2 is not supplied. Does not operate, and the output signal OUT2 does not fluctuate. That is, the case as shown in FIG. 4 is prevented beforehand. Therefore, generation of useless charging / discharging and useless power consumption is prevented. Furthermore, generation of a through current in the CMOS logic circuit is also prevented.

  The supply start timing of the power supply voltage VDD to the subsequent circuit block 10-2 is preferably after the voltage level of the output signal OUT1 of the previous circuit block 10-1 is determined, but is not limited thereto. . Even if the supply start timing of the power supply voltage VDD to the subsequent circuit block 10-2 is slightly before the voltage level of the output signal OUT1 of the previous circuit block 10-1 is determined, a certain effect can be obtained. At least the supply start timing of the power supply voltage VDD to the subsequent circuit block 10-2 should be delayed from the supply start timing of the power supply voltage VDD to the previous circuit block 10-1.

2. Second Embodiment In the second embodiment of the present invention, two types of power supply voltages VDD1 and VDD2 are used. The second power supply voltage VDD2 is higher than the first power supply voltage VDD1 (VDD2> VDD1). The second power supply voltage VDD2 is a power supply voltage for normal operation. On the other hand, the first power supply voltage VDD1 is an auxiliary power supply voltage used when returning from standby. The level of the first power supply voltage VDD1 is set to such an extent that the voltage level of the output signal of each circuit block 10 is determined.

2-1. Configuration FIG. 6 is a block diagram showing a configuration of a semiconductor device according to the second embodiment. The semiconductor device includes a first power supply line 1 that supplies a first power supply voltage VDD1, a second power supply line 2 that supplies a second power supply voltage VDD2, a plurality of circuit blocks 10, and a power supply control circuit 100. The circuit block 10 is the same as that in the first embodiment.

  The power supply control circuit 100 is provided between the first power supply line 1 and the second power supply line 2 and the plurality of circuit blocks 10, and the first power supply voltage VDD1 and the second power supply voltage VDD2 for the plurality of circuit blocks 10. To control the supply. More specifically, the power supply control circuit 100 includes a power distribution line PL, a first switch 110, a second switch 120, and a delay circuit 150.

  The relationship among the first power supply line 1, the first switch 110, the first switch control signal CON1, the power distribution line PL, the nodes N1 to N3, and the delay circuit 150 is the same as that in the first embodiment. The first power supply line 1 corresponds to the power supply line 1 in the first embodiment. The first switch control signal CON1 corresponds to the switch control signal CON in the first embodiment.

  The second switch 120 is provided between the second power supply line 2 and the nodes N1 to N3, and turns on / off the supply of the second power supply voltage VDD2 from the second power supply line 2 to each of the nodes N1 to N3. Control. More specifically, the second switch 120-1 is provided between the second power supply line 2 and the node N1, and the second switch 120-2 is provided between the second power supply line 2 and the node N2. The second switch 120-3 is provided between the second power supply line 2 and the node N3. These second switches 120-1 to 120-3 are simultaneously turned ON / OFF according to the same second switch control signal CON2. By turning ON / OFF these second switches 120-1 to 120-3, the second power supply voltage VDD2 from the second power supply line 2 to the nodes N1 to N3, that is, from the second power supply line 2 to the plurality of circuit blocks 10 is obtained. Can be controlled all at once.

2-2. Operation FIG. 7 is a timing chart showing the operation of the semiconductor device according to the second embodiment.

  At time t0, the first switch control signal CON1 changes from Low level to High level. As a result, the first switch 110 is turned ON, and the first power supply line 1 and the power distribution line PL are electrically connected. First, the voltage of the node N1 closest to the starting node starts to rise, and reaches the first power supply voltage VDD1 at time t1.

  Since the delay circuit 150 is interposed between the node N1 and the node N2, the voltage of the node N2 starts to rise later than the start of the rise of the voltage of the node N1. Preferably, the voltage at node N2 begins to rise after time t1. Then, at time t2 after a predetermined delay time Td from time t1, the voltage at the node N2 reaches the first power supply voltage VDD1.

  Further, since the delay circuit 150 is interposed between the node N2 and the node N3, the voltage of the node N3 starts to rise later than the start of the rise of the voltage of the node N2. Preferably, the voltage at node N3 begins to rise after time t2. Then, at time t3 after a predetermined delay time Td from time t2, the voltage at the node N3 reaches the first power supply voltage VDD1.

  As described above, when returning from the standby state, the first power supply voltage VDD1 is supplied (applied) in the order of the nodes N1, N2, and N3. That is, the first power supply voltage VDD1 is supplied (applied) in the order of the circuit blocks 10-1, 10-2, and 10-3.

  At time t4 after time t3, the first switch control signal CON1 changes from High level to Low level. As a result, the first switch 110 is turned OFF, and the electrical connection between the first power supply line 1 and the power distribution line PL is disconnected.

  Subsequently, at time t5, the second switch control signal CON2 changes from the Low level to the High level. Accordingly, the second switches 120-1 to 120-3 are turned on all at once, and the second power supply line 2 and the nodes N1 to N3 are electrically connected. As a result, the second power supply voltage VDD2 starts to be supplied almost simultaneously to the nodes N1 to N3 (circuit blocks 10-1 to 10-3). The voltages of the nodes N1 to N3 further rise from the first power supply voltage VDD1, and reach the second power supply voltage VDD2 at time t6. Thus, according to the present embodiment, the power supply control circuit 100 supplies the second power supply voltage VDD2 to the circuit blocks 10-1 to 10-3 after supplying the first power supply voltage VDD1 with a time difference. Supply all at once.

  At time t10, the second switch control signal CON2 changes from High level to Low level. Thereby, the second switches 120-1 to 120-3 are turned OFF, and the electrical connection between the second power supply line 2 and the nodes N1 to N3 is cut. The voltages at the nodes N1 to N3 begin to decrease from the second power supply voltage VDD2.

  Subsequently, at time t11, the first switch control signal CON1 changes from the Low level to the High level. As a result, the first switch 110 is turned ON, and the first power supply line 1 and the power distribution line PL are electrically connected. The voltages of the nodes N1 to N3 are maintained at the first power supply voltage VDD1. In this way, it is possible to turn on / off only the supply of the second power supply voltage VDD2 while maintaining the level of the first power supply voltage VDD1 at a minimum. Depending on the application, charge / discharge power can be further reduced by such control.

2-3. Effect According to the second embodiment, the same effect as in the first embodiment can be obtained. That is, when returning from the standby state, generation of useless charging / discharging can be prevented by sequentially shifting the supply start timing of the first power supply voltage VDD1 to the plurality of circuit blocks 10. Furthermore, generation of a through current in the CMOS logic circuit is also prevented.

  The second power supply voltage VDD2 may be supplied to the plurality of circuit blocks 10 at the same timing. This is because the voltage level of the output signal output from each circuit block 10 is determined when the voltage supplied to each circuit block 10 rises to the first power supply voltage VDD1. Since the voltage level of the output signal is fixed, no through current flows even when the second power supply voltage VDD2 is applied simultaneously. Since it is not necessary to delay the supply timing of the second power supply voltage VDD2, the time required for returning from the standby state is shortened. Further, since the delay circuit 150 is not necessary for supply control of the second power supply voltage VDD2, an increase in area is suppressed.

  Furthermore, according to the second embodiment, compared with the first embodiment, the power consumption when returning from the standby state is reduced. In the first embodiment, the voltage supplied to the circuit block 10 rises in one stage from the ground voltage GND to the operating voltage (second power supply voltage VDD2). In this case, the power consumption P required for charging the total capacity CL included in the circuit block 10 is expressed by the following equation (1).

Formula (1): P = CL × VDD2 ²

  On the other hand, according to the second embodiment, the voltage supplied to the circuit block 10 rises in two stages. Specifically, the voltage supplied to the circuit block 10 once rises from the ground voltage GND to the first power supply voltage VDD1, and further rises from the first power supply voltage VDD1 to the second power supply voltage VDD2. In this case, the power consumption P required for charging the total capacity CL included in the circuit block 10 is expressed by the following equation (2).

Formula (2): P = CL × (VDD1 ² + VDD2 × (VDD2−VDD1))

  For example, consider a case where VDD2 = 1.0 and VDD1 = 0.5. The power consumption P is “CL” in the case of Equation (1), but is “0.75CL” in the case of Equation (2). That is, the power consumption P can be reduced by 25% by the two-stage charging.

2-4. Layout Example FIG. 8 is a plan view showing an example of the layout of the semiconductor device according to the second embodiment.

  The first power supply voltage generator 160 generates the first power supply voltage VDD1 from the second power supply voltage VDD2. A configuration example of the first power supply voltage generation unit 160 will be described in detail later. Of course, a configuration in which the first power supply voltage VDD1 is externally applied is also possible.

  The first power supply voltage generator 160 also has a function of the first switch 110, and ON / OFF control of the supply of the first power supply voltage VDD1 to the power distribution wiring 170 according to the first switch control signal CON1. To do. The power distribution wiring 170 corresponds to the power distribution line PL in FIG. The power distribution wiring 170 is formed in the wiring layer and is formed so as to pass through the vicinity of the plurality of circuit blocks 10.

  The block power supply wiring 180 is a power supply wiring for supplying a power supply voltage (VDD1, VDD2) to each circuit block 10. For example, the block power supply wiring 180-1 supplies power supply voltages (VDD1, VDD2) to the circuit block 10-1, and the block power supply wiring 180-2 supplies power supply voltages (VDD1, VDD2) to the circuit block 10-2. To do. These block power supply wirings 180-1 and 180-2 are formed so as to intersect with the power distribution wiring 170 described above. Vias connecting the two wirings are formed at the intersection of the block power supply wiring 180-1 and the power distribution wiring 170, and this intersection corresponds to the node N1 in FIG. In addition, vias connecting the two wirings are formed at the intersection of the block power supply wiring 180-2 and the power distribution wiring 170, and this intersection corresponds to the node N2 in FIG.

  A delay circuit 150 is formed between the node N1 and the node N2. A delay circuit 150 is formed between the node N2 and the node N3 (not shown). Delay circuit 150 has a structure different from that of power distribution wiring 170 and is typically formed in a wiring layer different from that of power distribution wiring 170. For example, the delay circuit 150 is a polysilicon element formed on a substrate. The delay circuit 150 and the power distribution wiring 170 formed in different layers are connected by vias.

  A second switch 120-1 is provided between the block power supply wiring 180-1 and the second power supply line 2. A second switch 120-2 is provided between the block power supply wiring 180-2 and the second power supply line 2. Each second switch 120 includes a plurality of NMOS transistors connected in parallel. Each NMOS transistor includes a gate 121, a drain 122, and a source 123. A second switch control signal CON2 is applied to the gate 121. The drain 122 is connected to the second power supply line 2. The source 123 is connected to the block power supply wiring 180.

2-5. Method for generating switch control signal <First example>
FIG. 9A is a block diagram illustrating an example of a configuration for generating switch control signals (CON1, CON2). FIG. 9B is a timing chart showing the operation of the configuration shown in FIG. 9A.

  First, the operation control unit 200 switches the power activation / shutdown signal VCONT from the Low level to the High level. As a result, the operation mode becomes the power activation mode. When the power activation / shutdown signal VCONT changes to the high level, the control signal generator 210 switches the first switch control signal CON1 from the low level to the high level. As a result, the first switch 110 is turned ON.

  The first switch control signal CON1 is also input to the delay circuit 220. The delay circuit 220 delays the first switch control signal CON1 by a predetermined delay time, and outputs the delayed signal as the signal VDET1 to the control signal generation unit 210. The signal VDET1 changes from the Low level to the High level after a predetermined delay time from the first switch control signal CON1.

  When the signal VDET1 changes to the high level, the control signal generation unit 210 switches the first switch control signal CON1 from the high level to the low level. As a result, the first switch 110 is turned OFF. Furthermore, the control signal generator 210 switches the second switch control signal CON2 from the low level to the high level. As a result, the second switch 120 is turned ON.

  The second switch control signal CON2 is also input to the delay circuit 230. The delay circuit 230 delays the second switch control signal CON2 by a predetermined delay time, and outputs the delayed signal to the operation control unit 200 as the signal VDET2. The signal VDET2 changes from the Low level to the High level after a predetermined delay time from the second switch control signal CON2. The operation control unit 200 recognizes that the circuit blocks 10-1 to 10-3 are ready to be operated when the signal VDET2 is changed to the high level.

  In the power shutdown mode, the operation control unit 200 switches the power activation / shutdown signal VCONT from the high level to the low level. When the power activation / shutdown signal VCONT changes to the low level, the control signal generation unit 210 switches the second switch control signal CON2 from the high level to the low level. As a result, the second switch 120 is turned OFF.

  By appropriately designing the delay amounts in the delay circuits 220 and 230, the switch control signals CON1 and CON2 can be controlled at a desired timing. The configuration of this example does not require an analog voltage level detection circuit and can be designed with a digital circuit. Therefore, downsizing and low power can be achieved.

<Second example>
FIG. 10A is a block diagram illustrating another example of a configuration for generating switch control signals (CON1, CON2). FIG. 10B is a timing chart showing the operation of the configuration shown in FIG. 10A.

  First, the operation control unit 200 switches the power activation / shutdown signal VCONT from the Low level to the High level. As a result, the operation mode becomes the power activation mode. When the power activation / shutdown signal VCONT changes to the high level, the control signal generator 210 switches the first switch control signal CON1 from the low level to the high level. As a result, the first switch 110 is turned ON.

  When the first switch 110 is turned on, the voltages at the nodes N1, N2, N3,... Here, the node farthest from the starting node on the power distribution line PL is defined as a node NZ. The level detection circuit 240 compares the voltage at the node NZ with the first power supply voltage VDD1. When the voltage of the node NZ reaches the first power supply voltage VDD1, the level detection circuit 240 switches the signal VDET1 from the Low level to the High level. The signal VDET1 is input to the control signal generation unit 210.

  When the signal VDET1 changes to the high level, the control signal generation unit 210 switches the first switch control signal CON1 from the high level to the low level. As a result, the first switch 110 is turned OFF. Furthermore, the control signal generator 210 switches the second switch control signal CON2 from the low level to the high level. As a result, the second switch 120 is turned ON.

  When the second switch 120 is turned on, the voltages at the nodes N1, N2, N3. The level detection circuit 250 compares the voltage at the node NZ with the second power supply voltage VDD2. When the voltage of the node NZ reaches the second power supply voltage VDD2, the level detection circuit 250 switches the signal VDET2 from the Low level to the High level. The signal VDET2 is input to the operation control logic 200. The operation control unit 200 recognizes that the circuit blocks 10-1 to 10-3 are ready to be operated when the signal VDET2 is changed to the high level.

  In the power shutdown mode, the operation control unit 200 switches the power activation / shutdown signal VCONT from the high level to the low level. When the power activation / shutdown signal VCONT changes to the low level, the control signal generation unit 210 switches the second switch control signal CON2 from the high level to the low level. As a result, the second switch 120 is turned OFF.

  In this example, the level detection circuits 240 and 250 directly monitor the voltage at the node NZ. Therefore, even if the delay time and voltage rise time in the delay circuit 150 deviate from the design value due to factors such as manufacturing variations and temperature fluctuations, the switch control signals CON1 and CON2 can be controlled correctly.

2-6. Modification FIG. 11 is a block diagram showing a modification of the semiconductor device according to the second embodiment. In this modification, in addition to the first power supply voltage VDD1 and the second power supply voltage VDD2, the third power supply voltage VDD3 is further used. The third power supply voltage VDD3 is higher than the second power supply voltage VDD2 (VDD3>VDD2> VDD1). The third power supply line 3 supplies the third power supply voltage VDD3.

  The power supply control circuit 100 further includes a third switch 130 in addition to the configuration shown in FIG. The third switch 130 is provided between the third power supply line 3 and the nodes N1 to N3, and turns on / off the supply of the third power supply voltage VDD3 from the third power supply line 3 to each of the nodes N1 to N3. Control. More specifically, the third switch 130-1 is provided between the third power supply line 3 and the node N1, and the third switch 130-2 is provided between the third power supply line 3 and the node N2. The third switch 130-3 is provided between the third power supply line 3 and the node N3. The third switches 130-1 to 130-3 are simultaneously turned on / off in response to the same third switch control signal CON3. By turning these third switches 130-1 to 130-3 ON / OFF, the third power supply voltage VDD3 from the third power supply line 3 to the nodes N1 to N3, that is, from the third power supply line 3 to the plurality of circuit blocks 10 is obtained. Can be controlled all at once.

  In this modification, the first switch 110, the second switch 120, and the third switch 130 are turned on in this order. As a result, the voltage supplied to the circuit block 10 rises in three stages. Specifically, the voltage supplied to the circuit block 10 temporarily rises from the ground voltage GND to the first power supply voltage VDD1, then rises from the first power supply voltage VDD1 to the second power supply voltage VDD2, and then the second power supply. The voltage rises from the voltage VDD2 to the third power supply voltage VDD3. In this case, the power consumption P required for charging the total capacity CL included in the circuit block 10 is expressed by the following equation (3).

Formula (3): P = CL × (VDD1 ² + VDD2 × (VDD2−VDD1) + (VDD3 × (VDD3−VDD2))

  For example, consider a case where VDD3 = 1.0, VDD2 = 2/3, and VDD1 = 1/3. In this case, the power consumption P given by Equation (3) is “(2/3) CL”. That is, the power consumption P can be further reduced by the three-stage charging.

3. Third embodiment 3-1. Configuration and Operation In the above-described embodiment, propagation of the first power supply voltage VDD1 on the power distribution line PL is delayed. In the third embodiment of the present invention, instead, the propagation of the first switch control signal CON1 for controlling the first switch 110 is delayed.

  FIG. 12 is a block diagram showing a configuration of a semiconductor device according to the third embodiment. In the present embodiment, a first switch 110 is provided for each of the nodes N1, N2, and N3. Specifically, the first switch 110-1 is provided between the first power supply line 1 and the node N1. The first switch 110-2 is provided between the node N1 and the node N2. Further, the first switch 110-3 is provided between the node N2 and the node N3.

  The first switch control signal CON1 for ON / OFF control of the first switch 110 is supplied to the starting node on the switch control signal line SL. The first switch 110-1 is turned on / off according to the voltage of the node SN1 on the switch control signal line SL. The first switch 110-2 is turned on / off according to the voltage of the node SN2 on the switch control signal line SL. The first switch 110-3 is turned on / off according to the voltage of the node SN3 on the switch control signal line SL. The distance along the switch control signal line SL from the starting node is the shortest to the node SN1, the next shortest to the node SN2, and the longest to the node SN3.

  In order to set the supply start timing of the first power supply voltage VDD1 to the order of the nodes N1, N2, and N3, the timing to turn on the first switch 110 may be set to the order of 110-1, 110-2, and 110-3. . For this purpose, a delay circuit 150 is provided on the switch control signal line SL between the node SN1 and the node SN2. A delay circuit 150 is provided on the switch control signal line SL between the node SN2 and the node SN3. That is, the start node, the node SN1, the delay circuit 150, the node SN2, the delay circuit 150, and the node SN3 are arranged in this order on the switch control signal SL.

  With such a configuration, propagation of the first switch control signal CON1 on the switch control signal line SL is delayed. As a result, the first switches 110-1, 110-2, and 110-3 are turned on in this order, and the supply start timing of the first power supply voltage VDD1 is the order of the nodes N1, N2, and N3. Thereby, the same effect as the above-described embodiment can be obtained. The supply of the second power supply voltage VDD2 is the same as that in the above-described embodiment.

  The arrangement relationship between the delay circuit 150 and the nodes SN1 to SN3 is not limited to that shown in FIG. When considering the signal delay amount from the starting node by the delay circuit 150, the signal delay amount to the node SN1 is the first delay amount, and the signal delay amount to the node SN2 is the second delay amount larger than the first delay amount. Yes, it is sufficient if the signal delay amount to the node SN3 is a third delay amount that is larger than the second delay amount. As long as this condition is satisfied, the nodes SN1 to SN3 may be connected in parallel to the origin node.

  FIG. 13 shows another configuration example. In FIG. 13, the first switch 110-1 is provided between the node N <b> 1 and the first power supply line 1. The first switch 110-2 is provided between the node N 2 and the first power supply line 1. The first switch 110-3 is provided between the node N3 and the first power supply line 1. The rest is the same as in FIG. Even with such a configuration, the same operation can be realized and the same effect can be obtained.

  In FIG. 12 and FIG. 13, the first switches 110-1 to 110-3, the switch control signal line SL, and the delay circuit 150 constitute a “first switch circuit”. The first switch circuit controls ON / OFF the supply of the first power supply voltage VDD1 from the first power supply line 1 to the nodes N1 to N3. When power is restored, the first switch circuit electrically connects the first power supply line 1 and the node N1, and then electrically connects the first power supply line 1 and the node N2. The first power supply line 1 and the node N3 are electrically connected. That is, the first switch circuit supplies the first power supply voltage VDD1 in the order of the nodes N1, N2, and N3.

  On the other hand, the second switches 120-1 to 120-3 constitute a “second switch circuit”. The second switch circuit performs ON / OFF control of the supply of the second power supply voltage VDD2 from the second power supply line 2 to the nodes N1 to N3. When power is restored, the second switch circuit is turned on after the first switch circuit is turned off. When turned ON, the second switch circuit supplies the second power supply voltage VDD2 to the nodes N1 to N3 all at once.

3-2. Layout FIG. 14 is a plan view showing an example of the layout of the configuration shown in FIG. The description overlapping with the case of FIG. 8 is omitted as appropriate.

  The first power supply voltage generator 160 generates the first power supply voltage VDD1 from the second power supply voltage VDD2. The first power supply voltage generation unit 160 outputs the generated first power supply voltage VDD1 to the first power supply line 1. A configuration example of the first power supply voltage generation unit 160 will be described in detail later. Of course, a configuration in which the first power supply voltage VDD1 is externally applied is also possible.

  The first switch 110-1 is an NMOS transistor. The NMOS transistor includes a gate 111, a drain 112, and a source 113. The gate 111 is connected to the node SN1 on the switch control signal wiring 190. The drain 112 is connected to the first power supply line 1. The source 113 is connected to the block power supply wiring 180-1 (node N1).

  The first switch 110-2 is an NMOS transistor. The NMOS transistor includes a gate 111, a drain 112, and a source 113. The gate 111 is connected to the node SN2 on the switch control signal wiring 190. The drain 112 is connected to the block power supply wiring 180-1 (node N1). The source 113 is connected to the block power supply wiring 180-2 (node N2).

  The switch control signal wiring 190 formed in the wiring layer corresponds to the switch control signal line SL in FIG. The switch control signal wiring 190 is supplied with the first switch control signal CON1.

  A delay circuit 150 is formed between the node SN1 and the node SN2 of the switch control signal wiring 190. The delay circuit 150 has a different structure from the switch control signal wiring 190 and is typically formed in a wiring layer different from the switch control signal wiring 190. For example, the delay circuit 150 is a polysilicon element formed on a substrate. The delay circuit 150 and the switch control signal wiring 190 formed in different layers are connected by vias.

  The other configuration is the same as that shown in FIG.

4). About First Power Supply Voltage Generating Unit 160 FIG. 15 shows a circuit configuration example of the first power supply voltage generating unit 160. The first power supply voltage generator 160 has a structure called a switched capacitor. Specifically, as illustrated in FIG. 15, the first power supply voltage generation unit 160 includes two capacitive elements C1 and C2 and four switches S1 to S4. The operation of the first power supply voltage generator 160 is as follows.

  First, as shown in FIG. 16A, the switches S1 and S3 are turned on, while the switches S2 and S4 are turned off. This operation is hereinafter referred to as operation 1. By the operation 1, the first terminal of the capacitor C1 is electrically connected to the VDD2 terminal (terminal for inputting the second power supply potential VDD2), and the second terminal outputs the VDD1 terminal (first power supply potential VDD1). Terminal).

  Next, as shown in FIG. 16B, the switches S2 and S4 are turned on, while the switches S1 and S3 are turned off. This operation is hereinafter referred to as operation 2. By operation 2, the first terminal of the capacitor C1 is electrically connected to the VDD1 terminal, and the second terminal is electrically connected to the ground terminal. At this time, charge movement occurs via the switch S2 so that there is no potential difference between the capacitive elements C1 and C2. As a result, the potential VDD1 output to the VDD1 terminal after the operation 2 is given by the following equation. Here, VDD1 'is the value of VDD1 before operation 2.

  VDD1 = (C1 * (VDD2-VDD1 ') + C2 * VDD1') / (C1 + C2)

  When the above operation 1 and operation 2 are repeated, VDD1 gradually increases. FIG. 17 is a graph showing the rise of VDD1, where the vertical axis represents the value of VDD1 and the horizontal axis represents the number of executions of operation 2. As shown in FIG. 17, VDD1 gradually rises by the repetition of operation 1 and operation 2, and finally converges to VDD2 / 2. This convergence value (= VDD2 / 2) is constant regardless of the capacitance ratio of the capacitive elements C1 and C2. Therefore, high accuracy can be obtained without being affected by variations in capacitance values.

  According to this method, power consumption due to charge transfer in operation 2 occurs until the value of VDD1 converges, but after the convergence, there is no charge transfer, so no power consumption occurs. Further, when switching from the operation 1 to the operation 2, no change occurs in the charge amount stored in the capacitive elements C1 and C2, so that no power consumption occurs. Thus, according to this method, it is possible to generate the first power supply potential VDD1 from the second power supply potential VDD2 with high power efficiency.

  The convergence value of the first power supply potential VDD1 is not limited to VDD2 / 2. Other convergence values can be realized by changing the number of capacitive elements and switches. For example, in order to set the convergence value of VDD1 to VDD2 / 3, a circuit configuration as shown in FIG. 18 may be used. In the case of FIG. 18, the switches S1, S3, and S6 are turned on in the operation 1 and the other switches are turned off, and the switches S2, S5, S4, and S7 are turned on in the operation 2, and the other switches are turned off. .

  The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the above-described embodiments, and can be appropriately changed by those skilled in the art without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 1 1st power supply line 2 2nd power supply line 3 3rd power supply line 10 Circuit block 100 Power supply control circuit 110 1st switch 120 2nd switch 130 3rd switch 150 Delay circuit 160 1st power supply voltage generation part 170 Power distribution wiring 180 Block power supply wiring 190 Switch control signal wiring 200 Operation control unit 210 Control signal generation unit 220 Delay circuit 230 Delay circuit 240 Level detection circuit 250 Level detection circuit PL Power distribution line SL Switch control signal line N1, N2, N3 Nodes SN1, SN2, SN3 node CON switch control signal CON1 first switch control signal CON2 second switch control signal CON3 third switch control signal VDD power supply voltage VDD1 first power supply voltage VDD2 second power supply voltage VDD3 third power supply voltage

Claims (6)

A first power supply line for supplying a first power supply voltage;
A second power supply line for supplying a second power supply voltage higher than the first power supply voltage;
A pre-stage circuit block;
A subsequent circuit block that operates based on an output signal of the previous circuit block;
A power supply control circuit for controlling the supply of the first power supply voltage and the second power supply voltage to the front circuit block and the rear circuit block;
The power supply control circuit delays the supply start timing of the first power supply voltage to the subsequent circuit block from the supply start timing of the first power supply voltage to the previous circuit block, and further includes the preceding circuit block and A semiconductor device that supplies the second power supply voltage to both the front circuit block and the rear circuit block after the first power supply voltage is supplied to the rear circuit block. The semiconductor device according to claim 1,
The power supply control circuit supplies the second power supply voltage to the preceding circuit block and the succeeding circuit block simultaneously. The semiconductor device according to claim 1 or 2,
The power supply control circuit includes:
Power distribution wiring,
A first switch provided between the first power supply line and a starting point node on the power distribution line and configured to ON / OFF control the supply of the first power supply voltage from the first power supply line to the starting point node;
A node on the power distribution line, the first node connected to the power supply input of the previous circuit block;
A second node connected to a power supply input of the subsequent circuit block, which is a node on the power distribution line;
A delay circuit provided on the power distribution line so that a signal delay amount from the start node to the second node is larger than a signal delay amount from the start node to the first node. The semiconductor device according to claim 3,
The power supply control circuit further includes a second switch that performs ON / OFF control of the supply of the second power supply voltage from the second power supply line to the first node and the second node,
A semiconductor device in which the first switch is turned off and the second switch is turned on after the first switch is turned on and the first power supply voltage is supplied to both the preceding circuit block and the subsequent circuit block. The semiconductor device according to claim 1 or 2,
The power supply control circuit includes:
A first node connected to a power input of the previous circuit block;
A second node connected to the power input of the subsequent circuit block;
A first switch circuit that performs ON / OFF control of the supply of the first power supply voltage from the first power supply line to the first node and the second node;
The first switch circuit electrically connects the first power supply line and the first node, and then electrically connects the first power supply line and the second node. . The semiconductor device according to claim 5,
The power supply control circuit further includes a second switch circuit that performs ON / OFF control of the supply of the second power supply voltage from the second power supply line to the first node and the second node,
After the first switch circuit is turned on and the first power supply voltage is supplied to both the front-stage circuit block and the rear-stage circuit block, the first switch circuit is turned off and the second switch circuit is turned on. apparatus.

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