JP2013106116A - Ad conversion circuit and ad conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid lengthening an AD conversion time as a comparison time in a comparison section is made longer upon bit determination.SOLUTION: An analog voltage generation section 11 samples received analog signals in synchronism with an external clock signal Φs, and generates a first analog voltage and a second analog voltage on the basis of a control signal. A comparison section 12 compares the first analog voltage and the second analog voltage in terms of magnitude in synchronism with a clock signal Φc. A control section 13 gradually reduces a voltage difference between the first analog voltage and the second analog voltage, and generates a digital signal depending on the sampled analog signals in synchronism with the external clock signal Φs on the basis of the comparison result of the comparison section 12. A center voltage adjustment section 15 adjusts a center voltage between the first analog voltage and the second analog voltage to increase currents flowing through input transistors of the comparison section 12 when the number of signal transitions of the clock signal Φc is equal to or greater than a threshold.

Description

  The present invention relates to an AD conversion circuit and an AD conversion method.

  A successive approximation AD (Analogue to Digital) conversion circuit that is realized with a relatively simple circuit with few analog circuits is known. A successive approximation type AD converter circuit is used for various purposes because it is highly compatible with a CMOS (Complementary Metal-Oxide Semiconductor) process and can be miniaturized.

  The successive approximation AD conversion circuit includes, for example, a DA (Digital to Analogue) conversion circuit, a comparison unit, and a control circuit that controls the DA conversion circuit. The successive approximation AD converter circuit performs, for example, the following operation.

  The AD conversion circuit samples the analog signal in the sampling period and holds it as a sample voltage, and sequentially compares it with the comparison target voltage by the comparison unit. The control circuit adjusts the comparison target voltage generated by the DA converter circuit so that the voltage difference between the sample voltage and the comparison target voltage becomes smaller each time the comparison proceeds.

Based on the comparison result of the comparison unit, a digital signal corresponding to the analog signal is generated bit by bit from the most significant bit, and an N-bit digital signal is generated by N successive comparisons.
By the way, in order to obtain an N-bit digital signal, a clock signal of N times or more of the sampling frequency is used as an operation clock of the comparison unit. When such a clock signal is supplied by a PLL (Phase Looked Loop) or the like, the circuit area and power of the PLL increase. Therefore, a method of generating the signal inside the AD conversion circuit has been proposed.

  A successive approximation type AD conversion circuit that performs AD conversion on a differential analog signal is also known.

JP 2011-61597 A

  As described above, in the conventional successive approximation type AD converter circuit, the voltage difference between the sample voltage and the comparison target voltage decreases as the comparison proceeds. Similarly, when a differential analog signal is used, the voltage difference between the two input signals input to the comparison unit decreases as the comparison proceeds. That is, the voltage difference between two input signals input to the comparison unit becomes smaller as the lower bit is determined.

  When the voltage difference between the two input signals input to the comparison unit becomes small in this way, the time until the comparison result is obtained in the comparison unit becomes longer, and accordingly, the frequency of the operation clock of the comparison unit decreases. As a result, there is a problem that the AD conversion time becomes long.

  According to an aspect of the invention, an analog voltage generator that samples a received analog signal in synchronization with a first clock signal and generates a first analog voltage and a second analog voltage based on a control signal; A comparator for comparing the magnitudes of the first analog voltage and the second analog voltage in synchronization with a second clock signal, and reducing a voltage difference between the first analog voltage and the second analog voltage The control signal to be sent is sent to the analog voltage generation unit, and based on the comparison result of the comparison unit, a digital signal corresponding to the sampled analog signal is generated in synchronization with the first clock signal Unit, a clock signal generation unit that generates the second clock signal, and an input transition of the comparison unit when the number of signal transitions of the second clock signal exceeds a threshold value. As the current flowing through the motor increases, the center voltage adjusting unit for adjusting the center voltage of the first analog voltage and the second analog voltage, AD conversion circuit including a is provided.

  According to another aspect of the invention, the received analog signal is sampled in synchronization with the first clock signal, and the first analog voltage and the second analog voltage are generated based on the control signal. The magnitudes of the first analog voltage and the second analog voltage are compared in synchronization with a second clock signal, and the voltage difference between the first analog voltage and the second analog voltage is reduced. Generating a digital signal corresponding to the analog signal sampled in synchronization with the first clock signal based on the comparison result of the comparison unit, and the number of signal transitions of the second clock signal is equal to or greater than a threshold value. Then, an AD conversion method is provided that adjusts the center voltage of the first analog voltage and the second analog voltage so that the current flowing through the input transistor of the comparison unit increases.

  According to the disclosed AD conversion circuit and AD conversion method, it is possible to suppress an increase in the comparison time in the comparison unit at the time of bit determination, and thus it is possible to suppress an increase in the AD conversion time.

It is a figure which shows an example of the AD converter circuit of this Embodiment. It is a figure which shows an example of a comparison part. It is a figure which shows an example of the change of the voltages Vop and Vom when Vap is sufficiently larger than Vam. It is a figure which shows an example of the change of the voltage Vop and Vom when the difference of Vap and Vam is small. It is a figure which shows an example of the change of voltage Vop and Vom when a center voltage is increased. It is a figure which shows an example of a clock signal generation part. It is a timing chart which shows the operation example of the AD converter circuit at the time of converting an analog signal into an 8-bit digital signal. It is a figure explaining the element which determines 1 period of the clock signal (PHI) c. It is a figure which shows an example of the voltage difference of 2 inputs, and clock signal (PHI) c when the center voltage of 2 inputs of a comparison part is constant. It is a figure which shows an example of an analog voltage generation part and a center voltage adjustment part. It is a figure which shows the state of an example of the analog voltage generation part at the time of AD conversion, and a center voltage variable circuit. It is a figure which shows the modification of a center voltage adjustment part. It is a figure which shows an example of the voltage difference of 2 inputs of a comparison part, and clock signal (PHI) c when a center voltage is increased in steps. It is a figure which shows the mode of an example of the electric current which flows into the input transistor of a comparison part when a center voltage is increased in one step. It is a figure which shows the mode of an example of the electric current which flows into the input transistor of a comparison part when a center voltage is increased in steps.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating an example of an AD conversion circuit according to this embodiment.
An AD conversion circuit 10 shown in FIG. 1 is a successive conversion AD conversion circuit that inputs two analog signals that are differential signals, and includes an analog voltage generation unit 11, a comparison unit 12, and a clock signal generation unit 14. The center voltage (VCM) adjustment unit 15 is included.

  The analog voltage generator 11 samples the analog signal received via the terminals Vip and Vim in synchronization with the clock signal (hereinafter referred to as the external clock signal Φs) received via the terminal CK. That is, the analog voltage generation unit 11 holds the voltage value of the analog signal at the signal transition timing (for example, the rising timing) of the external clock signal Φs. The analog voltage generation unit 11 generates two analog voltages to be input to the comparison unit 12 based on the sampled analog signal and the control signal supplied from the control unit 13.

Although details will be described later, the analog voltage generation unit 11 is, for example, a charge redistribution DA conversion circuit having a plurality of capacitive elements and switches.
The comparison unit 12 inputs the two analog voltages generated by the analog voltage generation unit 11 via the non-inverting input terminal (+) and the inverting input terminal (−). Then, the comparison unit 12 compares the two analog voltages in synchronization with the clock signal Φc generated by the clock signal generation unit 14 and outputs the comparison result. In the example shown in FIG. 1, the comparison unit 12 outputs a complementary output signal as a comparison result.

  The control unit 13 receives the clock signal Φc and outputs a control signal for reducing the voltage difference between the two analog voltages generated by the analog voltage generation unit 11 each time the comparison unit 12 performs the comparison. To send. And the control part 13 produces | generates the digital signal according to the sampled analog signal based on the comparison result of the comparison part 12, and outputs it from terminal OUT.

  The clock signal generation unit 14 generates a clock signal Φc. Further, the clock signal generation unit 14 changes the cycle of the clock signal Φc according to the comparison time in the comparison unit 12. The clock signal generation unit 14 receives two complementary output signals from the comparison unit 12. As will be described in detail later, these two complementary output signals are “1” for one when the comparison unit 12 completes the comparison and “0” for the other, and both have the same value when the comparison is not complete. . The clock signal generation unit 14 is an operation clock for the comparison unit 12 so that the next comparison can be performed after the comparison time has elapsed (after the comparison is completed) based on the output signal of the comparison unit 12. The period of the clock signal Φc is changed.

  The center voltage adjusting unit 15 is configured to control the center voltages of the two analog voltages input to the comparison unit 12 so that the current flowing through the input transistor of the comparison unit 12 increases when the number of signal transitions of the clock signal Φc exceeds a threshold value. Adjust.

FIG. 1 shows an example of a voltage difference between two analog voltages (two inputs of the comparison unit 12) input to the comparison unit 12 and a clock signal Φc. The horizontal axis is time, and the vertical axis is voltage.
As shown in FIG. 1, the voltage difference between the two analog voltages generated by the analog voltage generator 11 is reduced each time the successive comparison proceeds. The comparison unit 12 tends to increase the comparison time as the voltage difference between the two input analog voltages decreases. In other words, the comparison time tends to be longer in the comparison for determining the value of the lower bit of the digital signal.

  Although details will be described later, the comparison time is shortened when the current flowing through the input transistor of the comparison unit 12 increases. Therefore, in the AD converter circuit 10 according to the present embodiment, the center voltage adjustment unit 15 increases the current flowing through the input transistor of the comparison unit 12 when the number of signal transitions of the clock signal Φc is equal to or greater than the threshold value. The center voltage of the two inputs of the comparison unit 12 is adjusted.

  FIG. 1 shows a waveform when the comparison unit 12 (see FIG. 2) in which the current flowing through the input transistor increases when the center voltage of two inputs increases is applied. As a signal transition of the clock signal Φc, the center voltage is increased from VCM1 to VCM2 when the number of signal falling times is three or more.

  In this way, when the signal transition of the clock signal Φc is equal to or greater than the threshold, the center voltage is adjusted so that the current flowing through the input transistor increases, for example, when the value of the lower bit is determined, the comparison unit 12 It is possible to suppress an increase in the comparison time at. Since the cycle of the clock signal Φc is changed according to the comparison time in the comparison unit 12, a decrease in the frequency of the clock signal Φc is suppressed by shortening the comparison time. As a result, it is possible to suppress an increase in AD conversion time.

  In addition, the current flowing through the input transistor of the comparison unit 12 is not increased in all periods during the successive comparison, but is increased when the signal transition of the clock signal Φc is equal to or greater than the threshold value. Increase in power can be suppressed.

Hereinafter, a part of the AD conversion circuit 10 shown in FIG. 1 will be described in more detail.
(Comparator 12)
FIG. 2 is a diagram illustrating an example of the comparison unit.

  The comparison unit 12 is realized by, for example, a latch type circuit as shown in FIG. 2 from the viewpoint of high-speed operation. The comparison unit 12 shown in FIG. 2 includes n-channel MOSFETs (hereinafter abbreviated as nMOS) 20 and 21 which are input transistors for inputting two analog voltages Vap and Vam. . Further, the comparison unit 12 includes nMOSs 22 and 23, p-channel MOSFETs (hereinafter abbreviated as pMOS) 24, 25, 26 and 27, and inverter circuits 28, 29, 30 and 31.

  The gates of the nMOSs 20 and 21 are connected to the analog voltage generator 11 and the center voltage adjuster 15 shown in FIG. 1, generated by the analog voltage generator 11, and the center voltage adjusted by the center voltage adjuster 15. Two analog voltages Vap and Vam are applied. The drain of the nMOS 20 is connected to the source of the nMOS 22, and the drain of the nMOS 21 is connected to the source of the nMOS 23. The sources of the nMOSs 20 and 21 are grounded.

  The gates of the nMOSs 22 and 23 are connected to the drains of each other. The drain of the nMOS 22 is further connected to the drains of the pMOSs 24 and 25, and the drain of the nMOS 23 is further connected to the drains of the pMOSs 26 and 27.

  The gates of the pMOSs 24 and 27 are connected to the clock signal generation unit 14 shown in FIG. 1, and the clock signal Φc is supplied from the clock signal generation unit 14. The gates of the pMOSs 25 and 26 are connected to the drains of each other. The sources of the pMOS 24 to 27 are connected to the power supply line VDD.

  The input terminal of the inverter circuit 28 is connected between the drain of the nMOS 22 and the drains of the pMOSs 24 and 25. The output terminal of the inverter circuit 28 is connected to the input terminal of the inverter circuit 29. The input terminal of the inverter circuit 30 is connected between the drain of the nMOS 23 and the drains of the pMOSs 26 and 27. The output terminal of the inverter circuit 30 is connected to the input terminal of the inverter circuit 31. The output terminals of the inverter circuits 29 and 31 are connected to the control unit 13 and the clock signal generation unit 14 shown in FIG. 1, and the output signals QOp and QOm that are the comparison results in the comparison unit 12 are the control unit 13 and the clock signal. It is supplied to the generation unit 14.

  When the voltage between the drain of the nMOS 22 and the drains of the pMOSs 24 and 25 is the voltage Vom, and the voltage between the drain of the nMOS 23 and the drains of the pMOSs 26 and 27 is the voltage Vop, the voltages Vop and Vom are, for example, It changes as follows.

FIG. 3 is a diagram illustrating an example of changes in the voltages Vop and Vom when Vap is sufficiently larger than Vam. The vertical axis represents voltage, and the horizontal axis represents time.
When the comparison unit 12 is reset, an L (Low) level clock signal Φc is supplied to the gates of the pMOSs 24 and 27. Thus, when the pMOSs 24 and 27 are turned on and the analog voltages Vap and Vam are not applied to the nMOSs 20 and 21, the nMOSs 20 and 21 are turned off, and the voltages Vop and Vom are applied to the power supply line VDD. The voltage is Vdd. Further, the nMOSs 22 and 23 are in an on state.

  When the analog voltages Vap and Vam are applied to the gates of the nMOSs 20 and 21 (timing t1), the voltages Vop and Vom are reduced by the currents Ip and Im flowing between the drains and the sources of the nMOSs 20 and 21 flowing in proportion to the voltages. I will do it.

  When the analog voltage Vap is sufficiently larger than the analog voltage Vam, the current Ip flows sufficiently more than the current Im. At this time, since the gate voltage of the nMOS 23 is lower than the gate voltage of the nMOS 22, the difference between the current Ip and the current Im becomes significant, and the speed at which the voltage Vom decreases is significantly faster than the speed at which the voltage Vop decreases. Become.

  When the voltage Vom reaches the threshold voltage Vpth of the pMOS 26 (timing t2), the pMOS 26 is turned on and the voltage Vop increases. As a result, the gate voltage of the nMOS 22 rises, so that more current Ip flows and the speed of decrease of the voltage Vom increases.

  When the voltage Vom reaches the threshold voltage Vnth of the nMOS 23 (timing t3), the nMOS 23 is turned off, the voltage Vop is clipped to the power supply voltage level, and the voltage Vom is clipped to the ground level (GND).

  As a result, the signal level of the output signal QOp of the inverter circuit 31 becomes H (High) level (or “1”), and the signal level of the output signal QOm of the inverter circuit 29 becomes L level (or “0”).

  In the above example, the analog voltages Vap and Vam are applied to the gates of the nMOS 20 and nMOS 21 that are the input transistors of the comparator 12, and the time from the timing t1 to the timing t3 until the voltages Vop and Vom become constant voltages. It will take. That is, the time from timing t1 to timing t3 determines the comparison time.

FIG. 4 is a diagram illustrating an example of changes in the voltages Vop and Vom when the difference between Vap and Vam is small. The vertical axis represents voltage, and the horizontal axis represents time.
As described above, when the comparison unit 12 is reset, the voltages Vop and Vom are the power supply voltage Vdd applied to the power supply line VDD.

  When the analog voltages Vap and Vam are applied to the gates of the nMOSs 20 and 21 (timing t4), the voltages Vop and Vom are reduced by the currents Ip and Im flowing in proportion to the voltages. However, when the difference between the analog voltage Vap and the analog voltage Vam is small, the current Ip and the current Im are substantially the same. In this case, since the gate voltages of the nMOS 22 and the nMOS 23 decrease almost in the same manner, it is difficult to make a difference between the current Ip and the current Im, and the speed at which the voltage Vom and the voltage Vop decrease is relatively slow.

  When the analog voltage Vap is slightly larger than the analog voltage Vam, the voltage Vom reaches the threshold voltage Vpth slightly faster than the voltage Vop (timing t5). As a result, the pMOS 26 is turned on and the voltage Vop increases. As a result, the gate voltage of the nMOS 22 increases, a large amount of current Ip flows, and the speed of decreasing the voltage Vom increases.

  When the voltage Vom reaches the threshold voltage Vnth of the nMOS 23 (timing t6), the nMOS 23 is turned off, the voltage Vop is clipped to the power supply voltage level, and the voltage Vom is clipped to the ground level (GND).

  As a result, the signal level of the output signal QOp of the inverter circuit 31 becomes H level (or “1”), and the signal level of the output signal QOm of the inverter circuit 29 becomes L level (or “0”).

  Thus, when the difference between the analog voltages Vap and Vam is small, the time until the voltages Vop and Vom become a constant voltage becomes longer than when the difference between the analog voltages Vap and Vam is large, and the comparison time becomes longer.

The currents Ip and Im flowing in the nMOSs 20 and 21 that are input transistors of the comparison unit 12 can be expressed as follows.
Ip∝β (Vap−Vth) = β (VCM + ΔV−Vth) (1)
Im∝β (Vam−Vth) = β (VCM−ΔV−Vth) (2)
Here, β is an element constant of the nMOS 20 and 21, and has a value corresponding to the gate width, gate length, carrier mobility, and gate insulating film capacitance. Vth is a threshold voltage of the nMOSs 20 and 21, and VCM is a center voltage (in-phase voltage) of the analog voltages Vap and Vam. ΔV is the difference between the analog voltages Vap and Vam from the center voltage VCM.

From the above equations (1) and (2), it can be seen that the currents Ip and Im can be increased by increasing the center voltage VCM when ΔV is fixed.
FIG. 5 is a diagram illustrating an example of changes in the voltages Vop and Vom when the center voltage is increased. The vertical axis represents voltage, and the horizontal axis represents time. Dotted lines indicate changes in the voltages Vop and Vom shown in FIG.

  FIG. 5 shows an example of changes in the voltages Vop and Vom when the center voltage VCM of the analog voltages Vap and Vam is larger than when the characteristics of the voltages Vop and Vom shown in FIG. 4 are obtained. When the center voltage VCM increases, the currents Ip and Im increase to increase the decrease speed of the voltages Vop and Vom, and the voltage Vom reaches the threshold voltage Vpth faster than the case shown in FIG. 4 (timing t5a). As a result, the timing at which the voltage Vop is clipped to the level of the power supply voltage and the voltage Vom is clipped to the ground level (GND) is advanced, and the comparison time can be reduced.

  In the example shown in FIG. 5, the voltage Vop is clipped to the power supply voltage level and the voltage Vom is clipped to the ground level (GND) at the timing t6a earlier than the timing t6 shown in FIG.

  When the comparison unit 12 as shown in FIG. 2 is used, in the AD conversion circuit 10 of the present embodiment, the center voltage adjustment unit 15 uses the center voltage VCM of the analog voltages Vap and Vam input to the comparison unit 12. By increasing, the comparison time can be shortened.

  Note that the comparison unit 12 is not limited to the circuit shown in FIG. For example, a pMOS may be used as the input transistor. In that case, the center voltage adjustment unit 15 can increase the currents Ip and Im and increase the comparison time by increasing the center voltage VCM of the analog voltages Vap and Vam to the minus side.

(Clock signal generator 14)
FIG. 6 is a diagram illustrating an example of the clock signal generation unit.
The clock signal generation unit 14 includes an XOR (exclusive OR) circuit 41, a delay circuit 42, a logic circuit 43, and a delay amount adjustment circuit 44.

  The XOR circuit 41 inputs the output signals QOp and QOm of the comparison unit 12 and outputs an exclusive OR of these signals. The delay circuit 42 generates a pulse signal by delaying and inverting the output signal of the XOR circuit 41.

  The logic circuit 43 receives the pulse signal generated by the delay circuit 42 and the ready signal from the outside. For example, when the ready signal changes from H level to L level, the logic circuit 43 sets the clock signal Φc to H level. Thereafter, when the ready signal remains in the L level state, the logic circuit 43 outputs the pulse signal output from the delay circuit 42 as the clock signal Φc.

  For example, the delay amount adjustment circuit 44 counts the number of signal transitions of the falling edge of the clock signal Φc generated during one cycle of the external clock signal Φs, outputs a count value count, and supplies the count value count to the center voltage adjustment unit 15. To do. The delay amount adjusting circuit 44 increases the delay amount in the delay circuit 42 when the count value is larger than the predetermined value, and decreases the delay amount when the count value is smaller than the predetermined value, thereby generating the generated clock signal Φc. Change the cycle.

  FIG. 7 is a timing chart showing an operation example of the AD conversion circuit when converting an analog signal into an 8-bit digital signal. FIG. 7 shows the external clock signal Φs, the clock signal Φc, the count value of the signal transition of the clock signal Φc (the count value of the falling edge), and the state of the AD conversion circuit 10.

  When the external clock signal Φs rises to the H level (timing t10), the analog voltage generator 11 samples the analog signal. When the external clock signal Φs falls to the L level (timing t11), each bit is determined when the sampled analog signal is converted into a digital signal. First, the determination of the most significant bit (bit 8) is performed, and thereafter, the determination of the lower bit side such as bit 7, bit 6, bit 5, bit 3, bit 2, bit 1 is performed in synchronization with the falling edge of the clock signal Φc. Is called.

  During this time, the delay amount adjustment circuit 44 of the clock signal generation unit 14 counts the falling edge of the clock signal Φc, and when the external clock signal Φs rises to the H level (timing t12), the signal transition counting period ends. When the clock signal Φc is generated, the delay amount adjustment circuit 44 adjusts the delay amount so that the 8-bit determination ends between timings t11 to t12.

FIG. 8 is a diagram illustrating elements that determine one cycle of the clock signal Φc.
As shown in FIG. 8, one cycle of the clock signal Φc is determined based on the comparison time in the comparison unit 12, the delay time (Δt) in the delay circuit 42, and the reset time of the comparison unit 12.

  The reset time of the comparison unit 12 is substantially constant regardless of the voltage difference between the two inputs of the comparison unit 12, and Δt is also constant after adjustment by the delay amount adjustment circuit 44. However, as described above, the comparison time becomes longer when the voltage difference between the two inputs of the comparison unit 12 is small.

  FIG. 9 is a diagram illustrating an example of the voltage difference between the two inputs and the clock signal Φc when the center voltage of the two inputs of the comparison unit is constant. The horizontal axis is time, and the vertical axis is voltage. FIG. 9 shows an example of the voltage difference between the two inputs of the comparison unit 12 and the clock signal Φc obtained when performing a 6-bit AD conversion operation.

  The voltage difference between the two analog voltages generated by the analog voltage generator 11 is reduced each time the successive comparison proceeds. As described above, the comparison time in the comparison unit 12 becomes longer as the voltage difference between two input analog voltages becomes smaller. Further, since the cycle of the clock signal Φc varies depending on the comparison time, as the comparison time becomes longer, the cycle of the clock signal Φc also becomes longer as shown in FIG.

  Therefore, in the AD conversion circuit 10 according to the present embodiment, as shown in FIG. 1, the center voltage adjustment unit 15 raises the center voltage when the falling edge of the clock signal Φc is detected three times, so that the comparison time is increased. Suppresses becoming longer.

(Analog voltage generator 11 and center voltage adjuster 15)
FIG. 10 is a diagram illustrating an example of the analog voltage generation unit and the center voltage adjustment unit. FIG. 10 shows an example of an analog voltage generation unit used for 5-bit AD conversion.

  The analog voltage generation unit 11 is, for example, a charge redistribution DA conversion circuit as shown in FIG. 10, and capacitive element units 50 and 51 having a plurality of capacitive elements, and a switch unit having a plurality of switches. 52, 53, 54, 55.

  In the example of FIG. 10, each of the capacitive element units 50 and 51 includes two capacitive elements having a capacitance value C, and the capacitance values are twice (2C), four times (4C), eight times (8C), 16 One double (16C) capacitive element is provided.

  One end of each capacitive element of the capacitive element section 50 is connected to the inverting input terminal (−) of the comparison section 12 shown in FIG. One end of each capacitive element of the capacitive element section 51 is connected to the non-inverting input terminal (+) of the comparison section 12 shown in FIG.

  The other end of each capacitive element of the capacitive element unit 50 is connected to each switch of the switch unit 52 that switches whether or not to connect to the signal line 82. The signal line 82 is connected to the terminal Vip shown in FIG. Hereinafter, the voltage of the analog signal input to the terminal Vip is also expressed as Vip. The other end of each capacitive element of the capacitive element unit 51 is connected to each switch of the switch unit 53 that switches whether or not to connect to the signal line 83. The signal line 83 is connected to the terminal Vim shown in FIG. Hereinafter, the voltage of the analog signal input to the terminal Vim is also expressed as Vim.

  Each switch of the switch unit 54 that switches whether or not the other end of one of the capacitive elements of the capacitive element unit 50 excluding one capacitive element having the capacitance value C is connected to the signal line 84 or the signal line 85. It is connected to the. Reference voltages Vrp and Vrm that determine the AD conversion range of the AD conversion circuit 10 are applied to the signal lines 84 and 85.

The other end of one capacitive element having a capacitance value C of the capacitive element unit 50 is connected to a switch that switches whether or not to connect to the signal line 85 in the switch unit 54.
Each switch of the switch unit 55 that switches whether or not the other end of the capacitive element of the capacitive element unit 51 except one capacitive element of the capacitance value C is connected to the signal line 84 or the signal line 85 is switched. It is connected to the. The other end of one capacitive element having a capacitance value C of the capacitive element unit 51 is connected to a switch for switching whether or not to connect to the signal line 84 in the switch unit 55.

  Each switch of the switch units 52 and 53 is, for example, an nMOS, a pMOS, or a CMOS, and is turned on or off in synchronization with the external clock signal Φs. For example, each of the switches 52 and 53 is turned on when the external clock signal Φs rises to the H level, and turned off when the external clock signal Φs falls to the L level.

  Each switch of the switch units 54 and 55 is, for example, an nMOS, a pMOS, or a CMOS, and is turned on or off based on a control signal output from the control unit 13 according to the comparison result in the comparison unit 12.

The center voltage adjustment unit 15 includes a center voltage variable circuit 60, an edge count comparison circuit 61, and a threshold supply circuit 62.
The center voltage variable circuit 60 includes capacitive element units 70 and 71 having a plurality of capacitive elements, and switch units 72, 73, 74, and 75 having a plurality of switches.

In the example of FIG. 10, the capacitive element units 70 and 71 each have four capacitive elements having a capacitance value C.
One end of each capacitive element of the capacitive element section 70 is connected to the inverting input terminal (−) of the comparison section 12 shown in FIG. One end of each capacitive element of the capacitive element section 71 is connected to the non-inverting input terminal (+) of the comparison section 12 shown in FIG.

  The other end of each capacitive element of the capacitive element unit 70 is connected to each switch of the switch unit 72 that switches whether to connect to the signal line 82. The other end of each capacitive element of the capacitive element unit 71 is connected to each switch of the switch unit 73 that switches whether or not to connect to the signal line 83.

The other end of each capacitive element of the capacitive element unit 70 is further connected to each switch of the switch unit 74 that switches whether to connect to the power supply line VDD or the ground line VSS.
The other end of each capacitive element of the capacitive element unit 71 is further connected to each switch of the switch unit 75 that switches whether to connect to the power supply line VDD or the ground line VSS.

  Each switch of the switch units 72 and 73 is, for example, an nMOS, a pMOS, or a CMOS, and is turned on or off in synchronization with the external clock signal Φs. For example, each of the switches 72 and 73 is turned on when the external clock signal Φs rises to the H level, and turned off when the external clock signal Φs falls to the L level.

  Each switch of the switch units 74 and 75 is, for example, an nMOS or a pMOS, and is turned on or off based on a control signal ctrl output from the edge count comparison circuit 61.

  The edge count comparison circuit 61 is a digital circuit (logic circuit), a count value count of the number of signal transitions (falling edges in the above example) of the clock signal Φc in the clock signal generation unit 14, and a threshold supply circuit 62. Compare with the threshold supplied from Then, the edge count comparison circuit 61 determines whether or not the count value count is equal to or greater than a threshold value.

  Furthermore, the edge count comparison circuit 61 generates and outputs a control signal ctrl for turning on or off each switch of the switch units 72 to 75 of the center voltage variable circuit 60 based on the comparison determination result. For example, when the threshold value is “3”, the edge count comparison circuit 61 receives the control signal ctrl for increasing the center voltage when the count value of the falling edge of the clock signal Φc is “3” or more. 60.

  The threshold supply circuit 62 is a register, for example, and stores the above threshold. The center voltage adjustment unit 15 may receive the threshold value from outside the AD conversion circuit 10.

  In the center voltage adjustment unit 15, the clock signal generation unit 14 can use the count value count of the signal transition counted by the delay amount adjustment circuit 44 that is used to change the cycle of the clock signal Φc. There is no need to newly provide a circuit for counting the count value count.

  As shown in FIG. 10, in the signal line 80, one end of the switch S1 is connected between the analog voltage generator 11 and the center voltage variable circuit 60, and the other end of the switch S1 is connected. The center voltage VCM is applied. In the signal line 81, one end of the switch S2 is connected between the analog voltage generation unit 11 and the center voltage variable circuit 60, and the center voltage VCM is applied to the other end of the switch S2. . The switches S1 and S2 are, for example, nMOS, pMOS, or CMOS, and are turned on or off in synchronization with the external clock signal Φs.

  FIG. 10 shows the state of the switch when sampling an analog signal. At the time of sampling, the switches of the switch units 52 and 53 are all turned on, and the switches of the switch units 54 and 55 are all turned off. For this reason, the voltage Vip applied to the signal line 82 is applied to each capacitive element of the capacitive element unit 50. Further, the voltage Vim applied to the signal line 83 is applied to each capacitive element of the capacitive element unit 51.

  Further, at the time of sampling, all the switches of the switch units 72 and 73 of the center voltage variable circuit 60 are turned on, and all the switches of the switch units 74 and 75 are turned off. Therefore, the voltage Vip applied to the signal line 82 is applied to each capacitive element of the capacitive element unit 70. Further, the voltage Vim applied to the signal line 83 is applied to each capacitive element of the capacitive element unit 71.

At the time of sampling, the switches S1 and S2 are turned on, and the center voltage VCM is applied to the signal lines 80 and 81.
FIG. 11 is a diagram illustrating a state of an example of the analog voltage generation unit and the center voltage variable circuit during AD conversion.

  At the time of AD conversion, all the switches of the switch units 52 and 53 of the analog voltage generation unit 11 are turned off, the connection between the capacitive element of the capacitive element unit 50 and the signal line 82 is disconnected, and the capacitive element and signal of the capacitive element unit 51 are disconnected. The connection with the line 83 is disconnected. The capacitive elements of the capacitive element units 50 and 51 are connected to the signal line 84 or the signal line by the switches of the switch units 54 and 55 in accordance with a control signal sent from the control unit 13 based on the comparison result in the comparison unit 12. 85.

  Further, at the time of AD conversion, the switches of the switch units 72 and 73 of the center voltage variable circuit 60 are all turned off, the connection between the capacitive element of the capacitive element unit 70 and the signal line 82 is disconnected, and the capacitive element of the capacitive element unit 71 And the signal line 83 are disconnected. The capacitive elements of the capacitive elements 70 and 71 are connected to the power supply line VDD or the ground line VSS by the switches of the switches 74 and 75 in accordance with the control signal sent from the edge count comparison circuit 61. The center voltage variable circuit 60 adjusts the center voltages of the analog voltages Vam and Vap by selecting a capacitive element to which the power supply voltage Vdd is applied according to the control signal.

During AD conversion, the switches S1 and S2 are turned off.
At the time of AD conversion, the analog voltage Vam applied to the signal line 80 connected to the inverting input terminal (−) of the comparison unit 12 and the signal line 81 connected to the non-inverting input terminal (+) of the comparison unit 12 The applied analog voltage Vap is expressed by the following equation.

Vap = VCM−Vim + (kC / (32C + Ca + Cb)) Vrp + ((32−k) C / (32C + Ca + Cb)) Vrm + (Cb / (32C + Ca + Cb)) Vdd (3)
Vam = VCM−Vip + ((32−k) C / (32C + Ca + Cb)) Vrp + (kC / (32C + Ca + Cb)) Vrm + (Cb / (32C + Ca + Cb)) Vdd (4)
Note that k is an integer of 1 ≦ k ≦ 32 determined according to the comparison result. Ca and Cb are the sum of the capacitance values of the capacitive elements connected to the ground line VSS and the total capacitance value of the capacitive elements connected to the power supply line VDD. In the example of FIG. 11, k = 16 and Ca = Cb = 2C. Vdd indicates the power supply voltage applied to the power supply line VDD.

Vap-Vam is expressed by the following equation.
Vap−Vam = (Vip−Vim) − ((32−2k) C / (32C + Ca + Cb)) (Vrp−Vrm) (5)
The center voltage (common-mode voltage) of the two analog voltages Vap and Vam is expressed by the following equation.

(Vap + Vam) / 2 = VCM − ((Vip + Vim) / 2) + (32C / (32C + Ca + Cb)) ((Vrp + Vrm) / 2) + (Cb / (32C + Ca + Cb)) Vdd (6)
In equation (6), (Vip + Vim) / 2 and (Vrp + Vrm) / 2 indicate the analog input and the common-mode voltage of the reference voltage, respectively, and are fixed values. Therefore, the center voltage can be adjusted by changing Cb by changing the number of capacitive elements to which the power supply voltage Vdd is applied, and changing the final term of Equation (6). For example, the center voltage can be increased by increasing Cb.

  Therefore, for example, when the count value of the falling edge of the clock signal Φc is equal to or greater than the threshold value, the edge count comparison circuit 61 switches the switches of the switch units 74 and 75 so that Ca = Cb = 2C. Let Ca = C and Cb = 3C. As a result, the center voltage of the two inputs of the comparison unit 12 can be increased, and when the lower three bits are determined, it is possible to suppress an increase in the comparison time in the comparison unit 12 for the reason described above. it can.

  As described above, the successive approximation type AD converter circuit 10 reduces the voltage difference between the two inputs of the comparison unit 12 for each successive comparison. As a result, Vap-Vam changes. It is desirable for the edge count comparison circuit 61 to control the switches of the switch units 74 and 75 so that Ca + Cb becomes constant in order to prevent deterioration of conversion accuracy.

As can be seen from equation (6), the center voltage can also be adjusted by adjusting the power supply voltage Vdd instead of Cb.
FIG. 12 is a diagram illustrating a modification of the center voltage adjustment unit. The same elements as those in FIG. 10 are denoted by the same reference numerals.

  In the center voltage adjusting unit 15a shown in FIG. 12, the center voltage variable circuit 60a is different from those shown in FIGS. 10 and 11, and the portions corresponding to the switch units 74 and 75 are not provided. In such a center voltage variable circuit 60a, Ca = Cb = 2C in the state shown in FIG.

  At the time of AD conversion, the edge count comparison circuit 61 controls on / off of the switches of the switch units 74 and 75, and changes the number of capacitive elements connected to the power supply line VDD and the capacitive elements connected to the ground line VSS. The center voltage can be adjusted.

When the center voltage variable circuit 60a shown in FIG. 12 is used, Vap−Vam is expressed by the following equation.
Vap−Vam = (32C / (32C + Ca + Cb)) (Vip−Vim) − ((32−2k) C / (32C + Ca + Cb)) (Vrp−Vrm) (7)
The center voltage (common-mode voltage) of the two analog voltages Vap and Vam is expressed by the following equation.

(Vap + Vam) / 2 = VCM− (32C / (32C + Ca + Cb)) ((Vip + Vim) / 2) − (Vrp + Vrm) / 2)) + ((Ca−Cb) / (32C + Ca + Cb)) Vdd (8)
In the above equation, (Vip + Vim) / 2 and (Vrp + Vrm) / 2 indicate the analog input and the common-mode voltage of the reference voltage, respectively, and are fixed values. Therefore, as can be seen from equation (8), the center voltage can be adjusted by changing Ca, Cb or the power supply voltage Vdd.

  By the way, the center voltage adjusting units 15 and 15a shown in FIGS. 10 to 12 adjust the center voltage in a plurality of stages according to the count value count so that the current flowing through the input transistor of the comparison unit 12 increases in a plurality of stages. You may adjust it. In this case, for example, the threshold supply circuit 62 stores a plurality of thresholds having different sizes and supplies them to the edge count comparison circuit 61.

  For example, when threshold values a, b, c such that threshold value a <threshold value b <threshold value c are supplied to the edge count comparison circuit 61, the edge count comparison circuit 61 determines the magnitude of the count value count and the threshold values a, b, c. In comparison, a control signal ctrl corresponding to the result is output.

  For example, when the count value count <threshold a, the edge count comparison circuit 61 outputs the control signal ctrl that makes the center voltage the lowest. When threshold value a ≦ count value count <threshold value b, the edge count comparison circuit 61 outputs a control signal ctrl for increasing the center voltage by one step. When threshold value b ≦ count value count <threshold value c, the edge count comparison circuit 61 outputs a control signal ctrl for increasing the center voltage by one more stage. When the count value count ≧ the threshold value c, the edge count comparison circuit 61 outputs a control signal ctrl that makes the center voltage the highest.

  FIG. 13 is a diagram illustrating an example of the voltage difference between the two inputs of the comparison unit and the clock signal Φc when the center voltage is increased stepwise. The horizontal axis is time, and the vertical axis is voltage. FIG. 13 shows an example of the voltage difference between the two inputs of the comparison unit 12 and the clock signal Φc, which is obtained when a 6-bit AD conversion operation is performed.

  In the example of FIG. 13, the state of change in the center voltage when threshold value a = 3, threshold value b = 4, and threshold value c = 5 is shown. At the timing t20 when the falling edge of the clock signal Φc is detected three times and the count value count becomes 3, the center voltage is increased by one step from VCM to VCMa. Further, at the timing t21 when the falling edge of the clock signal Φc is detected four times and the count value count becomes 4, the center voltage is further increased by one step and becomes VCMb. Further, at the timing t22 when the falling edge of the clock signal Φc is detected five times and the count value count becomes 5, the center voltage is further increased by one step and becomes VCMc.

  The voltage difference between the two inputs of the comparison unit 12 becomes smaller when the lower bit is determined, but a voltage difference is secured to some extent before the least significant bit. In some cases, the conversion speed can be secured without increasing the voltage. In that case, as shown in FIG. 13, the power increase can be suppressed by gradually adjusting the center voltage, and as a result, the average power can be reduced.

  FIG. 14 is a diagram illustrating an example of a current flowing in the input transistor of the comparison unit when the center voltage is increased in one stage. The horizontal axis represents time, and the vertical axis represents current. The state of the clock signal Φc is also shown. The dotted line shows the state of current flowing through the input transistor of the comparison unit 12 when the center voltage is increased from the beginning.

  When the center voltage is increased at the timing when the falling edge of the clock signal Φc occurs three times, the current flowing through the input transistor of the comparison unit 12 also increases. Also in this case, power consumption can be reduced as compared with the case where the center voltage is increased from the beginning. In addition, since the center voltage is not increased at the time of determination of the upper bits, the influence on the reliability of the device such as withstand voltage can be reduced.

  FIG. 15 is a diagram illustrating an example of a current flowing in the input transistor of the comparison unit when the center voltage is increased stepwise. The horizontal axis represents time, and the vertical axis represents current. The state of the clock signal Φc is also shown. The dotted line shows the state of current flowing through the input transistor of the comparison unit 12 when the center voltage is increased from the beginning.

  As shown in FIG. 13, when the center voltage is increased stepwise at the timings t20, t21, and t22 when the falling edge of the clock signal Φc is generated three times, four times, and five times, the input of the comparator 12 The current flowing through the transistor also increases stepwise. Also in this case, the power consumption can be further reduced as compared with the case where the center voltage is increased in one step as shown in FIG. In addition, since the center voltage is not increased at the time of determination of the upper bits, the influence on the reliability of the device such as withstand voltage can be reduced.

As described above, one aspect of the AD conversion circuit and the AD conversion method of the present invention has been described based on the embodiment, but these are merely examples and are not limited to the above description.
For example, in the above description, the analog voltage generation unit 11 and the comparison unit 12 are described as receiving differential signals, but may be configured to input single-phase signals.

DESCRIPTION OF SYMBOLS 10 AD conversion circuit 11 Analog voltage generation part 12 Comparison part 13 Control part 14 Clock signal generation part 15 Center voltage adjustment part Vip, Vim, CK, OUT terminal

Claims (6)

An analog voltage generator that samples the received analog signal in synchronization with the first clock signal and generates a first analog voltage and a second analog voltage based on the control signal;
A comparator that compares the first analog voltage with the second analog voltage in synchronization with a second clock signal;
The control signal for reducing the voltage difference between the first analog voltage and the second analog voltage is sent to the analog voltage generation unit, and the first clock signal is based on the comparison result of the comparison unit. A control unit that generates a digital signal corresponding to an analog signal sampled in synchronization with
A clock signal generator for generating the second clock signal;
When the number of signal transitions of the second clock signal exceeds a threshold value, the center voltage of the first analog voltage and the second analog voltage is adjusted so that the current flowing through the input transistor of the comparison unit increases. A center voltage adjustment unit
An AD conversion circuit comprising:   The center voltage adjustment unit includes a plurality of capacitive elements connected to an input terminal of the comparison unit and a plurality of switches, and selects the capacitive element to which a power supply voltage is applied by the plurality of switches. 2. The AD conversion circuit according to claim 1, wherein the voltage is adjusted.   The center voltage adjustment unit adjusts the center voltage so that a current flowing through the input transistor increases stepwise when the number of signal transitions exceeds the threshold value. The AD conversion circuit described in 1. The clock signal generation unit includes a circuit that counts the number of signal transitions and changes a cycle of the second clock signal according to a counting result;
The said center voltage adjustment part compares the said count result with the said threshold value, and determines whether the frequency | count of the said signal transition is more than the said threshold value, It is characterized by the above-mentioned. AD conversion circuit.   The center voltage adjustment unit compares the counting result with a plurality of threshold values, and the center voltage is increased in a stepwise manner according to the number of signal transitions and the plurality of threshold values. The AD converter circuit according to claim 1, wherein the AD converter circuit is adjusted. The received analog signal is sampled in synchronization with the first clock signal, and a first analog voltage and a second analog voltage are generated based on the control signal,
A comparator compares the first analog voltage and the second analog voltage in synchronization with a second clock signal;
The voltage difference between the first analog voltage and the second analog voltage is reduced, and an analog signal sampled in synchronization with the first clock signal is determined based on the comparison result of the comparison unit. Generate digital signals,
When the number of signal transitions of the second clock signal exceeds a threshold value, the center voltage of the first analog voltage and the second analog voltage is adjusted so that the current flowing through the input transistor of the comparison unit increases. To
An AD conversion method characterized by the above.

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