JP2013105249A - Layout design method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for enabling a timing adjustment that satisfies both a SETUP time and a HOLD time.SOLUTION: After the arrangement and wiring layout of a semiconductor integrated circuit is determined, delay information of violation data including a timing violation is extracted on the basis of timing information of data that transmits a given signal line. On the basis of the extracted delay information, a capacitance value to be added so as to eliminate the timing violation is calculated. On the basis of layout arrangement information of wiring that transmits the violation data, a power supply capacity cell adjacent to the wiring that transmits the violation data is detected. On the basis of the calculated capacitance value, the detected power supply capacity cell is replaced with an adjustment capacity cell having the same layout outline and power supply/GND wiring arrangement position as the power supply capacity cell. Then, rewiring is executed by connecting the gate of the replaced adjustment capacity cell with the wiring that transmits the violation data.

Description

  The present invention relates to an automatic layout design method for a semiconductor integrated circuit, and more particularly to an automatic layout design method for timing convergence of layout wiring.

  In recent years, in the field of semiconductor integrated circuits, the high-speed operation of devices has progressed, and the valid time of data to be input (hereinafter referred to as Valid width) has become shorter than the clock that is the reference of operation, and SETUP, HOLD, etc. Timing constraints on the clock are becoming stricter. In addition, since there is a demand for designing a large-scale device in a short period of time, cell-based automatic layout design is generally performed.

  In the technical field of automatic layout for designing a high-speed and large-scale device in a short period of time, a method capable of automatically correcting (adjusting) timings such as a wiring capacity load and a signal SETUP time and a HOLD time with respect to a clock has been desired. (For example, refer to Patent Document 1).

  Japanese Unexamined Patent Application Publication No. 2004-86772 discloses a technique related to a semiconductor integrated circuit design support apparatus that supports the design of a semiconductor integrated circuit. In the technique disclosed in Patent Document 1, the slope of the input waveform is automatically corrected by using dummy cells that are distributed in reserve. Referring to the description of Patent Document 1, the semiconductor integrated circuit design support apparatus identifies a driving cell whose slope of the input waveform input to the driven cell is larger than a predetermined value as a violation cell. In addition, the semiconductor integrated circuit design support apparatus has a function of searching for a dummy cell provided for correcting a circuit bug. Then, a logic matching process is performed by a combination of the specified violation cell, a driven cell driven by the violation cell, and a dummy cell, and a dummy cell is added to the violation cell and the driven cell to perform rewiring. ing.

  1A and 1B are flowcharts showing the operation of the semiconductor integrated circuit design support apparatus described in Patent Document 1. FIG. First, normal cells are arranged (step S1). Then, a function repair cell is arranged to suppress the number of correction steps when a circuit bug occurs (step S2). Next, the normal cells arranged in step S1 are wired (step S3). Thereafter, the delay information of each normal cell is extracted (step S4). Then, it is determined whether or not the slope (SLEW) of the input waveform input to the driven cell is larger than a predetermined value (step S5). If the slope (SLEW) of the input waveform input to the driven cell is not greater than the predetermined value (YES in step S5), the process ends. When the slope (SLEW) of the input waveform input to the driven cell is larger than a predetermined value (NO in step S5), driving is performed by a driving cell in which SLEW is larger than the predetermined value and a driving cell in which SLEW is larger than the predetermined value. It is determined whether or not the driven cell is one-to-one (step S6).

  FIG. 2 is a diagram for explaining a method for searching for dummy cells in the semiconductor integrated circuit design apparatus described in Patent Document 1. In FIG. When it is determined that the drive cell and the driven cell whose SLEW is larger than the predetermined value are 1: 1 (YES in step S6), the coordinates of the intermediate point between the drive cell and the driven cell are calculated. (Step S7). In the example shown in FIG. 2, the coordinates of the intermediate point 114 between the driving cell 105 and the driven cell 106 are calculated.

  Then, the functional repair cell 107 is searched from the intermediate point 114 toward the driving cell 105 and the driven cell 106 in the rectangular region 112 having the diagonal line 111 connecting the line connecting the driving cell 105 and the driven cell 106 (step). S8).

  When the functional repair cell 107 does not exist in the rectangular area 112 (NO in step S9), the rectangular area 112 is enlarged by an arbitrary magnification. Then, the function repair cell 110 is searched in the rectangular area 113 arranged so as to surround the rectangular area 112 (step S10).

  When functional repair cell 107 exists in rectangular area 112 (YES in step S9) or when functional repair cell 110 exists in rectangular area 113 (YES in step S11), driving cell 105 and driven cell 106 And a logic matching process by a combination of the function repair cell 107 or the function repair cell 110 searched by the dummy cell searcher (step S12). Then, the functional repair cell 107 or the functional repair cell 110 is added to the driving cell 105 and the driven cell 106 for rewiring (step S13), and the process returns to step S4.

  The technique described in Patent Document 1 aims to improve waveform inclination by using dummy cells when the inclination of the input waveform is large. It has the characteristics of executing cell detection for an input waveform violation, search for dummy cells for circuit bug correction, logic matching processing when using dummy cells, and rewiring using dummy cells. Specifically, in step S6 of the flow of FIG. 1, a cell that is in violation of the input waveform at timing NG is specified, and in step S7, the cell that is violated in FIG. Then, the existence and arrangement position of dummy cells are detected. The dummy cell is used to verify whether or not a logic violation occurs, and if there is no problem, a dummy cell is added between the output and the input to perform rewiring. If there is no dummy cell, the timing repair cell is additionally placed and rewiring is performed.

  In other words, the semiconductor integrated circuit design apparatus according to the technique described in Patent Document 1 specifies a violation cell that specifies a drive cell having a slope (SLEW) of an input waveform input to the first driven cell larger than a predetermined value as a violation cell. A specific process and a dummy cell search process for searching for a first dummy cell provided to correct a circuit bug are executed. In addition, a logic matching process is executed by a combination of the violation cell specified by the violation cell specification process, the first driven cell driven by the violation cell, and the first dummy cell searched by the dummy cell search process. The technique described in Patent Document 1 can reduce the man-hours for timing adjustment by executing a rewiring process for rewiring by adding a first dummy cell to the violating cell and the first driven cell.

Japanese Patent Laid-Open No. 2004-86772

  In the technique described in Patent Document 1, when there is a strict specification constraint regarding the Valid width of a signal line for transmitting input data with respect to a reference clock, when both the SETUP characteristics and the HOLD characteristics are satisfied, the SETUP time And the timing of the HOLD time cannot be finely adjusted. Therefore, there is a problem that both the SETUP constraint and the HOLD constraint cannot be satisfied.

  The reason will be described below. As shown in the flow of FIG. 1 described above, after determining a timing constraint violation in the timing determination step (step S5), a cell (corresponding to a buffer) is inserted in order to improve the slope (SLEW) violation of the input waveform. The process (step S14) to perform is implemented. However, just inserting a cell (equivalent to a buffer) increases the amount of timing adjustment, and induces a SETUP violation even if the HOLD constraint TAH violation can be avoided.

  The operation of the semiconductor integrated circuit design apparatus described in Patent Document 1 will be described using the timing chart of FIG. FIG. 3A is a timing chart showing an operation before inserting a cell (corresponding to a buffer) by the technique described in Patent Document 1. The time when the data A11 becomes an effective value, that is, the time t1 to the time t3 (the time when the change level of the data A11 becomes 1/2) is the Valid width TA1.

At time t4, the clock CLK changes from the initial power supply level (hereinafter referred to as H level) to the ground (GND) level (hereinafter referred to as L level). The SETUP time TA1S of the data A11 is indicated by time t4 to time t1,
SETUP constraint TAS <SETUP time TA1S
And satisfy the operating specifications. On the other hand, the HOLD constraint TA1H of the data A11 is from time t3 to time t4,
HOLD restriction TAH> HOLD time TA1H
Therefore, the operation specification is violated.

  FIG. 3B is a timing chart showing the operation after inserting a cell (corresponding to a buffer) with the technique described in Patent Document 1, and shows the timing of the delayed data A12. In the technique described in Patent Document 1, since the delay time cannot be finely adjusted by a cell (corresponding to a buffer), an excessive delay amount is added. The effective value of the data A12 (the time when the change level of the data A12 becomes 1/2) is delayed from the time t1 to the time t5.

Therefore, when the clock CLK changes from the initial H level to the L level at time t4,
HOLD time TA2H of data A12 is from time t4 to time t7,
HOLD constraint TAH <HOLD time TA2H
Therefore, the operation specifications are satisfied. On the other hand, the SETUP time TA2S of the data A12 is from time t5 to time t4,
SETUP constraint TAS> SETUP time TA2S
Therefore, the operation specification is violated. That is, the technique described in Patent Document 1 cannot adjust the timing to satisfy both the SETUP time and the HOLD time with respect to the clock CLK.

  In order to solve the above problem, the following semiconductor integrated circuit design support method is executed to automatically optimize the layout of the semiconductor integrated circuit. First, after determining the placement and wiring layout of the semiconductor integrated circuit, timing information of data propagating through a predetermined signal line is determined. Based on the timing information, delay information of violation data having a timing violation is extracted. Based on the extracted delay information, a capacity value to be added for eliminating the timing violation is calculated. Further, based on the layout arrangement information of the wiring that propagates the violation data, the power supply capacity cell in the vicinity of the wiring that propagates the violation data is detected. Further, based on the calculated capacitance value, the detected power supply capacity cell is replaced with an adjustment capacity cell having the same layout outline / power supply / GND wiring arrangement position as the power supply capacity cell. Then, rewiring is executed by connecting the replaced gate of the adjustment capacity cell and the wiring that propagates the violation data.

  In order to solve the above-mentioned problem, it is preferable to cause the semiconductor integrated circuit design support apparatus that automatically optimizes the layout of the semiconductor integrated circuit to execute the above method. In this case, the semiconductor integrated circuit design support apparatus includes a wiring processing unit, a storage unit, a wiring determination unit, a change inspection unit, and a change processing unit, thereby performing layout design and timing adjustment of the semiconductor integrated circuit. Do it automatically.

  In executing the above method, the adjustment capacity cell is preferably composed of a rectangular diffusion layer, a gate polysilicon layer stacked on the diffusion layer, and an upper metal wiring. In the center of two opposite sides of the diffusion layer rectangle, a gate polysilicon is arranged with a channel width set in advance so as to include the two sides. Further, one side of the gate polysilicon channel length is connected to a metal wiring terminal by a contact, and both sides of the gate polysilicon on the diffusion layer are connected to a GND wiring metal wiring by a contact. Then, the metal wiring of the power supply potential is arranged with a preset width on the upper side with respect to the channel length direction of the arranged gate policy, and the metal wiring with the GND potential is arranged on the lower side with a preset width.

  In carrying out the above method, the adjustment capacitor cell is preferably configured such that the other end connected to the metal wiring terminal of the gate polysilicon is formed on the diffusion layer so that the channel length is reduced.

  If the effect obtained by the representative one of the inventions disclosed in the present application is briefly described, there is an effect that it is possible to adjust the timing to satisfy both the SETUP time and the HOLD time.

FIG. 1A is a flowchart showing the operation of a conventional semiconductor integrated circuit design apparatus. FIG. 1B is a flowchart showing the operation of the conventional semiconductor integrated circuit design apparatus. FIG. 2 is a diagram for explaining a method for searching for dummy cells in a conventional semiconductor integrated circuit support design apparatus. FIG. 3 is a timing chart showing the operation of the conventional semiconductor integrated circuit design apparatus. FIG. 4 is a block diagram illustrating the configuration of the automatic layout design support system 1 for a semiconductor integrated circuit device according to the present invention. FIG. 5 is a block diagram conceptually illustrating the configuration of the automatic layout design support system 1. FIG. 6A is a plan view illustrating the layout of the power supply capacitor cell Ca. FIG. 6B is a plan view illustrating the layout of the adjustment capacitor cell Cb. FIG. 7 is a table illustrating the correspondence of the gate capacitance values to the gate lengths GX, GY, and GZ of the adjustment capacitance cell Cb. FIG. 8 is a flowchart illustrating the operation of the automatic layout design support system 1 of this embodiment. FIG. 9 is a layout diagram illustrating the result of arranging a plurality of power supply capacity cells Ca. FIG. 10 is a layout diagram illustrating the result of performing the wiring process. FIG. 11 is a timing chart illustrating the operation of the circuit to be designed at the stage where the processing in the wiring processing unit F1 is completed. FIG. 12 is a violation signal detection result table illustrating the configuration of the violation signal detection result. FIG. 13 is a table illustrating the configuration of the delay time calculation table. FIG. 14 is a table illustrating the configuration of the generated additional capacity calculation result table. FIG. 15 is a plan view illustrating a state where the cell search range 34 is set in the circuit to be designed. FIG. 16 is a plan view illustrating a state in which the search range is automatically enlarged. FIG. 17 is a plan view illustrating the result of replacing the power supply capacitor cell Ca with the adjustment capacitor cell Cb. FIG. 18 is a timing chart illustrating an example of the operation of the circuit to be designed when the power supply capacitor cell Ca is replaced with the adjustment capacitor cell Cb. FIG. 19 is a circuit diagram showing a circuit in which the delay is adjusted using the conventional technique. FIG. 20 is a circuit diagram illustrating a circuit whose delay is adjusted by the automatic layout design support system 1 of the present embodiment. FIG. 21 is a table showing the delay time according to the number of connections of the logic cell BUFFERi and the delay time according to the number of connections of the adjustment capacity cell Cbi (i = 1, 2,...). FIG. 22 is a graph showing changes in the delay value with respect to the number of connections of the logic cell BUFFERi (i = 1, 2,...) And the adjustment capacitor cell Cbi (i = 1, 2,...). FIG. 23 is a flowchart illustrating the operation of the second embodiment of the automatic layout design support system 1 of the present invention. FIG. 24 is a plan view illustrating a chip layout at a stage where the processing of the wiring processing unit F1 of the second embodiment is executed. FIG. 25 is a timing chart illustrating the operation of the semiconductor chip CP when the processing of the wiring processing unit F1 is completed. FIG. 26 is a plan view illustrating the configuration of the semiconductor chip CP in which the searched power source capacity cell Cai (i = 1, 2,...) Is replaced with the adjustment capacity cell Cbi (i = 1, 2,...). FIG. 27 is a timing chart illustrating the operation of the semiconductor chip CP after the replacement process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

[First Embodiment]
FIG. 4 is a block diagram illustrating the configuration of an automatic layout design support system 1 for a semiconductor integrated circuit device for carrying out the present invention. The automatic layout design support system 1 includes a computer device 2, a server 3, a recording medium 4, and a network 5.

  The computer apparatus 2 is an information processing apparatus such as an engineering workstation. The server 3 is a computer device that holds an execution program (application) executed by the computer device 2. The server 3 provides the execution program in response to a request from the computer apparatus 2 (client). The server 3 is connected to the computer device 2 via a network 5 such as the Internet.

  An execution program provided to the computer apparatus 2 is stored in the recording medium 4 provided in the server 3. The execution program stored in the recording medium 4 is downloaded to the computer apparatus 2 via the network 5. The downloaded program is stored in a storage medium (for example, a hard disk or a memory) provided in the computer apparatus 2. The computer device 2 performs processing based on the procedure indicated in the program.

  FIG. 5 is a block diagram conceptually illustrating the configuration of the automatic layout design support system 1 of this embodiment. As shown in FIG. 5, the automatic layout design support system 1 includes a wiring processing unit F1, a storage unit F2, a wiring determination unit F3, a change inspection unit F4, and a change processing unit F5. The automatic layout design support system 1 is configured as a layout design support device for a semiconductor integrated circuit as illustrated in FIG. 5 and provides a function of automatically performing timing adjustment.

  As shown in FIG. 5, the wiring processing unit F <b> 1 includes a logic cell placement unit 11, a dummy cell placement unit 12, a power source capacitor cell placement unit 13, and a wiring unit 14. The storage unit F2 reads and writes the circuit netlist D1, the logic cell delay library D2, the cell layout library D3, the timing constraint D4, the timing determination result D51, and the additional capacity calculation result D52. Hold in a possible state.

  The change processing unit F5 has a function of changing the layout of the capacity cell. 6A and 6B are plan views illustrating the layout of the capacity cell to be changed. FIG. 6A is a plan view illustrating the layout of the power supply capacitor cell Ca. FIG. 6B is a plan view illustrating the layout of the adjustment capacitor cell Cb. In the present embodiment, the change processing unit F5 includes data indicating the power supply capacity cell Ca and the adjustment capacity cell Cb. Further, the change processing unit F5 can replace both cells having the same cell size based on the processing result of the automatic layout design support system 1.

  As shown in FIG. 6A, the power source capacitor cell Ca includes a diffusion layer 21, a gate G1 stacked on the diffusion layer 21, and a metal wiring for supplying a voltage to the diffusion layer 21 and the gate G1 ( Power supply VDD, ground GND). The metal wiring is stacked above the layer including the diffusion layer 21 and the gate G1 in the stacking direction of the semiconductor manufacturing process. The gate G1 is connected to the metal wiring through the wiring 23.

  The diffusion layers 21 on both sides of the gate G1 are source / drain regions, and are connected to a metal wiring (ground GND) via a plurality of contacts CN1. The gate G1 is connected to a metal wiring (power supply VDD) via two contacts CN1. Here, the gate width G1 and the channel length of the gate G1 of the power supply capacity cell Ca are set to be large in order to ensure the capacity value with respect to the normally used gate.

  As shown in FIG. 6B, the gate G2 of the adjustment capacitor cell Cb has a different shape from the gate G1 provided in the power supply capacitor cell Ca. Further, the adjustment capacitor cell Cb is configured without the wiring 23 provided in the power supply capacitor cell Ca. Furthermore, the gate length of the gate G2 of the adjustment capacitor cell Cb can be changed to the length indicated by the gate lengths GX, GY, and GZ. The diffusion layer 22 below the gate G2 is connected to the metal wiring (ground GND) via four contacts CN2 on each side (eight on each side). That is, the power supply capacitor cell Ca and the adjustment capacitor cell Cb are configured with the same size outer shape, and the metal wiring (power supply VDD, ground GND) is configured at the same position.

  FIG. 7 is a table illustrating the correspondence of the gate capacitance values to the gate lengths GX, GY, and GZ of the adjustment capacitance cell Cb. For example, as shown in FIG. 7, when the gate G2 of the adjustment capacitor cell Cb has a gate length GX (μm), the capacitance value of the adjustment capacitor cell can be set to 5 PF. When the gate length is GY (μm), the capacity value of the adjustment capacity cell can be set to 10 PF. In the case of the gate length GZ (μm), the capacity value of the adjustment capacity cell can be set to 20 PF. Note that the gate capacitance value corresponding to the gate lengths GX, GY, and GZ can be arbitrarily set. Further, the change processing unit F5 includes data regarding a plurality of adjustment capacity cells Cbi (i = 1, 2,...) Having gate lengths GX, GY, and GZ. Therefore, in the following description of the embodiment, when a plurality of adjustment capacity cells Cbi are distinguished, they are described with branch numbers.

  The operation of the automatic layout design support system 1 of this embodiment will be described below. FIG. 8 is a flowchart illustrating the operation of the automatic layout design support system 1 of this embodiment. In step Sa1, as the processing of the logic cell placement unit 11, the wiring processing unit F1 performs a netlist D1 of a circuit describing information on the logic cell to be used and wiring connection, and a logic cell delay describing information on the timing of the logic cell. Arrangement of logic cells by automatic layout by inputting a library D2, a cell layout library D3 describing information on layout figures of logic cells, and a timing constraint D4 describing timing information of circuits to be satisfied after layout. Perform the process.

  Next, in step Sa2, dummy cell placement which is a spare element composed of a transistor used for correcting a logic defect is performed as processing of the dummy cell placement unit 12. Next, in step Sa3, as the processing of the power supply capacitor cell placement unit 13, the placement of the power supply capacitor cell Ca composed of a capacitive element is performed for power stabilization.

  FIG. 9 is a layout diagram illustrating a result of arranging a plurality of power supply capacity cells Ca, and shows a layout before timing adjustment. At the stage where the processing of step Sa3 is completed, a predetermined cell is arranged for each cell column (SC1, SC2, SC3, SC4). For example, as shown in FIG. 9, a logic cell 31 that operates based on the clock CLK is arranged in the cell column SC1. Further, the power supply capacity cell Ca1 and the power supply capacity cell Ca3 are arranged in the cell column SC2. In addition, a power supply capacity cell Ca2 is arranged in the cell column SC3. In the cell column SC4, a logic cell 32 that operates based on the clock CLK is arranged.

  Returning to FIG. 8, in step Sa4, wiring processing is temporarily performed on each logic cell arranged by performing the processing of step Sa1 and the processing of step Sa2 as the processing of the wiring unit. FIG. 10 is a layout diagram illustrating the result of performing the wiring process. Referring to FIG. 10, the logic cell 31 is connected to a wiring 33 for transmitting data A1 through a via VIA1. Similarly, the logic cell 32 is connected to the wiring 33 through the via VIA2. When these connections are completed, the processing of the wiring processing unit F1 ends.

  Next, processing in the wiring determination unit F3 will be described. Returning to FIG. 8, in step Sa5, the first determination process is executed. At this time, on the assumption that the SETUP constraint TAS of data A1 (or data A2 to be described later) on the wiring 33 is satisfied with respect to the clock CLK, it is determined whether there is a violation of the HOLD constraint TAH.

  FIG. 11 is a timing chart illustrating the operation of the circuit to be designed at the stage where the processing in the wiring processing unit F1 is completed. Until time t0, the clock CLK is at the power supply voltage level (referred to as H level), and at this time, the data value of the data A1 of the wiring 33 is indefinite.

At time t1, the expected value of data A1 is reached, and the amplitude level of data A1 is determined from 1/2 to H level or ground level (hereinafter referred to as L level). At time t4, the clock CLK changes from H level to L level, and the SETUP time TA1S of the data A1 is determined as time t4 to time t1. That means
SETUP time TA1S> SETUP constraint TAS
There will be no violation. On the other hand, the HOLD time TA1H is from time t4 to time t5,
HOLD time TA1H> HOLD constraint TAH
It is determined as a violation. If it is determined in step Sa5 that is the first determination process that there is a violation of the HOLD constraint TAH, the process proceeds to step Sa6. If there is no HOLD constraint TAH violation, the process is terminated.

  If it is determined in step Sa5 that is the first determination process that there is a violation of the HOLD constraint TAH, the violation signal detection result is stored in the timing determination result D51. FIG. 12 is a violation signal detection result table illustrating the configuration of the violation signal detection result. The violation signal detection result table holds data in which violation signal lines and violation times are associated with each other in a table format. As shown in FIG. 12, when the violation signal line is the wiring of the data A1 and the violation time is −0.02 ps, the data associated with them is described as the violation signal detection result.

  Returning to FIG. 8, in step Sa6, the second determination process is executed. In the second determination process, it is determined whether delay adjustment is possible without violating the SETUP constraint even if a logic cell is inserted. At this time, the valid width TA1 (time t1 to time t5) of the data obtained in step Sa5 is compared with the delay amount by the logic cell obtained from the logic cell delay library D2 used in the automatic layout, and the SETUP constraint is violated. It is determined whether or not delay adjustment is possible.

  If it is determined that the SETUP constraint TAS and the HOLD constraint TAH cannot be satisfied by the logic cell insertion, the process proceeds to step Sa7. In step Sa7, the additional capacity calculation unit generates an additional capacity calculation result table based on the delay time calculation table prepared in advance and the violation signal detection result table obtained in step Sa5.

  FIG. 13 is a table illustrating the configuration of the delay time calculation table. The delay time calculation table holds data in which violation time, additional capacity, delay time, and cell name are associated with each other. FIG. 14 is a table illustrating the configuration of the generated additional capacity calculation result table. The additional capacity calculation result table holds data in which the violation signal line, the violation time, and the additional capacity are associated with each other.

  Returning to FIG. 8, when it is determined in step Sa6 that the Valid width TA1 is larger than the delay of the logic cell and the logic cell can be inserted (Yes in step Sa6), the process proceeds to step Sa13. In step Sa13, logic cell insertion is performed, and timing delay adjustment by normal logic cell addition is performed by automatic layout.

  Next, in step Sa8, the signal line path that violates the HOLD constraint TAH is traced. Based on the traced path, a cell search range is set, and whether or not the power supply capacity cell exists in the search range is searched based on the cell name of the power supply capacity cell Ca.

  FIG. 15 is a plan view illustrating a state where the cell search range 34 is set in the circuit to be designed. Referring to FIG. 15, the wiring 33 connects the logic cell 31 (VIA1) and the logic cell 32 (VIA2). When it is determined that the HOLD restriction TAH is violated in the data A1 transmitted through the wiring 33, the cell search range 34 is set from the path of the wiring 33 that transmits the data A1 that violates the HOLD restriction. Then, the power supply capacity cell Ca1 and the power supply capacity cell Ca2 arranged in the cell search range 34 are searched.

  Next, in step Sa9, a third determination process is executed. In the third determination process, it is determined whether or not a power source capacity cell exists in the cell search range 34 based on the search result in step Sa8. If there is no power supply capacity cell in the cell search range 34 (when there is no power supply capacity cell Ca1 or power supply capacity cell Ca2), the process proceeds to step Sa10. In step Sa10, the cell search range expansion unit automatically expands the search range to an area where the logic cell 31 and the logic cell 32 can be arranged.

  FIG. 16 is a plan view illustrating a state in which the search range is automatically enlarged. The cell search range 34 obtained by tracing the signal line path illustrated in FIG. 15 is an area where the logic cell 31 and the logic cell 32 such as the cell search range 35 can be arranged as shown in FIG. The search range is automatically expanded. After the cell search range 35 is set, the process returns to step Sa8, and the cell search unit searches for the power source capacity cell Ca3 arranged in the cell search range 35.

  If it is determined in step Sa9 that the connectable power supply capacity cell Ca exists as a result of executing the third determination process (Yes in step Sa9), the process proceeds to step Sa11.

  In step Sa11, the fourth determination process is executed. In the fourth determination process, the additional capacity calculation unit determines whether the capacity value of the additional capacity calculated in step Sa7 is equal to or greater than the capacity value of the power supply capacity cell prepared in the logic cell delay library. As a result of the determination, if it is not equal or greater, the process proceeds to step Sa10, and the process of expanding the cell search range is executed again. Then, after expanding the cell search range again, the process returns to step Sa8, and the automatic layout flow is repeated until the load capacity becomes equal or greater.

  When the capacity value of the power supply capacity cell Ca becomes equal to or greater than the capacity value calculated in step Sa7 of the additional capacity calculation unit (Yes in step Sa11 of the fourth determination process), the process proceeds to step Sa12. In step Sa12, the cell changing unit replaces the power supply capacity cell Ca with the adjusted capacity cell Cb so as to correspond to the additional capacity stored in the additional capacity calculation result D52.

  The power source capacity cell Ca and the adjustment capacity cell Cb have the same outer shape and size, and the metal wiring (power source VDD, ground GND) is also arranged in the same manner, so that the surrounding logic cells and signal lines are not affected. Can be replaced. Further, by changing the size of the gate G2 to GX, GY, GZ, it is possible to prepare a plurality of adjustment capacity cells (Cb1, Cb2, etc.) having different capacitance values, and to adjust the delay amount to be adjusted. The combined timing adjustment can be made more finely.

  After the replacement of the power supply capacity cell Ca and the adjustment capacity cell Cb is completed in step Sa12, the process proceeds to step Sa14. In step Sa14, rewiring of the signal line, which is a violation of the HOLD timing, is performed by rewiring processing using information on the adjustment capacitor cell connected to the signal line.

  After performing the rewiring, the process returns to Step Sa5 of the first determination process again to determine whether there is a HOLD violation (Yes in Step Sa5), and the timing adjustment by a series of automatic layout is completed.

  FIG. 17 is a plan view illustrating the result of replacing the power supply capacitor cell Ca with the adjustment capacitor cell Cb. As shown in FIG. 17, the adjustment capacitor cell Cb1 of the cell column SC2 is connected to the wiring 36 of the data A2 via the via VIA3. This layout adds the expected additional capacity.

FIG. 18 is a timing chart illustrating an example of the operation of the circuit to be designed when the power supply capacitor cell Ca is replaced with the adjustment capacitor cell Cb. As shown in the timing chart of FIG. 18, a delay occurs in the data A2, so that at the time t2, the expected value of the data A2 is reached, and the amplitude level of the data A2 is determined from 1/2 to H level or L level. To do. At time t4, the clock CLK changes from the H level to the L level, and the SETUP time TA2S of the data A2 is determined as time t4 to time t2. That means
SETUP time TA2S> SETUP constraint TAS
There will be no violation. On the other hand, the HOLD time TA2H is from time t4 to time t7,
HOLD time TA1H <HOLD constraint TAH
Next. There is no violation.

[Comparative example]
As described above, the automatic layout design support system 1 of this embodiment can automatically finely adjust the timing of the SETUP time and the HOLD time. For this reason, if there are restrictions on the operation specifications for both the data SETUP characteristics and the HOLD characteristics with respect to the clock that is the reference for the operation, the SETUP restrictions and the HOLD of the device that operates at high speed without changing or inserting the logic cell. Both constraints can be satisfied. In the following, in order to facilitate understanding of the effects of the present invention, the fine adjustment of the timing of the data A1 violating the HOLD constraint TAH in the present invention will be described in comparison with the prior art.

  FIG. 19 is a circuit diagram illustrating a delay-adjusted circuit exemplified as a comparative example. As shown in FIG. 19, the delay adjustment of the data A1 input to the flip-flop FFa of the circuit is performed using the logic cell BUFFER1 and the logic cell BUFFER2. It is assumed that the logic cells BUFFER 1 and BUFFER 2 have the same delay.

  FIG. 20 is a circuit diagram illustrating a circuit whose delay is adjusted by the automatic layout design support system 1 of the present embodiment. As shown in FIG. 20, the delay adjustment of the data A1 input to the flip-flop FFa of the circuit is performed using the adjustment capacitor cell Cb1 and the adjustment capacitor cell Cb2. The adjustment capacity cell Cb1 and the adjustment capacity cell Cb2 are capacity cells having the same delay.

  FIG. 21 shows the delay time according to the number of connections when one or more logic cells BUFFERi (i = 1, 2,...) Are connected, and the adjustment capacity cell Cbi (i = 1, 2,...) Of this embodiment. This is a table showing the delay time according to the number of connections when one or more are connected. One logic cell BUFFERi (i = 1, 2,...) Has a delay value of 200 ps by two and 400 ps by two. Further, one adjustment capacity cell Cbi (i = 1, 2,...) Has a delay value of 20 ps for two and 40 ps for two.

  FIG. 22 is a graph showing a change in delay value with respect to the number of connections between the logic cell BUFFERi (i = 1, 2,...) And the adjustment capacitor cell Cbi (i = 1, 2,...) In FIG. As shown in FIG. 22, the adjustment capacity cell Cbi (i = i = 10) of the present embodiment is compared with the case where the delay adjustment is performed by inserting the logic cell BUFFERi (i = 1, 2,. In the case of adjusting the delay by adding 1, 2,..., The inclination is suppressed. This difference in the slope of the graph indicates that the automatic layout design support system 1 of this embodiment can adjust the delay time more finely than the case illustrated as a comparative example.

[Second Embodiment]
The second embodiment of the present invention will be described below. The automatic layout design support system 1 of the second embodiment described below has a function for performing timing adjustment of a plurality of data buses in the automatic layout design. FIG. 23 is a flowchart illustrating the operation of the second embodiment of the automatic layout design support system 1 of the present invention.

  In step Sb61, the wiring determination unit F32 of the second embodiment executes a fifth determination process to determine whether the laid wiring is a data bus. As a result of the determination, if the wiring is a data bus, the process proceeds to step Sb62. In step Sb62, it is determined whether or not the WINDOW width obtained by superimposing the valid widths of a plurality of data buses satisfies the SETUP constraint, the HOLD constraint, and the Valid width constraint. The wiring determination unit F32 generates determination result data in which a violation signal name, that is, a data bus name requiring correction (adjustment) and a violation time are associated, and stores the determination result data in the timing determination result D51. Thereafter, the change inspection unit F42 and the change processing unit F5 execute the automatic layout process in the same manner as in the first embodiment, based on the data bus name and the violation time of the timing determination result D51.

  FIG. 24 is a plan view illustrating a chip layout at a stage where the processing of the wiring processing unit F1 is executed in the automatic layout design support system 1 of the second embodiment. By performing the processing of the wiring processing unit F1, the memory macro MC, the flip-flop FF1, the flip-flop FF2, and the flip-flop FF3 are arranged in the semiconductor chip CP. A data bus BU1 is provided between the memory macro MC and the flip-flop FF1. Similarly, a data bus BU2 is provided between the memory macro MC and the flip-flop FF2, and a data bus BU3 is provided between the memory macro MC and the flip-flop FF3. A power capacity cell Ca10 is disposed on the data bus BU1, and a power capacity cell Ca13 is disposed on the data bus BU3. Note that the flip-flops FF1, FF2, and FF3 operate based on the clock CLK.

  FIG. 25 is a timing chart illustrating the operation of the semiconductor chip CP when the processing of the wiring processing unit F1 is completed. The Valid width TB1 indicates a time until the amplitude of the input data of the data bus BU1 becomes 1/2. The Valid width TB2 indicates the time until the amplitude of the input data of the data bus BU2 becomes 1/2. The Valid width TB3 indicates the time until the amplitude of the input data of the data bus BU3 becomes 1/2.

  As shown in FIG. 25, the Valid width TB1 of the data bus BU1 is the time from time t1 to time t6. The valid width TB2 of the data bus BU2 is the time from time t3 to time t10. The valid width TB3 of the data bus BU3 is the time from time t0 to time t5. The WINDOW width TWa of the data bus in which the data bus BU1, the data bus BU2, and the data bus BU3 are overlapped is from time t3 to time t5.

Referring to FIG. 25, the WINDOW width TWa of the data bus in which the Valid width TB1, the Valid width TB2, and the Valid width TB3 are overlapped is insufficient with respect to the Valid width constraint TB (time t4 to time t6) with respect to the clock CLK. It is shown that the constraints are not satisfied. The relationship with the Valid width constraint TB is
WINDOW width TWa <Valid width constraint TB
It has become.

  At this time, the valid width TB2 of the data bus BU2 satisfies the SETUP constraint TAS, the HOLD constraint TAH, and the Valid width constraint TB. Therefore, the change inspection unit F42 performs a timing correction (adjustment) process so as to approach the timing of the data bus BU2.

  Then, the change inspection unit F42 traces the data bus BU1 and the data bus BU3 in FIG. 24 to set a search range, and searches for the power source capacity cell Cai (i = 1, 2,...). The searched power source capacity cell Cai (i = 1, 2,...) Is adjusted in the timing according to the delay of the power source capacity cell Ci (i = 1, 2,...) As in the first embodiment. Is replaced.

  FIG. 26 is a plan view illustrating the configuration of the semiconductor chip CP in which the searched power source capacity cell Cai (i = 1, 2,...) Is replaced with the adjustment capacity cell Cbi (i = 1, 2,...). As shown in FIG. 26, the data bus BU1b is connected to the adjustment capacity cell Cb20, and the data bus BU3b is connected to the adjustment capacity cell Cb21. FIG. 27 is a timing chart illustrating the operation of the semiconductor chip CP after the replacement process. As shown in FIG. 27, the valid width TB1b of the data bus BU1b is from time t2 to time t9, and the valid width TB3b of the data bus BU3b is from time t1 to time t7, so that the HOLD constraint TAH has a margin. Become. Accordingly, the WINDOW width TWb obtained by superimposing the Valid widths TB1b, TB2, and TB3b of the plurality of data buses also satisfies the Valid width constraint TB.

  As described above, in the second embodiment, the wiring determination unit F32 of the automatic layout design support system 1 determines whether the wiring is a data bus. If the wiring is a data bus, the WINDOW width TWa obtained by overlapping the valid widths TB1, TB2, and TB3 of the plurality of data buses is specified. When the WINDOW width TWa is smaller than the Valid width constraint TB, the timing correction (fine adjustment) is performed by automatically replacing the adjusted capacity cell having the same size as the power supply capacity cell that is already arranged in the timing violation data bus. ) Is running. With such a configuration and operation, it becomes possible to secure a timing margin for the SETUP constraint TAS and HOLD constraint TAH of multiple data buses and the Valid width constraint TB, and further suppress re-design repetition due to countermeasures against timing violations. Can do.

  The embodiment of the present invention has been specifically described above. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 1 ... Automatic layout design support system 2 ... Computer apparatus 3 ... Server 4 ... Recording medium 5 ... Network 11 ... Logic cell arrangement part 12 ... Dummy cell arrangement part 13 ... Power supply capacity cell arrangement part 14 ... Wiring part 21 ... Diffusion layer 22 ... Diffusion Layer 23 ... wiring 31 ... logic cell 32 ... logic cell 33 ... wiring A1 ... data A2 ... data A11 ... data A12 ... data F1 ... wiring processing section F2 ... storage section F3 ... wiring determination section F4 ... change inspection section F5 ... change processing Portion F32 ... Wiring determination portion F42 ... Change inspection portion D1 ... Netlist D2 ... Logic cell delay library D3 ... Cell layout library D4 ... Timing constraint D51 ... Timing determination result D52 ... Additional capacity calculation result CP ... Semiconductor chip VDD ... Power supply G1 ... Gate G2 ... Gate CN1 ... Contact CN2 ... Contact GX ... Gate length GY ... Gate Long GZ ... Gate length GND ... Ground CP ... Semiconductor chip MC ... Memory macro Ca ... Power supply capacity cell Ca1 ... Power supply capacity cell Ca2 ... Power supply capacity cell Ca3 ... Power supply capacity cell Cb ... Adjustment capacity cell Cb1 ... Adjustment capacity cell Cb2 ... Adjustment capacity Cell Cbi ... Adjusted capacity cell Ca10 ... Power supply capacity cell Ca11 ... Power supply capacity cell Cb20 ... Adjusted capacity cell Cb21 ... Adjusted capacity cell BU1 ... Data bus BU2 ... Data bus BU3 ... Data bus BU1b ... Data bus BU2b ... Data bus TB1 ... Valid width TB2 ... Valid width TB3 ... Valid width TWa ... WINDOW width TWb ... WINDOW width TB ... Valid width constraint TA ... Valid width TA1S ... SETUP time TA2S ... SETUP time TA1H ... HOLD time TA2H ... HOLD time TAH ... HOLD constraint TAS SETUP constraint BUFFER1 ... logic cell BUFFER2 ... logic cell BUFFERi ... logic cell FF1 ... flip-flop FF2 ... flip-flop FF3 ... flip-flop FFA ... flip-flop VIA1 ... via VIA2 ... via VIA3 ... via SA1 ... cell search range SA1 ... cell column SC2 ... cell column SC3 ... cell column SC4 ... cell column CLK ... clock 105 ... driving cell 106 ... driven cell 107 ... repair cell 110 ... repair cell 111 ... diagonal 112 ... rectangular region 113 ... rectangular region 114 ... intermediate point

Claims (5)

A semiconductor integrated circuit design support method for automatically optimizing a layout of a semiconductor integrated circuit, the step of determining timing information of data propagated through a predetermined signal line after determining a layout wiring layout of the semiconductor integrated circuit When,
Extracting delay information of violation data having a timing violation based on the timing information;
Calculating a capacity value to be added for resolving the timing violation based on the extracted delay information;
Detecting power supply capacity cells in the vicinity of the wiring that propagates the violation data based on the layout arrangement information of the wiring that propagates the violation data;
Replacing the detected power supply capacity cell with an adjustment capacity cell having the same layout outline / power supply / GND wiring arrangement position as the power supply capacity cell based on the calculated capacity value;
A rewiring step for connecting the gate of the replaced capacity cell for adjustment and the wiring for propagating the violation data;
A semiconductor integrated circuit design support method comprising: The semiconductor integrated circuit design support method according to claim 1,
The step of detecting the power capacity cell further comprises:
A method for supporting the design of a semiconductor integrated circuit, comprising the step of expanding an inspection range based on arrangement information of wirings that propagate the violation data when the power source capacity cell cannot be detected. The semiconductor integrated circuit design support method according to claim 1, further comprising:
A method for supporting design of a semiconductor integrated circuit, comprising: after the step of extracting delay information of the violation data, determining whether a delay value extracted by the delay information is equal to or less than a value that cannot be adjusted by a logic cell. In the semiconductor integrated circuit design support method according to any one of claims 1 to 3,
Before the step of extracting delay information of the violation data,
Determining whether the wired signal line is a data bus; and
And a step of calculating a delay value necessary for the data bus based on a valid width of the data bus. In the semiconductor integrated circuit design support method according to any one of claims 1 to 4,
The violation data delay information is
A semiconductor integrated circuit design support method, which is information based on a Valid width of a data line having a HOLD timing violation.

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