JP2013101457A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can automatically set a more appropriate operation mode and operation frequency in accordance with an external power source voltage.SOLUTION: The semiconductor device in accordance with an embodiment comprises: a processor; a nonvolatile memory that can be accessed by the processor; and a voltage detection unit that detects the external power source voltage for driving at least the processor and the nonvolatile memory. The processor sets the operation mode and/or the operation frequency of at least one of the processor and the nonvolatile memory in accordance with a voltage detected by the voltage detection unit, by executing an instruction group.

Description

  The present invention relates to a semiconductor device including a processor and a nonvolatile memory.

  Conventionally, a microcomputer in which a processor and a nonvolatile memory are mounted on the same substrate has been used for various purposes. The type of external power supply supplied to such a microcomputer may be restricted depending on the device configuration and application of the mounting destination.

  A flash memory included in a microcomputer disclosed in Japanese Patent Application Laid-Open No. 07-029386 (Patent Document 1) is a high voltage generation circuit that generates a voltage having a level higher than a normal operation voltage used during a write or erase operation. A first power supply terminal for supplying a normal operation voltage from the outside, and a second power supply for supplying a voltage at a level higher than the normal operation voltage used during the write or erase operation from the outside Terminal. Then, either the high level voltage supplied to the second power supply terminal or the high voltage generated by the high voltage generation circuit is selected and supplied to the nonvolatile memory element. By switching between the boosted voltage and the external high voltage so as to erase and write data, there is an effect that it is not necessary to incorporate batteries with different voltages in the portable device.

Japanese Patent Application Laid-Open No. 07-029386

  As described above, the microcomputer as described above is assumed to be used for various purposes, and there is a need to improve the versatility of the external power supply. In other words, the type (voltage) of the external power supply provided to the microcomputer is limited by the device configuration and application of the mounting destination, so the voltage range that can be operated is expanded so that it is not subject to restrictions on the external power supply. Efforts to do so are underway.

  On the other hand, in order to make maximum use of the performance of the processor and the nonvolatile memory, it is preferable to automatically set a more suitable operation mode and operation frequency according to the voltage of the external power supply. However, there is no configuration having such a function.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device capable of automatically setting a more appropriate operation mode and operation frequency in accordance with the voltage of the external power supply. Is to provide.

  A semiconductor device according to an embodiment includes a processor, a nonvolatile memory that can be accessed by the processor, and a voltage detection unit that detects at least a voltage of an external power source for driving the processor and the nonvolatile memory. The processor sets an operation mode and / or an operation frequency for at least one of the processor and the nonvolatile memory in accordance with the voltage detected by the voltage detection unit by executing the instruction group.

  According to an embodiment, a more appropriate operation mode and operation frequency can be automatically set according to the voltage of the external power supply.

It is a schematic diagram which shows the structure of the microcomputer according to embodiment of this invention. It is a schematic diagram which shows the structure of the voltage detection part contained in the microcomputer according to embodiment of this invention. It is a figure which shows an example of the circuit structure which generates the clock signal in the microcomputer according to embodiment of this invention. It is a flowchart which shows the procedure of the setting process in the microcomputer according to embodiment of this invention, and access to flash memory. 5 is a flowchart showing a processing procedure in voltage detection processing of the external power source shown in FIG. 5 is a flowchart showing a processing procedure in voltage detection processing of the external power source shown in FIG. It is a flowchart which shows the modification of the procedure of the setting process in the microcomputer according to embodiment of this invention, and the access to flash memory.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that the same or corresponding parts in the drawings are denoted by the same reference numerals and description thereof will not be repeated.

<A. Overview>
The boot loader (instruction group) built in the microcomputer rewrites (accesses) the flash memory in the microcomputer according to the voltage of the external power supply supplied to the microcomputer. It is preferable to optimize the operation mode and the operation frequency. Further, in order to shorten the time required for rewriting data in the flash memory, it is necessary to set the operating frequency and the operating mode more suitably.

  When performing such setting, it is necessary to know the voltage of the external power source supplied to the microcomputer.

  As a conventional method, the user inputs the target voltage using the flash memory rewriting front-end software executed on the personal computer, and transmits the information to the microcomputer. The mode and operating frequency were set.

  However, in such a method, even if the user inputs incorrect voltage information (target voltage) with the flash memory rewriting front-end software executed on the personal computer, the microcomputer detects the error. Therefore, there is a possibility that the flash memory is rewritten outside the predetermined operating range of the microcomputer.

  Further, in a system in which voltage information (target voltage) is not notified to the microcomputer in advance, it is common to operate with a lower operating frequency of the CPU or flash memory in order to ensure the operation. There was a problem that the memory rewrite time was long.

  Therefore, in this embodiment, the voltage of the external power supply supplied to the microcomputer is detected, and more preferable operation modes and operation frequencies of the CPU and the flash memory are set according to the detected voltage.

  Specifically, the microcomputer according to the present embodiment includes a nonvolatile memory (flash memory) that can rewrite information (data) to be processed by a CPU (Central Processing Unit) that is a processor by electrical erasing / writing. Have The microcomputer includes a voltage detection unit that detects the voltage of an external power source supplied to the microcomputer and software (boot loader) that rewrites the flash memory.

  As an example, the voltage detection unit generates a plurality of types of voltages obtained by dividing the external power supply applied to the VCC terminal (power supply terminal) at different voltage division ratios, and selects a voltage level to be detected using a register. The selected voltage level is output from the selector. The output voltage and the reference voltage are compared by a comparator, and the comparison result is stored in a register. From this comparison result, the voltage of the external power supply supplied to the microcomputer can be determined, and the operation mode and the operation frequency of the CPU and the flash memory can be more suitably set by the boot loader according to the voltage of the external power supply.

<B. Overall configuration>
FIG. 1 is a schematic diagram showing a configuration of a microcomputer 1 according to the embodiment of the present invention. Referring to FIG. 1, microcomputer 1 includes a CPU 102, a boot ROM (Read Only Memory) 104, a flash memory 106, a clock generation circuit 108, and a voltage detection unit 110. These units are connected to each other via an internal bus 100 so that data communication is possible.

  The CPU 102 is a typical example of a processor, and controls each unit included in the microcomputer 1 by sequentially executing instructions in a predetermined order.

  The boot ROM 104 is a storage unit that stores a group of instructions for executing various processes when the microcomputer 1 is activated. That is, the boot ROM 104 functions as a boot loader. Specifically, when the microcomputer 1 is started, the CPU 102 loads and executes a group of instructions stored in the boot ROM 104 in a predetermined order, and is detected by the voltage detection unit 110 as described later. In accordance with the voltage, the operation mode and / or the operation frequency of the CPU 102 and the flash memory 106 are set to values according to the operation environment. The instruction group stored in the boot ROM 104 can include a program for executing various initialization processes in addition to the program for setting the operation mode and / or the operation frequency.

  The flash memory 106 is a typical example of a nonvolatile memory that can be accessed by the CPU 102 that is a processor, and stores data written by the CPU 102 in a nonvolatile manner. The flash memory 106 stores (programs) and erases (erases) data by applying a voltage to the memory cell. In this embodiment, as the flash memory 106, an arbitrary structure (NAND type or NOR type) and an arbitrary cell type (SLC (Single Level Cell) or MLC (Multi Level Cell)) can be adopted. . Further, the present invention is not limited to a flash memory, and a nonvolatile memory such as an MRAM (Magnetic Random Access Memory) or FeRAM (Ferroelectric Random Access Memory) may be adopted.

  The clock generation circuit 108 generates a clock signal for determining data transmission and processing timing of the CPU 102 and the flash memory 106 and the internal bus 100. As will be described later, the clock generation circuit 108 generates a clock signal having a plurality of operating frequencies for each device to be driven, and provides a clock signal having an operating frequency set by the CPU 102 to each component.

  The voltage detection unit 110 detects the voltage of the external power supply supplied to the microcomputer 1. The external power source drives at least the CPU 102 and the flash memory 106. The voltage detection unit 110 is electrically connected to a VCC terminal (power supply terminal) that is a terminal for supplying external power. More specifically, the voltage detection unit 110 includes a comparison processing circuit 120, a comparison switching register 122, a comparator 124, and a comparison result storage register 126.

  The comparison processing circuit 120 is a circuit that performs preprocessing in order to compare the voltage of the external power source input via the VCC terminal. The comparator 124 compares the voltage depending on the external power source with the reference voltage. The comparison switching register 122 switches the voltage signal input to the comparator 124 in order to determine the voltage level of the external power supply. The comparison result storage register 126 determines the voltage (voltage level) of the external power source based on the relationship between the magnitude relationship determined by the comparator 124 and the switching command in the comparison switching register 122.

  When the microcomputer 1 rewrites the contents of the flash memory 106, the voltage detection unit 110 detects the voltage of the external power supply supplied to the microcomputer 1, and the CPU 102 and the flash memory 106 are detected according to the voltage of the external power supply. A more preferable operation mode and / or operation frequency is set. The microcomputer 1 rewrites the flash memory 106 after setting a more preferable operation mode and / or operation frequency. Such operation mode and / or operation frequency setting processing is executed by the CPU 102 in accordance with a boot loader (instruction group) stored in the boot ROM 104.

<C. Voltage detector>
Next, an example of a specific configuration of the voltage detection unit 110 illustrated in FIG. 1 will be described with reference to FIG. FIG. 2 is a schematic diagram showing a configuration of voltage detection unit 110 included in microcomputer 1 according to the embodiment of the present invention. 2A shows a voltage detection unit 110A that is a configuration example for detecting the voltage of the external power supply by sequentially switching the reference voltage, and FIG. 2B sequentially switches the voltage dividing ratio of the external power supply. The voltage detection part 110B which is a structural example which is a structural example which detects the voltage of an external power supply is shown.

(C1: Configuration for switching the reference voltage)
In the voltage detector 110A shown in FIG. 2A, the comparison processing circuit 120A includes a voltage dividing resistor 1201 and 1202 connected in series between the VCC terminal and the ground GND, and an internal reference voltage source (not shown). And a level selection circuit 1204 to which an internal reference voltage is applied. The voltage detection unit 110 </ b> A includes a level selection register 1221 as the comparison switching register 122.

  A node 1203 at a connection point between the voltage dividing resistor 1201 and the voltage dividing resistor 1202 and the + terminal of the comparator 124 are electrically connected. That is, the detection voltage Vdet obtained by dividing the voltage of the external power supply by the ratio of the voltage dividing resistor 1201 and the voltage dividing resistor 1202 is input to the comparator 124. The level selection circuit 1204 divides the input internal reference voltage at a predetermined ratio according to a value (register value) set in the level selection register 1221 and outputs a reference voltage Vref. That is, the reference voltage Vref is input to the negative terminal of the comparator 124, and the comparator 124 determines the magnitude relationship between the detection voltage Vdet and the reference voltage Vref. The value set in the level selection register 1221 is sequentially switched by the CPU 102 in the voltage detection process of the external power supply. That is, by sequentially switching values set in the level selection register 1221, the reference voltage Vref input to the comparator 124 is changed, and based on the reference voltage Vref that reverses the magnitude relationship in the comparator 124. Determine the voltage (voltage level) of the external power supply. The comparison result in the comparator 124 is stored in the comparison result storage register 126 (FIG. 1).

  As described above, the voltage detection unit 110A shown in FIG. 2A generates the detection voltage Vdet obtained by dividing the voltage applied to the VCC terminal (power supply terminal) at a predetermined ratio, and the internal reference voltage. The level selection register 1221 selects the voltage level to be detected from the reference voltage Vref. Then, the detection voltage Vdet and the reference voltage Vref are compared by the comparator 124, and the comparison result is stored in the comparison result storage register 126 (FIG. 1).

  That is, the voltage detection unit 110A includes a comparator 124 that compares a voltage obtained by dividing the external power supply at a predetermined ratio with a predetermined reference voltage, and a reference voltage generation that switches the magnitude of the reference voltage to a plurality of types. The circuit includes a level selection circuit 1204 and a level selection register 1221 that are circuits, and a determination circuit that determines the voltage of the external power source based on the comparison result in the comparator 124 and the reference voltage output from the level selection circuit 1204.

(C2: Configuration for switching the voltage division ratio of the external power supply)
In the voltage detection unit 110B shown in FIG. 2B, the comparison processing circuit 120 includes a voltage dividing resistor 1205, 1206, 1207, 1208 connected in series between the VCC terminal and the ground GND, and a voltage dividing level selection. Circuit 1209. The voltage detection unit 110 </ b> B includes a level selection register 1222 as the comparison switching register 122.

  A node N1 at a connection point between the voltage dividing resistor 1205 and the voltage dividing resistor 1206, a node N2 at a connection point between the voltage dividing resistor 1206 and the voltage dividing resistor 1207, and a connection between the voltage dividing resistor 1207 and the voltage dividing resistor 1208. Each of the node N3 at the point is electrically connected to the voltage division level selection circuit 1209. Divided voltage level selection circuit 1209 outputs the specified voltage among the voltages from nodes N1, N2, and N3 to the + terminal of comparator 124 in accordance with the value (register value) set in level selection register 1222. To do. Further, the reference voltage Vref, which is an internal reference voltage, is input to the negative terminal of the comparator 124, and the comparator 124 determines the magnitude relationship between the detection voltage Vdet and the reference voltage Vref. The values set in the level selection register 1222 are sequentially switched by the CPU 102 in the external power supply voltage detection process. That is, by sequentially switching the value set in the level selection register 1222, the detection voltage Vdet input to the comparator 124 is changed, and based on the detection voltage Vdet in which the magnitude relationship in the comparator 124 is inverted, Determine the voltage (voltage level) of the external power supply. The comparison result in the comparator 124 is stored in the comparison result storage register 126 (FIG. 1).

  As described above, the voltage detection unit 110B illustrated in FIG. 2B is to detect a voltage level among a plurality of detection voltages obtained by dividing the voltage applied to the VCC terminal (power supply terminal) at different ratios. Is selected by the level selection register 1222 to generate the detection voltage Vdet. Then, the detection voltage Vdet and the reference voltage Vref are compared by the comparator 124, and the comparison result is stored in the comparison result storage register 126 (FIG. 1).

  That is, the voltage detection unit 110B is output by a voltage division level selection circuit 1209 that is a voltage division circuit that divides an external power supply and outputs a divided voltage (detection voltage Vdet) in a plurality of stages, and a voltage division level selection circuit 1209. A comparator 124 that compares a detected voltage Vdet with a predetermined reference voltage, an external power supply based on the detected voltage Vdet output from the divided voltage level selection circuit 1209 and the comparison result in the comparator 124. And a determination circuit for determining the voltage of.

<D. Operation mode / frequency setting>
Inside the microcomputer 1, various internal clock signals and internal voltages are generated using the supplied external power supply. Therefore, the voltage of the external power source affects the performance of the microcomputer 1. For example, the upper limit frequency of a clock signal for driving the CPU 102 or the like is restricted according to the voltage of the external power supply. In the flash memory 106, the write (program) operation is performed by charge injection to the floating gate, and the erase (erase) operation is performed by extracting the charge from the floating gate by applying a voltage to the channel. For this reason, the voltage of the external power source for generating these applied voltages is important.

  Therefore, the microcomputer 1 sets an operation mode and / or an operation frequency for the CPU 102 and the flash memory 106 according to the voltage of the external power supply. Specifically, as shown in the following table, an operation voltage range is defined in advance for each of a plurality of operation modes, and an appropriate operation mode is set according to the detected voltage of the external power supply.

  With the settings defined in the above table, the operation mode is switched mainly when the voltage of the external power supply is 2.7 V and 1.62 V. For example, if the voltage of the external power supply is 3.0 V, any of the operation modes 1 to 3 can be set, but the operation mode 1 is selected from the viewpoint of performing higher-speed processing. On the other hand, if the voltage of the external power supply is 2.5 V, only the operation modes 2 and 3 can be set (however, in the operation mode 2, only the read (read) operation to the flash memory 106 is possible. ). At this time, if a write operation to the flash memory 106 is required, the operation mode 3 is selected.

  The operating frequencies of the various clock signals may be fixed values according to the respective operation modes, but may be further changed according to the voltage of the external power supply. That is, in the former case, only the operation mode for the CPU 102 and the flash memory 106 is set according to the voltage of the external power supply. On the other hand, in the latter case, the operation mode and the operation frequency for the CPU 102 and the flash memory 106 are set according to the voltage of the external power supply.

  As an example, the operating frequencies of various clock signals can be set as follows depending on the operation mode.

  Thus, after setting the operation mode, the clock signal used by each component of the microcomputer 1 is set in more detail, so that the performance of the microcomputer 1 is maximized according to the voltage of the external power supply. It can be demonstrated.

  Note that only the operating frequency for the CPU 102 and the flash memory 106 may be set according to the voltage of the external power supply without dividing the above-described operation modes.

  FIG. 3 shows an example of a circuit configuration for generating a clock signal in microcomputer 1 according to the embodiment of the present invention. Referring to FIG. 3, in microcomputer 1, a FlashIF clock (FCLK), a system clock (ICLK), peripheral module clocks (PCLKB, PCLKD), and an external bus clock (BCLK) are mainly used. These clock signals correspond to the clock signal setting examples described above.

  The Flash IF clock (FCLK) is a clock signal used for access (read operation, write operation, erase operation) to the flash memory 106. The system clock (ICLK) is a clock signal used for data transmission of the internal bus 100 and driving of the CPU 102. The peripheral module clocks (PCLKB, PCLKD) are clock signals used for driving peripheral modules (timer unit, A / D conversion unit, D / A conversion unit, etc.) such as input / output of the microcomputer 1. The external bus clock (BCLK) is a clock signal used for exchanging data between the microcomputer 1 and an external device.

  Referring to FIG. 3, as a configuration for generating a clock signal of microcomputer 1, main clock oscillator 1081, sub clock oscillator 1082, high speed clock oscillator 1083, low speed clock signal oscillator 1084, and selectors 130 and 140 are provided. , 144, 148, 152, registers 132, 142, 146, 150, 154, and a frequency divider 134.

  The main clock oscillator 1081, the sub clock oscillator 1082, the high speed clock oscillator 1083, and the low speed clock signal oscillator 1084 each generate a clock signal having a predetermined operating frequency. The selector 130 selects one of the clock signals from the respective oscillators and outputs it to the frequency divider 134. The selector 130 selects a clock signal according to a value (CKSEL) set in the register 132. Basically, a value corresponding to the selected operation mode is set in the register 132. That is, the operating frequency of the clock signal input to the frequency divider 134 is switched according to the set operation mode.

  The frequency divider 134 generates a plurality of clock signals obtained by dividing the input clock signal by different frequency division ratios. The respective clock signals are given to the selectors 140, 144, 148, 152 by buses arranged in parallel, respectively.

  The selector 140 outputs the clock signal selected according to the value (FCK) set in the register 142 as the FlashIF clock (FCLK).

  The selector 144 outputs the clock signal selected according to the value (ICK) set in the register 146 as the system clock (ICLK).

  The selector 148 outputs the clock signals (two types) selected according to the values (PCKB, PCKD) set in the register 150 as peripheral module clocks (PCLKB, PCLKD).

  The selector 152 outputs the clock signal selected according to the value (BCK) set in the register 150 as the external bus clock (BCLK).

  As described above, typically, the CPU 102 sets values corresponding to the selected operation mode in the register 132 and sets values corresponding to the selected operation frequency in the registers 142, 146, 150, and 154. To do.

<E. Processing procedure>
Next, a processing procedure executed in microcomputer 1 according to the present embodiment will be described. Basically, the processing for setting the operation mode and / or the operation frequency of the CPU 102 and the flash memory 106 to values according to the operation environment is executed when the microcomputer 1 is shipped or when the firmware is updated. That is, the CPU 102 sets the operation mode and / or the operation frequency of the CPU 102 and the flash memory 106 at the time of startup after power-on.

(E1: Setting process)
FIG. 4 is a flowchart showing a setting process and a procedure for accessing the flash memory in microcomputer 1 according to the embodiment of the present invention. 5 and 6 are flowcharts showing a processing procedure in the voltage detection processing of the external power source shown in FIG.

  Referring to FIG. 4, when the microcomputer 1 is turned on, CPU 102 executes a boot loader stored in boot ROM 104 (step S2). Subsequently, the CPU 102 determines whether or not execution of setting of the operation mode and the operation frequency of the CPU 102 and the flash memory 106 is requested (step S4). When the power is first turned on to the microcomputer 1 or when the firmware is updated, execution of the setting process is requested.

  If execution of the setting of the operation mode and the operation frequency is not requested (NO in step S4), the processes in steps S6 to S10 are skipped, and the process proceeds to step S20.

  When execution of setting of the operation mode and the operation frequency is requested (YES in step S4), CPU 102 executes voltage detection processing of the external power supply (step S6). Details of the voltage detection processing of the external power supply will be described later with reference to FIGS.

  Subsequently, the CPU 102 sets a more preferable operation mode and / or a more preferable operation frequency of the CPU 102 based on the voltage of the external power supply detected by the voltage detection process of the external power supply (step S8). Further, the CPU 102 sets a more preferable operation mode and / or a more preferable operation frequency of the flash memory 106 based on the voltage of the external power supply detected by the voltage detection process of the external power supply (step S10). In addition, you may perform the process of step S8 and S10 in parallel.

  With the above processing, the setting of the operation mode and the operation frequency of the CPU 102 and the flash memory 106 is completed. Thereafter, the CPU 102 determines whether or not an access request to the flash memory 106 has occurred (step S20). If an access request to the flash memory 106 has not occurred (NO in step S20), the processes in and after step S20 are repeated.

  If an access request to the flash memory 106 is generated (YES in step S20), the CPU 102 determines the type of access to the flash memory 106 (step S22). Then, the CPU 102 executes any one of an erase (erase) process, a read (load) process, a write (program) process, and a blank check process according to the type determined in step S22 (step S24). And the process after step S20 is repeated.

(E2: External power supply voltage detection process 1)
As an example of the voltage detection process of the external power supply, a process of detecting the voltage of the external power supply by the voltage detection unit 110A illustrated in FIG.

  Referring to FIG. 5, CPU 102 sets reference voltage Vref to the highest level (step S100). Specifically, the CPU 102 sets a value for setting the reference voltage Vref to the highest level in the level selection register 1221 (FIG. 2A).

  Subsequently, the CPU 102 activates the voltage detection unit 110A (step S102), and reads the comparison result (voltage detection signal in FIG. 2A) in the voltage detection unit 110A (step S104). Then, the CPU 102 determines whether or not the detected voltage Vdet is equal to or higher than the current reference voltage Vref (step S106).

  When detection voltage Vdet is equal to or higher than current reference voltage Vref (YES in step S106), CPU 102 determines that the voltage level of the external power source is equal to or higher than the maximum level (step S108). Then, the process ends.

  When the detection voltage Vdet is lower than the current reference voltage Vref (NO in step S106), the CPU 102 sets the reference voltage Vref to a level lower by one step from the current level (step S110), and detects the voltage. The comparison result in unit 110A is read (step S112). Then, the CPU 102 determines whether or not the detection voltage Vdet is equal to or higher than the current reference voltage Vref (step S118).

  When the detection voltage Vdet is equal to or higher than the current reference voltage Vref (YES in step S118), the CPU 102 sets the voltage level of the external power supply to be equal to or higher than the current reference voltage Vref and the current reference voltage. It is determined that the level is less than one level higher than the level of Vref (step S120). Then, the process ends.

  When the detected voltage Vdet is less than the current reference voltage Vref (NO in step S118), the CPU 102 determines whether or not the current reference voltage Vref is at the lowest level (step S122).

  If current reference voltage Vref is at the lowest level (YES in step S122), CPU 102 determines that the voltage level of the external power supply is lower than the lowest level (step S124). Then, the process ends.

  If the current reference voltage Vref is not at the lowest level (NO in step S122), the processing from step S110 is executed.

(E3: External power supply voltage detection process 2)
As another example of the voltage detection process of the external power supply, a process of detecting the voltage of the external power supply by the voltage detection unit 110B illustrated in FIG.

  Referring to FIG. 6, CPU 102 selects detection voltage Vdet at the lowest level (step S200). Specifically, the CPU 102 sets a value for selecting the lowest level detection voltage Vdet in the level selection register 1222 (FIG. 2B). That is, the CPU 102 drives the voltage division level selection circuit 1209 so that the voltage division ratio is the lowest.

  Subsequently, the CPU 102 activates the voltage detection unit 110B (step S202), and reads the comparison result (voltage detection signal in FIG. 2B) in the voltage detection unit 110B (step S204). Then, the CPU 102 determines whether or not the current detection voltage Vdet is equal to or higher than the reference voltage Vref (step S206).

  If current detection voltage Vdet is equal to or higher than reference voltage Vref (YES in step S206), CPU 102 determines that the voltage level of the external power supply is equal to or higher than the maximum level (step S208). Then, the process ends.

  When current detection voltage Vdet is lower than reference voltage Vref (NO in step S206), CPU 102 selects detection voltage Vdet that is higher by one step from the current level (step S210), and voltage detection unit 110B. The comparison result is read out (step S212). Then, the CPU 102 determines whether or not the current detection voltage Vdet is equal to or higher than the reference voltage Vref (step S218).

  When current detection voltage Vdet is equal to or higher than reference voltage Vref (YES in step S218), CPU 102 sets the voltage level of the external power supply to be equal to or higher than the level corresponding to the current voltage dividing ratio, and It is determined that the level is lower by one level than the level corresponding to the partial pressure ratio (step S220). Then, the process ends.

  When current detection voltage Vdet is lower than reference voltage Vref (NO in step S218), CPU 102 determines whether or not current detection voltage Vdet is at the highest level (step S222).

  When current detection voltage Vdet is the highest level (YES in step S222), CPU 102 determines that the voltage level of the external power supply is lower than the lowest level (step S224). Then, the process ends.

  If the current detection voltage Vdet is not at the highest level (NO in step S222), the processing from step S210 is executed.

(E4: Modification)
In place of, or in addition to, the above-mentioned shipment / update time, when the flash memory 106 is accessed, the operation mode and / or the operation frequency of the CPU 102 and the flash memory 106 are set to values according to the operation environment. Processing may be performed. That is, the CPU 102 sets the operation mode and / or operation frequency of the CPU 102 and the flash memory 106 in response to a request for access to the flash memory 106.

  FIG. 7 is a flowchart showing a modification of the procedure of the setting process and the access to the flash memory in microcomputer 1 according to the embodiment of the present invention.

  Referring to FIG. 7, when the microcomputer 1 is powered on, CPU 102 executes a boot loader stored in boot ROM 104 (step S52).

  Subsequently, the CPU 102 determines whether or not an access request to the flash memory 106 has occurred (step S54). If an access request to the flash memory 106 has not occurred (NO in step S54), the processes in and after step S54 are repeated.

  When an access request to the flash memory 106 is generated (YES in step S54), the CPU 102 sets the operation mode and the operation frequency of the CPU 102 and the flash memory 106. That is, first, the CPU 102 executes a voltage detection process for the external power supply (step S56). Subsequently, the CPU 102 sets a more preferable operation mode and / or a more preferable operation frequency of the CPU 102 based on the voltage of the external power supply detected by the voltage detection process of the external power supply (step S58). Further, the CPU 102 sets a more preferable operation mode and / or a more preferable operation frequency of the flash memory 106 based on the voltage of the external power supply detected by the voltage detection process of the external power supply (step S60). In addition, you may perform the process of step S58 and S60 in parallel.

  Thereafter, the CPU 102 determines the type of access to the flash memory 106 (step S62). Then, the CPU 102 executes any one of an erase (erase) process, a read (load) process, a write (program) process, and a blank check process according to the type determined in step S52 (step S64). And the process after step S54 is repeated.

<F. Summary>
According to the present embodiment, when the flash memory needs to be rewritten, a suitable operation mode and operation frequency are automatically set by detecting the voltage of the external power supply supplied to the microcomputer. . Therefore, it is possible to prevent the microcomputer from malfunctioning when the user erroneously inputs voltage information (target voltage) as in the prior art. As a result, it is possible to set the operation mode and the operation frequency of the CPU and the flash memory more suitable for the operation of the microcomputer in accordance with the voltage of the external power supply, and the flash memory rewriting time can be shortened.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 microcomputer, 100 internal bus, 102 CPU, 104 ROM, 106 flash memory, 108 clock generation circuit, 110, 110A, 110B voltage detection unit, 120, 120A, 120B comparison processing circuit, 122 comparison switching register, 124 comparison 126, comparison result storage register, 130, 140, 144, 148, 152 selector, 132, 142, 146, 150, 154 register, 134 frequency divider, 1081 main clock oscillator, 1082 subclock oscillator, 1083 high-speed clock oscillator, 1084 Low-speed clock signal oscillator, 1201, 1202, 1205, 1206, 1207, 1208 voltage dividing resistor, 1203, N1, N2, N3 node, 1204 level selection circuit, 1209 voltage dividing level択回 path, 1221 and 1222 level selection register, GND Ground.

Claims (5)

A processor;
A non-volatile memory accessible by the processor;
A voltage detection unit for detecting a voltage of an external power source for driving at least the processor and the nonvolatile memory;
The processor executes an instruction group to set an operation mode and / or an operation frequency for at least one of the processor and the non-volatile memory according to a voltage detected by the voltage detection unit. .   The semiconductor device according to claim 1, wherein the processor sets an operation mode and / or an operation frequency for at least one of the processor and the non-volatile memory at startup after power-on.   The processor according to claim 1 or 2, wherein the processor sets an operation mode and / or an operation frequency for at least one of the processor and the nonvolatile memory in response to a request for access to the nonvolatile memory. The semiconductor device described. The voltage detector is
A comparison circuit that compares a voltage obtained by dividing the external power supply by a predetermined ratio with a predetermined reference voltage;
A reference voltage generating circuit for switching the reference voltage to a plurality of types;
The determination circuit which determines the voltage of the said external power supply based on the comparison result in the said comparison circuit, and the said reference voltage output from the said reference voltage generation circuit, The control circuit of any one of Claims 1-3 Semiconductor device. The voltage detector is
A voltage dividing circuit that divides the external power source and outputs a divided voltage of a plurality of stages;
A comparison circuit that compares the divided voltage output by the voltage dividing circuit with a predetermined reference voltage;
The determination circuit according to claim 1, further comprising: a determination circuit that determines a voltage of the external power source based on a divided voltage output from the voltage dividing circuit and a comparison result in the comparison circuit. Semiconductor device.

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