JP2013098421A - Multilayer ceramic substrate and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer ceramic substrate and a manufacturing method thereof in which productivity is improved and the occurrence of deformation or disconnection inside the substrate can be reduced by preventing an interlayer connecting conductor from being pushed up even if shrinkage in a thickness direction is large.SOLUTION: A second internal wiring layer 11 which contains a conductor, crystallized glass and mullite and has conductivity is provided at the same position as an interlayer connecting conductor part 13 in a plane view so as to be brought into contact with the interlayer connecting conductor part 13 directly or via a first internal wiring layer 9 in at least one thickness direction of the interlayer connecting conductor part 13. Regarding the crystallized glass, its glass transition point (Tg) is lower than a calcination/shrinkage starting temperature and further, its crystallization temperature (Tc) is higher than the calcination/shrinkage starting temperature and lower than a temperature of the calcination/shrinkage starting temperature + 150°C.

Description

  The present invention relates to a multilayer ceramic substrate having high electrical connection reliability and a method for manufacturing the same. The present invention relates to a multilayer ceramic substrate that can be used for a manufacturing substrate and the like, and a manufacturing method thereof.

  In recent years, as an electrical inspection of ICs, there is an increasing demand for performing inspection on a silicon wafer basis. In particular, at the present time when the size of silicon wafers is increasing, it is necessary to deal with wafers having a diameter of 300 mm (12 inches).

  Further, when inspecting these silicon wafers, it is necessary to form connection terminals that contact IC pads (IC pads) on the IC inspection substrate of the measuring jig, and these connection terminals are repeatedly contacted. Therefore, strength is required.

  In order to satisfy these requirements, a multilayer ceramic substrate is used as an IC inspection substrate. However, in the conventional normal manufacturing method, due to shrinkage variation during firing of the ceramic substrate, connection to an IC pad is possible. Obtaining the required dimensional accuracy is not easy.

Therefore, in recent years, a non-shrinkage firing technique has been developed as a method of manufacturing a ceramic substrate that requires such dimensional accuracy.
As this non-shrinkage firing technology, a constraining sheet (shrinkage suppression sheet) made of a ceramic sheet that does not sinter at the temperature at which the green sheet laminate is fired is laminated on the upper and lower surfaces of a green sheet laminate in which green sheets containing ceramics are laminated. Thus, a method has been developed in which, when baked, the shrinkage suppression sheet suppresses shrinkage in the plane direction (XY direction) when the green sheet laminate shrinks, and realizes high dimensional accuracy.

  In addition to this, by disposing a shrinkage suppression sheet that suppresses shrinkage in the planar direction in the inner layer of the green sheet laminate, and by diffusing the glass component in the green sheet into the shrinkage suppression sheet during firing, it is high. Techniques for achieving dimensional accuracy have also been developed.

  In such a non-shrinkage firing technique, firing is performed while suppressing shrinkage in the planar direction. However, in any method, since the green sheet does not shrink during firing, it does not become dense, and therefore shrinkage in the thickness direction (Z direction) is not caused. It has the feature of becoming larger.

  By the way, normally, an internal wiring conductor is disposed on the surface of each green sheet inside the green sheet laminate, and an interlayer connection conductor (via conductor) connected to the internal wiring conductor so as to penetrate the green sheet in the thickness direction. However, this via conductor shrinks evenly in the plane direction and the thickness direction even if it is non-shrinking firing or normal firing that is not shrink shrink firing.

  On the other hand, as described above, the green sheet is greatly shrunk in the thickness direction during the non-shrinkage firing, so that the behavior of the via conductor and the green sheet during the non-shrink firing is greatly different.

  In other words, during normal firing, which is not shrink-free firing technology, the green sheet shrinks evenly in the planar direction and thickness direction, so there are gaps or bumps (after firing) between the via conductor after firing and the ceramic layer. In the non-shrinkage firing technique, the green sheet tends to shrink greatly in the thickness direction, but the via conductor tends to shrink evenly in the planar method and thickness direction. As a result, gaps and protrusions are generated between the via conductor after firing and the ceramic layer. As a result, the electrical connection between the via conductor and the internal wiring conductor may be impaired.

  As a countermeasure against this, many methods have been studied for matching shrinkage behavior between via conductors and green sheets, and even for via conductor push-up that occurs due to shrinkage mismatch in the thickness direction, Studies on structural surfaces and materials have been made (see Patent Documents 1 to 3).

Specifically, Patent Document 1 discloses a technique for reducing the push-up of the via conductor by providing a shrinkage-suppressing green layer (including an inorganic material that is not sintered during firing) on the end face side in the thickness direction of the via conductor. It is disclosed. Patent Document 2 discloses a technique for reducing the push-up of the via conductor by arranging a metal foil on the end face side in the thickness direction of the via conductor. Further, Patent Document 3 discloses a technique for reducing the push-up of the via conductor by adjusting the contraction timing by adding W or Sb ₂ O ₃ to the via conductor.

JP 2001-257473 A Japanese Patent Laid-Open No. 10-107445 JP-A-6-69651

  However, as in the technique of Patent Document 1, when an inorganic material that is not sintered is locally disposed inside the green sheet laminate, for example, when firing while applying pressure, a pressure distribution is generated, In the (baked) multilayer ceramic substrate, disconnection of the internal wiring conductor may occur between the portion where the inorganic material is disposed and the portion where the inorganic material is not disposed.

  In addition, as in the technique of Patent Document 2, when a metal foil is used inside to suppress the via conductor from being pushed up, the metal foil suppresses the via conductor from being pushed up in the thickness direction. In addition, pattern formation with a metal foil takes a lot of work such as exposure and development, and the metal components of unnecessary pattern portions are removed and discarded during development, which is very expensive. It becomes a process.

  Further, in the method of adjusting the shrinkage timing with the green sheet and adjusting the shrinkage behavior in the thickness direction of the via conductor by appropriately adjusting the additive to the via conductor as in the technique of Patent Document 3, The amount of push-up depends on fluctuations in the design (connection length) of the conductor, and the manufacturing content needs to be reviewed depending on the design.

  The present invention has been made in view of the above problem, and even when the productivity is high and the shrinkage in the thickness direction is large, the push-up of the interlayer connection conductor is suppressed, and deformation, disconnection, etc. are generated inside the substrate. An object of the present invention is to provide a multilayer ceramic substrate and a method for manufacturing the same.

  (1) In the present invention, as a first aspect, a plurality of ceramic layers are laminated, a first internal wiring layer disposed between the ceramic layers, and a first internal wiring layer penetrating in the thickness direction of the ceramic layers. In a method for manufacturing a multilayer ceramic substrate comprising an interlayer connection conductor portion electrically connected to a wiring layer, an interlayer connection conductor forming portion that becomes the interlayer connection conductor portion after firing, and the first internal wiring layer after firing A first step of laminating a plurality of green sheets having a first internal wiring forming layer to form a green sheet laminate, and the green sheet laminate is baked on at least one surface of the green sheet laminate. A second step of forming a green composite laminate by laminating a shrinkage suppression sheet that does not sinter at the temperature to be bonded; and degreasing and firing the green composite laminate to form a ceramic laminate A fourth step of removing the unsintered layer of the shrinkage suppression sheet remaining on the surface of the ceramic laminate after the firing, and after removing the unsintered layer, the ceramic A fifth step of forming a surface conductor layer on the surface of the multilayer body, and before laminating the green sheet, at the same position as the interlayer connection conductor formation portion in plan view, and forming the interlayer connection conductor A conductive material including a conductor, crystallized glass, and mullite so as to be in contact with at least one of the thickness direction of the portion directly with the interlayer connection conductor formation portion or through the first internal wiring formation layer. (2) A push-up preventing layer to be an internal wiring layer is formed, and as the crystallized glass, the glass transition point (Tg) is lower than the firing shrinkage start temperature, and the crystallization temperature (Tc) is equal to the firing shrinkage start temperature. High and which comprises using a lower than the firing shrinkage initiation temperature + 150 ℃ material.

  In this aspect, in manufacturing a multilayer ceramic substrate, before laminating the green sheets, it is at the same position as the interlayer connection conductor formation portion (hereinafter sometimes simply referred to as a via formation portion) in plan view, and A second internal wiring layer having conductivity, including a conductor, crystallized glass, and mullite so as to be in contact with at least one of the forming portions in the thickness direction directly or via the first internal wiring formation layer A push-up preventing layer is formed. For example, as illustrated in FIG. 1A described later, a first internal wiring formation layer, a push-up prevention layer, and a via formation portion are disposed.

  At the same time, as the crystallized glass of the push-up preventing layer, the glass transition point (Tg) is lower than the firing shrinkage start temperature, and the crystallization temperature (Tc) is higher than the firing shrinkage start temperature and lower than the firing shrinkage start temperature + 150 ° C. Use materials.

  Thereby, as will be described in detail later, even if the productivity is high (no need to review the metal foil and manufacturing contents) and the shrinkage in the thickness direction is large during firing, the first inside of the via formation portion Since pushing up to the wiring formation layer can be suppressed, the occurrence of deformation or disconnection in the substrate (particularly, the first internal wiring layer after firing) can be reduced.

  That is, in this aspect, unlike the above-described prior art, an inorganic material that does not sinter is not locally disposed in the green sheet laminate, so that pressure distribution is unlikely to occur during firing, and thus the first internal wiring layer The disconnection is difficult to occur. Further, since no metal foil is disposed inside, the manufacturing process can be simplified and the cost can be reduced. Furthermore, the manufacturing process can be simplified because it is not necessary to review the manufacturing contents due to variations in the design (connection length) of the via conductor.

Hereinafter, the reason which prescribed | regulated the structure of crystallized glass in this aspect is demonstrated in detail.
In this crystallized glass, the relationship between the temperature and viscosity when the crystallized glass is fired, and the glass transition point (Tg) and the crystallization temperature (Tc) are those shown in FIG. It is done. That is, when the temperature rises, the viscosity decreases, and the crystallization temperature (Tc) is higher than the glass transition point (Tg).

  First, when a multilayer ceramic substrate is manufactured in this embodiment, a region in which the viscosity of the ceramic is reduced (for example, after the ceramic shrinkage start temperature (for example, after 750 ° C.) until the ceramic is densified (for example, (750 to 800 ° C.), the viscosity of the push-up preventing layer that comes into contact with the via forming portion needs to be higher than the viscosity of the ceramic. Due to the difference in viscosity, the push-up preventing layer having a high viscosity arranged in the shrinkage direction (thickness direction) of the via forming portion serves as a shield, and push-up in the thickness forming direction of the via forming portion when the ceramic shrinks can be prevented.

  Specifically, first, the crystallized glass contained in the push-up prevention layer needs to soften earlier than the firing shrinkage start temperature of the ceramic and help the shrinkage of the push-up prevention layer. Therefore, in this embodiment, “the glass transition point (Tg) of crystallized glass is lower than the firing shrinkage start temperature” is set.

  Further, in order to produce the viscosity difference, in the region where the viscosity of the ceramic is lowered, the viscosity of the push-up preventing layer is increased (to the extent that the viscosity difference is produced), that is, crystallization is performed to the extent that the viscosity is increased ( Crystallization of crystallized glass) is required.

In order to obtain the effect of this crystallization, the firing shrinkage start temperature is considered to be about the range of the crystallization temperature -150 ° C. to the crystallization temperature, and this point was confirmed by experiments.
Thus, in this embodiment, “the crystallization temperature of the crystallized glass is higher than the firing shrinkage start temperature of the ceramic and the firing shrinkage start temperature of the ceramic + 150 ° C. (for example, 900 ° C.)”.

  If the crystallization temperature exceeds the shrinkage start temperature + 150 ° C., the crystallization is insufficient in the temperature range where the ceramic viscosity is lowered, and the viscosity of the push-up preventing layer may be lower than the viscosity of the ceramic. In that case, the above-mentioned push-up preventing effect may not be obtained.

Therefore, in this aspect, as described above, the characteristics of the crystallized glass of the push-up preventing layer are defined, and the effect of preventing push-up by this is clear from the experimental examples described later.
As will be apparent from experimental examples to be described later, it is more desirable to have a crystallization temperature in the region where the ceramic viscosity decreases (specifically, 750 to 800 ° C.) because the amount of wiring deformation is small.

Note that mullite contained in the push-up prevention layer is an inorganic filler, and has an effect of suppressing a decrease in viscosity of the push-up prevention layer.
Here, the firing shrinkage start temperature is the temperature at which the material starts shrinking when the ceramic layer material (green sheet or the like) is fired during the production of the multilayer ceramic layer.

(2) In the present invention, as a second aspect, the area of the push-up prevention layer is larger than the area of the interlayer connection conductor forming portion in plan view.
In this embodiment, since the area of the push-up prevention layer is larger than the area of the via formation portion, even if the behavior of the via formation portion pushes up the push-up prevention layer during firing, the push-up prevention layer is extensive. Since it is formed, there is an advantage that deformation and disconnection inside the substrate due to the push-up hardly occur.

(3) In the present invention, as a third aspect, the crystallization temperature of the crystallized glass is in the range of 780 ° C to 900 ° C.
As will be apparent from the experimental examples described later, when the crystallization temperature of the crystallized glass is in the range of 780 ° C. to 900 ° C., there is an advantage that deformation or disconnection due to push-up is unlikely to occur.

  (4) In the present invention, as a fourth aspect, the content ratio of the crystallized glass and the mullite with respect to all inorganic materials in the material constituting the push-up preventing layer is 20% by volume or more.

  In this aspect, since the content ratio of crystallized glass and mullite with respect to all inorganic materials of the push-up prevention layer is 20% by volume or more, the above-mentioned push-up prevention effect is large, and the occurrence of deformation and disconnection inside the substrate is effective. Can be prevented.

Note that the crystallized glass is more suitable for the above-described effect of preventing the push-up when the crystallized glass and the mullite have the same volume.
In addition, when the content of crystallized glass and mullite is 30% by volume or less, sufficient electrical conductivity can be ensured (for example, electrical resistivity ρ <8 μΩ · cm), paste characteristics (fillability, viscosity stability over time) Etc.) is also preferable.

  (5) The present invention provides a ceramic laminate in which a plurality of ceramic layers are laminated, a first internal wiring layer arranged in a plane direction between the ceramic layers, and a thickness direction of the ceramic layer as a fifth aspect. In a multilayer ceramic substrate provided with an interlayer connection conductor (for example, via) that penetrates and is electrically connected to the first internal wiring layer, the multilayer ceramic substrate is in the same position as the interlayer connection conductor in plan view, and Conductivity including a conductor, crystallized glass, and mullite so as to be in contact with the interlayer connection conductor portion directly or via the first internal wiring layer on at least one of the interlayer connection conductor portions in the thickness direction. The crystallized glass has a glass transition point (Tg) lower than the firing shrinkage start temperature, and the crystallization temperature (Tc) is higher than the firing shrinkage start temperature and is fired. Wherein the lower shrink starting temperature + 0.99 ° C..

  In the multilayer ceramic substrate of this aspect, since the crystallized glass used has the above characteristics, as described above, it is possible to suppress the via formation portion from being pushed up with respect to the first internal wiring formation layer during firing. Therefore, in the multilayer ceramic substrate obtained by firing, there is a remarkable effect that there is little deformation or disconnection of the first internal wiring layer.

That is, in the multilayer ceramic substrate having the above-described configuration, an excellent substrate with less deformation and disconnection can be realized at the time of manufacturing by solving the conventional problems.
In the present invention, the arrangement shown in FIG. 1A is given as the arrangement of the first internal wiring layer, the second internal wiring layer, and the interlayer connection conductor portion (hereinafter sometimes simply referred to as via). .

  In FIG. 1A, P is a first internal wiring layer (formed by firing the first internal wiring forming layer), Q is a second internal wiring layer (formed by firing the push-up preventing layer), and R is It is an interlayer connection conductor part (interlayer connection conductor formation part is baked).

(6) In the present invention, as a sixth aspect, the area of the second internal wiring layer is larger than the area of the interlayer connection conductor portion in plan view.
In this aspect, since the area of the second internal wiring layer is larger than the area of the via, even when the above-described push-up occurs, deformation or disconnection hardly occurs. Therefore, the multilayer ceramic substrate having this configuration has an advantage that deformation and disconnection are further reduced.

(7) In the present invention, as a seventh aspect, the crystallization temperature of the crystallized glass is in the range of 780 ° C to 900 ° C.
As will be apparent from the experimental examples described later, when the crystallization temperature of the crystallized glass is in the range of 780 ° C. to 900 ° C., there is an advantage that deformation or disconnection due to push-up is unlikely to occur.

(8) The present invention, as an eighth aspect, is characterized in that a content of the crystallized glass and the mullite in the second internal wiring layer is 20% by volume or more.
In this aspect, since the content of crystallized glass and mullite in the second internal wiring layer is 20% by volume or more, the above-described push-up prevention effect is great, and the occurrence of internal deformation and disconnection is effectively prevented. it can.

In the present invention described above, examples of the conductor included in the second internal wiring layer (push-up preventing layer) include Ag, Pd, and Pt. Further, as the crystallized glass, glass such as SiO ₂ —Al ₂ O ₃ —B ₂ O ₃ —BaO—MgO, Nd ₂ O ₃ —TiO ₂ —SiO ₂ , SiO ₂ —CaO—MgO—ZnO, etc. Is mentioned.

(A) is explanatory drawing which illustrates arrangement | positioning of the 1st internal wiring layer in this invention, a 2nd internal wiring layer, and an interlayer connection conductor part, (b) is explanatory drawing which shows the relationship between the temperature and viscosity of crystallized glass. is there. (A) is sectional drawing which shows the state which fractured | ruptured the principal part of the multilayer ceramic substrate along the thickness direction, (b) is the 1st inside when the multilayer ceramic substrate is seen from the thickness direction (direction perpendicular to the substrate surface) It is explanatory drawing which shows an example of arrangement | positioning of a wiring layer, a 2nd internal wiring layer, and an interlayer connection conductor part. It is a top view which shows a part of surface of the board | substrate for IC inspection of this embodiment. It is explanatory drawing which shows the usage method of the board | substrate for IC inspection of this embodiment. It is explanatory drawing which shows a part of manufacturing method of the multilayer ceramic substrate of this embodiment. It is explanatory drawing which shows a part of manufacturing method of the multilayer ceramic substrate of this embodiment. (A) is explanatory drawing which shows the experimental method which investigates the electroconductivity of Experimental example 1, (b) is explanatory drawing which shows the board | substrate deformation amount of Experimental example 2. FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Embodiment]
a) First, the multilayer ceramic substrate of this embodiment will be described with reference to FIGS.

Here, as a multilayer ceramic substrate, a substrate used for an IC inspection substrate will be described as an example.
As shown in FIG. 2 (a), a part of the IC inspection substrate 1 includes an IC inspection substrate 1 having a multilayer ceramic substrate 5 in which a plurality of ceramic layers 3 are laminated in the plate thickness direction (vertical direction in the figure) (for example, A rectangular parallelepiped sintered body having a thickness of 5 mm, a length of 100 mm, and a width of 100 mm, and an electrode 7 formed on the surface of the multilayer ceramic substrate 5.

The ceramic layer 3 is made of, for example, a low temperature fired glass ceramic obtained by firing a mixture of a glass component and a ceramic component at a low temperature of about 800 to 1050 ° C., for example.
Specifically, each ceramic layer 3 is made of a glass ceramic whose main component is mullite and borosilicate glass, and SiO, Al ₂ O ₃ and B ₂ O _{3 are} contained in the borosilicate glass.

  The electrode 7 is formed on the front and back surfaces of the multilayer ceramic substrate 5, and the electrode 7 has a structure in which Ti / Cu / Ni / Au layers are sequentially stacked. In addition, as a conductor which comprises the electrode 7, the thing which combined Ti, Cr, Mo, Cu, Ni, Au, and those can be employ | adopted.

  Further, in the multilayer ceramic substrate 5 (specifically, at the boundary between the ceramic layers 3), as will be described later, the first internal wiring layer 9 and the second internal wiring layer 11 (having conductivity) are disposed at predetermined positions. And are arranged.

  Moreover, the electrode 7 on the front surface and the electrode 7 on the back surface of the multilayer ceramic substrate 5 are electrically connected via the first internal wiring layer 9 (or further via the second internal wiring layer 11 in some places). An interlayer connection conductor portion (via) 13 extending in the thickness direction of the substrate is formed. In addition, as a conductor which comprises the 1st internal wiring layer 9 and the via | veer 13, conductors, such as Ag, Ag / Pt alloy, and Ag / Pd alloy which can be simultaneously fired at the low temperature at the time of baking of a glass ceramic, can be used.

  In FIG. 2A, the front-side electrode 7 and the back-side electrode 7 are shown not to be electrically connected. Actually, however, the first internal wiring layer 9 is provided at other locations. And are electrically connected through vias 13.

b) Next, the arrangement of the first internal wiring layer 9, the second internal wiring layer 11, the via 13, etc., which are the main parts of the present embodiment, will be described.
As shown in FIG. 2A, in the portion A (the via 13 on the left side of the figure), the end surface 15 of the via 13 is covered on one side (downward in the figure) of the via 13 in the thickness direction (the vertical direction). The second internal wiring layer 11 is formed, and the first internal wiring layer 9 is laminated so as to cover the surface of the second internal wiring layer 11 (downward in the figure).

  In the B portion (via 13 in the center of the figure), the first internal wiring layer 9 is formed on one side in the thickness direction of the via 13 (upward in the figure) so as to cover the end face 15 of the via 13. A second internal wiring layer 11 is laminated on the surface of the internal wiring layer 9 (upper side in the figure). Further, only the second internal wiring layer 11 is disposed on the other side in the thickness direction of the via 13 (downward in the figure) so as to cover the end face 15 of the via 13.

  Further, in the portion C (the via 13 on the right side of the figure), the first internal wiring layer 9 is formed on one side in the thickness direction of the via 13 (upward in the figure) so as to cover the end face of the via 13. A second internal wiring layer 11 is laminated on the surface of the internal wiring layer 9 (upper side in the figure).

  Specifically, in FIG. 2 (b), as shown in a plan view of the portion A viewed from above (in FIG. 2 (a)) (shown as seen through the shape of each member), the via The second internal wiring layer 11 having a larger area than the end surface 15 is disposed so as to cover all of the 13 end faces 15, and the second internal wiring layer 11 is covered so as to cover an area wider than the second internal wiring layer 11. A first internal wiring layer 9 having the following is arranged.

The size relationship of the end face 15 of the via 13, the second internal wiring layer 11, and the first internal wiring layer 9 is the same for the B and C portions.
Note that, at the lower end of the portion B (in FIG. 2A), only the second internal wiring layer 11 having a larger area than the end face 15 is disposed so as to cover the entire end face 15 of the via 13.

  In particular, in the present embodiment, the second internal wiring layer 11 is made of a conductor (Ag), crystallized glass, and mullite, and the crystallized glass has a glass transition point (Tg) of, for example, 645 ° C. (for IC inspection) The temperature of the substrate 1 is lower than the firing shrinkage start temperature (for example, 750 ° C.) and the crystallization temperature (Tc) is, for example, 790 ° C., which is higher than the firing shrinkage start temperature and lower than the firing shrinkage start temperature + 150 ° C. ing.

As this crystallized glass, SiO ₂ —Al ₂ O ₃ —B ₂ O ₃ —BaO—MgO glass can be used.
In the present embodiment, the content of crystallized glass and mullite in the second internal wiring layer 11 is 20% by volume or more.

  As shown in FIG. 3, in this embodiment, a plurality of electrodes 7 are formed on the multilayer ceramic substrate 5, and a conductive probe (connection terminal) 16 is connected as shown in FIG. An IC inspection jig (silicon wafer electric inspection jig) 17 is configured.

  This IC inspection jig 17 corresponds to, for example, a φ300 mm (12 inch) silicon (Si) wafer 18, and the probe 16 contacts the IC terminal 19 on the silicon wafer 18 (before cutting out each IC). Thus, it is possible to inspect a large number of ICs at a time.

c) Next, a specific example of the method for manufacturing the multilayer ceramic substrate 5 of the present embodiment will be described in detail with reference to FIGS.
<Manufacture of green sheets>
First, as a raw material powder for forming the ceramic layer 3, a borosilicate glass powder containing SiO ₂ , Al ₂ O ₃ , and B ₂ O ₃ as main components (average particle size: 3 μm, specific surface area: 1.0 m ²⁾ / G) and mullite powder (average particle size: 3 μm, specific surface area: 1.0 m ² / g).

  In addition, an acrylic binder is used as a binder component (resin component) when forming a ceramic green sheet, and DOP (di-ophthalate phthalate) is used as a plasticizer component that imparts appropriate flexibility to the green sheet after molding. MEK (methyl ethyl ketone) was prepared as a solvent having a high slurry viscosity and sheet strength.

  Next, the borosilicate glass powder and the mullite powder were weighed to a weight ratio of 50:50 and a total amount of 1 kg, and placed in an alumina pot. A ceramic slurry was obtained by adding 120 g of the acrylic resin (binder) and appropriate amounts of a plasticizer (DOP) and a solvent (MEK) to the pot and mixing them for 5 hours.

  Using the obtained ceramic slurry, a green sheet (ceramic green sheet for low-temperature firing) 21 having a thickness of 0.15 mm was obtained by a doctor blade method as shown in FIG.

<Manufacture of shrinkage suppression sheet>
In addition to the step of producing the green sheet 21, in order to produce the shrinkage suppression sheet 23 shown in FIG. 5B, the ceramic raw material powder has an average particle size of 3 μm and a specific surface area of 1 m ² / g. Alumina powder was prepared.

Furthermore, an acrylic binder was prepared as a binder component during sheet formation, DOP as a plasticizer component, and MEK as a solvent.
Then, similarly to the green sheet 21, after the alumina powder was charged into the pot made of alumina, the acrylic resin and the plasticizer (DOP) were charged, and further the solvent (MEK) was charged to obtain a slurry. .

Using this slurry, a shrinkage suppression sheet 23 having a thickness of 0.30 mm was produced by a doctor blade method.
<Manufacture of multilayer ceramic substrate>
Next, as shown in FIG. 5C, a through hole (through hole) 25 was formed in the green sheet 21 by punching.

  Next, as shown in FIG. 5 (d), the through hole 25 is filled with a conductive paste (becomes an interlayer connection conductor portion (via) 13 after firing), an interlayer connection conductor formation portion (via formation portion). 27 was formed.

  This conductive paste for via 13 is made of ethyl cellulose as a resin in a powder raw material in which 20 parts by volume of borosilicate glass powder having a softening point of 760 ° C. is added to 100 parts by volume of silver powder having an average particle size of 3.5 μm. While adding resin, adding terpineol as a solvent, it knead | mixes with a 3 roll mill, and was produced.

  Next, as shown in FIG. 5E, the surface of the green sheet 21 is printed by a conductive paste so as to cover the surface of the via formation portion 27 and the like (later with the first internal wiring layer 9). The first internal wiring formation layer 29 which is a conductor pattern was formed.

  The conductive paste for the first internal wiring formation layer 29 is a powder material obtained by adding 5 parts by volume of a borosilicate glass powder having a softening point of 700 ° C. to 100 parts by volume of silver powder having an average particle size of 2.0 μm. In addition to adding ethyl cellulose resin as a resin, terpineol was added as a solvent, and kneading was carried out using a three-roll mill.

  Next, as shown in FIG. 5F, the surface of the first internal wiring formation layer 29 is printed with a conductive paste so as to cover the projection area in the thickness direction of the via formation portion 27 (later A push-up preventing layer 31 which is a conductor pattern (to be the second internal wiring layer 11) was formed.

  The conductive paste for the push-up preventing layer 31 is composed of 10 parts by volume of borosilicate glass powder having a softening point of 790 ° C. and 10 parts by volume of mullite as an inorganic filler with respect to 100 parts by volume of silver powder having an average particle diameter of 2 μm. In addition to adding ethylcellulose resin as a resin and adding terpineol as a solvent to a powder raw material to which is added, and kneading in a three-roll mill.

In addition, the borosilicate glass which is this crystallized glass is a SiO ₂ —Al ₂ O ₃ —B ₂ O ₃ —BaO—MgO glass as described above. Further, the glass transition point (Tg) of this borosilicate glass is 645 ° C., which is lower than the firing shrinkage start temperature (for example, 750 ° C.) described later. Moreover, the crystallization temperature (Tc) is 790 ° C., which is higher than the firing shrinkage start temperature and lower than the firing shrinkage start temperature + 150 ° C.

As the crystallization temperature of these crystallized glasses, for example, those in the range of 780 ° C. to 900 ° C. are used.
Moreover, in this embodiment, the content rate of the crystallized glass and the mullite in the inorganic component in the push-up prevention layer 31 is 20 volume% or more. In addition, as a ratio of crystallized glass and mullite, an equal amount is preferable.

Next, as shown in FIG. 5 (g), the green sheets 21 were laminated to form a green sheet laminate 33. In each green sheet 21, a via forming portion 27 corresponding to the via 13 and a first internal wiring corresponding to the first internal wiring layer 9 are formed at necessary positions corresponding to the fired multilayer ceramic layer 5. Since the members constituting the push-up preventing layer 31 corresponding to the layer 29 and the second internal wiring layer 11 are formed, by laminating them, the structure shown in FIG.
Next, as shown in FIG. 6A, the shrinkage suppression sheets 23 were laminated on both sides of the green sheet laminate 33 to form a green composite laminate 35.

  Next, with a press machine (not shown), while applying a pressing force of 0.2 MPa from both sides in the stacking direction of the green composite laminate 35, after degreasing, firing was performed at 850 ° C. for 30 minutes, and FIG. ), A composite laminated sintered body 39 (unsintered shrinkage suppression sheet 23 remains on the surface of the ceramic laminated body 37) was obtained.

  Next, as shown in FIG. 6 (c), the (unsintered) shrinkage suppression sheets 23 remaining on both main surfaces of the composite laminated sintered body 39 are removed with an ultrasonic cleaner using water as a medium. As a result, a ceramic laminate 37 was obtained.

Thereafter, both outer surfaces of the ceramic laminate 37 were polished by lapping using alumina abrasive grains.
Next, as shown in FIG. 6 (d), for example, after a Ti thin film is formed by sputtering on the surface of the polished ceramic laminate 37 (that is, the multilayer ceramic substrate 5) corresponding to the via 13, it is sequentially formed. Then, Cu plating, Ni plating, and Au plating were performed to form an electrode 7 to complete the multilayer ceramic substrate 5.

c) Next, the effect of this embodiment will be described.
In the present embodiment, when the multilayer ceramic substrate 5 is manufactured, before laminating the green sheets 21, it is at the same position as the via formation portion 27 in plan view and at least one of the via formation portions 27 in the thickness direction. In addition, a push-up preventing layer 31 including a conductor, crystallized glass, and mullite is formed so as to be in contact with the via forming portion 27 directly or via the first internal wiring forming layer 29. At the same time, as the crystallized glass of the push-up preventing layer 31, the glass transition point (Tg) is lower than the firing shrinkage start temperature, and the crystallization temperature (Tc) is higher than the firing shrinkage start temperature and the firing shrinkage start temperature + 150 ° C. Use low material.

  Thereby, productivity can be made higher than before. In addition, even when the shrinkage in the thickness direction is large during firing, the push-up of the via forming portion 27 can be suppressed, so that the occurrence of deformation or disconnection in the substrate can be reduced.

  In this embodiment, since the area of the push-up prevention layer 31 is larger than the area of the via formation part 27, even when the via formation part 27 shows a behavior that pushes up the push-up prevention layer 31 during firing. Deformation and disconnection due to push-up are unlikely to occur.

Furthermore, in this embodiment, since the crystallization temperature of crystallized glass is in the range of 780 ° C. to 900 ° C., deformation and disconnection due to push-up are less likely to occur from this point.
Moreover, in the present embodiment, the content ratio of crystallized glass and mullite with respect to all inorganic materials of the push-up preventing layer 27 is 20% by volume or more, so that there is an advantage that deformation and disconnection due to further push-up hardly occur.
<Experimental example>
Next, experimental examples conducted for confirming the effects of the present invention will be described.

(1) Experimental example 1
In this Experimental Example 1, the conduction in the multilayer ceramic substrate was examined.
First, a plurality of multilayer ceramic substrates used for the experiment were manufactured by the same manufacturing method as in the above embodiment.

  Specifically, as shown in Table 1 below (inorganic component), the crystallized glass and inorganic filler used were changed to produce a conductor paste for the push-up preventing layer 31. Other conditions (for example, conductors of conductor paste, resin and solvent, compositions of other conductor pastes, compositions of green sheets, etc.) are the same as in the above embodiment.

Then, using these materials, samples in the range of the present invention (Examples 1 to 4) and samples outside the range of the present invention (Comparative Examples 1 to 4) are prepared in the same procedure as in the above embodiment. did.
Specifically, the crystallized glass of Examples 1 and 4 is a SiO ₂ —Al ₂ O ₃ —B ₂ O ₃ —BaO—MgO system (GA60 manufactured by Nippon Electric Glass Co., Ltd.). Is an Nd ₂ O ₃ —TiO ₂ —SiO ₂ system (GA55 manufactured by Nippon Electric Glass Co., Ltd.), and the crystallized glass of Example 3 is an SiO ₂ —CaO—MgO—ZnO system (manufactured by Nippon Electric Glass Co., Ltd.). GA63). Moreover, the crystallized glass of Comparative Examples 2 and 4 is SiO ₂ —Al ₂ O ₃ —B ₂ O ₃ —BaO—MgO (GA60 manufactured by Nippon Electric Glass Co., Ltd.), and the crystallized glass of Comparative Example 3 is It is a SiO ₂ —B ₂ O ₃ —ZnO system (ASF 1891 manufactured by Asahi Glass Co., Ltd.). In Comparative Example 1, crystallized glass is not used.

  Then, with respect to the multilayer ceramic substrate of each sample, as shown in FIG. 7A, two vias (X) are formed in the internal wiring layer (Y) (the second internal wiring at a predetermined position of the first internal wiring layer). The conduction between the conduction paths connected in the layer in which the layers were laminated) was confirmed.

Specifically, the conduction between the vias was confirmed with respect to 30 such conduction paths, and the occurrence rate (%) of the conduction failure (non-conduction) was obtained. The results are shown in Table 1 below.
(2) Experimental example 2
In this Experimental Example 2, the multilayer ceramic substrate of each sample used in Experimental Example 1 was broken in the thickness direction along the via, and as shown in FIG. The amount of protrusion at the via portion of the internal wiring layer: wiring deformation amount Δh) was measured.

  Specifically, the deformation amount at 40 locations for each sample was measured 200 times with an optical microscope having a length measuring function, and the average value was obtained. The results are shown in Table 1 below.

  As apparent from Table 1, in Examples 1 to 4 within the scope of the present invention, since the conditions of claims 1 and 5 are satisfied, the amount of deformation of the wiring is small, and hence the occurrence rate of poor conduction is small. It turns out that it is.

In Example 4, since the total amount of crystallized glass and mullite is 20% by volume or less, the viscosity of the push-up preventing layer is somewhat low, and therefore, it is considered that the performance is inferior to other examples.
On the other hand, in Comparative Example 1, since crystallized glass is not used, a sufficient viscosity cannot be obtained in the push-up preventing layer above the shrinkage start temperature of the ceramic. Absent.

Further, in Comparative Example 2, since mullite is not used, a sufficient viscosity cannot be obtained in the push-up prevention layer, and therefore, the amount of wiring deformation and the occurrence rate of continuity failure are not preferable.
Furthermore, in Comparative Example 3, the crystallization temperature is lower than the ceramic shrinkage start temperature, and the push-up prevention layer becomes brittle. Therefore, the amount of wiring deformation and the occurrence rate of poor conduction are not preferable.

Moreover, in the comparative example 4, since alumina is used, the amount of wiring deformation and the occurrence rate of continuity failure are not preferable.
In addition, this invention is not limited to the said embodiment and Example at all, and it cannot be overemphasized that it can implement with a various aspect in the range which does not deviate from this invention.

(1) For example, a shrinkage suppression sheet may be disposed only on one side of the green laminate.
(2) Moreover, it is not necessary to pressurize at the time of baking.

DESCRIPTION OF SYMBOLS 1 ... IC inspection board 3 ... Ceramic layer 5 ... Multilayer ceramic substrate 7 ... Electrode 9 ... 1st internal wiring layer 11 ... 2nd internal wiring layer 13 ... Interlayer connection conductor part (via)
21 ... Green sheet 23 ... Shrinkage suppression sheet 27 ... Interlayer conductor formation part (via formation part)
DESCRIPTION OF SYMBOLS 29 ... 1st internal wiring formation layer 31 ... Push-up prevention layer 33 ... Green sheet laminated body 35 ... Green composite laminated body 37 ... Ceramic laminated body

Claims (8)

A plurality of ceramic layers are laminated, a first internal wiring layer disposed between the ceramic layers, and an interlayer connection conductor portion that penetrates in the thickness direction of the ceramic layer and is electrically connected to the first internal wiring layer In a method for manufacturing a multilayer ceramic substrate comprising:
A green sheet laminate is formed by laminating a plurality of green sheets having an interlayer connection conductor forming portion that becomes the interlayer connection conductor portion after firing and a first internal wiring formation layer that becomes the first internal wiring layer after firing. A first step of
A second step of forming a green composite laminate by laminating a shrinkage suppression sheet not sintered at a temperature at which the green sheet laminate is sintered on at least one surface of the green sheet laminate;
A third step of degreasing and firing the green composite laminate to form a ceramic laminate;
A fourth step of removing the unsintered layer of the shrinkage suppression sheet remaining on the surface of the ceramic laminate after the firing;
A fifth step of forming a surface conductor layer on the surface of the ceramic laminate after removing the unsintered layer, and
Before laminating the green sheet, it is at the same position as the interlayer connection conductor formation portion in plan view, and directly with the interlayer connection conductor formation portion at least in the thickness direction of the interlayer connection conductor formation portion. Or forming a push-up preventing layer that is a conductive second internal wiring layer including a conductor, crystallized glass, and mullite so as to be in contact with each other via the first internal wiring formation layer;
As the crystallized glass, a material having a glass transition point (Tg) lower than the firing shrinkage start temperature and a crystallization temperature (Tc) higher than the firing shrinkage start temperature and lower than the firing shrinkage start temperature + 150 ° C. is used. A method for producing a multilayer ceramic substrate.   2. The method of manufacturing a multilayer ceramic substrate according to claim 1, wherein an area of the first internal wiring formation layer is larger than an area of the interlayer connection conductor formation portion in a plan view.   The method for producing a multilayer ceramic substrate according to claim 1 or 2, wherein the crystallization temperature of the crystallized glass is in a range of 780C to 900C.   The content rate of the said crystallized glass with respect to all the inorganic materials in the material which comprises the said push-up prevention layer, and the said mullite is 20 volume% or more, The any one of Claims 1-3 characterized by the above-mentioned. A method for producing a multilayer ceramic substrate. A ceramic laminate in which a plurality of ceramic layers are laminated, a first internal wiring layer disposed in a planar direction between the ceramic layers, and electrically passing through the ceramic layer in the thickness direction to the first internal wiring layer In a multilayer ceramic substrate provided with connected interlayer connection conductors,
It is in the same position as the interlayer connection conductor in plan view, and contacts at least one of the interlayer connection conductors in the thickness direction directly with the interlayer connection conductor or via the first internal wiring layer And having a second internal wiring layer including a conductor, crystallized glass, and mullite and having conductivity,
The crystallized glass is
A multilayer ceramic substrate having a glass transition point (Tg) lower than a firing shrinkage start temperature and a crystallization temperature (Tc) higher than the firing shrinkage start temperature and lower than the firing shrinkage start temperature + 150 ° C.   6. The multilayer ceramic substrate according to claim 5, wherein an area of the second internal wiring layer is larger than an area of the interlayer connection conductor portion in a plan view.   The crystallization temperature of the crystallized glass is in the range of 780 ° C to 900 ° C, and the multilayer ceramic substrate according to claim 5 or 6.   8. The multilayer ceramic substrate according to claim 5, wherein a content ratio of the crystallized glass and the mullite in the second internal wiring layer is 20% by volume or more.