JP2013090519A - Power source system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power source system of a digital control type having a plurality of DCDC converters connected together in parallel, the power source system capable of suitably preventing generation of difference in on-switching timings of respective switching elements of the DCDC converters due to delay in transmission of a synchronization pulse.SOLUTION: A master controller 16a outputs a synchronization pulse in a predetermined cycle to each of first and second slave controllers 16b and 16c, and resets its own counter value when the counter value reaches a specified value. Further, the first and second slave controllers 16b and 16c resets their respective counter values upon input of a synchronization pulse. With the above configuration, the master controller 16a accelerates output of a synchronization pulse by delay time due to compound delay with regard to the reset timing of its own counter value.

Description

  The present invention includes a plurality of power conversion devices that have a controller for turning on and off switching elements, and that convert and output an input voltage to a predetermined value by turning on and off the switching elements, and the plurality of power conversion devices are connected in parallel. The present invention relates to a power system.

  Conventionally, as can be seen, for example, in Patent Document 1 below, there is known an analog control type power supply system that supplies power to a load by a plurality of DCDC converters connected in parallel. Specifically, in this system, each of a plurality of DCDC converters is provided with a controller, and each of these controllers operates a switching element of the DCDC converter provided therein. In each of these controllers, the output voltage of the DCDC converter and the target voltage are compared by a comparator, and the output signal of the comparator based on the comparison result and the carrier (for example, a triangular wave or a sawtooth wave) are compared in magnitude. And based on this magnitude comparison result, an operation signal (PWM signal) for turning on / off the switching element is generated and output to the switching element. As a result, the output voltage of the DCDC converter is feedback-controlled to the target voltage.

JP 2009-1000051 A

  Further, as a power supply system, there is a digital control system in addition to the analog control system. In a digital control type power supply system, the switching element is normally turned on and off as follows in each of the plurality of controllers.

  At least one of the plurality of controllers (hereinafter referred to as a master controller) outputs a reference signal at an ON / OFF operation cycle of a switching element corresponding to the controller. Further, the master controller sets the switching timing of the switching element corresponding to the master controller in association with the output timing of the reference signal. On the other hand, a controller (hereinafter referred to as a slave controller) other than the master controller among the plurality of controllers sets the switching timing of the switching element corresponding to the controller to the ON state in relation to the input timing of the reference signal.

  Here, when the reference signal is transmitted through the signal path in each controller or the signal path connecting between the master controller and the slave controller, the reference signal is transmitted from the master controller due to the time delay in the transmission of the reference signal. A certain delay time may be required from when a signal is output until this signal is input to the slave controller. At this time, the input timing of the reference signal in the slave controller is delayed from the output timing of the reference signal in the master controller, the switching timing of the switching element corresponding to the slave controller to the ON state, and the switching element corresponding to the master controller There is a concern that the time interval with the switching timing to the ON state may deviate from what was initially assumed. In this case, the output characteristics of the parallel-connected body of the DCDC converter may deviate from what was initially assumed.

  Such a problem is not limited to a digital control type power conversion device, and may occur even in an analog control type.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to turn on each switching element of a plurality of power converters in a power supply system in which a plurality of power converters are connected in parallel. It is in providing the power supply system which can suppress suitably that the switching timing of this shifts | deviates from an appropriate thing.

  Hereinafter, means for solving the above-described problems and the operation and effects thereof will be described.

  The invention according to claim 1 includes a plurality of power conversion devices having a controller for turning on / off a switching element, and a plurality of power conversion devices that convert an input voltage into a predetermined output by turning on / off the switching element. In a power supply system in which devices are connected in parallel, the controller is provided in each of the plurality of power conversion devices and the switching element of the power conversion device provided therein is operated, and the plurality of controllers And at least one of the controllers outputs a reference signal at an on / off operation cycle of the switching element corresponding to itself to the other controller, and the controller that outputs the reference signal The reference signal indicates the switching timing of the switching element corresponding to The controller that does not output the reference signal among the plurality of controllers associates the switching timing of the switching element corresponding to itself with the input timing of the reference signal. The controller that sets and outputs the reference signal, based on a delay time required for transmission of the reference signal from the controller to a controller that does not output the reference signal, the switching timing corresponding to itself and the output timing of the reference signal, The process of setting the time interval is performed.

  A certain delay time may be required to transmit the reference signal from a controller (hereinafter referred to as a master controller) that outputs a reference signal among a plurality of controllers to another controller (hereinafter referred to as a slave controller). Here, in the above invention, based on the delay time, the master controller performs a process of setting a time interval between the switch-on timing corresponding to itself and the output timing of the reference signal. According to such an invention, the input timing of the reference signal to the slave controller is greatly delayed from the output timing of the reference signal of the master controller, so that the switching timing to the ON state corresponding to the slave controller and the above corresponding to the master controller It is possible to suppress the time interval with the switching timing to the ON state from greatly deviating from the initially assumed time interval. Thereby, it can suppress that the output characteristic of a power supply system shift | deviates from what was initially assumed.

  According to a second aspect of the invention, in the first aspect of the invention, the reference signal includes the switching timing corresponding to a controller that outputs the reference signal and the switching timing corresponding to a controller that does not output the reference signal. The controller that outputs the reference signal is a process for setting the reference signal output timing earlier with respect to the switching timing corresponding to the controller as the delay time is longer. It is characterized by performing.

  In the above-described invention, the reference signal output from the master controller corresponds to the switching timing corresponding to the master controller and the slave controller so that the requested current of the power supply destination of the power supply system is equally shared among the plurality of power conversion devices. This is used to match the switching timing. Here, if the switching timing corresponding to each of the plurality of controllers is shifted due to the delay time, the current burden of the power conversion device provided with the switching element that has been switched to the ON state first increases, and the current burden is increased. There is a risk that the reliability of the power converter that becomes large may be reduced.

  In this regard, in the above-described invention, in the master controller, the longer the delay time, the faster the output timing of the reference signal with respect to the switching timing corresponding to the master controller. For this reason, it can suppress that the said switching timing corresponding to each of a some controller shifts | deviates, and can suppress that the electric current burden of a specific power converter device becomes large resulting from the said delay time. . Thereby, the fall of the reliability of a power supply system can be suppressed suitably.

  According to a third aspect of the present invention, in the first or second aspect of the invention, the controller performs an on / off operation of the switching element by a binary signal, and the reference signal is supplied to at least one of the plurality of controllers. A time difference detecting means for detecting a time difference between a logic inversion timing of the binary signal generated by the controller that outputs and a logic inversion timing of the binary signal generated by the controller that does not output the reference signal; The controller that outputs the reference signal further performs a process of variably setting the time interval based on the time difference detected by the time difference detection means.

  In the master controller, there may occur a situation in which the time interval between the switching timing corresponding to itself and the output timing of the reference signal deviates from an appropriate one. This is because, for example, the delay time changes due to aging degradation of the power supply system, or the delay time differs for each power supply system due to individual differences in the power supply systems. Here, the time difference between the logic inversion timing of the binary signal generated by the master controller and the logic inversion timing of the binary signal generated by the slave controller may change due to aging of the power supply system. The time difference can be different for each power supply system. Focusing on these points, the time difference is considered to be an index for determining the time interval.

  In view of this point, in the above invention, the time interval is variably set based on the time difference detected by the time difference detection means. Thereby, the influence which aged deterioration etc. of a power supply system exert on the said time interval can be suppressed suitably.

  The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein a plurality of controllers that do not output the reference signal are a plurality of controllers, and a controller that outputs the reference signals is In the setting process, the time interval is set based on a delay time other than the minimum value among the delay times required for transmission of the reference signal from the controller that outputs the reference signal to each of the controllers that do not output the reference signal. A delay that is shorter than the delay time used in the setting process among the delay times required for transmitting the reference signal from the controller that outputs the reference signal to each of the controllers that do not output the reference signal. For the controller that does not output the reference signal corresponding to time, the acquisition timing of the reference signal is delayed. Further, a delay means for extending is further provided.

  The delay times between the master controller and the slave controller may be different from each other. In this case, even if the processing for setting the time interval is performed in the master controller, there is a possibility that the situation in which the switching timing corresponding to each of the plurality of power conversion devices is not properly deviated can be appropriately suppressed. . Here, in the above invention, by providing the delay means, the slave controller delays the acquisition timing of the reference signal serving as a reference for determining the switching timing. As a result, even when the delay times between the master controller and the slave controller are different from each other, the influence of the difference on the shift in the switching timing can be suitably suppressed.

  According to a fifth aspect of the invention, in the invention of the fourth aspect, the controller turns on and off the switching element by a binary signal, and outputs the reference signal to at least one of the plurality of controllers. Means for detecting each of the time differences between the logic inversion timing of the binary signal generated by the controller and the logic inversion timing of the binary signal generated by each of the controllers not outputting the reference signal; The delay unit variably sets a delay degree of the acquisition timing of the reference signal based on each of the detected time differences.

  The time difference between the logic inversion timing of the binary signal generated by the master controller and the logic inversion timing of the binary signal generated by each of the slave controllers is different from the output timing of the reference signal of the master controller and the slave controller. This is an index for grasping the degree of deviation from the input timing of each reference signal. In view of this point, in the above invention, the delay degree of the acquisition timing of the reference signal is variably set in the above manner by the delay means. As a result, it is possible to suppress the occurrence of a situation where the delay degree of the reference signal acquisition timing is deviated from an appropriate one due to deterioration of the power system over time.

The lineblock diagram of the power supply system concerning a 1st embodiment. The figure which shows the generation | occurrence | production factor of the transmission delay of a synchronous pulse. The figure which shows an example of the transmission delay aspect of the synchronous pulse concerning a prior art. The figure which shows an example of the output timing advance process concerning 1st Embodiment. The block diagram of the power supply system concerning 2nd Embodiment. The figure which shows the processing content of the comparison value setting process concerning the embodiment. The figure which shows the outline | summary of the delay adjustment part concerning 3rd Embodiment. The figure which shows the processing content of the comparison value setting process and delay time adjustment process concerning the embodiment.

(First embodiment)
Hereinafter, a first embodiment in which a digital control type power supply system according to the present invention is applied to a hybrid vehicle including a rotating machine and an engine as an in-vehicle main machine will be described with reference to the drawings.

  FIG. 1 shows the overall configuration of the power supply system according to the present embodiment.

  The illustrated high voltage battery 10 is an in-vehicle load power supply source on the in-vehicle high voltage system side, and is a storage battery having a predetermined high voltage of, for example, several hundred volts or more. In addition, as said vehicle-mounted load, there exists a rotary machine (motor generator) which is not shown in figure as a vehicle-mounted main machine, for example. Moreover, as the high voltage battery 10, for example, a lithium ion storage battery or a nickel hydride storage battery can be employed.

  The high voltage battery 10 is connectable to a plurality (three) of DCDC converters 12a, 12b, 12c connected in parallel. The output sides of these DCDC converters 12a, 12b, and 12c are connected to the vehicle load 13 on the vehicle low voltage system side. In the present embodiment, a low-voltage battery or an engine driving actuator (a fuel injection valve or the like) is assumed as the in-vehicle load 13. The low voltage battery is a storage battery (for example, a lead storage battery) that outputs a predetermined low voltage (for example, 12 V).

  By the way, in this embodiment, hereinafter, among these DCDC converters 12a, 12b, and 12c, 12a is referred to as a master DCDC, 12b is referred to as a first slave DCDC, and 12c is referred to as a second slave DCDC.

  In the present embodiment, the structure and performance of the master DCDC 12a, the first slave DCDC 12b, and the second slave DCDC 12c are the same. For this reason, in the present embodiment, the details of the DCDC converter will be described below centering on the master DCDC 12a, and detailed illustration of the inside of the second slave DCDC 12c is omitted. Further, the first slave DCDC 12b and the second slave DCDC 12c are basically labeled according to the symbols given to the master DCDC 12a.

  The master DCDC 12a is a digital control type power conversion device configured to include a power conversion circuit 14a and a controller (hereinafter referred to as a master controller 16a). Specifically, the master DCDC 12a is configured such that these components are mounted on a circuit board (for example, a single circuit board) and the circuit board is housed in a casing (case), and the voltage of the high-voltage battery 10 is reduced. This is an isolated converter that outputs.

  The power conversion circuit 14a includes a series connection of a pair of switching elements Sp1 and Sn1, a parallel connection of a series connection of a pair of switching elements Sp2 and Sn2 (full bridge circuit), and a transformer 18. Yes. Here, in this embodiment, an N-channel MOS transistor is assumed as the switching element Sjk (j = p, n, k = 1, 2).

  The input terminals (drains) of the switching elements Sp1 and Sp2 on the high potential side are connected to the positive electrode side of the high voltage battery 10, and the output terminals (sources) of the switching elements Sn1 and Sn2 on the low potential side are the negative electrode side of the high voltage battery 10. It is connected to the. A parasitic diode or a free wheel diode (not shown) of the switching element Sjk is connected between the drain and source of the switching element Sjk.

  Both ends of the primary side coil 18t of the transformer 18 are connected to the connection point of the pair of switching elements Sp1 and Sn1 and the connection point of the pair of switching elements Sp2 and Sn2, respectively.

  Both ends of the secondary side coil 18s of the transformer 18 are connected to the anode sides of the diodes RD1 and RD2, and the cathode sides of the diodes RD1 and RD2 are short-circuited. The diodes RD1 and RD2 are connected to a smoothing circuit 20 (LC filter) including a reactor 20t and a capacitor 20s.

  The primary side of the high-voltage battery 10 and the master DCDC 12a constitutes a high-voltage system and is insulated from the ground line GL connected to the case of the master DCDC 12a. On the other hand, the secondary side of the master DCDC 12a constitutes a low voltage system that operates using the ground line GL as a reference potential.

  For this reason, in this embodiment, the midpoint tap mt of the secondary side coil 18s of the transformer 18 is connected to the ground line GL. According to such a configuration, the diodes RD1 and RD2 are configured such that the high-potential side switching element Sp1 and the low-potential side switching element Sn2 are turned on, or the high-potential side switching element Sp2 and the low-potential side switching element Sn1. Depending on whether or not is turned on, a voltage of “½” of the voltage across the secondary coil 18s is alternately output. The midpoint tap mt is a terminal connected to the center of the secondary side coil 18s of the transformer 18 (the midpoint that is equidistant from both terminals).

  On the primary side of the master DCDC 12a, an input side voltage sensor 22 for detecting the input voltage of the full bridge circuit is provided. Further, an output side voltage sensor 26 for detecting the output voltage of the master DCDC 12a (the output voltage from the smoothing circuit 20) is provided on the secondary side of the master DCDC 12a.

  The master controller 16a includes a counter unit 30a, a PWM comparison value generator 32a, a PWM signal generator 34a, a synchronization pulse generator 36a, and a synchronization pulse comparison value generator 38a, and supplies power to the in-vehicle load 13. Therefore, it is a digital processing means for generating an operation signal gjk for turning on / off the switching element Sjk via the driver circuit 27.

  Specifically, the counter unit 30a counts up the counter value in synchronization with a clock (master clock) input at a predetermined cycle. The counter unit 30a resets its own counter value when its own counter value reaches the upper limit value. That is, the counter value is a sawtooth signal (carrier) generated by digital processing.

  The PWM comparison value generator 32a sets the PWM comparison value based on the detection values of the input side voltage sensor 22 and the output side voltage sensor 26. The PWM comparison value is basically set as an operation amount for feedback control of the output voltage of the master DCDC 12a to the target voltage. Specifically, for example, proportional integral control (PI) based on the deviation between the output voltage and the target voltage is used. Control). Here, as the PWM comparison value is set to be larger, the duty “Ton / Tα” of the switching element ON time Ton relative to the specified time Tα is increased. Note that the PWM comparison value is a value within the range of the lower limit value and the upper limit value of the counter value.

  Incidentally, since the high voltage system and the low voltage system are insulated by an insulating element (for example, a photocoupler) (not shown), the detection value of the input side voltage sensor 22 is transmitted to the PWM comparison value generator 32a via the insulating element. Entered. The detected value as an analog signal is converted into a digital signal by an AD converter (not shown), and then used for calculating a PWM comparison value.

  The PWM signal generator 34a is a PWM signal (binary signal) as the operation signal gjk based on the magnitude comparison between the counter value output from the counter unit 30a and the PWM comparison value output from the PWM comparison value generator 32a. Is generated. More specifically, a logic “H” PWM signal is generated when the counter value is smaller than the PWM comparison value, and a logic “L” PWM signal is generated when the counter value is equal to or greater than the PWM comparison value.

  Here, in the present embodiment, the PWM signal is supplied to each of the DCDC converters 12a to 12c so that the on-timing of the switching element Sjk is synchronized in each of the master DCDC 12a, the first slave DCDC 12b, and the second slave DCDC 12c. Generate. This is because the DCDC converters 12a to 12c are equally burdened with the required current of the in-vehicle load 13.

  The generated PWM signal gjk is transmitted to the open / close control terminal (gate) of the switching element Sjk via the PWM output terminal 40a and the driver circuit 27, whereby the switching element Sjk is turned on / off. Further, since the counter value is reset at a predetermined cycle by the counter unit 30a, the time interval (reset cycle) at which the counter value is reset becomes the switching cycle of the switching element.

  In the present embodiment, as described above, the PWM signal for each of the switching elements Sjk is set so that the pair of switching elements Sp1 and Sn2 and the pair of switching elements Sp2 and Sn1 are basically turned on and off alternately. Generated. This generation method will be described by taking the master controller 16a as an example. Specifically, for example, a PWM signal for the switching element Sp1 is generated by comparing a counter value and a PWM comparison value, and the generated PWM signal for the switching element Sp1 is converted into a PWM signal. A PWM signal for the switching element Sn1 is generated by performing a logic inversion process and a dead time generation process. Then, a PWM signal for the switching elements Sp2 and Sn2 is generated by subjecting the generated PWM signals for the switching elements Sp1 and Sn1 to a phase shift process of logic inversion timing.

  Incidentally, the method of generating the PWM signal is not limited to the method described above, and for example, the following method may be used. First, a PWM signal for the switching element Sp2 is generated by comparing the size of the counter value and the PWM comparison value, and a logic inversion process and a dead time generation process are performed on the generated PWM signal for the switching element Sp2, thereby generating a PWM signal for the switching element Sn2. Is generated. Then, a PWM signal for the switching elements Sp1 and Sn1 is generated by subjecting the generated PWM signals for the switching elements Sp2 and Sn2 to a phase shift process at a logic inversion timing.

  Further, as a method for generating the PWM signal, for example, the following method may be used. First, a PWM signal for each of the switching element Sp1 and the switching element Sp2 is generated separately by comparing the counter value and the PWM comparison value. Next, a PWM signal for each of the switching element Sn1 and the switching element Sn2 is generated by performing a logic inversion process and a dead time generation process on the PWM signal generated for each of the switching element Sp1 and the switching element Sp2.

  The master controller 16a further resets its counter value from the synchronization pulse output terminal 42a in order to make the first slave controller 16b and the second slave controller 16c know the reference timing for generating the PWM signal. A synchronization pulse is output as a reference signal. Specifically, a synchronization pulse is generated and output based on a magnitude comparison between the counter value output from the counter unit 30a and the synchronization pulse comparison value output from the synchronization pulse comparison value generator 38a. More specifically, a synchronization pulse is generated and output at a timing at which the counter value matches the synchronization pulse comparison value. The sync pulse comparison value is a value within the range of the lower limit value and the upper limit value of the counter value.

  The synchronization pulse output from the synchronization pulse output terminal 42a is input to the counter unit 30b of the first slave controller 16b via the synchronization pulse input pin 44b of the first slave controller 16b and the second slave controller 16c. Are input to a counter unit (not shown) of the second slave controller 16c via a synchronization pulse input pin (not shown).

  Each of the counter units of the first slave controller 16b and the second slave controller resets its counter value at the timing when the synchronization pulse is input thereto.

  Incidentally, as described above, although the master DCDC 12a, the first slave DCDC 12b, and the second slave DCDC 12c have the same structure, the master controller 16a does not need a synchronization pulse input function. For this reason, in this embodiment, the synchronous pulse input terminal 44a of the master controller 16a is not used. Further, since no sync pulse is output from the slave controllers 16b and 16c, the sync pulse output terminals of the slave controllers 16b and 16c are not used.

  Next, output timing advance processing according to the present embodiment will be described. This process is a process for advancing the output timing of the synchronization pulse with respect to the reset timing of the counter value in the master controller 16a. Hereinafter, the reason why the output timing advance processing is employed and details of this processing will be described.

  A certain delay time may occur from when the synchronization pulse is output from the synchronization pulse generator 36a of the master controller 16a to when the synchronization pulse is input to the counter units of the first and second slave controllers 16b and 16c. As shown in FIG. 2, this occurs due to various delay factors such as logic delay, element delay, and signal line delay.

  Specifically, the logic delay is a delay caused by a predetermined time required for a predetermined process executed in each controller. The element delay is a delay caused by various elements that are signal paths in each controller. Furthermore, the propagation delay is a delay caused by a signal path connecting the controllers. Hereinafter, in this embodiment, these delays are collectively referred to as a composite delay.

  In addition, not only a synchronous pulse but the delay about the PWM signal produced | generated by each controller (each DCDC converter) may also arise. The delay of the PWM signal will be described by taking the master DCDC 12a as an example. The delay caused by the PWM signal output from the PWM signal generator 34a being transmitted through the driver circuit 27 (driver delay) and the output from the driver circuit 27 There is a delay (switching element delay) due to the fact that a certain time is required until the switching element is actually turned on after the PWM signal to be transmitted is transmitted to the gate of the switching element.

  When the composite delay occurs, for example, when a control logic for synchronizing the output timing of the synchronization pulse and the reset timing is adopted in the master controller 16a, as shown in FIG. 3, the reset timing of each counter value in the master controller 16a Therefore, the reset timing of each counter value of the first slave controller 16b and the second slave controller 16c is shifted.

  Specifically, FIG. 3A-1 shows the transition of the counter value of the counter unit 30a of the master controller 16a, and FIG. 3B-1 shows the PWM output from the PWM signal generator 34a of the master controller 16a. FIG. 3C-1 shows the transition of the sync pulse output from the sync pulse generator 36a of the master controller 16a. FIG. 3A-2 shows the transition of the counter value of the counter unit 30b of the first slave controller 16b, and FIG. 3B-2 shows the PWM signal generator 34b of the first slave controller 16b. FIG. 3C-2 shows the transition of the synchronization pulse input to the counter unit 30b of the first slave controller 16b. Incidentally, in FIG. 3, the operation state of the second slave controller 16c is omitted. FIG. 3 shows only one of the PWM signals gjk for the four switching elements Sjk generated by each controller.

  In the illustrated example, a synchronization pulse is output at time t1, which is the reset timing of the counter value of the master controller 16a. This synchronization pulse is input to the counter unit 30b of the first slave controller 16b at time t2 with a delay time due to the composite delay.

  When a transmission delay of the synchronization pulse occurs, even if the counter value reset timing of the master controller 16a and the counter value reset timing of the first slave controller 16b are intended to be synchronized, this cannot be realized. The on-switching timings of the switching elements corresponding to the master DCDC 12a and the first slave DCDC 12b are shifted from each other. In this case, since the current burden of the DCDC converter corresponding to the switching element that has been switched to the ON state first becomes large, the current burden of a specific DCDC converter among the DCDC converters 12a, 12b, and 12c included in the power supply system is large. There is a risk. In this case, the reliability of the power supply system may be reduced.

  In order to solve such a problem, in the present embodiment, the output timing advance processing is performed in the master controller 16a. Here, the degree to which the synchronization pulse output timing is advanced with respect to the reset timing in the master controller 16a is increased as the delay time is longer. This can be realized by setting the synchronization pulse comparison value generated by the synchronization pulse comparison value generator 38a. That is, the synchronization pulse comparison value is set smaller as the delay time is longer.

  FIG. 4 shows an example of the output timing advance processing according to the present embodiment. Specifically, each of FIGS. 4A-1 to 4C-2 corresponds to each of FIGS. 3A-1 to 3C-2.

  In the illustrated example, in the master controller 16a, the synchronization pulse output timing (time t1) is advanced from the reset timing (time t2) by the delay time caused by the composite delay. Therefore, the time difference between the counter value reset timing in the master controller 16a and the counter value reset timing in the first slave controller 16b can be intended (the reset timings can be synchronized). As a result, it is possible to suppress the deviation of the on-switching timings of the switching elements corresponding to each of the master controller 16a, the first slave controller 16b, and the second slave controller 16c, and the current load of these DCDC converters can be evenly distributed. Can be

  In the present embodiment, the sync pulse comparison value is a fixed value set in advance. Here, a method for setting the synchronization pulse comparison value will be described. For example, the following method can be adopted.

  First, in the shipping inspection of the manufacturing process of the power supply system, the logical inversion timing of the PWM signal output from the PWM output terminal 40a of the master controller 16a, the first slave controller 16b, and the first Each time difference from the logic inversion timing of the PWM signal output from each PWM output terminal of the second slave controller 16c is detected. Then, a synchronization pulse comparison value is determined based on the detected time difference. Here, when the detected time differences are substantially the same, any one of the detected time differences is selected, and the output timing of the synchronization pulse is advanced with respect to the reset timing of the master controller 16a by the selected time difference. A sync pulse comparison value that can be determined may be determined. On the other hand, if these detected time differences are significantly different, a synchronization pulse comparison that can advance the output timing of the synchronization pulse relative to the reset timing by the maximum value / minimum value of these time differences or the average value of these time differences. What is necessary is just to set a value.

  As described above, in the present embodiment, the output timing advance processing for advancing the output timing of the synchronization pulse with respect to the reset timing of its own counter value is performed in the master controller 16a. Thereby, the fall of the adjustment precision of the output voltage of each DCDC converter with which a power supply system is equipped can be suppressed, and the fall of the reliability of a power supply system can be avoided suitably by extension.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  FIG. 5 shows a configuration of the power supply system according to the present embodiment. In FIG. 5, the same members and the like as those shown in FIG. In FIG. 5, only the controller portion is mainly shown for each DCDC converter.

  As illustrated, the master controller 16a, the first slave controller 16b, and the second slave controller 16c are further provided with pulse measuring units 46a, 46b, and 46c, and communication units 48a, 48b, and 48c. Yes.

  The pulse measurement unit 46b of the first slave controller 16b receives the PWM signal output from the PWM output terminal 40b corresponding to itself and the PWM signal output from the PWM output terminal 40a of the master controller 16a. The pulse measurement unit 46c of the second slave controller 16c receives the PWM signal output from the PWM output terminal 40c corresponding to itself and the PWM signal output from the PWM output terminal 40a of the master controller 16a. The

  Each of the communication units 48 a, 48 b, 48 c has a function of transmitting the output signal of the pulse measurement unit corresponding to itself via the internal bus 50 to another communication unit.

  Next, the comparison value setting process according to the present embodiment will be described.

  In this process, first, a pair of PWM signals among the four PWM signals output from the master controller 16a and the four PWM signals output from the first slave controller 16b (second slave controller 16c). The time difference between the logic inversion timing of the PWM signal output from the master controller 16a and the logic inversion timing of the PWM signal output from the first slave controller 16b (second slave controller 16c) is calculated as a pulse measurement unit 46b (46c). ) To measure. Then, based on the measured time difference, the synchronization pulse comparison value is variably set so as to update the degree to which the synchronization pulse output timing is advanced with respect to the reset timing in the master controller 16a.

  FIG. 6 shows the contents of the comparison value setting process according to the present embodiment. Specifically, FIG. 6 shows the processing contents in each of the master controller 16a and the first slave controller 16b. Regarding the comparison value setting process, the processing contents of the first slave controller 16b and the second slave controller 16c are the same, and therefore the illustration of the second slave controller 16c is omitted in FIG. Yes. In the present embodiment, the comparison value setting process is executed when the power supply system is activated (a period during which the process for enabling the power supply system is executed).

  First, as shown in S10, a PWM signal is output from each of the master controller 16a and the first slave controller 16b. In the present embodiment, each controller outputs a PWM signal for a specific (one) switching element.

  Subsequently, as shown in S12, in the pulse measurement unit 46b of the first slave controller 16b, the logic of the PWM signal output from the PWM output terminal 40b corresponding to itself is inverted from “L” to “H”. And a time difference ΔT from the timing at which the logic of the PWM signal output from the PWM output terminal 40b of the master controller 16a is inverted from “L” to “H” is measured.

  Subsequently, as shown in S14, the time difference ΔT measured by the pulse measurement unit 46b of the first slave controller 16b is used to generate the synchronous pulse comparison value of the master controller 16a via the communication unit 48b, the internal bus 50, and the communication unit 48a. To the device 38a.

  Subsequently, as shown in S16, the synchronization pulse comparison value generator 38a sets a synchronization pulse comparison value based on the received time difference ΔT. Specifically, the longer the received time difference ΔT is, the more the synchronization pulse output timing is required to be earlier than the reset timing of the master controller 16a. Therefore, the longer the time difference ΔT is, the smaller the synchronization pulse comparison value may be set. .

  If the influence of the propagation delay caused by the signal path from the PWM output terminal 40a of the master controller 16a to the pulse measurement unit 46b of the first slave controller 16b is very small, the output timing of the synchronization pulse is set to the master by the time difference ΔT. A synchronization pulse comparison value that can be earlier than the reset timing of the controller 16a may be set.

  Thus, in the present embodiment, the comparison value setting process is performed. The delay time resulting from the composite delay may differ for each power supply system due to individual differences in the power supply systems. For this reason, according to the said process, the suitable synchronous pulse comparison value reflecting the individual difference of a power supply system can be defined.

  Also, according to such processing, the process related to the synchronization pulse comparison value adaptation in the manufacturing process of the power supply system is abolished on the condition that the comparison value setting process is performed at the time of starting the system after the power supply system is shipped. We can expect. In this case, the default value of the synchronization pulse comparison value may be, for example, a median value (a value determined in advance by experiments or the like) within a range that the comparison value can take.

  Further, the delay time may change due to aging degradation of the power supply system. For this reason, according to the comparison value setting process, it is possible to preferably avoid that the reset timing of the master controller 16a, the first slave controller 16b, and the second slave controller 16c greatly deviates due to the change in the delay time. it can.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to the drawings with a focus on differences from the second embodiment.

  In the present embodiment, as shown in FIG. 7, the first slave controller 16b and the second slave controller 16c are further provided with a first delay adjustment unit 52b and a second delay adjustment unit 52c. Then, a delay time adjustment process is performed by the delay adjustment units 52b and 52c. This process is a process for delaying the input timing of the synchronization pulse to the counter unit in the first and second slave controllers 16b and 16c. The master controller 16a, the first slave controller 16b, and the second slave controller This is a process for removing a shift in reset timing between 16c.

  That is, the delay times may be different between the controllers 16a, 16b, and 16c. In this case, the master controller 16a and the second slave controller 16c can be suppressed even if the shift of the reset timing between the master controller 16a and the first slave controller 16b can be suppressed by performing the output timing advance processing, for example. There is a possibility that a shift in reset timing between the two cannot be appropriately suppressed.

  FIG. 8 shows the processing contents of the delay time adjustment processing and the comparison value setting processing according to the present embodiment. In FIG. 8, the same processing contents as those in FIG. 6 are denoted by the same reference numerals for the sake of convenience. In the present embodiment, as in the second embodiment, the delay time adjustment process is executed together with the comparison value setting process when the power supply system is activated.

  First, as shown in S10a, a PWM signal is output from each of the master controller 16a, the first slave controller 16b, and the second slave controller 16c. In the present embodiment, the PWM signal for a specific (one) switching element is output in each controller, similar to the processing content of S10 of FIG.

  Subsequently, as shown in S12, in the pulse measurement unit 46b of the first slave controller 16b, the logic of the PWM signal output from the PWM output terminal 40b corresponding to itself is inverted from “L” to “H”. And the time difference (first time difference ΔT1) from the timing when the logic of the PWM signal output from the PWM output terminal 40b of the master controller 16a is inverted from “L” to “H”.

  Further, as shown in S18, in the pulse measurement unit 46c of the second slave controller 16c, the timing of the logic of the PWM signal output from the PWM output terminal 40c corresponding to itself is inverted from “L” to “H” Then, the time difference (second time difference ΔT2) from the timing at which the logic of the PWM signal output from the PWM output terminal 40b of the master controller 16a is inverted from “L” to “H” is measured.

  Subsequently, as shown in S14, the first time difference ΔT1 measured by the pulse measurement unit 46b of the first slave controller 16b is used as the synchronization pulse of the master controller 16a via the communication unit 48b, the internal bus 50, and the communication unit 48a. It transmits to the comparison value generator 38a. Further, as shown in S20, the second time difference ΔT2 measured by the pulse measuring unit 46c of the second slave controller 16c is used as the synchronous pulse comparison value generator 38a via the communication unit 48c, the internal bus 50, and the communication unit 48a. Send to.

  Subsequently, as shown in S16, the synchronization pulse comparison value generator 38a sets a synchronization pulse comparison value based on the received first time difference ΔT1 and second time difference ΔT2. In the present embodiment, a synchronization pulse comparison value is set such that the synchronization pulse output timing is advanced by the maximum value of the detected time difference with respect to the reset timing of the master controller 16a. For example, when the second time difference ΔT2 (60 nsec) reaches the maximum value, a synchronization pulse comparison value is set so that the synchronization pulse output timing is advanced by the second time difference ΔT2 with respect to the reset timing of the master controller 16a.

  Subsequently, as indicated by S22, the first delay adjustment time is set as a time obtained by subtracting the first time difference ΔT1 from the time advanced by the output timing advance processing. Specifically, for example, if the first time difference ΔT1 = 40 nsec and the second time difference ΔT2 = 60 nsec, 20 nsec is set as the first delay adjustment time. Then, the set first delay adjustment time is transmitted to the first delay adjustment unit 52b. As a result, as shown in S24, the first delay adjustment unit 52b performs the delay time adjustment process.

  On the other hand, as indicated by S26, the second delay adjustment time (0 nsec) is set as a time obtained by subtracting the second time difference ΔT2 from the time advanced by the output timing advance processing. And it transmits to the 2nd delay adjustment part 52c. Thereby, as shown in S28, the second delay adjustment unit 52c performs the delay time adjustment process. In the present embodiment, since the second delay adjustment time is “0”, the input timing of the synchronization pulse is not delayed by the delay time adjustment processing.

  As described above, in the present embodiment, the delay time adjustment process is performed together with the comparison value setting process, whereby the master controller 16a, the first slave controller 16b, and the second slave controller 16c have different delay times. Even if it exists, the shift | offset | difference of the reset timing of these controllers 16a, 16b, and 16c can be removed appropriately.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  In each of the above embodiments, one of the plurality of DCDC converters provided in the power supply system is the master DCDC. However, the present invention is not limited to this. For example, when four or more DCDC converters connected in parallel are provided, some of the DCDC converters may be part of the DCDC converters, and a plurality may be used as the master DCDC. Here, a power supply system provided with two master DCDCs will be described. For example, a plurality of DCDC converters provided in the power supply system are divided into a first group and a second group each including a pair of master DCDCs. The master DCDC may operate the power supply system by outputting a reference signal (synchronization pulse) to the slave DCDC of its own group.

  In each of the above embodiments, an up counter that counts up the counter value is used as the counter unit. However, the present invention is not limited to this, and a down counter that counts down the counter value may be used. In this case, for example, the counter unit 30a included in the master controller 16a resets its own counter value when its own counter value reaches its lower limit (“0”).

  The manner of generating the operation signal associated with its own counter value that is sequentially counted is not limited to the method based on the magnitude comparison between the counter value and the PWM comparison value. For example, a method may be employed in which a controller (for example, a non-volatile memory) that stores a pulse pattern of a PWM signal associated with a counter value is provided in a controller and a PWM signal is generated based on the pulse pattern.

  In each of the above embodiments, the sawtooth wave signal is used as the counter value (carrier) used for generating the PWM signal. However, the present invention is not limited to this, and for example, a triangular wave signal may be used.

  The DCDC converter provided in the power supply system is not limited to the same structure and performance, and the DCDC converters may have different structures and performance. In this case, the configurations of the master controller and the slave controller are also different, and the delay time is likely to be different between the master controller and each of the plurality of slave controllers. For this reason, it is considered that the merit of applying the output timing advance processing and delay time adjustment processing to such a power supply system is great.

  The method for determining the synchronization pulse comparison value is not limited to the one exemplified in the first embodiment. For example, by the external device, the output timing of the synchronization pulse from the synchronization pulse generator 36a or the synchronization pulse output terminal 42a of the master controller 16a and the respective synchronization pulse inputs of the first slave controller 16b and the second slave controller 16c. A time difference from the input timing of the synchronization pulse to the terminal or the counter unit may be detected, and the synchronization pulse comparison value may be determined based on the detected time difference.

  The method for updating the synchronization pulse comparison value is not limited to the one exemplified in the second embodiment. For example, the time difference between the master controller 16a and the first slave controller 16b is measured every time the power supply system is activated, and the measured time difference is stored in a storage unit (nonvolatile memory), and the stored time difference is stored. The sync pulse comparison value may be updated based on the change amount (for example, the change amount between the previous time difference and the current time difference). Specifically, for example, the synchronization pulse comparison value may be updated by increasing or decreasing the synchronization pulse comparison value according to the amount of change in the time difference. This method is due to the fact that the change in the time difference is correlated with the change in the degree of advancement of the synchronization pulse output timing due to the deterioration of the power supply system over time. In such a method, for example, the signal delay time due to the propagation delay in the signal path from the PWM output terminal 40a of the master controller 16a to the pulse measurement unit 46b of the first slave controller 16b is large, and synchronization is performed by the measured time difference. It is considered that this method is effective when the deviation of the reset timing between the controllers cannot be adjusted appropriately depending on the method of advancing the pulse output timing.

  In the second embodiment, the time difference of the logical inversion timing of the PWM signal is measured in the pulse measurement units of the first and second slave controllers 16b and 16c. However, the present invention is not limited to this, and the pulse measurement unit 46a of the master controller 16a. You may measure in.

  In each of the DCDC converters of the second and third embodiments, a sensor is provided on the high-voltage system side, such as a sensor that detects a voltage on the electrical path from the driver circuit 27 to the gate of the switching element Sjk, and the sensor on the high-voltage system side Comparison value setting processing and delay time adjustment processing may be performed using the detected values.

  Specifically, for example, a sensor for detecting the gate voltage of the switching element is provided, and in the first slave controller 16b, the logic of the PWM signal output from the PWM output terminal 40a of the master controller 16a is changed from “L” to “H”. And the timing at which the gate voltage of the switching element of the master DCDC 12a exceeds the threshold voltage that defines the ON state is measured. In the first slave controller 16b, the timing at which the logic of the PWM signal output from the PWM output terminal 40b of the controller 16b is inverted from “L” to “H”, and the gate of the switching element of the first slave DCDC 12b. The time interval from the timing when the voltage exceeds the threshold voltage is measured. Then, as the value obtained by subtracting the time interval corresponding to the master controller 16a from the time interval corresponding to the first slave controller 16b is larger than 0, the synchronization pulse is reset with respect to the reset timing of the counter value in the master controller 16a. The output timing should be advanced. Thereby, it is considered that the influence of the driver delay and the switching element delay on the deviation of the ON switching timing of the switching element can be suppressed.

  In the second embodiment, the situation in which the comparison value setting process is executed is not limited to when the power supply system is activated, but may be during normal operation of the power supply system, for example. In this case, from the viewpoint of improving the detection accuracy of the delay time, it is desirable to interrupt the comparison value setting process when the operating state of the power supply system becomes a transient state.

  The output timing advance processing is not limited to that exemplified in the third embodiment. For example, a delay time other than the minimum value and the maximum value is selected from the delay time required for the synchronization pulse to be transmitted from the master controller to each of the plurality of slave controllers, and the master controller reset timing is set by the selected delay time. On the other hand, processing for advancing the output timing of the synchronization pulse may be performed. Even in this case, some of the switching timings of the switching elements corresponding to the respective DCDC converters can be synchronized. In this case, in the controller corresponding to the delay time shorter than the delay time advanced by the output timing advance processing, the delay time adjustment processing is unnecessary.

  The output timing of the synchronization pulse from the master controller 16a is not limited to the counter value reset timing. For example, the synchronization pulse may be output at a timing when the counter value becomes a predetermined value smaller than the upper limit value.

  In each of the above embodiments, the on-switching timings of the switching elements of the plurality of DCDC converters are synchronized with each other. However, the present invention is not limited to this. For example, it is good also as a structure which makes the ON switching timing of each switching element of these DCDC converters mutually differ. Specifically, for example, as shown in FIG. 4 of Japanese Patent Application Laid-Open No. 2009-1000051, a value obtained by dividing the switching period by the number of DCDC converters is defined as a specified time, and each switching element of a plurality of DCDC converters is turned on. The switching timing may be shifted from the specified time. In this case, due to the delay time, the output voltage behavior of each of the DCDC converters may deviate from the initially assumed value, which may increase the ripple (fluctuation) of the output voltage of the power supply system. For this reason, it is thought that application of this invention is effective also to such a power supply system.

  The DCDC converter to which the present invention is applied is not limited to the digital control type, and may be an analog control type. Even in this case, in the slave controller, if a circuit configuration that determines the ON switching timing of the switching element in relation to the input timing of the reference signal output from the master controller is employed, due to the delay time, There is a possibility that the on-switching timings corresponding to the respective DCDC converters are shifted from each other. For this reason, it is considered that application of the present invention is also effective for a power supply system including an analog control type DCDC converter.

  The power conversion device is not limited to a step-down converter, and may be a step-up converter. Further, the power conversion device is not an insulation type, and may be a non-insulation type as shown in FIG. 1 of Japanese Patent Application Laid-Open No. 2009-1000051, for example.

  -As a switching element with which a power converter device is provided, not only what was illustrated by said each embodiment but a bipolar transistor, IGBT, etc. may be sufficient, for example.

  The vehicle to which the present invention is applied is not limited to a hybrid vehicle, and may be, for example, an electric vehicle including only a rotating machine as an in-vehicle main unit. The application object of the present invention is not limited to a vehicle.

  DESCRIPTION OF SYMBOLS 10 ... High voltage battery, 12a ... Master DCDC, 12b ... 1st slave DCDC, 12c ... 2nd slave DCDC, 16a ... Master controller, 16b ... 1st slave controller, 16c ... 2nd slave controller, Sp1, Sn1 , Sp2, Sn2... Switching elements.

Claims (5)

A power supply having a controller for turning on / off a switching element, comprising a plurality of power conversion devices that convert the input voltage into a predetermined value by the on / off operation of the switching device, and connecting the plurality of power conversion devices in parallel In the system,
The controller is provided in each of the plurality of power converters and the switching element of the power converter provided by itself is an operation target,
A part and at least one of the plurality of controllers outputs a reference signal to the other controllers with an on / off operation cycle of the switching element corresponding to the controller.
The controller that outputs the reference signal sets the switching timing to turn on the switching element corresponding to the reference signal in relation to the output timing of the reference signal,
The controller that does not output the reference signal among the plurality of controllers sets the switching timing to turn on the switching element corresponding to the controller in association with the input timing of the reference signal,
The controller that outputs the reference signal has a time interval between the switching timing corresponding to itself and the output timing of the reference signal based on a delay time required for transmitting the reference signal from the controller to a controller that does not output the reference signal. The power supply system characterized by performing the process which sets. The reference signal is for matching the switching timing corresponding to a controller that outputs the reference signal and the switching timing corresponding to a controller that does not output the reference signal,
The controller that outputs the reference signal performs, as the setting process, a process of advancing the output timing of the reference signal with respect to the switching timing corresponding to the controller as the delay time is longer. The power supply system according to 1. The controller turns on and off the switching element by a binary signal,
At least one of the plurality of controllers includes logic inversion timing of the binary signal generated by the controller that outputs the reference signal and logic of the binary signal generated by the controller that does not output the reference signal. A time difference detecting means for detecting a time difference from the inversion timing is further provided;
The power supply system according to claim 1, wherein the controller that outputs the reference signal further performs a process of variably setting the time interval based on the time difference detected by the time difference detection unit. Among the plurality of controllers, there are a plurality of controllers that do not output the reference signal,
The controller that outputs the reference signal has a delay other than the minimum value among the delay times required for transmission of the reference signal from the controller that outputs the reference signal to each of the controllers that does not output the reference signal as the setting process. Based on the time, processing to set the time interval,
The reference corresponding to a delay time shorter than the delay time used in the setting process among the delay times required for transmission of the reference signal from the controller that outputs the reference signal to each of the controllers that do not output the reference signal The power supply system according to any one of claims 1 to 3, wherein the controller that does not output a signal further includes a delay unit that delays the acquisition timing of the reference signal. The controller turns on and off the switching element by a binary signal,
At least one of the plurality of controllers includes a logic inversion timing of the binary signal generated by the controller that outputs the reference signal and the binary signal generated by each of the controllers that do not output the reference signal. Means for detecting each of the time differences from the logic inversion timing of
5. The power supply system according to claim 4, wherein the delay unit variably sets a delay degree of the acquisition timing of the reference signal based on each of the detected time differences.

Images