JP2013090225A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the input/output clock skew of a semiconductor device.SOLUTION: A semiconductor device includes: a first buffer 1 and a second buffer 8 that are driven by an I/O voltage power supply; a voltage determination unit 5 that generates a voltage determination signal showing a voltage level of the I/O voltage power supply; an echo clock generator 7 that adjusts the phase of an output clock signal on the basis of an input clock signal inputted via the first buffer 1 and outputs the output clock signal to the second buffer; and a storage unit 6 that stores mode information for selecting the relationship between the voltage determination signal and the adjustment amount of the phase. The echo clock generator 7 determines the adjustment amount of the phase of the output clock signal on the basis of the voltage determination signal and the mode information.

Description

  The present invention relates to a semiconductor device, and more particularly to suppression of input / output clock skew that occurs in a semiconductor device.

  As speeding up by miniaturization of LSI (Large Scale Integration) technology advances, there is a margin for a phase error between an echo clock signal output from a semiconductor device and an external clock signal of an external device (system) using the semiconductor device. It is running low. For this reason, the frequency of use of the clock synchronization circuit for compensating the phase error is increasing.

  For example, in a semiconductor memory device, the operating frequency has recently been increased in order to increase the memory access speed. As a result, the required specifications have become severe with respect to variations in the skew of the echo clock signal with respect to the reference clock signal (hereinafter also referred to as “input / output clock skew” as appropriate), and countermeasures for suppressing the skew are required. As an example, a specific description will be given using a synchronous semiconductor memory device such as a DDR SDRAM (Double Data Rate Synchronous DRAM).

  A synchronous semiconductor memory device performs data transmission with an external device using an external clock signal input from an external device (for example, a memory controller) as a reference clock signal. This is because between the external clock signal input from the external device to the semiconductor memory device and the data output from the semiconductor memory device in order to stably transmit data between the semiconductor memory device and the external device. This is because time synchronization is important. Data output from the semiconductor memory device is output in synchronization with the echo clock signal. The echo clock signal is delayed because the reference clock signal passes through each element in the semiconductor memory device. As a result, when data is output from the semiconductor memory device to the outside, the output data is output without being synchronized with the reference clock signal.

Therefore, in order to stably transmit data output from the semiconductor memory device to an external device, the echo clock signal delayed through each element in the semiconductor memory device is accurately positioned at the edge or center of the reference clock signal. In order to achieve this, the echo clock signal and the reference clock signal must be synchronized by decompensating the reference clock signal with the time that data is placed on the bus.
As a clock synchronization circuit that performs such a function, there are a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit. Since some PLL circuits have a frequency multiplexing (multiplication) function, they are also used when the clock frequency of the external device and the clock frequency of the semiconductor device are not the same frequency but different from each other. The DLL circuit is used when the clock frequency of the external device and the clock frequency of the semiconductor device are the same. As measures for suppressing skew, various improvements have been made with respect to PLL circuits and DLL circuits.

  For example, Patent Document 1 discloses a PLL circuit improved to a level at which a phase error can be ignored. In the PLL circuit of Patent Document 1, as shown in FIG. 23, an input / output clock skew is suppressed by using a PLL unit 10P and variable delay lines (VDL: Variable Delay Adjustment circuits) 1IP and 1RP. This technique is intended to suppress the phase error because the ratio of the phase error determined by the semiconductor manufacturing variation of the PLL section increases with respect to the clock frequency that increases year by year. In the PLL circuit, two VDLs (VDL1IP, VDL1RP) for delaying the input clock signal and the delayed feedback clock signal, a phase comparator (PD) 3P for determining a phase difference between the input clock signal and the delayed feedback clock signal, and a phase From the comparison result, a control logic circuit 2P for controlling the delay values of VDL1IP and 1RP is added before the PLL unit 10P. Thereby, even if the phase error of the PLL unit 10P exists, the PLL circuit can suppress the input / output clock skew to a level at which the input / output clock skew can be ignored with respect to the clock frequency by the phase comparator 3P canceling the phase difference. it can.

Patent Document 2 discloses a delay locked loop (DLL) circuit that stably performs a delay locked operation regardless of the level fluctuation of the external power supply voltage. The delay-fixed loop circuit of Patent Document 2 outputs a voltage-fixed clock by delaying the source clock, a voltage level detector that detects the level of the external power supply voltage, a phase comparator that compares the phases of the source clock and the feedback clock A clock delay unit. The clock delay unit designates one of the first and second delay unit units as a start delay unit unit and the other as a connected delay unit unit according to the output signal of the voltage level detection unit. In response to the output signal of the phase comparison unit, the clock delay unit delays the source clock in units of a start delay unit until the predetermined delay amount, and after the predetermined delay amount in units of connected delay units, Output as a fixed delay clock.
In the delay locked loop circuit of Patent Document 2, at least one delay unit is selected from a plurality of delay units having different delay amounts according to the detection result of the level fluctuation of the external power supply voltage. Then, the source clock is delayed using the selected delay units in order, and output as a delay fixed clock signal. By performing the delay fixing operation described above, the delay fixing operation is stably performed regardless of the level fluctuation of the external power supply voltage.

JP 2003-188720 A JP 2011-15384 A

  However, in the PLL circuit of Patent Document 1, the phase error between the input clock signal and the delayed feedback clock signal cannot be canceled unless the accuracy of the phase comparator 3P is higher than the phase error accuracy of the PLL unit 10P. In addition, there is a problem that the delay amount of the PLL circuit varies due to the variation of the external power supply voltage.

  In the delay locked loop circuit disclosed in Patent Document 2, in response to the delay amount inside the delay locked loop circuit fluctuating due to the external power supply voltage, the delay locked loop operation is stably performed regardless of the external power supply voltage. Do. For this reason, it is possible to remove the influence of the level fluctuation of the external power supply voltage on the delay locked loop circuit. However, it is extremely difficult to match the phase of the reference clock signal and the echo clock signal output from the semiconductor device only by switching the delay unit used for delay adjustment in the delay locked loop circuit. The reason is that the slew rate of the input clock signal and the output load on the output clock signal are different for each external device (for example, a customer system that uses the semiconductor device) on which the semiconductor device is mounted. This is because it affects the input / output clock skew.

  Therefore, even if the variation in the delay amount due to the level variation of the external power supply voltage is eliminated in the delay locked loop circuit, the variation in the delay amount in the delay unit circuit is only suppressed. In other words, in a delay locked loop circuit, an external clock signal (reference clock signal) input to the semiconductor device or an echo clock signal output from the semiconductor device due to external environmental factors such as a signal slew rate of the external device or an output load. No measures will be taken against the delay. Therefore, the skew between the reference clock signal and the echo clock signal due to external environmental factors cannot be suppressed. As a result, a phase difference occurs between the reference clock signal and the echo clock signal. This is a problem that also occurs in the PLL circuit of Patent Document 1.

  Here, an example of the influence of the external clock signal input to the semiconductor device, that is, the reference clock signal and the echo clock signal output from the semiconductor device, from the external device and the external power supply voltage will be described.

  FIG. 24 is an image diagram showing the input of the reference clock signal and the output of the echo clock signal in the semiconductor device. The reference clock signal (CK / CK #) is input to the internal processing unit 94 of the semiconductor device 90 via the input buffer (receiver circuit) 91. The echo clock signal (QK / QK #) is output from the semiconductor device 90 via the output buffers (driver circuits) 92 and 93. The internal processing unit 94 is a circuit that implements a function realized by the semiconductor device 90. The internal processing unit 94 includes a PLL circuit 941 that matches the phase of the echo clock signal with respect to the reference clock signal. FIG. 25 shows an example of occurrence of skew between the reference clock signal and the echo clock signal. In FIG. 25, a delay occurs because the reference clock signal passes through each element included in the internal processing unit 94 of the semiconductor device 90, and a phase difference (CK-QK skew) occurs in the echo clock signal with respect to the reference clock signal. Is shown.

  On the other hand, the input of the reference clock signal and the output of the echo clock signal are input / output PAD 191, package LCR (PKG LCR) 192 component, package ball (PKG BALL) 193, printed circuit board LCR (PCB LCR) (not shown). It is affected by the component or presence / absence of transmission line termination (not shown). Since these influence the slew rate of the reference clock signal and the output load on the echo clock signal, the reference clock signal and the echo clock signal have different influences for each external device. As a result, the waveforms of the reference clock signal and the echo clock signal shown as an example in FIG. 25 are different for each external device. In addition, power is supplied to the input buffer 91 and the output buffers 92 and 93 from the I / O voltage power supply, but the signal slew rate is affected by the output load and the voltage level of the I / O power supply voltage. This will be specifically described with reference to FIG.

FIG. 26 shows an example in which the waveforms of the reference clock signal and the echo clock signal change depending on the I / O voltage and the input slew rate. FIG. 26 is an image diagram of the semiconductor device 90 shown in FIG. 24. A reference clock signal (CK / CK #) is input to the input buffer 91, and an echo clock signal (QK / QK #) is output from the output buffers 92 and 93. Shows the case. In addition, FIG. 26 shows a case where the voltage level of the applied I / O voltage power supply is higher and lower than an arbitrary reference voltage.
In FIG. 26, reference sign VSSQ / VDDQ indicates power supplied from the I / O voltage power supply. The waveform of the reference clock signal (CK / CK #) is indicated by a solid line (CK) and a dotted line (CK #) that are thicker than the power supply VSSQ / VDDQ. The waveform of the echo clock signal (QK / QK #) is indicated by a solid line (QK) and a dashed line (QK #) that are thicker than the power supply VSSQ / VDDQ and thinner than the reference clock signal (CK / CK #). The CK-QK skew is a skew of the echo clock signal with respect to the reference clock signal.

When the voltage level of the I / O voltage power supply is higher than an arbitrary reference voltage (HIGH I / O VOLTAGE), the echo clock signal is delayed with respect to the reference clock signal. At this time, the magnitude of the CK-QK skew differs depending on the signal slew rate of the external device.
On the other hand, when the voltage level of the I / O voltage power supply is lower than an arbitrary reference voltage (LOW I / O VOLTAGE), the echo clock signal becomes earlier than the reference clock signal.
Since the magnitude of the CK-QK skew varies depending on various factors, the magnitude relationship of the CK-QK skew shown in FIG. 26 is merely an example.

As shown in FIG. 26, the CK-QK skew (input / output clock skew) varies depending on the voltage level of the I / O voltage power supply and external environmental factors (signal slew rate, output load, etc.) generated from the external device. Therefore, there is a problem that the input / output clock skew is not sufficiently suppressed only by improving the accuracy of the delay amount in the clock synchronization circuit, such as the PLL circuit of Patent Document 1 and the delay locked loop circuit of Patent Document 2. Referring to FIG. 24, Patent Documents 1 and 2 merely focus on improving the accuracy of functions corresponding to the PLL circuit 941 included in the internal processing unit 94.
In addition, in recent years, the voltage level of the I / O power supply voltage that can be taken by the external device has become widespread, and there is a need for the semiconductor device to operate in a wider range of voltage levels than before.

  As described above, in order to suppress the input / output clock skew of the semiconductor device by increasing the speed in the recent semiconductor device, in particular, the semiconductor memory device and widening the voltage level of the power supply voltage that can be adopted by the external device, There is a need to remove the factors that arise from external devices equipped with.

  The semiconductor device of the present invention has an echo clock generation unit that adjusts and outputs the phase of the echo clock signal based on the reference clock signal, and the echo clock generation unit is an I / O voltage that drives the input buffer and the output buffer. The phase adjustment amount is determined based on the voltage level of the power supply and the mode information indicating the relationship between the voltage level of the I / O voltage power supply and the phase adjustment amount.

  According to the present invention, input / output clock skew of a semiconductor device can be suppressed.

1 is a block diagram illustrating a schematic configuration example of a semiconductor device according to an embodiment of the present invention. It is a figure explaining the effect | action and effect of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows an example of the relationship between a voltage determination signal and mode information, and delay amount. 1 is a block diagram showing a configuration example of a semiconductor device according to Embodiment 1 of the present invention. FIG. 5 is a circuit diagram illustrating a configuration example in which the semiconductor device illustrated in FIG. 4 is more specifically realized. FIG. 3 is a circuit diagram illustrating an example of an I / O voltage determination circuit according to the first embodiment. It is a circuit diagram which shows an example of the counter of an I / O voltage determination circuit. It is a circuit diagram which shows an example of VDL_R. It is a circuit diagram showing an example of VDL_F. It is a 1st conversion table (in the case of CODESTEP: 0) which shows an example of the delay amount determined from the combination of a voltage determination signal (VDLCODE) and a mode (CODESTP). It is a 1st conversion table (in the case of CODESTEP: 1) which shows an example of the delay amount determined from the combination of a voltage determination signal (VDLCODE) and mode (CODESTP). It is a 1st conversion table (in the case of CODESTEP: 2) which shows an example of the delay amount determined from the combination of a voltage determination signal (VDLCODE) and a mode (CODESTP). It is a 1st conversion table (in the case of CODESTEP: 3) which shows an example of the delay amount determined from the combination of a voltage determination signal (VDLCODE) and a mode (CODESTP). It is a 2nd conversion table (in the case of CODESTEP: 0) which shows an example of the delay amount determined from the combination of a voltage determination signal (VDLCODE) and a mode (CODESTP). It is a 2nd conversion table (in the case of CODESTEP: 1) which shows an example of the delay amount determined from the combination of a voltage determination signal (VDLCODE) and a mode (CODESTP). It is a 2nd conversion table (in the case of CODESTEP: 2) which shows an example of the delay amount determined from the combination of a voltage determination signal (VDLCODE) and a mode (CODESTP). It is a 2nd conversion table (in the case of CODESTEP: 3) which shows an example of the delay amount determined from the combination of a voltage determination signal (VDLCODE) and a mode (CODESTP). It is the graph showing the information of the table shown to FIG. 6 is a timing chart illustrating an operation example of a semiconductor device when a voltage VDDQ of an I / O voltage power supply is lower than a reference voltage. 6 is a timing chart illustrating an operation example of a semiconductor device when a voltage VDDQ of an I / O voltage power supply is higher than a reference voltage. It is a figure which shows the timing image of the skew of the reference clock signal and echo clock signal of a prior art. It is a figure which shows the timing image of the skew of the reference | standard clock signal and echo clock signal of the semiconductor device of this embodiment. It is a circuit diagram which shows the structural example of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 6 is a circuit diagram illustrating an example of an I / O voltage determination circuit according to a second embodiment. It is a figure which shows the structural example of the printed circuit board carrying the semiconductor device which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structural example of the semiconductor device which concerns on Embodiment 3 of this invention. FIG. 6 is a circuit diagram illustrating an example of an I / O voltage determination circuit according to a third embodiment. FIG. 10 is a circuit diagram illustrating an example of a counter according to the third embodiment. FIG. 10 is a diagram illustrating an image for adjusting a skew between a reference clock signal and an echo clock signal in the third embodiment. It is a figure which shows the structural example of the semiconductor device containing a memory controller. 1 is a diagram illustrating a configuration of a PLL circuit disclosed in Patent Document 1. FIG. It is an image figure which shows the input of the reference clock signal in a semiconductor device, and the output of an echo clock signal. It is a figure which shows the example of generation | occurrence | production of the skew of a reference clock signal and an echo clock signal. It is a figure which shows an example in which the waveform of a reference | standard clock signal and an echo clock signal changes with I / O voltage and an input slew rate.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

In order to suppress input / output clock skew, not only changes in the voltage level of the I / O power supply voltage, but also external environmental factors such as the slew rate of the reference clock signal and the output load of the feedback clock signal In addition, since external environmental factors have a variety of influences, it is not sufficient to cope with linear changes or increasing the delay amount to the reference voltage. The present invention provides a semiconductor device that realizes clock synchronization processing that can cope with these.
In one aspect of the embodiment of the present invention, when the reference clock signal used by the semiconductor device and the echo clock signal output from the semiconductor device are synchronized, the voltage level of the I / O power supply voltage and the factors of the external environment Thus, the delay amount between the reference clock signal and the echo clock signal is determined. Specifically, the delay amount is determined using mode information that adds an influence from the external device to the semiconductor device in addition to the voltage determination signal indicating the voltage level of the I / O power supply voltage.
The semiconductor device of the present invention can be applied to a network memory product controlled by a memory controller such as an FPGA (Field Programmable Gate Array).

FIG. 1 is a block diagram showing a schematic configuration example of a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 includes a first buffer 1, a voltage determination unit 5, a storage unit 6, an echo clock generation unit 7, and a second buffer 8. The echo clock generation unit 7 includes a delay adjustment unit 2, a phase adjustment unit 3, and a feedback unit 4.
The first buffer 1 is driven by an I / O voltage power source, receives a reference clock signal, and outputs an input clock signal into its own device.
The echo clock generator 7 adjusts the phase of the output clock signal based on the input clock signal input via the first buffer 1 and outputs the adjusted signal to the second buffer 8.
The second buffer 8 is driven by an I / O voltage power supply, receives an output clock signal from the echo clock generation unit 7, and outputs the echo clock signal to the outside.
Here, the reference clock signal coincides with the external clock signal input from the external device to the semiconductor device 100, and is a signal used as the reference clock when the semiconductor device 100 performs internal processing. The echo clock signal is a signal output from the semiconductor device 100 to an external device, and includes an internal clock skew.

The voltage determination unit 5 determines the voltage level of the I / O voltage power supply and generates a voltage determination signal. For example, a result of comparing the voltage level of the I / O voltage power supply with an arbitrary reference voltage is generated as a voltage determination signal. The I / O voltage power supply supplies power to the first buffer 1 and the second buffer 8 of the semiconductor device 100. In the semiconductor device 100, at least the first buffer 1, the second buffer 8, and the feedback unit 4 use the same I / O voltage power supply (VDDQ / VSSQ).
The storage unit 6 records mode information for adding the influence of the external environment to the own device with respect to the voltage level of the I / O voltage power supply. In other words, the mode information selects the relationship between the voltage adjustment signal and the phase adjustment amount of the output clock signal adjusted by the echo clock generator 7. In addition, the storage unit 6 is configured so that a user of the semiconductor device 100 can set mode information from the outside.
The delay adjusting unit 2 receives the input clock signal and the feedback clock signal, adjusts the delay amount of the input clock signal using the voltage determination signal and the mode information, and generates an input clock adjustment signal (first clock signal). Then, the feedback clock adjustment signal (second clock signal) is generated by adjusting the delay amount of the feedback clock signal. The feedback clock signal is a signal generated by the feedback unit 4 and will be described in detail by the feedback unit 4.

The phase adjustment unit 3 receives the input clock adjustment signal and the feedback clock adjustment signal, and uses a delay adjustment clock signal (third clock signal) in which the phase of the feedback clock adjustment signal matches the phase of the input clock adjustment signal as an output clock signal. To the second buffer 8 and the feedback unit 4. The second buffer 8 outputs an echo clock signal based on the output clock signal.
The feedback unit 4 feeds back a feedback clock signal based on the output clock signal to the delay adjustment unit 2. The feedback unit 4 is configured such that the feedback clock signal is input to the delay adjustment unit 2 through the same elements as the echo clock signal.

In the configuration of the semiconductor device 100 in FIG. 1, the delay adjustment unit 2 uses mode information that adds an influence from an external device to the semiconductor device 100 in addition to a voltage determination signal indicating the voltage level of the I / O power supply voltage. Thus, the delay amount is determined.
Here, the operation and effect of the semiconductor device 100 will be described with reference to FIG. FIG. 2 shows one mode in which the present invention is applied to the semiconductor device 109.

The semiconductor device 109 in FIG. 2 will be described including the correspondence with the semiconductor device 100 in FIG.
The buffer (first input buffer) 11 is an input buffer that receives a reference clock signal and outputs an input clock signal. A buffer (first output buffer) 12 receives the output clock signal and outputs an echo clock signal, and a buffer (second output buffer) 13 is an output buffer that receives the output clock signal and outputs an inverted echo clock signal. is there. The buffer 11 corresponds to the first buffer 1 in FIG. 1, and the buffers 12 and 13 correspond to the second buffer 8 in FIG.
The processing unit 9-1 is a circuit that performs internal processing in accordance with the semiconductor device 109.

The buffer (second input buffer) 41 is an input buffer that receives the replica clock signal and the inverted replica clock signal and outputs a feedback clock signal. A buffer (third output buffer) 42 receives the output clock signal and outputs a replica clock signal, and a buffer (fourth output buffer) 43 receives the output clock signal and outputs an inverted replica clock signal. is there. The buffers 41 to 43 and the processing unit 9-2 correspond to the feedback unit 4. The feedback unit 4 imitates the buffers 11 to 13 and is configured so that each element in the internal processing is the same. In other words, the feedback unit 4 has a configuration equivalent to the buffer 41 (third buffer) having the same configuration as the buffer 11 (first buffer 1) and the buffers 12 and 13 (second buffer 8). It is composed of buffers 42 and 43 (fourth buffer). Here, “equivalent” means that they are structurally equivalent or have the same electrical characteristics.
The processing unit 9-2 has the same configuration as the processing unit 9-1. In the semiconductor device 109, an internal clock skew occurs due to the elements included in the processing unit 9-1. For this reason, the delays between the processing unit 9-1 and the buffers 12 and 13 and between the processing unit 9-2 and the buffers 42 and 43 are the same.

  In the semiconductor device 100 shown in FIG. 1 or the semiconductor device 109 shown in FIG. 2, not only the internal clock skew but also an echo clock signal (QK) with respect to a reference clock signal (CK / CK #) existing as a specification of a network memory or the like. / QK #), for example, a PLL circuit is used as the phase adjustment unit 3 in order to suppress the skew (CK-QK skew). In order to suppress the skew between the reference clock signal and the echo clock signal, the phase adjustment unit 3 forms a feedback loop, creates a feedback clock signal imitating the echo clock signal, and feeds it back to the phase adjustment unit 3. The feedback loop corresponds to the feedback unit 4 in FIG. 1, but has a circuit configuration in which, for example, a replica driver circuit (buffers 42 and 43 in FIG. 2) and a receiver circuit (buffer 41 in FIG. 2) are inserted. use.

Depending on the replica configuration formed by the feedback loop, it is preferable that the paths (A) + (B) and (C) shown in FIG. 2 have the same skew between the reference clock signal and the echo clock signal. However, in reality, the paths of the reference clock signal and the echo clock signal cannot be reproduced by the buffers 41 to 43 arranged inside the chip of the semiconductor device 109, and thus a deviation occurs. This is because it is difficult to match all settings of external environmental factors depending on the external device between the reference clock signal and echo clock signal paths and the feedback loop.
Specifically, as shown in FIG. 26, the signals input and output by the buffers 11 to 13 are different signals for each external device based on the signal slew rate, output load, and the like due to the difference in these settings. Form a waveform. On the other hand, in the feedback loop, it is difficult to imitate the signal waveform according to external environmental factors generated from the external device. In addition, skew between the reference clock signal and the echo clock signal occurs due to differences in amplitude level, signal slew rate, and the like. In particular, one of the parameters for increasing the delay difference between the reference clock signal and the echo clock signal due to the difference between the signal waveform in the path of the reference clock signal and the echo clock signal and the signal waveform in the feedback loop is the I / O voltage power supply. Voltage level. This is as described with reference to FIG.

In order to solve this problem, the reference clock signal depends on the voltage level of the I / O voltage power supply and external environmental factors in the paths (A) + (B) and (C) shown in FIG. When the delay difference between the signal and the echo clock signal occurs, the delay adjusting unit 2 functions to compensate the delay difference. Specifically, the delay adjustment unit 2 determines the delay amount by a combination of the mode information that predicts the signal slew rate and output load of the external device and the voltage determination signal that indicates the voltage level of the I / O voltage power source, Adjust the delay difference.
For this reason, as the mode information, a plurality of modes indicating the voltage dependency are set by assuming the signal slew rate of various input signals assumed as an external device and some output loads, and the storage unit 6 as the mode information. Stored in advance.
FIG. 3 is a diagram illustrating an example of the relationship between the voltage determination signal, the mode information, and the delay amount. As shown in FIG. 3, the delay amount is determined according to the combination of the voltage determination signal and the mode information (specifically, the mode) stored in the storage unit 6. The plurality of modes are set so that different delay amounts are associated with the voltage levels of the I / O voltage power supply. In the example shown in FIG. 3, six types of modes 1 to 6 are shown as mode information, and the amount of delay that changes according to the voltage level of the I / O voltage power supply is different for each mode.

For example, modes 1, 2, and 3 in which the delay amount changes in proportion to the voltage level of the I / O voltage power supply, and modes 4, 5, and 6 that are not linear characteristics are set. Even in the non-linear characteristic mode, the amount of change in the delay amount according to the voltage level is set to be the smallest in mode 4 and subsequently increase in the order of mode 5 and mode 6.
When a system is configured by combining a semiconductor device with an external device and the system is evaluated, a mode set in the storage unit 6 is selected according to the characteristics of the external device. Further, the mode can be selected again and set in the storage unit 6 according to the operation of the system. As a specific mode selection, for example, when the input / output terminal addition is large in the customer's external device, the mode that increases the change in the delay amount is selected. Alternatively, when the transistor characteristic of the feedback unit 4 in the semiconductor device 100 is not a linear characteristic with respect to the voltage, a change in the delay amount is selected from another mode instead of the simple linear mode.
A specific configuration example of a semiconductor device according to the present invention will be described below with reference to the drawings.

Embodiment 1. FIG.
FIG. 4 is a block diagram illustrating a configuration example of the semiconductor device according to the first embodiment. The semiconductor device 101 includes a buffer 11 as the first buffer 1, buffers 12 and 13 as the second buffer 8, a first variable delay line (VDL) unit (first delay adjustment unit) 21 as the delay adjustment unit 2, and a second VDL. Unit (second delay adjustment unit) 22, phase adjustment unit 3 includes PLL unit 31, feedback unit 4 includes buffers 41 to 43, voltage determination unit 5, and storage unit 6. For ease of explanation, in the semiconductor device 101, the processing units 9-1 and 9-2 shown in FIG. 2 are omitted, and the processing unit 9-1 and 9-2 are arranged on a path from the PLL unit 31 to the buffers 12, 13, 42, and 43. Description of the elements etc. which are present is omitted. As shown in FIG. 4, at least the buffers 11 to 13, 41 to 43 (components surrounded by a two-dot broken line) are supplied with the power VDDQ / VSSQ from the I / O voltage power supply.

The first VDL unit 21 receives the input clock signal from the buffer 11 and delays the input clock signal when the voltage level of the I / O voltage power supply is lower than the reference voltage based on the voltage determination signal and the mode information (mode). The first delay amount to be increased (input clock delay amount) is selected, and when the voltage level of the I / O voltage power source is equal to or higher than the reference voltage, zero is selected as the first delay amount. The first VDL unit 21 delays the input clock signal by the selected first delay amount to generate an input clock adjustment signal.
The second VDL unit 22 receives the feedback clock signal from the buffer 41, and delays the feedback clock signal when the voltage level of the I / O voltage power supply is higher than the reference voltage based on the voltage determination signal and the mode information (mode). The second delay amount to be increased (feedback clock delay amount) is selected, and when the voltage level of the I / O voltage power source is equal to or lower than the reference voltage, zero is selected as the second delay amount. The second VDL unit 22 delays the feedback clock signal by the selected second delay amount to generate a feedback clock adjustment signal.

In FIG. 4, an example in which the delay adjustment unit 2 includes the first VDL unit 21 and the second VDL unit 22 will be described, but the present invention is not limited to this. Based on the voltage determination signal and the mode information, the delay adjustment unit 2 increases the delay of the feedback clock signal when the voltage level of the I / O voltage power source is higher than the reference voltage, and the voltage level of the I / O voltage power source becomes the reference level. Other configurations may be used as long as the delay amount for increasing the delay of the input clock signal is selected as the delay amounts of the input clock signal and the feedback clock signal when the voltage is lower than the voltage.
The other components are the same as those shown in FIGS. 1 and 2 and will not be described.

  FIG. 5 shows a configuration example in which the semiconductor device 101 shown in FIG. 4 is more specifically realized. The semiconductor device 102 of FIG. 5 includes buffers 11 to 16, VDL_R 23, VDL_R 24, PLL 32, buffers 41 to 43, I / O voltage determination circuit 51, MRS (Mode Register Set) 61, FUSE 62, and OR circuit 63. FIG. 5 shows the processing units 9-1 and 9-2. The buffers 11 to 16 and 41 to 43 are supplied with power VDDQ / VSSQ from the I / O voltage power supply. When the configuration of the semiconductor device 102 in FIG. 5 is associated with the components in FIG. 1, the first buffer 1 is the buffers 11, 14, 15, the second buffer 8 is the buffers 12, 13, 16, and the delay adjustment unit 2. VDL_R23, VDL_R24, PLL 32 as phase adjustment unit 3, buffers 41-43 and processing unit 9-2 as feedback unit 4, I / O voltage determination circuit 51 as voltage determination unit 5, MRS 61, FUSE 62, and OR as storage unit 6 Circuit 63 is obtained.

The buffer 14 is an input buffer for inputting a command for activating the MRS 61. The buffer 15 is an input buffer for inputting an address for performing processing according to the command. The buffer 16 is an output buffer that outputs data.
The VDL_R 23 receives the input clock signal (RVCLK signal) from the buffer 11, generates an RPCLK signal (input clock adjustment signal, first clock signal) in which the delay of the input clock signal is adjusted, and outputs it to the PLL 32. VDL_R23 corresponds to the first VDL unit 21 of FIG.
The VDL_F 24 receives the feedback clock signal (FVCLK signal) from the buffer 41, generates an FPCLK signal (feedback clock adjustment signal, second clock signal) in which the delay of the feedback clock signal is adjusted, and outputs the FPCLK signal to the PLL 32. VDL_F 24 corresponds to the second VDL unit 22 of FIG.

The PLL 32 receives the RPCLK signal and the FPCLK signal, and outputs a PCLK signal (output clock signal) whose phase is synchronized. The circuit configuration of the PLL 32 may be any PLL circuit that can realize the functions described above. Since the circuit configuration itself is not important here, the description is omitted.
The I / O voltage determination circuit 51 uses the power supply VDDQ / VSSQ supplied from the I / O voltage power supply and the reference level VREF as the reference voltage to determine the voltage level of the I / O voltage power supply and to determine n bits (n Is an integer greater than zero), and VDLCODE is output to VDL_R23 and VDL_F24. The I / O voltage determination circuit 51 will be described later with reference to FIGS.

The MRS 61 holds mode information. The MRS 61 may hold predetermined mode information, or may hold mode information set from the outside.
The FUSE 62 holds the initial setting of the semiconductor device 102.
The OR circuit 63 generates a logical product of the mode value held by the MRS 61 and the value held by the FUSE 62 as a CODESTP signal (mode and mode information). Although FIG. 5 shows an example in which the CODESTP signal is generated by the OR circuit 63, a value held by the MRS 61 may be used as the CODESTP signal.

By using the MRS 61 and / or the FUSE 62, a function capable of setting the mode value from the outside is realized.
In the semiconductor device 102 of FIG. 5, the PLL 32 that is a source for adjusting the phases of the reference clock signal CK / CK # and the echo clock signal QK / QK #, and the I / O voltage determination circuit that determines the I / O voltage level inside the chip. 51, VDL_R23 and VDL_F24 for adjusting the delay amount according to the I / O voltage determination result, MRS 61 for outputting a signal capable of switching the setting of the voltage determination result and the VDL delay amount, and FUSE 62.

  Next, the I / O voltage determination circuit 51 will be described in detail. FIG. 6 is a diagram illustrating a detailed configuration example of the I / O voltage determination circuit. The I / O voltage determination circuit 51 includes a VDDQ voltage division level generation circuit 511, an amplifier circuit 512, an amplifier determination latch circuit 513, a counter 514, a pulse generation circuit 515, and a frequency division switching circuit 516.

  The VDDQ voltage division level generation circuit 511 includes a series resistance output unit 5111 and a switch unit 5112. The series resistance output unit 5111 connects the VDDQ that is the voltage of the I / O voltage power supply and the VSSQ that is the reference level in series with a plurality of resistors, and generates a divided voltage level. The switch unit 5112 provides a switch transistor between a plurality of resistors constituting the series resistance output unit 5111, switches the switch transistor according to VDLCODE [n-1: 0] output from the counter 514, and selects a voltage selected by the switch transistor The voltage division level VDDQR of VDDQ is taken out.

The amplifier circuit 512 compares and determines the divided voltage level VDDQR and the reference level VREF, and generates an AMPLEV signal as a determination result. Since the amplifier circuit 512 generates the voltage determination signal using the divided voltage level VDDQR, the half value of the reference voltage is used as the reference level VREF.
The amplifier determination latch circuit 513 latches the AMPLEV signal, which is the determination result of the amplifier circuit 512, with a pulse LATPLS generated by timing control based on the PCLK signal output from the PLL 32, and holds the DLAT signal.

The counter 514 generates the code signal VDLCODE [n−1: 0] from the DLAT signal, which is latch data, and the pulse UPPLS generated from the PCLK signal and controlled in timing, to the VDL_R23, VDL_F24, and VDDQ voltage division level generation circuit 511. Forward to.
The pulse generation circuit 515 generates pulses LATPLS and UPPLS based on the DIVCLK signal output from the frequency division switching circuit 516.
The frequency division switching circuit 516 switches the PCLK signal to an arbitrary frequency division and outputs it as a DIVCLK signal. Here, a case where the PCLK signal is switched to frequency division by 2 is shown as an example.

  FIG. 7 shows a detailed circuit example of the counter 514. In the counter 514, the adders 5141-0 to 5141- (n-1) detect the H / L of the DLAT signal and add / subtract, and the UPDATE registers 5142-0 to 5142- (n-1) trigger the pulse UPPLS. VDLCODE [n-1: 0] is output.

Next, VDL_R23 and VDL_F24 will be described in detail. FIG. 8A shows an example of VDL_R24, and FIG. 8B shows an example of VDL_F24.
The VDL_R 23 includes a first VDL selector circuit (VDL_R selector circuit) 231, a first delay selection circuit (VDL_R delay selection circuit) 232, and a first code selector circuit (VDL_R code selector circuit) 233. The first VDL selector circuit 231 includes a first conversion table 2311. The VDL_F 24 includes a second VDL selector circuit (VDL_F selector circuit) 241, a second delay selection circuit (VDL_F delay selection circuit) 242, and a second code selector circuit (VDL_F code selector circuit) 243. The second VDL selector circuit 241 includes a second conversion table 2411.
9A to 9D show an example of the first conversion table 2311. 9E to 9H show an example of the second conversion table 2411. FIG. 10 shows a graph representing information of the tables shown in FIGS.

The first VDL selector circuit 231 or the second VDL selector circuit 241 selects the delay amount corresponding to the voltage level of the I / O voltage power supply for VDLCODE [3: 0] determined by the I / O voltage determination circuit 51 To VDLSEL [7: 0] R or VCLSEL [7: 0] F. VDL_R23 and VDL_F24 in FIGS. 8A and 8B show an example in which the number of bits n of VDLCODE shown in FIGS. 6 and 7 is 4 bits. In addition, here, as an example, a case where 4-bit VDLCODE is converted into 8-bit VDLSEL is shown.
The first VDL selector circuit 231 uses the first conversion table 2311 to convert VDLCODE [3: 0] to VDLSEL [7: 0] R. The second VDL selector circuit 241 converts VDLCODE [3: 0] to VDLSEL [7: 0] F using the second conversion table 2411. 9A to 9H show the delay amounts on the RVCLK side and the FVCLK side, the first conversion table 2311 and the second conversion table 2411 do not need to hold the delay amount. In the configuration example of FIGS. 8A and 8B, the first delay selection circuit 232 or the second delay selection circuit 242 is determined by VDLSEL [7: 0] R or VCLSEL [7: 0] F and CODESTP [1: 0]. The first delay amount or the second delay amount is determined by selecting one delay path from among a plurality of delay paths included in.

  The first delay selection circuit 232 or the second delay selection circuit 242 includes a plurality of delay paths. The plurality of delay paths select a delay amount according to VDLSEL [7: 0] R or VCLSEL [7: 0] F output from the first VDL selector circuit 231 or the second VDL selector circuit 241. Specifically, the number of delay elements of a plurality of delay paths is selected. Although FIG. 8A shows an example of a plurality of delay paths provided in the first delay selection circuit 232, the plurality of delay paths is not limited to this and may be realized by other circuit configurations. In addition, the circuit configuration of the delay path varies depending on the delay amount employed as the first delay amount. Although the second delay selection circuit 242 is not specifically shown in FIG. 8B, it may have a circuit configuration corresponding to the delay amount employed as the second delay amount. The plurality of delay paths included in the first delay selection circuit 232 and the second delay selection circuit 242 depend on the first delay amount and the second delay amount, and when realized by the same circuit configuration, It may be realized by a different circuit configuration.

The first code selector circuit 233 or the second code selector circuit 243 receives CODESTP [1: 0] determined by the MRS 61 and the FUSE 62, and determines a delay amount according to the value of CODESTP [1: 0]. Specifically, the first code selector circuit 233 selects a delay path from among a plurality of delay paths included in the first delay selection circuit 232 by CODESTP [1: 0], thereby reducing the delay amount. decide. The same applies to the second delay selection circuit 242.
When the first code selector circuit 233 receives the RVCLK signal, the first code selector circuit 233 delays the RVCLK signal according to the determined first delay amount to generate and output the RPCLK signal. On the other hand, when the second code selector circuit 243 receives the FVCLK signal, the second code selector circuit 243 delays the FVCLK signal according to the determined second delay amount and generates and outputs the FPCLK signal.

8A selects a first delay amount from a combination of a VDLCODE signal as a voltage determination signal and a CODEST signal based on MRS 61 or FUSE 62 controlled by an external pin. For this reason, the first delay selection circuit 232 is configured to change the delay value according to the number of stages of inverters. The means for changing the delay value is not limited to using the number of inverter stages, and switching of load capacity, Fanout, etc., for example, can be considered.
As shown in FIGS. 9A to 9H and FIG. 10, a plurality of patterns are designed in advance as an example of the relationship between the VDLCODE signal that can be selected by the CODESTP signal and the respective delay amounts of VDL_R23 and VDL_F24. 9A to 9H, “L” means “Low” and “H” means “High”. The RVCLK signal side delay amount is a first delay amount used by VDL_R23, and the FVCLK signal side delay amount is a second delay amount used by VDL_24. Based on the tester evaluation of the system, the result of checking the characteristics of the system as a real product is fed back using the mode. This makes it possible to set the optimum relationship between the VDLCODE signal (voltage determination signal) and the CODESTP signal (mode) after system construction.

  In the example shown in FIGS. 9A to 9H and FIG. 10, the VDLCODE signal has a default value of 8 (VDLCODE: 4′h8), and the delay amount at this time is zero. When the VDLCODE signal is 0 to 7, a delay amount greater than zero is selected on the RVCLK signal side (VDL_R23) according to the CODESTP signal values 0 to 3, and when the VDLCODE signal is 9 to 15, the FVCLK side (VDL_F24). The delay amount greater than zero is selected according to the values 0 to 3 of the CODESTP signal. Thus, based on preset information (for example, FIGS. 9A to 9H, FIG. 10), the delay amount is selected in VDL_R23 and VDL_F24 by the combination of the VDLCODE signal as the voltage determination signal and the CODESTP signal as the mode. Is done. 9A to 9H, D1 to D6 are arbitrary numerical values, and it is assumed that D5, D3, D1, and D2 (D5 <D3 <D1 <D2) are larger in this order.

8A, 8B, and FIGS. 9A to 9H show a configuration in which various delay amounts can be selected by associating the 4-bit VDLCODE signal (voltage determination signal) with the 8-bit VDLSEL signal. It is not limited to this. The delay amount may be associated with the combination of the voltage determination signal and the mode. For example, in FIGS. 8A and 8B, the case of using a plurality of delay amounts that can be associated with a combination of a 1-bit VDLCODE signal as a voltage determination signal and a plurality of bits CODESTP as a mode is excluded. Absent. In this case, the voltage determination signal may be input to the first delay selection circuit 232 or the second delay selection circuit 242 without passing through the first VDL selector circuit 231 or the second VDL selector circuit 241.
In addition, the number of bits of the voltage determination signal and the mode illustrated in FIGS. 8A and 8B is an example, and voltage determination signals and modes of other numbers of bits may be used.

  11 and 12 are timing charts showing an example of the operation of the semiconductor device when the voltage VDDQ is lower and higher than the reference voltage. Specifically, it is an example of a timing chart showing a change in a VDL delay value and a reference clock and an echo clock skew according to the operation of the I / O voltage determination circuit and its output signal. 11 and 12, the reference voltage is V1 (V) (V1 is a positive value), and the reference level VREF used by the I / O voltage determination circuit 51 is one half (V1 / 2) of the reference voltage V1. The case will be described as an example. One cycle of VDL adjustment is indicated by an arrow at the bottom of the chart, and the number of VDL adjustment cycle is described at the top. The value of the reference level VREF with respect to the divided voltage level VDDQR is indicated by a dotted line. The voltage determination signal is a 4-bit VDLCODE signal and uses a combination of the voltage determination signal and the mode shown in FIGS. 9A to 9H and FIG. The DIVCLK signal indicates the case of the divide-by-2 mode. In addition, for ease of explanation, FIGS. 11 and 12 use, as an example, the case where the value of CODESTP [1: 0] shown in FIGS. 9A and 9E is zero, and the value of D1 shown in the delay amount is 20 ps. It is said.

  FIG. 11 shows an example of the operation when the voltage VDDQ is lower than the reference voltage V1 and the value of the CK-QK skew is -60 ps in the phase adjustment cycle 1. In the first cycle of VDL adjustment, the I / O voltage determination circuit 51 outputs a default value 8 as the initial value of the VDLCODE signal. In the second cycle, the counter 514 is decremented by one, the value of the VDLCODE signal is 7, and the delay amount determined by VDL_R23 is +20 ps. In the third cycle, one more counter 514 is subtracted, the VDLCODE signal is 6 and the delay amount is +40 ps. In the fourth cycle, one more counter 514 is subtracted, the VDLCODE signal is value 5, and the delay amount is +60 ps. In the fifth cycle, one counter 514 is added, the value of the VDLCODE signal is 6, and the delay amount is +40 ps. In the sixth cycle, the counter 514 is decremented by 1, the VDLCODE signal becomes the value 5, and the delay amount becomes +60 ps. In the first to sixth VDL adjustment cycles, the delay amount determined by the VDL_F 24 is always zero.

FIG. 12 shows an example of the operation when the voltage VDDQ is higher than the reference voltage V1 and the value of the CK-QK skew is +60 ps in the phase adjustment cycle 1. In the first cycle of VDL adjustment, the I / O voltage determination circuit 51 outputs a default value 8 as the initial value of the VDLCODE signal. In the second cycle, one counter 514 is added, the value of the VDLCODE signal is 9, and the delay amount determined by VDL_F24 is +20 ps. In the third cycle, one more counter 514 is added, the value of the VDLCODE signal is 10, and the delay amount is +40 ps. In the fourth cycle, one more counter 514 is added, the value of the VDLCODE signal is 11, and the delay amount is +60 ps. In the fifth cycle, one counter 514 is subtracted, the VDLCODE signal is 10 and the delay amount is +40 ps. In the sixth cycle, one counter 514 is added, the VDLCODE signal is 11 and the delay amount is +60 ps. In the first to sixth VDL adjustment cycles, the delay amount determined by VDL_R23 is always zero.
11 and 12, in the seventh and subsequent cycles, the divided voltage level VDDQR repeatedly takes values before and after the reference level VREF.

  As shown in FIGS. 11 and 12, in the semiconductor devices 101 and 102 of this embodiment, the delay value of the VDL is automatically adjusted according to the voltage level of the I / O voltage power supply, and the reference clock signal CK / CK # and The skew (CK-QK skew) of the echo clock signal QK / QK # is suppressed. In this example, it is assumed that when the voltage VDDQ of the I / O voltage power supply is lower than the reference voltage, the path of the feedback clock signal becomes slower than the path of the input clock signal and the output clock signal. The delay of VDL_R23 on the reference side) is increased to suppress the advance of the phase of the feedback clock signal with respect to the input clock signal. On the other hand, when the voltage VDDQ of the I / O voltage power supply is higher than the reference voltage, the delay amount of VDL_F24 on the feedback clock signal side (feedback side) is increased to suppress the phase delay of the echo clock signal with respect to the reference clock signal.

  FIG. 13 shows a skew timing image between the reference clock signal (CK / CK #) and the echo clock signal (QK / QK #) of the conventional circuit. FIG. 14 shows a timing image of the skew between the reference clock signal and the echo clock signal of the semiconductor device of this embodiment. 13 and 14, regarding the voltage level of the I / O voltage power supply, the upper stage shows the case where the voltage VDDQ is lower than the reference voltage (at the time of low VDDQ), and the lower stage shows the case where the voltage VDDQ is higher than the reference voltage (at the time of high VDDQ).

  As shown in FIGS. 13 and 14, the conventional circuit adjusts the phases of the two clock signals while the echo clock signal is delayed with respect to the reference clock signal at the time of low VDDQ. On the other hand, at the time of high VDDQ, the phases of the two clock signals are adjusted while the echo clock signal is faster than the reference clock signal. In FIG. 13, when the CK-QK skews at the time of low VDDQ and at the time of high VDDQ are combined, the total CK-QK skew becomes, for example, a length obtained by adding the CK-QK skews. In other words, in the conventional circuit, when the semiconductor device inputs the reference clock signal and outputs the echo clock signal, the influence of external environmental factors caused by the external device or the fluctuation of the voltage level of the I / O voltage power supply The impact is not considered. Therefore, it is not possible to compensate for the deviation of the echo clock signal due to these effects. As a result, this shift appears in the skew between the reference clock signal and the echo clock signal.

  In contrast, in the semiconductor device of this embodiment, the CK-QK skews at the time of low VDDQ and at the time of high VDDQ are combined in order to compensate for the delay and speed of the echo clock signal generated at the time of low VDDQ and high VDDQ. The total CK-QK skew is shorter than that shown in FIG. This is because the delay adjusting unit 2 selects the delay amount so that the input clock signal and the feedback clock signal input to the phase adjusting unit 3 are compensated for the delay and speed of the echo clock signal with respect to the reference clock signal. It is realized by.

In other words, the delay adjustment unit 2 eliminates the delay or speedup of the echo clock signal with respect to the reference clock signal due to the voltage level of the I / O voltage power supply and external environmental factors of the external device. A delay amount selected in accordance with the voltage level of the voltage power supply and external environmental factors of the external device is used. More specifically, a delay amount corresponding to the combination of the voltage determination signal and the mode information is added to each of the input clock signal and the feedback clock signal. As a result, the phase adjusting unit 3 outputs an output clock signal that compensates for the delay and speed of the echo clock signal with respect to the reference clock signal, and thus the skew between the reference clock signal and the echo clock signal is suppressed.
As described above, in FIG. 14, by adjusting the VDL so as to cancel the phase difference between the reference clock signal and the echo clock signal, which is generated according to the voltage level of the I / O power supply voltage, the total CK-QK skew is reduced. It represents being suppressed.

  As described above, in the semiconductor device according to the present embodiment, the delay adjustment unit 2, specifically, the first VDL unit 21 and the second VDL unit 22 (VDL_R 24, VDL_F 24) Is adjusted so as to cancel the delay difference fluctuation between the path constituted by the feedback unit 4 and the path for inputting / outputting the input clock signal and the feedback clock signal in accordance with the external environmental factor caused by the external device equipped with . In other words, the delay adjusting unit 2 adjusts the amount of delay between the input clock signal input to the phase adjusting unit 3 and the feedback clock signal. As a result, it is possible to suppress fluctuations in the voltage level of the I / O voltage power supply and internal clock skew caused by external environmental factors. In addition, since the relationship between the external environment factor and the voltage level can be considered by using the mode information, it is possible to suppress the internal clock skew caused by the external environment factor from increasing due to the voltage level of the I / O voltage power source. it can.

Embodiment 2. FIG.
In the second embodiment, an aspect in which the determination cycle for determining the voltage level of the I / O voltage power supply can be changed from the outside will be described. In FIG. 1 or FIG. 4, the storage unit 6 stores a determination cycle set from the outside, and the determination cycle is notified from the storage unit 6 to the voltage determination unit 5. Hereinafter, description will be given using a specific circuit diagram.

FIG. 15 is a circuit diagram showing a configuration example of a semiconductor device according to Embodiment 2 of the present invention. The semiconductor device 103 has a configuration in which the functions of the MRS 64 and the I / O voltage determination circuit 52 are changed and an OR circuit 65 is added to the semiconductor device 102 shown in FIG. The other components with the same reference numerals are the same as those in FIG.
The MRS 64 holds a frequency division number set from the outside in addition to holding a mode set from the outside.
The OR circuit 65 generates a logical product of the frequency division number held by the MRS 64 and the value held by the FUSE 62 as a DIVSEL signal (determination period). Although FIG. 15 shows an example in which the DIVSEL signal is generated by the OR circuit 65, the frequency division number held by the MRS 64 may be used as the DIVSEL signal.
15, MRS 64, FUSE 62, and OR circuits 63 and 65 correspond to the storage unit 6 in FIG. 1 or FIG.

FIG. 16 shows an example of the I / O voltage determination circuit. The I / O voltage determination circuit 52 receives the DIVSEL signal from the OR circuit 65.
The frequency division switching circuit 521 receives the DIVSEL signal from the OR circuit 65, divides the PCLK signal from the PLL 32 according to the DIVSEL signal, and outputs it as the DIVCLK signal. As shown in FIG. 16, the PCLK signal, which is an internal clock signal of the semiconductor device 103, is switched to 1-m frequency division (m is a value larger than 1) by the DIVSEL signal controlled by the MRS 64 or Fuse 62, and output as the DIVCLK signal. To do. This allows the I / O voltage determination circuit 52 to switch the voltage determination update frequency. In particular, by making it possible to set the determination cycle from the outside using the MRS 64, it is possible to set the determination cycle at the time of initial setting and to change the determination cycle even after the semiconductor device 103 is operated. Therefore, the determination cycle can be changed according to the operating status of the system in which the semiconductor device 103 is mounted. Thereby, the voltage level of the I / O voltage power source can be determined at an appropriate timing.

Embodiment 3. FIG.
In the third embodiment, an aspect in which the skew between the reference clock signal and the echo clock signal can be adjusted on the system side on which the semiconductor device is mounted will be described.
FIG. 17 is a diagram illustrating a configuration example of a printed board on which the semiconductor device according to the second embodiment of the present invention is mounted. FIG. 17 shows a connection image diagram in which the semiconductor device 103 and the memory controller 201 for controlling the semiconductor device 103 are mounted on the printed circuit board 200.
As shown in FIG. 17, the semiconductor device 104 is connected between the chip 301 and the memory controller 201 via a PAD 191, a package LCR 192, a package ball 193, and a printed circuit board LCR 291.
The wiring on the printed circuit board between the memory controller 201 and the semiconductor device 103 (memory) differs from system to system, and it is not always necessary for the system to match the skew between the input clock signal and the feedback clock signal at the input / output unit of the semiconductor device 102. It may not be optimal.
Therefore, in the present embodiment, an aspect will be described in which the skew between the input clock signal and the feedback clock signal can be shifted by a signal instructed from the memory controller 201 after being incorporated into the system.

  FIG. 18 is a block diagram illustrating a configuration example of a semiconductor device according to the third embodiment of the present invention. The semiconductor device 104 is configured such that the MRS 66 receives a command from the memory controller 201 and notifies the I / O voltage determination circuit 53 to the semiconductor device 103 of FIG. The semiconductor device 104 is different from the semiconductor device 103 of FIG. 15 in that the functions of the MRS 66 and the I / O voltage determination circuit 53 are changed and an OR circuit 67 is added. Other components with the same reference numerals are the same as those in FIG.

The MRS 66 holds an offset value in addition to the mode and frequency division number set from the outside. The offset value is a value set from the memory controller 201 to the MRS 66.
The OR circuit 67 generates a logical product of the offset value held by the MRS 66 and the value held by the FUSE 62 as a COFFSET signal (offset amount). Although FIG. 18 shows an example in which the COFFSET signal is generated by the OR circuit 67, the offset value held by the MRS 66 may be used as the COFFSET signal.
18, MRS 66, FUSE 62, and OR circuits 63, 65, 67 correspond to the storage unit 6 of FIG. 1 or FIG.

FIG. 19 is a circuit diagram illustrating an example of an I / O voltage determination circuit according to the third embodiment. FIG. 19 shows a process in which the I / O voltage determination circuit 53 receives the COFFSET signal together with components such as the MRS 66. The I / O voltage determination circuit 53 in FIG. 19 has a configuration in which the function of the counter 531 is changed with respect to the I / O voltage determination circuit 52 in FIG. 16, and other components with the same reference numerals are the same as those in FIG. Since there is, explanation is omitted.
The counter 531 receives the n-bit COFFSET signal from the OR circuit 67 and forcibly sets an offset to the delay amount.
FIG. 20 shows an example of a circuit diagram of the counter according to the third embodiment. The counter 531 adds an adder 5311-0 to 5311- (n-1) to the subsequent stage of the UPDATE register 5142-0 to 5142- (n-1) and adds COFFSET [n-1: 0] to the VDLCODE. Output [n-1: 0] As shown in FIG. 18 and FIG. 19, by adding an n-bit COFFSET signal as an output signal of the MRS 66, an offset is forcibly set to the delay values of the VDL_R23 and VDL_F24.

FIG. 21 shows an image for adjusting the skew between the reference clock signal and the echo clock signal in the third embodiment. A series of operations for setting various offset values suppresses the skew between the input clock signal and the feedback clock signal as shown in FIG. 21, and the input clock signal, the feedback clock signal, and the skew as a system set as in the case of deskew training. It is also possible to search for the optimum value of. In general, deskew training is a sequence for finding an optimal phase point at which data can be captured by shifting the phase relationship between an input clock signal and an input data signal on a test basis in a receiving apparatus.
According to the semiconductor device of this embodiment, for example, after assembling as a system in which a semiconductor device (memory) and a memory controller are combined, an optimal input / output clock skew value is set by a signal output from the memory controller. Is possible. Alternatively, after the semiconductor device and another system are assembled as a set, an optimal input / output skew for the entire set can be set by a signal output from the system.

18 illustrates the configuration example in which the function of setting the offset value is added to the semiconductor device 103 illustrated in FIG. 15, the function of the present embodiment can be added to the semiconductor device 102 illustrated in FIG. 5. is there. Furthermore, the function of this embodiment can be added to the printed circuit board 200 in the semiconductor device 101 shown in FIG. 4 or the semiconductor device 100 shown in FIG.
In addition, FIG. 17 shows an example in which the semiconductor device 104 and the memory controller 201 are mounted on the printed circuit board 200, but the present invention is not limited to this configuration. The semiconductor device according to the present invention may include a memory controller. FIG. 22 shows a structural example of a semiconductor device including a memory controller. The semiconductor device 300 of FIG. 22 may include a memory 302 and a memory controller 303. The memory 302 includes components included in the semiconductor device 100 illustrated in FIG. The memory controller 303 realizes the same function as the memory controller 202 shown in FIG. The memory 302 and the memory controller 303 transmit and receive signals via various signal lines including the package LCR 192 in the semiconductor device 105.

Other embodiments.
In each of the above embodiments, the PLL unit 31 or the PLL 32 is shown as an example of the phase adjustment unit 3 in FIG. 1, but is not limited thereto. For example, when the frequencies of the reference clock signal and the input clock signal in the semiconductor device 100 match, a DLL circuit can be used instead of the PLL unit 31 or the PLL 32.
In addition, the phase adjustment unit 3 is not limited to the PLL circuit and the DLL circuit, and may be realized by other circuits as long as the phase adjustment unit 3 has a function of matching the phases of the input clock signal and the feedback clock signal. .

  As described above, according to the preferred embodiment of the present invention, the voltage level of the I / O voltage power supply and the external environmental factors (for example, the slew rate of the input signal, the output load on the output signal) generated from the external device In response, the input clock signal and the feedback clock signal are synchronized. In other words, the delay amount is adjusted by the delay adjustment unit 2 (for example, VDL) so as to remove the influence of the power supply voltage level and external environmental factors on the two clock signals input to the phase adjustment unit 3 of FIG. Thus, it becomes possible to input the two clock signals adjusted in the delay amount to the phase adjusting unit 3.

  In addition, this invention is not limited to embodiment shown above. Within the scope of the present invention, it is possible to change, add, or convert each element of the above-described embodiment to a content that can be easily considered by those skilled in the art.

DESCRIPTION OF SYMBOLS 1 1st buffer 2 Delay adjustment part 3 Phase adjustment part 4 Feedback part 5 Voltage determination part 6 Storage part 7 Echo clock generation part 8 2nd buffer 9-1, 9-2 Processing part 11-16, 41-43 buffer 21 First VDL unit (first delay adjustment unit)
22 Second VDL unit (second delay adjustment unit)
23 VDL_R
24 VDL_R
31 PLL circuit 32 PLL
51 I / O voltage determination circuit 61 MRS
62 FUSE
63, 64 OR circuits 100-105, 109 Semiconductor device 191 PAD
192 Package LCR
193 Package balls 201 and 303 Memory controller 231 First VDL selector circuit 232 First delay selection circuit 233 First code selector circuit 241 Second VDL selector circuit 242 Second delay selection circuit 243 Second code selector circuit 291 Printed circuit board LCR
301 chip 302 memory 511 VDDQ voltage division level generation circuit 512 amplifier circuit 513 amplifier determination latch circuit 514 counter 515 pulse generation circuit 516 frequency division switching circuit 2311 first conversion table 2411 second conversion table 5111 series resistance output unit 5112 switch unit 5141-0 to 5141- (n-1), 5311-0 to 5311- (n-1) Adder 5142-0 to 5142- (n-1) UPDATE register

Claims (18)

First and second buffers driven by an I / O voltage power supply;
A voltage determination unit that generates a voltage determination signal indicating a voltage level of the I / O voltage power supply;
An echo clock generator that adjusts the phase of the output clock signal based on the input clock signal input via the first buffer and outputs the signal to the second buffer;
A storage unit for storing mode information for selecting a relationship between the voltage determination signal and the phase adjustment amount;
Have
The echo clock generation unit is a semiconductor device that determines an adjustment amount of the phase of the output clock signal based on the voltage determination signal and the mode information. The echo clock generator is
A phase adjustment unit that generates and outputs a third clock signal by synchronizing the phase or delay of the second clock signal with the first clock signal;
A feedback unit for generating a feedback clock signal based on the third clock signal;
Based on the voltage determination signal and the mode information, a first delay amount is added to the input clock signal to generate the first clock signal, and a second delay amount is added to the feedback clock signal. A delay adjusting unit for generating the second clock signal;
The semiconductor device according to claim 1, comprising: The delay adjustment unit
Based on the voltage determination signal, the first conversion table, and the mode information, one delay path is selected from a plurality of delay paths having different delay amounts, and is set as the first delay amount.
The second delay amount is selected by selecting another delay path from among a plurality of delay paths having different delay amounts based on the voltage determination signal, the second conversion table, and the mode information. Item 3. The semiconductor device according to Item 2.   The delay adjustment unit includes the first and second conversion tables so as to suppress a clock skew between a reference clock signal input to the first buffer and an echo clock signal output from the second buffer. The semiconductor device according to claim 3, wherein the semiconductor device is configured.   5. The feedback unit according to claim 1, wherein the feedback unit includes a third buffer having a configuration equivalent to that of the first buffer and a fourth buffer having a configuration equivalent to that of the second buffer. The semiconductor device according to one item. The mode information includes a plurality of modes that associate different delay amounts with arbitrary voltage levels of the I / O voltage power supply,
The storage unit records one mode of the plurality of modes as the mode information,
The delay adjustment unit includes the first delay amount corresponding to a combination of the voltage determination signal and the one mode, and a plurality of delay amounts associated with the voltage determination signal and the plurality of modes. 5. The semiconductor device according to claim 2, wherein the semiconductor device is configured to select a second delay amount. 6.   The semiconductor device according to claim 6, wherein the delay adjustment unit is configured such that a delay amount that changes in accordance with a voltage level of the I / O voltage power supply has a different size for each mode. The voltage determination unit generates a result of comparing the voltage level of the I / O voltage power supply with a reference voltage as the voltage determination signal,
When the voltage level of the I / O voltage power source is higher than the reference voltage based on the voltage determination signal and the one mode, the delay adjustment unit determines the second delay amount as the first delay amount. The first delay amount is configured to be larger than the second delay amount when the voltage level of the I / O voltage power supply is lower than the reference voltage. 8. The semiconductor device according to 6 or 7. The delay adjustment unit
When the input clock signal is received and the voltage level of the I / O voltage power supply is lower than a reference voltage, the first delay amount is selected based on the voltage determination signal and the one mode, and the I / O A first delay adjustment unit configured to generate the first clock signal by setting the first delay amount to zero when the voltage level of the voltage power supply is equal to or higher than a reference voltage;
When the feedback clock signal is received and the voltage level of the I / O voltage power source is higher than a reference voltage, the second delay amount is selected based on the voltage determination signal and the one mode, and the I / O 9. A second delay adjustment unit configured to set the second delay amount to zero and generate the second clock signal when a voltage level of a voltage power source is equal to or lower than a reference voltage. Semiconductor device.   The delay adjustment unit is configured to correspond to a mode in which the first delay amount and the second delay amount change in proportion to a voltage level of the I / O voltage power source. The semiconductor device according to claim 6.   The delay adjustment unit increases the amount of change in the first delay amount and the second delay amount according to the voltage level as the difference between the voltage level of the I / O voltage power supply and the reference voltage increases. The semiconductor device according to claim 6, wherein the semiconductor device is configured to correspond to a mode.   The delay adjustment unit is configured so that the first delay amount and the second delay amount that change according to a voltage level of the I / O voltage power supply correspond to a mode that is not linear characteristics. 12. The semiconductor device according to claim 6, wherein the semiconductor device is characterized in that:   The delay adjustment unit is configured to select the number of delay elements according to a mode recorded by the storage unit and the determined voltage level. The semiconductor device according to claim 1.   The delay adjustment unit adds an offset amount to the voltage determination signal, and the first delay amount and the second delay associated with a combination of the voltage determination signal obtained by adding the offset amount and the mode information. The semiconductor device according to claim 2, wherein the semiconductor device is configured to select an amount. The voltage determination unit determines the voltage level at an arbitrary cycle to generate a voltage determination signal,
The delay adjustment unit generates the first clock signal and the second clock signal according to the generation of the voltage determination signal. Semiconductor device. The storage unit records a determination period that identifies the arbitrary period,
The semiconductor device according to claim 15, wherein the voltage determination unit generates the voltage determination signal in the determination cycle.   The semiconductor device according to claim 2, wherein the phase adjustment unit is one of a PLL (Phase-locked Loop) circuit and a DLL (Digital Locked Loop) circuit.   The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor memory device.

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