JP2013089781A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having serially connected elements constituting an inverter circuit that allows preventing the occurrence of reduction in a withstand voltage by an influence of high potential wiring of the serial connection.SOLUTION: First and second elements each include a transistor performing switching of a current and a diode performing reflow, a first main electrode of the transistor and a first main electrode of the diode are electrically connected, and a second main electrode of the transistor and a second main electrode of the diode are electrically connected. In the first and second elements, the first main electrode of the transistor in the first element and the second main electrode of the transistor in the second element are electrically connected. Moreover, the first and second elements are disposed so that a conductive semiconductor region between the first main electrode of the transistor in the first element and a drift region and a conductive semiconductor region between the second main electrode of the transistor in the second element and the drift region are faced to each other, in a plan view of a semiconductor substrate.

Description

  The present invention relates to a semiconductor device, and more particularly, in a semiconductor device including semiconductor elements connected in series to form an inverter circuit, prevents a reduction in breakdown voltage due to the influence of the serially connected wiring (high potential wiring). The present invention relates to a semiconductor device that can be used.

  In recent years, a semiconductor element in which a switching transistor and a reflux diode are mounted on one semiconductor layer has been developed. This type of semiconductor element is used by being incorporated into various electric control circuits depending on the application. For example, an inverter circuit that converts DC power to AC power is configured by connecting a plurality of semiconductor elements of this type.

  Patent Document 1 discloses an example of a semiconductor element used in an inverter circuit for power conversion (see FIG. 1). In this semiconductor element, a lateral IGBT (Lateral Insulated Gate Bipolar Transistor: hereinafter referred to as LIGBT) and a free wheeling diode (hereinafter referred to as FWD) are mounted on one SOI (Semiconductor on Insulator) substrate. It is configured. An inverter circuit is configured by connecting two semiconductor elements in series.

  FIG. 9 is a plan layout view showing an embodiment of a semiconductor element. FIG. 10 is a diagram showing a planar layout of each of the LIGBT and FWD electrodes shown in FIG.

  As shown in FIG. 9, the first trench isolation / separation part 120 makes a round in a square shape when the SOI substrate 2000 is viewed in plan. In addition, the second trench isolation part 140 is provided at a distance from the first trench isolation part 120, and the periphery of the first trench isolation part 120 is rectangular when the SOI substrate 2000 is viewed from above. It is going around. The first trench isolation part 120 and the second trench isolation part 140 extend in parallel, and the distance between them is constant.

  The element regions 160 and 180 sandwiched between the first trench isolation part 120 and the second trench isolation part 140 are adjacent to each other in the adjacent part 110 when the SOI substrate 2000 is viewed in plan view.

  A LIGBT is disposed in the first element region 160, and an FWD is disposed in the second element region 180.

  In this semiconductor device, as shown in FIG. 10, the collector electrode 420 of the LIGBT and the cathode electrode 1420 of the FWD are in contact with each other and are integrally formed as one common electrode. A cathode bonding pad 190 is provided. For this reason, the connection wiring which connects the collector electrode 420 and the cathode electrode 1420 is unnecessary. Further, the emitter electrode 480 of the LIGBT and the anode electrode 1480 of the FWD are in contact with each other and are integrally formed as one common electrode, and an emitter / anode bonding pad 150 is provided on the common electrode. . For this reason, the connection wiring which connects the emitter electrode 480 and the anode electrode 1480 is also unnecessary. Thereby, the wiring which connects LIGBT and FWD does not extend above the drift region of LIGBT and FWD. Therefore, in this semiconductor element, the potential distribution in the drift region becomes nonuniform due to the current flowing through the connection wiring connecting the emitter electrode 480 and the anode electrode 1480 and the connection wiring connecting the collector electrode 420 and the cathode electrode 1420. Does not occur. Therefore, there is an advantage that a breakdown voltage drop due to these connection wirings does not occur in the semiconductor element. Reference numeral 440 represents a gate electrode.

  However, in order to connect in series the semiconductor element that constitutes the upper arm of the inverter circuit (see FIG. 1) and the semiconductor element that constitutes the lower arm, a semiconductor element having exactly the same structure is used for the upper arm and the lower arm. When these are arranged side by side with respect to the substrate, the following problems may occur.

  That is, for example, an emitter region is formed on the outer peripheral side of each semiconductor element, and a collector region is formed on the inner peripheral side. In this case, the wiring A (see FIG. 1) connecting the emitter region in the upper arm and the collector region in the lower arm straddles the drift region of the lower arm. For this reason, the electron concentration on the surface of the drift region (breakdown voltage holding region) is induced by the potential of the connection wiring, and the charge balance of the drift region is lost. As a result, in the drift region, the potential distribution is non-uniform, the depletion layer is prevented from growing during reverse bias, and the breakdown voltage may be reduced.

JP 2011-61051 A

  The present invention has been made in view of such circumstances, and in a semiconductor device including semiconductor elements connected in series to form an inverter circuit, the breakdown voltage is reduced due to the influence of the wiring connected in series (high potential wiring). An object of the present invention is to provide a semiconductor device capable of preventing the occurrence.

The first invention is
A semiconductor device formed on a semiconductor substrate and having first and second elements having the same conductivity type connected in series,
The first and second elements are each
A transistor having a first main electrode and a second main electrode, configured to allow current to flow through the drift region between the first main electrode and the second main electrode, and for switching current;
A first main electrode and a second main electrode, a current flowing through the drift region between the first main electrode and the second main electrode, and a diode that performs reflux; and
A first main electrode of the transistor and a first main electrode of the diode are electrically connected; a second main electrode of the transistor and a second main electrode of the diode are electrically connected;
The first element and the second element are:
The first main electrode of the transistor in the first element is electrically connected to the second main electrode of the transistor in the second element; and
When the semiconductor substrate is viewed in plan, the conductive semiconductor region between the first main electrode of the transistor and the drift region in the first element, and the second main of the transistor in the second element. The semiconductor device is arranged so that the electrode and the conductive semiconductor region between the drift regions face each other.

  According to the first invention, when the semiconductor substrate is viewed in plan, for example, the first and second transistors are arranged such that the emitter region of the transistor in the first element faces the collector region of the transistor in the second element. Two elements are arranged. Therefore, the wiring connecting the emitter region and the collector region does not have to straddle the drift region. As a result, in a semiconductor device including semiconductor elements connected in series to form an inverter circuit, it is possible to prevent a breakdown voltage from being reduced due to the influence of the serially connected wiring (high potential wiring).

According to a second invention, in the first invention,
The first and second elements are configured in a loop shape,
When the semiconductor substrate is viewed in plan, the first element is disposed inside a loop of the second element.

  According to the second invention, since the first element is arranged inside the loop of the second element, the entire semiconductor device can be configured compactly.

According to a third invention, in the first invention,
The semiconductor device is a device that converts a direct current into an alternating current.

  According to the third aspect of the invention, it is possible to obtain a conversion device that does not cause a decrease in breakdown voltage due to the influence of the high potential wiring.

According to a fourth invention, in the first invention,
The transistor and the diode are LIGBT and FWD, respectively.

  According to the fourth aspect of the invention, a semiconductor device can be configured using LIGBT and FWD.

According to a fifth invention, in the first invention,
The transistor and the diode are LDMOS and FWD, respectively.

  According to the fifth aspect of the present invention, a semiconductor device can be configured using LDMOS and FWD.

According to a sixth invention, in the first invention,
The transistor and the diode are a LIGBT and an LDMOS, respectively.

  According to the sixth aspect of the invention, a semiconductor device can be configured using LIGBT and LDMOS.

  According to the present invention, in a semiconductor device including semiconductor elements connected in series to form an inverter circuit, a semiconductor device capable of preventing a decrease in breakdown voltage due to the influence of the wiring connected in series (high potential wiring). Can get.

The figure which shows the outline of the circuit structure of the inverter circuit built in the inverter module The top view which shows the layout of the semiconductor device which concerns on 1st Embodiment The top view which shows the layout of each electrode arrange | positioned at the semiconductor device which concerns on 1st Embodiment on FIG. It is sectional drawing corresponding to the II line | wire of FIG. 2, and is sectional drawing of LIGBT in the vicinity of the adjacent part with FWD. It is sectional drawing corresponding to the II-II line of FIG. 2, and sectional drawing of FWD in the vicinity of the adjacent part with LIGBT. The top view which shows the layout of the semiconductor device which concerns on 2nd Embodiment The top view which shows the layout of each electrode arrange | positioned at the semiconductor device which concerns on 2nd Embodiment on FIG. The top view which shows the layout of the semiconductor device which concerns on 3rd Embodiment The figure which shows the layout of the semiconductor element of patent document 1 The top view which shows the layout of each electrode arrange | positioned at the semiconductor element of patent document 1 on FIG.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.
Before describing the configuration of the semiconductor device according to the first embodiment, first, an inverter circuit including the semiconductor device will be described.

  FIG. 1 is a diagram showing an outline of a circuit configuration of an inverter circuit incorporated in an inverter module. Inverter circuits 100, 101, and 102 are provided between high-voltage DC power supply 300 and motor 400, respectively, convert DC power supplied from high-voltage DC power supply 300 into AC power, and transfer the AC power to motor 400. Supply. Note that the DC power supplied from the high-voltage DC power supply 300 is generally boosted by a converter, and the converter is often incorporated in an inverter module. A capacitor 200 is provided between the high-voltage DC power supply 300 and the inverter circuits 100, 101, and 102 to smooth the DC power.

  In the example shown in FIG. 1, three inverter circuits 100, 101, and 102 are provided. In the following description, the three inverter circuits 100, 101, and 102 may be collectively referred to as an inverter circuit 1000. The inverter circuit 100 includes two elements 111 and 112 connected in series, the inverter circuit 101 includes two elements 113 and 114 connected in series, and the inverter circuit 102 includes two elements 115 and 114 connected in series. 116 is provided. The three inverter circuits 100, 101, and 102 include six elements 111 to 116 in total. Each inverter circuit corresponds to the semiconductor device according to the present embodiment.

  The element 111 constitutes the upper arm of the inverter circuit, and the element 112 constitutes the lower arm of the inverter circuit. Similarly, the element 113 constitutes an upper arm, the element 114 constitutes a lower arm, the element 115 constitutes an upper arm, and the element 116 constitutes a lower arm. In the following description, the elements 111, 113, and 115 may be referred to as upper arms. The elements 112, 114, and 116 are sometimes referred to as lower arms. As will be described later, the six elements 111 to 116 are mounted on one SOI substrate, and are configured by one chip. Each of the six elements 111 to 116 may be mounted on a separate SOI substrate. Each of the elements 111 to 116 includes transistors Tr1 to Tr6 that perform current switching, and reflux diodes D1 to D6 connected in parallel to the transistors Tr1 to Tr6. A lateral IGBT (Lateral Insulated Gate Bipolar Transistor: hereinafter referred to as LIGBT) is adopted for the transistors Tr1 to Tr6. As the free-wheeling diodes D1 to D6, free-wheeling diodes (hereinafter referred to as FWD) are employed. A gate control signal is applied to the gates of the transistors Tr1 to Tr6 from an inverter drive circuit (not shown).

  As shown in FIG. 1, the inverter circuit 1000 includes a U-phase arm, a V-phase arm, and a W-phase arm connected in parallel between the high-voltage wiring 100H and the low-voltage wiring 100L of the high-voltage DC power supply 300. Each arm corresponds to the semiconductor device according to the present embodiment. As described above, the U-phase arm is composed of the elements 111 and 112 connected in series via the intermediate node Nm1. As described above, the V-phase arm is configured by the elements 113 and 114 connected in series via the intermediate node Nm2. As described above, the W-phase arm is composed of elements 115 and 116 connected in series via intermediate node Nm3.

  The intermediate nodes Nm1 to Nm3 are connected to the phase output lines Uout, Vout, Wout. Each phase output line Uout, Vout, Wout is connected to one end of each phase coil of the three-phase motor 400. The other end of each phase coil is commonly connected to the neutral point. Note that the motor 400 in this example has three phases, but the technology disclosed in this specification can be applied to various AC motors without limiting the number of phases.

  As described above, all of the six elements 111 to 116 are composed of LIGBT and FWD and have a common form. Hereinafter, the element 111 constituting the inverter circuit 100 (semiconductor device) will be described in detail with reference to FIGS. FIG. 2 is a plan view showing the layout of the element 111. FIG. 3 is a plan view showing the layout of each electrode disposed in the element 111 in an overlapping manner with FIG.

  In the inverter circuit as shown in FIG. 1, the LIGBT of the upper arm 111 and the LIGBT of the lower arm 112 are normally driven alternately, the LIGBT of the upper arm 113 and the LIGBT of the lower arm 114 are driven alternately, The LIGBT of the arm 115 and the LIGBT of the lower arm 116 are driven alternately. However, when the drive is switched, both are temporarily turned on, and the high-voltage wiring 100H and the low-voltage wiring 100L are short-circuited. Then, since a high voltage is applied between the emitter and the collector when the LIGBT is in the on state, an excessive current due to a short circuit flows between the emitter and the collector. That is, a large current flows through the LIGBT at the time of switching although instantaneously. On the other hand, since the FWD has a high resistance from the high-voltage wiring 100H side to the low-voltage wiring 100L side, the possibility that an excessive current due to a short circuit flows is low.

  In the present embodiment, the upper arm 111 and the lower arm 112 have the same structure but have different sizes. Specifically, as shown in FIG. 2, the upper arm 111 and the lower arm 112 are configured in a loop shape (square shape). Further, the upper arm 111 is formed to be smaller than the lower arm 112 so that the upper arm 111 is arranged inside the loop of the lower arm 112 with a space when the SOI substrate 20 is viewed in plan. As shown in FIG. 2, the semiconductor layer 26 of the SOI substrate 20 includes a first trench isolation portion 12 and a second trench isolation portion 14 that penetrate the semiconductor layer 26 in each of the upper arm 111 and the lower arm 112. Is provided. The first trench isolation / separation portion 12 makes a round when the SOI substrate 20 is viewed in plan. The second trench isolation part 14 is provided away from the first trench isolation part 12 and makes a round around the first trench isolation part 12 when the SOI substrate 20 is viewed in plan. The 1st trench insulation isolation | separation part 12 and the 2nd trench insulation isolation | separation part 14 are extended in parallel, and the space | interval is constant.

  In each of the upper arm 111 and the lower arm 112, the element regions 16 and 18 sandwiched between the first trench isolation portion 12 and the second trench isolation portion 14 are isolated from the peripheral semiconductor layer 26. The first element region 16 and the second element region 18 have a current flow direction (a direction from the first trench insulation isolation portion 12 side to the second trench insulation isolation portion 14 side) when the semiconductor layer 26 is viewed in plan view. Adjacent to each other. The element region including the first element region 16 and the second element region 18 is formed so as to make a circuit. Although the form which makes a round is not specifically limited, In the example shown by FIG.2, 3, it is made into the square shape as a whole.

  4 is a cross-sectional view corresponding to the line I-I in FIG. 2, and is a cross-sectional view of the LIGBT in the vicinity of the adjacent portion to the FWD. As shown in FIG. 4, the SOI substrate 20 includes a semiconductor support layer 22, a buried insulating layer 24, and a semiconductor layer 26. The semiconductor support layer 22 is formed of single crystal silicon into which an n-type or p-type impurity is introduced at a high concentration. The buried insulating layer 24 is made of silicon oxide. The semiconductor layer 26 is formed of single crystal silicon into which n-type impurities are introduced at a low concentration.

  As shown in FIG. 4, the LIGBT is formed in the first element region 16 sandwiched between the first trench isolation portion 12 and the second trench isolation portion 14. The first trench isolation portion 12 extends through the semiconductor layer 26 to the buried insulating layer 24, and includes a silicon oxide film 12a and a polysilicon core 12b covered with the oxide film 12a. Yes. Similarly, the second trench isolation portion 14 penetrates the semiconductor layer 26 and reaches the buried insulating layer 24, and includes a silicon oxide film 14a and a polysilicon core portion 14b covered with the oxide film 14a. I have.

As shown in FIG. 4, the LIGBT includes a p ⁺ type body contact region 31, an n ⁺ type emitter region 32, a p type body region 33, an n ⁻ type drift region 34, and an n ⁺ type. Embedded region 35, n-type buffer region 36, and p ⁺ -type collector region 37.

  The body contact region 31, the emitter region 32, and the body region 33 are conductive semiconductor regions, and are provided on the second trench isolation portion 14 side in the surface layer portion of the semiconductor layer 26. In particular, the body contact region 31 and the body region 33 are in contact with the side surface of the second trench isolation portion 14. Emitter region 32 is separated from drift region 34 by body region 33. The drift region 34 is provided between the body region 33 and the buffer region 36 and is a region that holds a potential difference when the LIGBT is turned off. The buried region 35 is provided in the back layer portion of the semiconductor layer 26, and is provided between the first trench isolation portion 12 and the second trench isolation portion 14. The buffer region 36 and the collector region 37 are provided on the first trench isolation portion 12 side in the surface layer portion of the semiconductor layer 26. In particular, the buffer region 36 and the collector region 37 are provided on the first trench isolation portion 12. It touches the side. The collector region 37 is separated from the drift region 34 by the buffer region 36. Note that these cross-sectional structures are common throughout the first element region 16. Therefore, the body contact region 31, the emitter region 32, and the body region 33 are provided over the entire first element region 16 along the side surface of the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. ing. Similarly, the buffer region 36 and the collector region 37 are conductive semiconductor regions, and extend over the entire first element region 16 along the side surface of the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. Is provided. The conductive semiconductor region including the body contact region 31, the emitter region 32, and the body region 33 in the upper arm 111, and the conductive semiconductor region including the buffer region 36 and the collector region 37 in the lower arm 112 are formed at positions facing each other. ing.

  As shown in FIG. 4, the LIGBT further includes an interlayer insulating film 41, a collector electrode 42 (first main electrode of the transistor), a LOCOS (Local Oxidation of Silicon) oxide film 43, a gate electrode 44, and a planar gate. A portion 47 and an emitter electrode 48 (second main electrode of the transistor) are provided.

  The interlayer insulating film 41 covers the surface of the SOI substrate 20 and is made of silicon oxide. The collector electrode 42 is disposed on the surface of the interlayer insulating film 41 on the first trench green separation portion 12 side. In particular, the collector electrode 42 is also disposed above the first trench isolation portion 12. The collector electrode 42 is disposed above the first trench isolation portion 12 along at least the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. Further, a part of the collector electrode 42 extends through the interlayer insulating film 41 and is in contact with the collector region 37 via the contact portion 42a. The contact portion 42 a is provided over the entire first element region 16 along the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. The collector electrode 42 extends beyond the buffer region 36 in the direction from the first trench isolation part 12 to the second trench isolation part 14 (leftward in the case of FIG. 4) when the SOI substrate 20 is viewed in plan. It is desirable that it is not arranged.

  The LOCOS oxide film 43 is provided on the surface of the drift region 34, and the gate electrode 44 formed of silicon oxide is disposed on the surface of the interlayer insulating film 41 between the collector electrode 42 and the emitter electrode 48. ing. A portion of the gate electrode 44 extends through the interlayer insulating film 41 and is in contact with the planar gate portion 47. The planar gate portion 47 has a planar electrode 45 and a gate insulating film 46, and faces the surface of the body region 33 that separates the emitter region 32 and the drift region 34. The planar electrode 45 covers the surface of the gate insulating film 46 and a part of the surface of the LOCOS oxide film 43, and is formed of polysilicon into which impurities are introduced at a high concentration. The gate insulating film 46 is made of silicon oxide.

  The emitter electrode 48 is disposed on the surface of the interlayer insulating film 41 on the second trench isolation portion 14 side. In particular, the emitter electrode 48 is also disposed above the second trench isolation portion 14. . The emitter electrode 48 is disposed above the second trench isolation part 14 along at least the second trench isolation part 14 when the SOI substrate 20 is viewed in plan. Further, the emitter electrode 48 partially extends through the interlayer insulating film 41 and is in contact with the body contact region 31 and the emitter region 32 via the contact portion 48a. The contact portion 48 a is provided over the entire first element region 16 along the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. In the adjacent portion 11, the collector electrode 42 and the emitter electrode 48 are arranged with an interval in the x-axis direction, and the gate electrode 44 is arranged within the interval.

FIG. 5 is a cross-sectional view corresponding to the line II-II in FIG. 2, and is a cross-sectional view of the FWD in the vicinity of the adjacent portion to the LIGBT. As shown in FIG. 5, in the FWD, some configurations are common to the LIGBT configurations. In the following, only the configuration different from the LIGBT will be described, common configurations will be denoted by common reference numerals, and description thereof will be omitted. The FWD includes a p ⁺ -type anode contact region 131, a p-type anode region 133, an n-type cathode region 136, an n ⁺ -type cathode contact region 137, and a cathode electrode 142 (first main electrode of the diode). And the anode electrode 148 (second main electrode of the diode), which is different from the LIGBT.

  The anode contact region 131 and the anode region 133 are provided on the second trench isolation portion 14 side in the surface layer portion of the semiconductor layer 26. In particular, the anode contact region 131 and the anode region 133 are in contact with the side surface of the second trench isolation portion 14. The anode region 133 is manufactured by the same manufacturing process as the body region 33 of the LIGBT, and has the same dopant, concentration, and diffusion depth as the body region 33. The cathode region 136 and the cathode contact region 137 are provided on the first trench isolation portion 12 side in the surface layer portion of the semiconductor layer 26. In particular, the cathode region 136 and the cathode contact region 137 are in contact with the side surfaces of the first trench isolation portion 12. The cathode region 136 is manufactured in the same manufacturing process as the buffer region 36 of the LIGBT, and has the same dopant, concentration, and diffusion depth as the buffer region 36. These cross-sectional structures are common throughout the second element region 18. Therefore, the anode contact region 131 and the anode region 133 are provided over the entire second element region 18 along the side surface of the second trench isolation part 14 when the SOI substrate 20 is viewed in plan. Similarly, the cathode region 136 and the cathode contact region 137 are provided over the entire second element region 18 along the side surface of the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.

  Further, the body region 33 of the LIGBT and the anode region 133 of the FWD are in contact with each other via a trench insulation isolation portion provided in the adjacent portion 11 shown in FIG. For this reason, these p-type regions 33 and 133 circulate in the element regions 16 and 18 along the side surfaces of the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. Further, the buffer region 36 of the LIGBT and the cathode region 136 of the FWD are also in contact with each other via a trench isolation portion provided in the adjacent portion 11 shown in FIG. For this reason, these n-type regions 36 and 136 also circulate in the element regions 16 and 18 along the side surface of the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan.

  The cathode electrode 142 is disposed on the surface of the interlayer insulating film 41 on the first trench isolation portion 12 side. In particular, the cathode electrode 142 is also disposed above the first trench isolation portion 12. The cathode electrode 142 is disposed above the first trench isolation portion 12 along at least the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. Further, a part of the cathode electrode 142 extends through the interlayer insulating film 41 and is in contact with the cathode contact region 137 through the contact portion 142a. The contact portion 142 a is provided over the entire second element region 18 along the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan. Further, the cathode electrode 142 is disposed beyond the cathode region 136 in the direction from the first trench insulation isolation portion 12 to the second trench insulation isolation portion 14 (leftward in the case of FIG. 5) when viewed in plan. Desirably not.

  The anode electrode 148 is disposed on the surface of the interlayer insulating film 41 on the second trench isolation portion 14 side. In particular, the anode electrode 148 is also disposed above the second trench isolation portion 14. The anode electrode 148 is disposed above the second trench isolation part 14 along at least the second trench isolation part 14 when the SOI substrate 20 is viewed in plan. Further, a part of the anode electrode 148 extends through the interlayer insulating film 41 and is in contact with the anode contact region 131 through the contact portion 148a. The contact portion 148a is provided over the entire second element region 18 along the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. The anode electrode 148 preferably extends partially through the interlayer insulating film 41 and is in contact with the planar electrode 45. Further, the anode electrode 148 is disposed beyond the planar electrode 45 in the direction from the second trench insulation isolation portion 14 to the first trench insulation isolation portion 12 (rightward in the case of FIG. 5) when viewed in plan. Desirably not. In the adjacent portion 11, the cathode electrode 142 and the anode electrode 148 are arranged at an interval in the x-axis direction.

  Further, the contact portion 48a of the emitter electrode 48 of the LIGBT and the contact portion 148a of the anode electrode 148 of the FWD are adjacent to each other in the adjacent portion 11 shown in FIG. For this reason, these contact portions 48 a and 148 a make a round along the second trench isolation portion 14 when the SOI substrate 20 is viewed in plan. Further, the contact portion 42a of the collector electrode 42 of the LIGBT and the contact portion 142a of the cathode electrode 142 of the FWD are also adjacent in the adjacent portion 11 shown in FIG. For this reason, these contact portions 42 a and 142 a make a round along the first trench isolation portion 12 when the SIO substrate 20 is viewed in plan.

  The collector electrode 42, the gate electrode 44, and the emitter electrode 48 of the LIGBT, and the cathode electrode 142 and the anode electrode 148 of the FWD are manufactured in the same manufacturing process using vapor deposition technology. Aluminum is used as the material for these electrodes.

  As shown in FIG. 3, the collector electrode 42 of the LIGBT of the upper arm 111 and the cathode electrode 142 of the FWD of the upper arm 111 are in the range inside the first trench isolation portion 12 when the SOI substrate 20 is viewed in plan view. Is provided. That is, the LIGBT collector electrode 42 of the upper arm 111 and the FWD cathode electrode 142 of the upper arm 111 are one common electrode. A collector / cathode bonding pad 19 is provided on the one common electrode.

  Also, the LMIT emitter electrode 48 of the upper arm 111, the FWD anode electrode 148 of the upper arm 111, the LIGBT collector electrode 42 of the lower arm 112, and the FWD cathode electrode 142 of the lower arm 112, It is provided outside the two trench isolation parts 14 and in a range inside the first trench isolation part 12 of the lower arm 112. That is, the LIGBT emitter electrode 48 of the upper arm 111 and the FWD anode electrode 148 of the upper arm 111, and the LIGBT collector electrode 48 of the lower arm 112 and the FWD cathode electrode 142 of the lower arm 112 are one common electrode. is there. An emitter / anode / collector / cathode bonding pad 50 is provided on the one common electrode.

  Further, the LMIT emitter electrode 48 of the lower arm 112 and the FWD anode electrode 148 of the lower arm 112 are provided in a range outside the second trench isolation portion 14 of the lower arm 112 in plan view. That is, the LMIT emitter electrode 48 of the lower arm 112 and the FWD anode electrode 148 of the lower arm 112 are one common electrode. An emitter / anode bonding pad 15 is provided on the one common electrode.

  According to the first embodiment, when the SOI substrate 20 is viewed in plan, the LIGBT emitter region 32 in the upper arm 111 and the LIGBT collector region 37 in the lower arm 112 face each other. An arm 112 is arranged. Therefore, the wiring connecting the emitter region 32 and the collector region 37 does not need to straddle the drift region of the LIGBT. Thereby, in the semiconductor device including the upper arm 111 and the lower arm 112 connected in series, even if a high voltage is applied to the serially connected wiring (electrode plate in the illustrated example), the breakdown voltage does not decrease in the LIGBT.

  Further, according to the first embodiment, the collector electrode 42 of the LIGBT and the cathode electrode 142 of the FWD are configured as one common electrode. For this reason, the connection wiring which connects the collector electrode 42 and the cathode electrode 142 is unnecessary. Further, the emitter electrode 48 of the LIGBT and the anode electrode 148 of the FWD are also configured as one common electrode. For this reason, the connection wiring which connects the emitter electrode 48 and the anode electrode 148 is also unnecessary. Accordingly, even if a high voltage is applied to the wiring (electrode plate in the illustrated example) that connects the LIGBT and the FWD, the breakdown voltage does not decrease in the LIGBT and the FWD.

(Second Embodiment)
A second embodiment of the semiconductor device according to the present invention will be described with reference to the drawings.
FIG. 6 is a plan view showing a layout of the semiconductor device according to the second embodiment. FIG. 7 is a plan view showing the layout of each electrode disposed in the semiconductor device according to the second embodiment, overlaid on FIG. In addition, about the structure similar to 1st Embodiment, the same referential mark is attached | subjected and the description is abbreviate | omitted.

  In the first embodiment, the upper arm 111 is disposed inside the loop of the lower arm 112. On the other hand, in the second embodiment, the lower arm 112A is arranged on the side of the upper arm 111 when the SOI substrate 20 is viewed in plan. Although not shown, the same applies to the other arms.

  In order to achieve the above arrangement, the lower arm 112A of the second embodiment has the positional relationship between the inner peripheral portion and the outer peripheral portion of the loop reversed with respect to the lower arm 112 of the first embodiment. Specifically, an emitter region and an anode region are positioned on the inner peripheral side of the lower arm 112A, and a collector region and a cathode region are positioned on the outer peripheral side. Thus, the emitter electrode and the anode electrode are positioned on the inner peripheral side of the upper arm 111, and the collector electrode and the cathode electrode are positioned on the outer peripheral side of the lower arm 112A. And the collector electrode and cathode electrode of the upper arm 111 are comprised integrally. Further, the emitter electrode and the anode electrode of the lower arm 112A are integrally formed. Further, the emitter electrode and cathode electrode of the upper arm 111 and the collector electrode and anode electrode of the lower arm 112A are integrally formed (that is, four types of electrodes are integrally formed).

  Thereby, similarly to the first embodiment, it is possible to prevent the breakdown voltage of the LIGBT and the FWD from decreasing.

  In the second embodiment, the positional relationship between the inner peripheral portion and the outer peripheral portion of the lower arm is reversed with respect to the first embodiment, but instead, the inner peripheral portion and the outer periphery of the upper arm are reversed. You may reverse the positional relationship of a side part.

(Third embodiment)
A third embodiment of the semiconductor device according to the present invention will be described with reference to the drawings.
FIG. 8 is a plan view showing the layout of the semiconductor device according to the third embodiment. Components common to those of the semiconductor device according to the first embodiment are denoted by common reference numerals and description thereof is omitted.

  In the semiconductor device according to the third embodiment, part of the element regions 16 and 18 sandwiched between the first trench isolation portion 12 and the second trench isolation portion 14 of the upper arm 111A is a plan view of the SOI substrate 20. Sometimes, it reciprocates at least twice (in the illustrated example, it reciprocates four times along the y-axis direction). In other words, part of the element regions 16 and 18 surrounded by the first trench isolation portion 12 and the second trench isolation portion 14 has a comb-like shape when the SOI substrate 20 is viewed in plan view. It can also be said. Further, in the illustrated example, in the comb-like portion, LIGBTs and FWDs are alternately arranged for each bent portion, and three LIGBTs and three FWDs are formed as the entire upper arm 111A. By adopting such a comb-like shape, the area of the element regions 16 and 18 occupying the semiconductor layer 26 can be increased, and the mounting area can be reduced.

  In order to equalize the characteristics of the upper arm 111A and the lower arm 112, when the SOI substrate 20 is viewed in plan, the upper arm 111A and the lower arm 112 have the same LIGBT area, and the upper arm 111A and the lower arm 112 It is preferable that the FWD areas be equal.

  As mentioned above, although each embodiment of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the above-described embodiments. For example, in each of the above embodiments, a LIGBT is used as a transistor and an FWD is used as a diode. Instead of this, an LDMOS (Laterally Diffused Metal Oxide Semiconductor) is used as a transistor and an FWD is used as a diode. May be. Further, LIGBT may be used as a transistor and LDMOS may be used as a diode. When LDMOS is used as a diode, a parasitic diode of LDMOS is used.

  The present invention provides a semiconductor device including semiconductor elements connected in series to form an inverter circuit, and the like as a semiconductor device capable of preventing a decrease in breakdown voltage due to the influence of the wiring (high potential wiring) connected in series. Is available.

DESCRIPTION OF SYMBOLS 11 Adjacent part 12 1st trench isolation part 13 3rd trench isolation part 14 2nd trench isolation part 15 Emitter-anode bonding pad 16 1st element area 18 2nd element area 19 Collector-cathode bonding pad 20 SOI Substrate 22 Semiconductor support layer 24 Buried insulating layer 26 Semiconductor layer 42 Collector electrode 48 Emitter electrode 50 Emitter / anode / collector / cathode bonding pad 111, 111A Upper arm 112, 112A Lower arm 142 Cathode electrode 148 Anode electrode

Claims (6)

A semiconductor device formed on a semiconductor substrate and having first and second elements having the same conductivity type connected in series,
The first and second elements are each
A transistor having a first main electrode and a second main electrode, configured to allow current to flow through the drift region between the first main electrode and the second main electrode, and for switching current;
A first main electrode and a second main electrode, a current flowing through the drift region between the first main electrode and the second main electrode, and a diode that performs reflux; and
A first main electrode of the transistor and a first main electrode of the diode are electrically connected; a second main electrode of the transistor and a second main electrode of the diode are electrically connected;
The first element and the second element are:
The first main electrode of the transistor in the first element and the second main electrode of the transistor in the second element are electrically connected; and
When the semiconductor substrate is viewed in plan, a conductive semiconductor region between the first main electrode of the transistor and the drift region in the first element, and the second main of the transistor in the second element. A semiconductor device, wherein an electrode and a conductive semiconductor region between the drift regions are arranged to face each other. The first and second elements are configured in a loop shape,
The semiconductor device according to claim 1, wherein the first element is disposed inside a loop of the second element when the semiconductor substrate is viewed in plan.   The semiconductor device according to claim 1, wherein the semiconductor device is a device that converts a direct current into an alternating current.   The semiconductor device according to claim 1, wherein the transistor and the diode are LIGBT and FWD, respectively.   The semiconductor device according to claim 1, wherein the transistor and the diode are an LDMOS and an FWD, respectively.   The semiconductor device according to claim 1, wherein the transistor and the diode are a LIGBT and an LDMOS, respectively.

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