JP2013088886A - Semiconductor integrated circuit and operation method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve protection against illegal access to an MRAM as a built-in memory of a semiconductor integrated circuit.SOLUTION: A semiconductor integrated circuit (10) comprises a processor (1) and a non-volatile memory (3). The non-volatile memory (3) includes a plurality of magnetic random access memory cells and a plurality of magnetic read-only memory cells. The plurality of magnetic random access memory cells can be rewritten by normal writing using the processor (1), and the plurality of magnetic read-only memory cells cannot be rewritten by normal writing using the processor (1). A sensing circuit (2) connected with the non-volatile memory (3) detects a state transition of the plurality of magnetic read-only memory cells due to illegal access to the non-volatile memory (3). The sensing circuit (2) notifies the processor (1) of a detection result of the illegal access in response to the state transition.

Description

  The present invention relates to a semiconductor integrated circuit incorporating a magnetic random access memory (MRAM) and a method for operating the same, and more particularly to a technique effective for improving protection against unauthorized access to an MRAM as a built-in memory of a semiconductor integrated circuit. is there.

  In recent years, a magnetic memory device, that is, a magnetic random access memory (MRAM) has attracted attention as a memory mounted on a large-scale semiconductor integrated circuit (LSI) called a system-on-chip (SoC). Has been. MRAM not only has the advantage that data is not lost when the power is cut off, as in SRAM, but also has a data rewrite time compared to a semiconductor non-volatile memory that can be electrically rewritten and erased, such as a flash memory. Has the advantage of being short.

  Patent Document 1 below discloses a magnetic tunnel junction (MTJ) in which an extremely thin tunnel insulating film is formed between a fixed layer (pinned layer) made of a magnetic film and a free layer (free layer) made of a magnetic film. A magnetic memory device configured as an MRAM with a Magnetic Tunnel Junction).

  In the magnetic tunnel junction (MTJ) of the magnetic memory device, the magnetization direction of the fixed layer (pinned layer) is fixed in a fixed direction, while the magnetization direction of the free layer (free layer) can be controlled from the outside. When the magnetization direction of the fixed layer (pinned layer) and the magnetization direction of the free layer (free layer) are in the same direction, a large tunnel current flows through the tunnel insulating film. When the magnetization direction of the fixed layer (pinned layer) is opposite to the magnetization direction of the free layer (free layer), the tunnel current of the tunnel insulating film is smaller than that in the same direction.

  In Patent Document 2 below, in order to prevent unauthorized use or unauthorized reading of data stored in an MRAM cell, a security device in which a permanent magnet and a soft magnetic flux closing layer are stacked is arranged in the vicinity of the MRAM array, and a soft magnetic flux It is described that when the closed layer is removed, the stored contents of the MRAM cell are destroyed by the magnetic flux from the permanent magnet to protect the secret information.

  In Japanese Patent Application Laid-Open Publication No. 2003-259259, a package includes a magnetic device that generates a magnetic flux surrounding a chip including the magnetic memory element in order to protect the magnetic memory element disposed inside the integrated circuit device from illegal activities. When the package is not damaged, the magnetic field is suppressed from reaching the magnetic memory element. When the package is damaged due to illegal activities, the magnetic field reaches the magnetic memory element and the state of the magnetic memory element changes. The magnetic device for generating magnetic flux is formed on the main surface of the chip on which the magnetic memory element is arranged.

JP 2008-218649 A JP-T-2006-511892 JP-T-2006-511936

  Prior to the present invention, the present inventor engaged in the development of a large-scale semiconductor integrated circuit (LSI) called a system-on-chip (SoC) equipped with an MRAM as a built-in memory.

  In this development, prior to the present invention, the present inventor disclosed in the background art described in Patent Document 2 described above that the permanent magnet and the soft magnetic flux closing layer of the security device are simultaneously removed, so that the memory contents of the MRAM cell are stored. It was clarified that there is a problem that it is possible to illegally access confidential information without destroying.

  In this development, prior to the present invention, the present inventor further disclosed that the background art described in Patent Document 3 described above is a magnetic memory disposed on the main surface of the chip from the back surface of the chip on which no magnetic memory element is disposed. It has been clarified that there is a problem that unauthorized access to secret information is possible by sensing leakage magnetic flux from the element.

  The present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.

  Accordingly, an object of the present invention is to improve protection against unauthorized access to an MRAM as a built-in memory of a semiconductor integrated circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a typical embodiment of the present invention is a semiconductor integrated circuit (10) including a processor (1) and a nonvolatile memory (3) (see FIG. 1).

  The non-volatile memory (3) includes a plurality of magnetic random access memory cells (MRAM cells) and a plurality of magnetic read only memory cells (MROM cells) (see FIG. 2).

  The plurality of magnetic random access memory cells (MRAM Cell) of the nonvolatile memory (3) can be rewritten by normal writing by the processor (1), and the plurality of magnetic leads of the nonvolatile memory (3) The only memory cell (MROM Cell) cannot be rewritten by the normal writing by the processor (1).

  The semiconductor integrated circuit (10) further includes a sensing circuit (2) connected to the nonvolatile memory (3).

  The sensing circuit (2) is capable of sensing a state transition of the plurality of magnetic read-only memory cells (MROM cells) due to unauthorized access to the nonvolatile memory (3).

  In response to the state transition of the plurality of magnetic read-only memory cells (MROM cells) due to the unauthorized access of the nonvolatile memory (3), the sensing circuit (2) displays the detection result of the unauthorized access as the processor ( 1) (see FIG. 1).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to improve protection against unauthorized access to the MRAM as the built-in memory of the semiconductor integrated circuit.

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit 10 according to the first embodiment of the present invention. FIG. 2 is a diagram showing a configuration of the nonvolatile memory 3 configured by an MRAM that can detect unauthorized access to the nonvolatile memory 3 in the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. is there. FIG. 3 is a diagram showing the structure of the magnetic tunnel junction (MTJ) of the cell MRAM Cell of the magnetic random access memory (MRAM) of the nonvolatile memory 3 according to the first embodiment of the present invention shown in FIG. FIG. 4 is a diagram showing the structure of the cell MRAM Cell of the magnetic random access memory (MRAM) of the nonvolatile memory 3 according to the first embodiment of the present invention shown in FIG. FIG. 5 is a bird's eye view for showing the structure of the cell MRAM Cell of the magnetic random access memory (MRAM) of the nonvolatile memory 3 according to the first embodiment of the present invention shown in FIG. FIG. 6 shows the word line magnetic field H to the free layer Free of the magnetic tunnel junction MTJ of the MRAM cell arranged at the intersection of the write word line WWL of the intermediate layer wiring and the bit line BL of the upper layer wiring shown in the bird's eye view of FIG. it is a bird's-eye view showing the effect of _WWL and the bit line magnetic field H _BL. FIG. 7 is a diagram showing an astroid curve showing the relationship between the magnetic field magnitudes of the word line magnetic field H _WWL and the bit line magnetic field H _BL shown in the bird's eye views of FIGS. 5 and 6 and the threshold value for magnetization reversal. FIG. 8 shows a magnetic random access memory (MRAM) cell MRAM Cell and a magnetic read only memory (MROM) included in the nonvolatile memory 3 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. It is a figure which shows the structure of cell MROM Cell. FIG. 9 shows a magnetic random access memory (MRAM) cell MRAM Cell and a magnetic read only memory (MROM) included in the nonvolatile memory 3 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. It is a figure which shows the other structure of cell MROM Cell. FIG. 10 is a diagram showing configurations of the illegal write detection circuit 2 and the nonvolatile memory 3 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. FIG. 11 is a diagram showing another configuration of the unauthorized write detection circuit 2 and the nonvolatile memory 3 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. FIG. 12 is a diagram for explaining the protection operation of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. 1 based on the unauthorized access detection result by the unauthorized write detection circuit 2 described in FIG. 10 or FIG. . FIG. 13 is a diagram for explaining another protection operation of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. 1 based on the unauthorized access detection result by the unauthorized write detection circuit 2 described in FIG. 10 or FIG. It is. FIG. 14 explains still another protection operation of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. 1 based on the unauthorized access detection result by the unauthorized write detection circuit 2 described in FIG. 10 or FIG. FIG. FIG. 15 is a diagram showing a structure of a package according to the second embodiment of the present invention for magnetically shielding the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. It is. FIG. 16 is a diagram showing a QFP package as a configuration example for magnetically shielding the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. 1 to 14. FIG. 17 shows another structure of the QFP package according to the second embodiment of the present invention for magnetically shielding the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. FIG. FIG. 18 shows the structure of the BGA package according to the second embodiment of the present invention for magnetically shielding the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. FIG. FIG. 19 shows another structure of the BGA package according to the second embodiment of the present invention for magnetically shielding the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. FIG.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A typical embodiment of the present invention is a semiconductor integrated circuit (10) including a processor (1) and a nonvolatile memory (3) (see FIG. 1).

  The non-volatile memory (3) includes a plurality of magnetic random access memory cells (MRAM cells) and a plurality of magnetic read only memory cells (MROM cells) (see FIG. 2).

  The plurality of magnetic random access memory cells (MRAM Cell) of the nonvolatile memory (3) can be rewritten by normal writing by the processor (1), and the plurality of magnetic leads of the nonvolatile memory (3) The only memory cell (MROM Cell) cannot be rewritten by the normal writing by the processor (1).

  The semiconductor integrated circuit (10) further includes a sensing circuit (2) connected to the nonvolatile memory (3).

  The sensing circuit (2) is capable of sensing a state transition of the plurality of magnetic read-only memory cells (MROM cells) due to unauthorized access to the nonvolatile memory (3).

  In response to the state transition of the plurality of magnetic read-only memory cells (MROM cells) due to the unauthorized access of the nonvolatile memory (3), the sensing circuit (2) displays the detection result of the unauthorized access as the processor ( 1) (see FIG. 1).

  According to the embodiment, the protection against unauthorized access to the MRAM as the built-in memory of the semiconductor integrated circuit can be improved.

  In a preferred embodiment, normal access by the processor (1) of the plurality of magnetic random access memory cells (MRAM Cell) of the nonvolatile memory (3) according to the detection result of the unauthorized access of the sensing circuit (2). The operation is stopped (see FIG. 12).

  In another preferred embodiment, the sensing circuit (2) generates an interrupt to the processor (1) according to the detection result of the unauthorized access.

  The normal access operation by the processor (1) of the plurality of magnetic random access memory cells (MRAM Cell) of the nonvolatile memory (3) is stopped by the interrupt (FIG. 12). reference).

  In still another preferred embodiment, the sensing circuit (2) sets flag information to the processor (1) according to the detection result of the unauthorized access.

  According to the flag information, the normal access operation by the processor (1) of the plurality of magnetic random access memory cells (MRAM Cell) of the nonvolatile memory (3) is stopped (see FIG. 13).

  According to a more preferred embodiment, the semiconductor integrated circuit (10) further includes an input / output port (8) connected to the nonvolatile memory (3).

  The input / output port (8) is capable of reading information stored in the plurality of magnetic random access memory cells (MRAM cells) of the nonvolatile memory (3) to the outside of the semiconductor integrated circuit (10).

  According to the detection result of the unauthorized access of the sensing circuit (2), the storage information of the plurality of magnetic random access memory cells (MRAM cells) of the nonvolatile memory (3) by the input / output port (8). The reading of the semiconductor integrated circuit (10) to the outside is stopped (see FIG. 14).

  In another more preferred embodiment, each of the plurality of magnetic random access memory cells (MRAM Cell) of the non-volatile memory (3) is composed of a ferromagnetic layer, and the magnetization direction can be controlled from the outside. It includes an MRAM magnetic tunnel junction (MTJ) comprising an MRAM free layer (1002), an MRAM tunnel insulation layer (1001) made of an insulation layer, and an MRAM fixed layer (1000) (FIGS. 8 and 9). reference).

  The MRAM pinned layer (1000) is composed of a laminated film of a ferromagnetic layer and an antiferromagnetic layer, and the magnetization direction of the ferromagnetic layer is strongly fixed by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer.

  In still another more preferred embodiment, each of the plurality of magnetic read-only memory cells (MROM Cell) of the nonvolatile memory (3) includes an MROM upper fixed layer (1022) and an MROM comprising an insulating layer. An MROM magnetic tunnel junction (MTJ) including a tunnel insulating layer (1021) and an MROM lower layer fixed layer (1020) is included (see FIGS. 8 and 9).

  The MROM upper pinned layer (1022) and the MROM lower pinned layer (1020) are formed of a laminated film of a ferromagnetic layer and an antiferromagnetic layer, and a ferromagnetic layer is formed by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer. The magnetization direction of is strongly fixed.

  In another more preferred embodiment, before the semiconductor integrated circuit (10) receives the unauthorized access of the nonvolatile memory (3), the plurality of magnetic read-only memory cells of the nonvolatile memory (3) Low level storage information is written in (MROM Cell).

  The sensing circuit (2) has an OR having a plurality of input terminals connected to a plurality of bit lines (BL01, BL04, BL07, BL09... BL23) connected to the plurality of magnetic read-only memory cells (MROM Cell). A circuit (OR) is included (see FIG. 10).

  In still another more preferred embodiment, before the semiconductor integrated circuit (10) receives the unauthorized access of the nonvolatile memory (3), the plurality of magnetic read-only memories of the nonvolatile memory (3) High-level storage information is written in the cell (MROM Cell).

  The sensing circuit (2) is a NAND having a plurality of input terminals connected to a plurality of bit lines (BL01, BL04, BL07, BL09... BL23) connected to the plurality of magnetic read-only memory cells (MROM Cell). A circuit (NAND) is included (see FIG. 11).

  In a specific embodiment, the semiconductor chip of the semiconductor integrated circuit (10) including the processor (1) and the nonvolatile memory (3) includes an upper magnet member (20) and a lower magnet member (30) having a package structure. ) (See FIGS. 15 to 19).

In another specific embodiment, the lower magnetic field (H _20D ) from the upper magnet member (20) and the lower magnet member (30) between the upper magnet member (20) and the lower magnet member (30) of the package structure. The upper magnetic field (H _30U ) from the lower magnet member (30) is canceled (see FIGS. 15 to 19).

  In the most specific embodiment, one of the upper magnet member (20) and the lower magnet member (30) of the package structure is destroyed and removed by the unauthorized access of the nonvolatile memory (3). As a result, the state transition of the plurality of magnetic read-only memory cells (MROM cells) of the nonvolatile memory (3) occurs (see FIGS. 15 to 19).

  [2] A typical embodiment of another aspect of the present invention is an operation method of a semiconductor integrated circuit (10) including a processor (1) and a nonvolatile memory (3) (see FIG. 1).

  The non-volatile memory (3) includes a plurality of magnetic random access memory cells (MRAM cells) and a plurality of magnetic read only memory cells (MROM cells) (see FIG. 2).

  The plurality of magnetic random access memory cells (MRAM Cell) of the nonvolatile memory (3) can be rewritten by normal writing by the processor (1), and the plurality of magnetic leads of the nonvolatile memory (3) The only memory cell (MROM Cell) cannot be rewritten by the normal writing by the processor (1).

  The semiconductor integrated circuit (10) further includes a sensing circuit (2) connected to the nonvolatile memory (3).

  The sensing circuit (2) is capable of sensing a state transition of the plurality of magnetic read-only memory cells (MROM cells) due to unauthorized access to the nonvolatile memory (3).

  In response to the state transition of the plurality of magnetic read-only memory cells (MROM cells) due to the unauthorized access of the nonvolatile memory (3), the sensing circuit (2) displays the detection result of the unauthorized access as the processor ( 1) (see FIG. 1).

  According to the embodiment, the protection against unauthorized access to the MRAM as the built-in memory of the semiconductor integrated circuit can be improved.

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<Configuration of semiconductor integrated circuit>
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit 10 according to the first embodiment of the present invention.

  A semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. 1 includes a processor 1, an illegal write detection circuit 2, a nonvolatile memory 3 composed of a magnetic random access memory (MRAM), a peripheral function module 4, a volatile property. A memory 5 and an internal bus 6 are included.

  The processor 1 includes a central processing unit (CPU) and a digital signal processor (DSP), and the central processing unit (CPU) and the digital signal processor (DSP) execute an operation program stored in the nonvolatile memory 3. The processing data of the processor 1 is stored in the nonvolatile memory 3 and the volatile memory 5. In particular, the secret information of the processing data of the processor 1 is stored in a non-volatile memory 3 constituted by a magnetic random access memory (MRAM). The processor 1 accesses the nonvolatile memory 3, the peripheral function module 4, and the volatile memory 5 through the internal bus 6.

<Protection against unauthorized access>
As described above, when the secret information is stored as magnetic data in the nonvolatile memory 3 configured by the magnetic random access memory (MRAM), the nonvolatile memory configured by the MRAM is measured by measuring the leakage magnetic field or applying the magnetic field. There is a risk that 3 will receive an unauthorized access attack.

  Therefore, the unauthorized write detection circuit 2 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. 1 has a function of sensing unauthorized access to the nonvolatile memory 3. As a result, when the unauthorized write detection circuit 2 detects unauthorized access to the nonvolatile memory 3, it notifies the unauthorized access detection result to at least one of the processor 1, the internal bus 6, and the external terminal. .

<< Detection of unauthorized access to non-volatile memory 3 >>
FIG. 2 is a diagram showing a configuration of the nonvolatile memory 3 configured by an MRAM that can detect unauthorized access to the nonvolatile memory 3 in the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. is there.

  As shown in FIG. 2, the nonvolatile memory 3 includes a plurality of memory cells 300... 3MN arranged in a matrix composed of a plurality of rows and a plurality of columns. The matrix includes write word lines WWL0, WWL1, WWL2, WWL3... WWLM and read word lines RWL0, RWL1, RWL2, RWL3... RWLM arranged in a horizontal row direction, and bit lines arranged in a vertical column direction. BL0, BL1, BL2, BL3... BLN are included.

  First, the memory cells 300, 301, 302, 303... 30N in the first row connected to the write word line WWL0 and the read word line RWL0 in the first row are all magnetic random access memories (MRAM). Cell MRAM Cell. The memory cells 300, 301, 302, 303... 30N in the first row are connected to bit lines BL0, BL1, BL2, BL3.

  Second, of the second row memory cells 310, 311, 312, 313,... 31N connected to the second row read word line RWL1, the memory cell 312 is a magnetic read only memory (MROM) cell MROM. The other memory cells 310, 311, 313,... 31N are constituted by magnetic random access memory (MRAM) cells MRAM Cell. The other memory cells 310, 311, 313,... 31N are connected to the write word line WWL1 of the second row, but the memory cell 312 constituted by the magnetic read only memory (MROM) cell MROM Cell is the second row. It is not connected to the write word line WWL1 of the eye. Therefore, the write word line WWL1 in the second row is formed in the shape of a bypass wiring around the memory cell 312. The memory cells 310, 311, 312, 313,... 31N in the second row are connected to bit lines BL0, BL1, BL2, BL3,.

  Third, the memory cells 320, 321, 322, 323,... 32N in the third row connected to the write word line WWL2 and the read word line RWL2 in the third row are all magnetic random access memories (MRAM). Cell MRAM Cell. The memory cells 320, 321, 322, 323,... 32N in the third row are connected to bit lines BL0, BL1, BL2, BL3,.

  Fourth, of the memory cells 330, 331, 332, 333,... 33N in the fourth row connected to the read word line RWL3 in the fourth row, the memory cell 331 is a magnetic read only memory (MROM) cell MROM. The other memory cells 330, 332, 333,... 31N are constituted by magnetic random access memory (MRAM) cells MRAM Cell. The other memory cells 330, 332, 333... 31N are connected to the write word line WWL3 in the fourth row, but the memory cell 331 constituted by the magnetic read only memory (MROM) cell MROM Cell is in the fourth row. It is not connected to the write word line WWL3 of the eye. Accordingly, the write word line WWL3 in the fourth row is formed in the shape of a bypass wiring around the memory cell 331. The memory cells 330, 331, 332, 333,... 33N in the fourth row are connected to bit lines BL0, BL1, BL2, BL3,.

  The Mth memory cells 3M0, 3M1, 3M2, 3M3,... 3MN connected to the Mth write word line WWLM and the read word line RWLM are all magnetic random access memories (MRAM). Cell MRAM Cell. The memory cells 3M0, 3M1, 3M2, 3M3,... 3MN in the Mth row are connected to bit lines BL0, BL1, BL2, BL3,.

  In the nonvolatile memory 3 shown in FIG. 2, the memory cell 312 in the second row and the memory cell 331 in the fourth row which are configured by the magnetic read only memory (MROM) cell MROM Cell are shown in FIG. 1. In the normal writing by the processor 1 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention, rewriting is impossible.

  Therefore, the memory cell 312 in the second row and the memory cell 331 in the fourth row constituted by the magnetic read only memory (MROM) cell MROM Cell in FIG. Initial writing can be performed by supplying a strong magnetic field to the semiconductor wafer of the semiconductor integrated circuit 10. Thereafter, when the non-volatile memory 3 constituted by the MRAM is subjected to an unauthorized access attack, the measurement of the leakage magnetic field or the application of the magnetic field causes the first read-only memory (MROM) cell MROM Cell shown in FIG. The memory cell 312 in the second row and the memory cell 331 in the fourth row change state from the initial write state.

  As described above, the state transition from the initial write state of the memory cells 312 and 331 configured by the MROM Cell of the magnetic read-only memory (MROM) caused by the unauthorized access attack of the nonvolatile memory 3 is caused by the bit lines BL1 and BL2. It can be sensed by inversion of the read output signal.

  On the other hand, in the non-volatile memory 3 shown in FIG. 2, other memory cells 300, 301, 302, 303... 30N, 310, 311, 313... 31N constituted by magnetic random access memory (MRAM) cells MRAM Cell. 320, 321, 322, 323 ... 32N, 330, 332, 333 ... 33N, 3M0, 3M1, 3M2, 3M3,... 3MN are generated by the processor 1 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. In normal writing, it can be rewritten.

<< Magnetic Random Access Memory Magnetic Tunnel Junction >>
FIG. 3 is a diagram showing the structure of the magnetic tunnel junction (MTJ) of the cell MRAM Cell of the magnetic random access memory (MRAM) of the nonvolatile memory 3 according to the first embodiment of the present invention shown in FIG.

  As shown in FIG. 3, the magnetic tunnel junction (MTJ) of the cell MRAM Cell of the magnetic random access memory (MRAM) of the nonvolatile memory 3 is insulated from the fixed layer Fix composed of the antiferromagnetic layer 3000 and the ferromagnetic layer 3001. The tunnel insulating layer Tunnel made of the layer 3002 and the free layer Free made of the ferromagnetic layer 3003 are formed. In particular, in the fixed layer Fix, adjacent spins are arranged in opposite directions, and the antiferromagnetic layer 3000 that does not have a magnetic moment as a whole and adjacent spins are arranged in the same direction, resulting in a large magnetic moment as a whole. The magnetization direction of the ferromagnetic layer 3001 is strongly fixed by exchange coupling with the ferromagnetic layer 3001 possessed.

  In the semiconductor manufacturing process of the semiconductor integrated circuit 10, the magnetization direction of the ferromagnetic layer 3001 of the fixed layer Fix is fixed in a fixed direction by supplying a magnetic field having the maximum strength to the semiconductor wafer of the semiconductor integrated circuit 10, while the free layer Free. The magnetization direction of the ferromagnetic layer 3003 can be controlled from the outside. When the magnetization direction of the ferromagnetic layer 3001 of the fixed layer Fix and the magnetization direction of the ferromagnetic layer 3003 of the free layer Free are in the same direction, a large tunnel current is generated in the tunnel insulating layer Tunnel formed of the insulating layer 3002. Flowing. On the other hand, when the magnetization direction of the ferromagnetic layer 3001 of the fixed layer Fix is opposite to the magnetization direction of the ferromagnetic layer 3003 of the free layer Free, the tunnel insulating layer Tunnel formed of the insulating layer 3002 The tunnel current is smaller than in the case of the same direction.

<< Cell structure of MRAM >>
FIG. 4 is a diagram showing the structure of the cell MRAM Cell of the magnetic random access memory (MRAM) of the nonvolatile memory 3 according to the first embodiment of the present invention shown in FIG.

  4A shows a circuit configuration of a cell MRAM Cell of a magnetic random access memory (MRAM), and FIG. 4B shows a semiconductor device structure of the cell MRAM Cell of the magnetic random access memory (MRAM).

  As shown in FIG. 4A, one magnetic random access memory (MRAM) cell MRAM Cell is constituted by an N-channel MOS transistor TR and the magnetic tunnel junction MTJ described with reference to FIG. The source S, gate G, and drain D of the N-channel MOS transistor TR are connected to the ground voltage Vss, the read word line RWL, and one end (fixed layer Fix) of the magnetic tunnel junction MTJ, respectively, and the other end of the magnetic tunnel junction MTJ. (Free layer Free) is connected to the bit line BL. The write word line WWL is disposed in parallel with the read word line RWL in the vicinity of one end (fixed layer Fix) of the magnetic tunnel junction MTJ.

As shown in FIG. 4B, an N ⁺ impurity source region S and an N ⁺ impurity drain region D are formed inside a P-type well region P-Well formed in the semiconductor chip of the semiconductor integrated circuit 10. ^On the surface of the channel region between the ⁺ impurity source region S and the N ⁺ impurity drain region D, a gate electrode G made of polycrystalline silicon is formed via a gate oxide film. Therefore, an N-channel MOS transistor TR is formed by the P-type well region P-Well, the N ⁺ impurity source region S, the N ⁺ impurity drain region D, and the gate electrode G.

As shown in FIG. 4B, the N ⁺ impurity source region S is connected to the ground voltage Vss by the lower layer wiring, the gate electrode G forms the read word line RWL, and the N ⁺ impurity drain region D is the lower layer wiring. And one end (fixed layer Fix) of the magnetic tunnel junction MTJ by the intermediate layer wiring. Immediately below one end (fixed layer Fix) of the magnetic tunnel junction MTJ, the write word line WWL is formed near the one end (fixed layer Fix) of the magnetic tunnel junction MTJ and in parallel with the read word line RWL by the intermediate layer wiring. The The other end (free layer Free) of the magnetic tunnel junction MTJ is connected to the bit line BL formed by the upper layer wiring.

  FIG. 5 is a bird's eye view for showing the structure of the cell MRAM Cell of the magnetic random access memory (MRAM) of the nonvolatile memory 3 according to the first embodiment of the present invention shown in FIG.

As shown in the bird's eye view of FIG. 5, the read word line RWL formed by the lowermost gate electrode G and the write word line WWL formed by the intermediate layer wiring are arranged in parallel. The N ⁺ impurity drain region D is connected to one end (fixed layer Fix) of the magnetic tunnel junction MTJ by a lower layer wiring and an intermediate layer wiring. Immediately below one end (fixed layer Fix) of the magnetic tunnel junction MTJ, a write word line WWL is formed close to and parallel to one end (fixed layer Fix) of the magnetic tunnel junction MTJ by an intermediate layer wiring. The other end (free layer Free) of the magnetic tunnel junction MTJ is connected to the bit line BL formed by the upper layer wiring.

As shown in the bird's eye view of FIG. 5, a write word line magnetic field H _{WWL in} the direction of the arrow is formed by flowing a write word line current I _WWL in the direction of the arrow through the write word line WWL formed by the intermediate layer wiring. By flowing a bit line current I _BL in the direction of the arrow through the bit line BL formed by the upper layer wiring, a bit line magnetic field H _{BL in} the direction of the arrow is formed. Therefore, the magnetization direction of the free layer Free at the other end of the magnetic tunnel junction MTJ is determined by the word line magnetic field H _WWL and the bit line magnetic field H _BL .

FIG. 6 shows the word line magnetic field H to the free layer Free of the magnetic tunnel junction MTJ of the MRAM cell arranged at the intersection of the write word line WWL of the intermediate layer wiring and the bit line BL of the upper layer wiring shown in the bird's eye view of FIG. it is a bird's-eye view showing the effect of _WWL and the bit line magnetic field H _BL. A magnetic tunnel junction MTJ of the MRAM cell is arranged at the intersection of the write word line WWL of the intermediate layer wiring and the bit line BL of the upper layer wiring, and the write word line current I _WWL in the direction of the arrow is supplied to the write word line _WWL. A bit line current IBL in the direction of the arrow is supplied to _BL .

  Ferromagnetic materials generally have a direction that tends to magnetize (state of low energy) depending on the crystal structure and shape, etc., and this direction is called the easy axis (Easy Axis). keep. On the other hand, the direction in which magnetization is difficult is referred to as a hard magnetization axis (Hard Axis). In order to reverse the direction of magnetization, a magnetic field is applied in a direction opposite to the magnetization with respect to the easy axis to change the direction of magnetization. It is known that if a magnetic field is applied in the hard axis direction at this time, the direction of magnetization is reversed even if the magnetic field in the easy axis direction is smaller than when there is no magnetic field in the hard axis direction.

  Therefore, only the MRAM cell at the intersection point where the magnetic field is applied in both the hard axis direction and the easy axis direction is written, and the magnetic field exceeding the write threshold is not applied to many other MRAM cells. It can be prevented from happening. In this way, writing to the two-dimensional matrix MRAM cell array can be realized.

《Astroid Curve》
FIG. 7 is a diagram showing an astroid curve showing the relationship between the magnetic field magnitudes of the word line magnetic field H _WWL and the bit line magnetic field H _BL shown in the bird's eye views of FIGS. 5 and 6 and the threshold value for magnetization reversal.

The astroid curve includes four arcs, and in the region inside the four arcs of the astroid curve, the magnitudes of the word line magnetic field H _WWL and the bit line magnetic field H _BL are less than the magnetization reversal threshold. Therefore, the magnetization direction of the free layer Free at the other end of the magnetic tunnel junction MTJ cannot be reversed. However, in the region outside the four arcs of the astroid curve, the magnetic field magnitudes of the word line magnetic field H _WWL and the bit line magnetic field H _BL are equal to or greater than the magnetization reversal threshold. It becomes possible to reverse the magnetization direction of the end free layer Free.

As shown in the bird's-eye view of FIGS. 5 and 6, by passing a bit line current IBL in the direction of the arrow through the bit line _BL , the magnetic tunnel junction MTJ corresponds to the “1” write in the first quadrant of FIG. It is possible to determine the magnetization direction of the free layer Free at the other end. By flowing a bit line current I _BL in the direction opposite to the arrow direction through the bit line _BL , the magnetization direction of the free layer Free at the other end of the magnetic tunnel junction MTJ is changed corresponding to the “0” write in the fourth quadrant of FIG. Can be determined.

<< MRAM cell and MROM cell of nonvolatile memory >>
FIG. 8 shows a magnetic random access memory (MRAM) cell MRAM Cell and a magnetic read only memory (MROM) included in the nonvolatile memory 3 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. It is a figure which shows the structure of cell MROM Cell.

  As shown in FIG. 8, the first MRAM cell 100, the second MRAM cell 101, the first MROM cell 102, and the third MRAM cell 103 are connected to the bit line BL0.

  The first MRAM cell 100 includes a free layer 1002 composed of a ferromagnetic layer whose magnetization direction can be controlled from the outside, a tunnel insulating layer 1001 made of an insulating layer, and a laminated film of a ferromagnetic layer and an antiferromagnetic layer And a magnetic tunnel junction (MTJ) including a fixed layer 1000 in which the magnetization direction of the ferromagnetic layer is strongly fixed by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer. The free layer 1002 of the magnetic tunnel junction (MTJ) is connected to the bit line BL0, the fixed layer 1000 of the magnetic tunnel junction (MTJ) is connected to the drain of the N channel MOS transistor TR, and the gate of the N channel MOS transistor TR is the read word Connected to line RWL0, the source of N-channel MOS transistor TR is connected to ground voltage Vss. A write word line WWL0 is formed adjacent to the fixed layer 1000 of the magnetic tunnel junction (MTJ).

  The second MRAM cell 101 also includes a free layer 1012 that is formed of a ferromagnetic layer and whose magnetization direction can be controlled from the outside, a tunnel insulating layer 1011 formed of an insulating layer, and a laminated film of a ferromagnetic layer and an antiferromagnetic layer And a magnetic tunnel junction (MTJ) including a fixed layer 1010 in which the magnetization direction of the ferromagnetic layer is strongly fixed by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer. The free layer 1012 of the magnetic tunnel junction (MTJ) is connected to the bit line BL0, the fixed layer 1010 of the magnetic tunnel junction (MTJ) is connected to the drain of the N channel MOS transistor TR, and the gate of the N channel MOS transistor TR is the read word Connected to line RWL1, the source of N-channel MOS transistor TR is connected to ground voltage Vss. A write word line WWL1 is formed adjacent to the fixed layer 1010 of the magnetic tunnel junction (MTJ).

  The third MRAM cell 103 also includes a free layer 1032 which is composed of a ferromagnetic layer and whose magnetization direction can be controlled from the outside, a tunnel insulating layer 1031 made of an insulating layer, and a laminated film of a ferromagnetic layer and an antiferromagnetic layer And a magnetic tunnel junction (MTJ) including a fixed layer 1030 in which the magnetization direction of the ferromagnetic layer is strongly fixed by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer. The free layer 1032 of the magnetic tunnel junction (MTJ) is connected to the bit line BL0, the fixed layer 1030 of the magnetic tunnel junction (MTJ) is connected to the drain of the N channel MOS transistor TR, and the gate of the N channel MOS transistor TR is the read word Connected to line RWLN, the source of N-channel MOS transistor TR is connected to ground voltage Vss. In the fixed layer 1010 of the magnetic tunnel junction (MTJ), a write word line WWLN is formed in the vicinity.

  The first MROM cell 102 is composed of a laminated layer of a ferromagnetic layer and an antiferromagnetic layer, and a fixed layer 1022 in which the magnetization direction of the ferromagnetic layer is strongly fixed by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer. A tunnel insulating layer 1021 composed of a layer, and a fixed layer 1020 composed of a laminated film of a ferromagnetic layer and an antiferromagnetic layer, in which the magnetization direction of the ferromagnetic layer is strongly fixed by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer. The magnetic tunnel junction (MTJ) which consists of these is included. The fixed layer 1022 of the magnetic tunnel junction (MTJ) is connected to the bit line BL0, the fixed layer 1020 of the magnetic tunnel junction (MTJ) is connected to the drain of the N channel MOS transistor TR, and the gate of the N channel MOS transistor TR is the read word Connected to line RWL2, the source of N channel MOS transistor TR is connected to ground voltage Vss. In the fixed layer 1020 of the magnetic tunnel junction (MTJ), the write word line WWL2 is formed so as to be bypassed without being close to it.

  The magnetic tunnel junction (MTJ) of the first MRAM cell 100, the second MRAM cell 101, the first MROM cell 102, and the third MRAM cell 103 shown in FIG. 8 is the semiconductor according to the first embodiment of the present invention shown in FIG. It can be formed using the semiconductor manufacturing process of the integrated circuit 10.

  First, a plurality of N-channel MOS transistors TR and a plurality of write word lines WWL0, WWL1, WWL2, and WWLN of the first MRAM cell 100, the second MRAM cell 101, the first MROM cell 102, and the third MRAM cell 103 are formed.

  Next, an interlayer insulating film is formed on the plurality of N-channel MOS transistors TR and the plurality of write word lines WWL0, WWL1, WWL2, and WWLN in the first MRAM cell 100, the second MRAM cell 101, the first MROM cell 102, and the third MRAM cell 103. It is formed.

  Next, trenches for forming a plurality of magnetic tunnel junctions (MTJ) are formed in the interlayer insulating film above the plurality of N-channel MOS transistors TR by plasma etching.

  Next, a sandwich structure of fixed layers 1000, 1010, 1020, 1030, tunnel insulating layers 1001, 1011, 1021, 1031 and fixed layer 1022 is formed inside the plurality of trenches above the plurality of N-channel MOS transistors TR. Deposited by plasma deposition. That is, the fixed layer 1022 is first formed at the top of each sandwich structure of the first MRAM cell 100, the second MRAM cell 101, and the third MRAM cell 103.

  In this state, by supplying a magnetic field having the maximum strength to the semiconductor wafer of the semiconductor integrated circuit 10, the magnetization directions of the lowermost fixed layers 1000, 1010, 1020, and 1030 of the plurality of sandwich structures and the uppermost layers of the plurality of sandwich structures. The magnetization direction of the fixed layer 1022 is fixed.

  Thereafter, an etching resistant mask is formed on the uppermost fixed layer 1022 of the sandwich structure of the first MROM cell 102, and then the top of each sandwich structure of the first MRAM cell 100, the second MRAM cell 101, and the third MRAM cell 103 is formed. The fixed layer 1022 is removed by plasma etching.

  Next, free layers 1002, 1012, 1032 are deposited by plasma deposition on the top of the sandwich structure of the first MRAM cell 100, the second MRAM cell 101, and the third MRAM cell 103.

  In this state, by supplying a magnetic field weaker than the above-described maximum strength magnetic field to the semiconductor wafer of the semiconductor integrated circuit 10, the magnetization directions of the first MRAM cell 100, the second MRAM cell 101, and the third MRAM cell 103 can be set to arbitrary directions. Can be unified. Even if this weak magnetic field is supplied to the semiconductor wafer of the semiconductor integrated circuit 10, the bottom fixed layer 1000 of the plurality of sandwich structures of the first MRAM cell 100, the second MRAM cell 101, the first MROM cell 102, and the third MRAM cell 103 is used. The magnetization direction fixed at 1010, 1020, 1030 does not change.

  FIG. 9 shows a magnetic random access memory (MRAM) cell MRAM Cell and a magnetic read only memory (MROM) included in the nonvolatile memory 3 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. It is a figure which shows the other structure of cell MROM Cell.

  The nonvolatile memory 3 shown in FIG. 9 is different from the nonvolatile memory 3 shown in FIG. 8 in the following points.

  That is, in the nonvolatile memory 3 shown in FIG. 9, the uppermost portion of the sandwich structure of the first MRAM cell 100, the second MRAM cell 101, the first MROM cell 102, and the third MRAM cell 103 of the nonvolatile memory 3 shown in FIG. Magnetic materials 1003, 1013, 1023, and 1033 are added. In the nonvolatile memory 3 shown in FIG. 9, antiferromagnetic materials 1003, 1013, and 1033 added to the top of the sandwich structure of the first MRAM cell 100, the second MRAM cell 101, and the third MRAM cell 103 are formed from the ferromagnetic layer. It has a small exchange coupling strength with the free layers 1002, 1012, and 1022, which are configured and the magnetization direction can be controlled from the outside. On the other hand, in the non-volatile memory 3 shown in FIG. 9, the antiferromagnetic material 1023 added to the top of the sandwich structure of the first MROM cell 102 is a fixed layer that is composed of a ferromagnetic layer and has a strongly fixed magnetization direction. 1022 and a strong exchange coupling. For example, the antiferromagnetic material 1003, 1013, 1033 having a small exchange coupling strength is MgO (magnesium oxide) or the like, and the antiferromagnetic material 1023 having a large exchange coupling strength is FeMn (manganese iron alloy) or the like.

  The magnetic tunnel junction (MTJ) of the first MRAM cell 100, the second MRAM cell 101, the first MROM cell 102, and the third MRAM cell 103 shown in FIG. 9 is the semiconductor according to the first embodiment of the present invention shown in FIG. It can be formed using the semiconductor manufacturing process of the integrated circuit 10.

  That is, up to the sandwich structure of the first MRAM cell 100, the second MRAM cell 101, the first MROM cell 102, and the third MRAM cell 103 of the nonvolatile memory 3 shown in FIG. Can be formed using.

  Thereafter, an antiferromagnetic material 1003 is formed on the top of the sandwich structure of the first MRAM cell 100, an antiferromagnetic material 1013 is formed on the top of the sandwich structure of the second MRAM cell 101, and the sandwich of the third MRAM cell 103 is formed. An antiferromagnetic material 1033 is formed on the top of the sandwich structure. At this time, the antiferromagnetic materials 1003, 1013, and 1033 can be simultaneously deposited by plasma deposition such as MgO (magnesium oxide) having a small exchange coupling strength.

  Finally, an antiferromagnetic material 1023 is deposited on the top of the sandwich structure of the first MROM cell 102 by, for example, plasma deposition such as FeMn (manganese iron alloy) having a high exchange coupling strength.

<< Unauthorized Write Detection Circuit and Nonvolatile Memory >>
FIG. 10 is a diagram showing configurations of the illegal write detection circuit 2 and the nonvolatile memory 3 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG.

  As shown in FIG. 10, the non-volatile memory 3 has read word lines RWL0, RWL1, RWL2, RWL3... RWL15 arranged in the horizontal row direction of the matrix and the vertical column direction as described in FIG. A plurality of white square MRAM cells MRAM Cell and black square MROM cells MROM Cell are included at the intersections of the arranged bit lines BL0, BL1, BL2, BL3... BL23.

  In order to supply the unauthorized access detection information of the nonvolatile memory 3 to the plurality of input terminals of the unauthorized write detection circuit 2, the read word lines RWL1 and RWL2 connected to the plurality of black square MROM cells MROM Cell of the nonvolatile memory 3 , RWL3, RWL3, RWL6, RWL7, RWL9, RWL12, RWL14, RWL15 are sequentially driven to a selected voltage level by a read word line driving circuit (not shown).

  As a result, the bit lines BL01, BL04, BL07, BL09... BL23 connected to the plurality of black square MROM cells MROM Cell of the nonvolatile memory 3 are connected to the plurality of black square MROM cells MROM Cell of the nonvolatile memory 3. Are read out. On the other hand, the plurality of input terminals of the illegal write detection circuit 2 are connected to bit lines BL01, BL04, BL07, BL09... BL23 to which the plurality of black square MROM cells MROM Cell of the nonvolatile memory 3 are connected. In the example shown in FIG. 10, the illegal write detection circuit 2 is configured by an OR circuit OR, and the multiple input terminals of the OR circuit OR are connected to bit lines BL01, BL04, BL07, BL09... BL23.

  Before the unauthorized access of the secret information, the magnetization direction of the upper fixed layer of the magnetic tunnel junction MTJ of all the black square MROM cells MROM Cell of the nonvolatile memory 3 of FIG. 10 is “0” in the fourth quadrant of FIG. "It supports writing. Therefore, before the unauthorized access of the secret information, all the stored information of all the black square MROM cells MROM Cell included in the nonvolatile memory 3 of FIG. 10 is at the low level “0”. As a result, the read word lines RWL1, RWL2, RWL3, RWL6, RWL7, RWL9, RWL12, RWL14, and RWL15 of the nonvolatile memory 3 are sequentially driven to a selected voltage level by a read word line driving circuit (not shown). Even if all the read signals are read from all the black square MROM cells MROM Cell of the nonvolatile memory 3 to the bit lines BL0, BL1, BL2, BL3... BL23, the output of the OR circuit OR constituting the illegal write detection circuit 2 The signal is low level “0” (no unauthorized access).

  After the unauthorized access of the secret information, the magnetization direction of the free layer of the magnetic tunnel junction MTJ of at least one cell of the plurality of black square MROM cells MROM Cell of the nonvolatile memory 3 of FIG. It corresponds to “1” writing in the first quadrant. Therefore, after receiving unauthorized access of secret information, the storage information of at least one cell of the plurality of black square MROM cells MROM Cell included in the nonvolatile memory 3 of FIG. It has become. As a result, the read word lines RWL1, RWL2, RWL3, RWL6, RWL7, RWL9, RWL12, RWL14, and RWL15 of the nonvolatile memory 3 are sequentially driven to a selected voltage level by a read word line driving circuit (not shown). The high level “1” read signal of at least one cell of the plurality of black square MROM cells MROM Cell of the nonvolatile memory 3 is read to the bit lines BL0, BL1, BL2, BL3. The output signal of the OR circuit OR constituting the detection circuit 2 is high level “1” (with unauthorized access).

  FIG. 11 is a diagram showing another configuration of the unauthorized write detection circuit 2 and the nonvolatile memory 3 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG.

  The illegal write detection circuit 2 and the nonvolatile memory 3 according to the first embodiment of the present invention shown in FIG. 11 are different from the illegal write detection circuit 2 and the nonvolatile memory 3 according to the first embodiment of the present invention shown in FIG. Is the following point.

  That is, the illegal write detection circuit 2 according to the first embodiment of the present invention shown in FIG. 11 is configured by a NAND circuit NAND, and the multiple input terminals of the NAND circuit NAND are connected to the bit lines BL01, BL04, BL07, BL09. Has been.

  Before the unauthorized access of the confidential information, the magnetization direction of the upper fixed layer of the magnetic tunnel junction MTJ of all the black square MROM cells MROM Cell of the nonvolatile memory 3 of FIG. 11 is in the first quadrant shown in FIG. "1" writing is supported. Therefore, before the unauthorized access of the secret information, all the stored information of all the black square MROM cells MROM Cell in the nonvolatile memory 3 of FIG. 11 is at the high level “1”. As a result, the read word lines RWL1, RWL2, RWL3, RWL3, RWL6, RWL7, RWL9, RWL12, RWL14, and RWL15 of the nonvolatile memory 3 are sequentially driven to a selected voltage level by a read word line driving circuit (not shown). Thus, even if all the read signals are read from all the black square MROM cells MROM Cell of the nonvolatile memory 3 to the bit lines BL0, BL1, BL2, BL3... BL23, the NAND circuit NAND constituting the illegal write detection circuit 2 Output signal is low level “0” (no unauthorized access).

  However, after receiving unauthorized access of secret information, the magnetization direction of the free layer of the magnetic tunnel junction MTJ of at least one cell of the plurality of black square MROM cells MROM Cell of the nonvolatile memory 3 of FIG. 7 corresponds to “0” writing in the fourth quadrant. Therefore, after receiving unauthorized access of secret information, the storage information of at least one cell of the plurality of black square MROM cells MROM Cell included in the nonvolatile memory 3 of FIG. 11 is low level “0”. It has become. As a result, the read word lines RWL1, RWL2, RWL3, RWL3, RWL6, RWL7, RWL9, RWL12, RWL14, and RWL15 of the nonvolatile memory 3 are sequentially driven to a selected voltage level by a read word line driving circuit (not shown). As a result, a low level “0” read signal of at least one of the plurality of black square MROM cells MROM Cell of the nonvolatile memory 3 is read to the bit lines BL0, BL1, BL2, BL3. The output signal of the NAND circuit NAND constituting the write detection circuit 2 is high level “1” (with unauthorized access).

《Protection operation based on unauthorized access detection result》
FIG. 12 is a diagram for explaining the protection operation of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. 1 based on the unauthorized access detection result by the unauthorized write detection circuit 2 described in FIG. 10 or FIG. .

  In the example of FIG. 12, the unauthorized write detection circuit 2 generates an interrupt to the processor 1 based on the unauthorized access detection result, and the operation of the central processing unit (CPU) included in the processor 1 is forcibly stopped. It is. Therefore, the normal access of the secret information of the plurality of MRAM cells MRAM Cell included in the nonvolatile memory 3 by the central processing unit (CPU) of the processor 1 is forcibly stopped by the interrupt.

  Accordingly, an IC card or a portable terminal equipped with the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. 1 is illegally used by an unauthorized user due to theft or the like, and the nonvolatile memory 3 performs an unauthorized access attack. When received, it is possible to improve protection against unauthorized access.

  FIG. 13 is a diagram for explaining another protection operation of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. 1 based on the unauthorized access detection result by the unauthorized write detection circuit 2 described in FIG. 10 or FIG. It is.

  In the example of FIG. 13, based on the unauthorized access detection result, the unauthorized write detection circuit 2 changes the unauthorized access flag information stored in the flag register 7 from a low level “0” (no unauthorized access) to a high level “1” (illegal access). Update to Accessed). Accordingly, in response to the unauthorized access flag information of high level “1” (with unauthorized access) in the flag register 7, a plurality of MRAM cells MRAM Cell included in the nonvolatile memory 3 by the central processing unit (CPU) of the processor 1 are stored. Normal access to confidential information will be forcibly stopped.

  FIG. 14 explains still another protection operation of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. 1 based on the unauthorized access detection result by the unauthorized write detection circuit 2 described in FIG. 10 or FIG. FIG.

  In the example of FIG. 14, the unauthorized write detection circuit 2 supplies a data input / output operation stop signal via the input / output external terminal of the semiconductor integrated circuit 10 to the input / output port 8 based on the unauthorized access detection result. The data input / output operation of the input / output port 8 is forcibly stopped. In normal operation in which unauthorized access is not detected, the secret information of the plurality of MRAM cells MRAM Cell of the nonvolatile memory 3 can be read out from the input / output port 8 to the outside of the semiconductor integrated circuit 10 via the internal bus 6. It is said. Accordingly, in response to the unauthorized access detection result, reading of the secret information of the plurality of MRAM cells MRAM Cell of the nonvolatile memory 3 to the outside of the semiconductor integrated circuit 10 via the input / output port 8 is forcibly stopped. .

  In each of the examples shown in FIGS. 12 to 14, the light emitting diode (LED) connected to the external terminal of the semiconductor integrated circuit 10 blinks in response to the unauthorized access detection result by the unauthorized write detection circuit 2. It is also possible to notify the result of unauthorized access to the outside of the semiconductor integrated circuit 10 by various methods.

[Embodiment 2]
《Magnetic shield of semiconductor integrated circuit》
FIG. 15 is a diagram showing a structure of a package according to the second embodiment of the present invention for magnetically shielding the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. It is.

  As shown in FIG. 15, the present invention shown in FIG. 1 incorporates a non-volatile memory 3 including a plurality of magnetic random access memory (MRAM) cells MRAM Cell and a plurality of magnetic read only memory (MROM) cells MROM Cell. The semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment is disposed between the upper magnet member 20 and the lower magnet member 30.

As shown in the bird's eye view of FIG. 15A, an upper surface magnetic field H _20U is formed from the N pole N to the S pole S on the upper surface of the upper magnet member 20, and the N pole N to the S pole S on the lower surface of the upper magnet member 20. Is formed with a lower magnetic field H _20D , an upper magnetic field H _30U is formed between the N pole N and the S pole S on the upper surface of the lower magnet member 30, and from the N pole N to the S pole S on the lower surface of the lower magnet member 30. A bottom magnetic field H _30D is formed.

As shown in the sectional view of FIG. 15B, the semiconductor chip of the semiconductor integrated circuit 10 incorporating the nonvolatile memory 3 is disposed between the upper magnet member 20 and the lower magnet member 30, so that the upper magnet Between the member 20 and the lower magnet member 30, the lower surface magnetic field H _20D of the upper magnet member 20 and the upper surface magnetic field H _30U of the lower magnet member 30 are canceled out.

  Therefore, in this magnetic equilibrium state, a plurality of magnetic random access memories (MRAM) of the nonvolatile memory 3 formed on the semiconductor chip of the semiconductor integrated circuit 10 disposed between the upper magnet member 20 and the lower magnet member 30. The magnetic influence on the cell MRAM Cell and the plurality of magnetic read only memory (MROM) cells MROM Cell can be ignored.

  However, if one of the upper magnet member 20 and the lower magnet member 30 is destroyed and removed by an unauthorized access attack to the semiconductor chip of the semiconductor integrated circuit 10 including the nonvolatile memory 3, the magnetic field balance state is lost. . As a result, the magnetization direction of the upper fixed layer of the magnetic tunnel junction MTJ of the plurality of magnetic read-only memory (MROM) cells MROM Cell of the nonvolatile memory 3 is reversed by the influence of the residual magnetic flux from the remaining magnet member.

  As described with reference to FIGS. 10 and 11, the reversal of the magnetization direction of the upper fixed layer of the magnetic tunnel junction MTJ of the MROM Cell of the plurality of magnetic read-only memories (MROM) of the nonvolatile memory 3 is illegal. It can be detected by the write detection circuit 2.

  FIG. 16 shows the structure of the QFP package according to the second embodiment of the present invention for magnetically shielding the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. FIG.

  QFP is an abbreviation for Quad Flat Package, and a metal lead connection terminal LD is derived from each side of the rectangular package PKG.

  The semiconductor chip of the semiconductor integrated circuit 10 in the QFP package shown in FIG. 16 has a plurality of magnetic random accesses similar to the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. A nonvolatile memory 3 including a memory (MRAM) cell MRAM Cell and a plurality of magnetic read-only memory (MROM) cells MROM Cell is incorporated.

  As shown in FIG. 16, the lower surface of the semiconductor chip of the semiconductor integrated circuit 10 is fixed to the lower magnet member 30 with an insulating adhesive, while the upper surface of the semiconductor chip of the semiconductor integrated circuit 10 is fixed to the upper magnet with an insulating adhesive. It is fixed to the member 20. The plurality of pad electrodes formed on the upper surface of the semiconductor chip of the semiconductor integrated circuit 10 are electrically connected to the plurality of lead connection terminals LD through the plurality of bonding wires BW.

  As shown in FIG. 16, since the semiconductor chip of the semiconductor integrated circuit 10 incorporating the nonvolatile memory 3 is disposed between the upper magnet member 20 and the lower magnet member 30, the upper magnet member 20 and the lower magnet member 30, the lower magnetic field of the upper magnet member 20 and the lower magnetic field of the lower magnet member 30 are canceled out.

  However, one of the upper magnet member 20 and the lower magnet member 30 is destroyed by an attack of unauthorized access to the semiconductor chip of the semiconductor integrated circuit 10 sealed in the QFP package shown in FIG. If removed, the equilibrium state of the magnetic field is lost. As a result, the magnetization direction of the upper fixed layer of the magnetic tunnel junction MTJ of the plurality of magnetic read-only memory (MROM) cells MROM Cell of the nonvolatile memory 3 is reversed by the influence of the residual magnetic flux from the remaining magnet member.

  As described with reference to FIGS. 10 and 11, the reversal of the magnetization direction of the upper fixed layer of the magnetic tunnel junction MTJ of the MROM Cell of the plurality of magnetic read-only memories (MROM) of the nonvolatile memory 3 is illegal. It can be detected by the write detection circuit 2.

  FIG. 17 shows another structure of the QFP package according to the second embodiment of the present invention for magnetically shielding the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. FIG.

  The package PKG shown in FIG. 17 is different from the package PKG shown in FIG. 16 in the following points.

  That is, in the package PKG shown in FIG. 17, the soft magnetic layer 40 is formed on the upper magnet member 20 in order to reduce the strength of the upper magnetic field from the upper magnet member 20, and the lower magnetic field from the lower magnet member 30 is formed. In order to reduce the strength, a soft magnetic layer 50 is formed below the lower magnet member 30. Therefore, when the semiconductor integrated circuit 10 having the package PKG shown in FIG. 17 is mounted on various electronic devices, it is possible to reduce the influence on the various electronic devices from the upper surface magnetic field and the lower surface magnetic field. Other than that, the same functions as those of the package PKG shown in FIG. 16 can be realized by the package PKG shown in FIG.

  FIG. 18 shows the structure of the BGA package according to the second embodiment of the present invention for magnetically shielding the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. FIG.

  BGA is an abbreviation for Ball grid array, and the bottom surface of the substrate 60 of the package PKG includes a plurality of connection balls ball arranged in a grid (grid). The plurality of connection balls ball are formed in a hemispherical shape due to the surface tension of the solder. The plurality of pad electrodes formed on the upper surface of the semiconductor chip of the semiconductor integrated circuit 10 are electrically connected to the plurality of connection balls ball on the bottom surface of the substrate 60 of the package PKG through the plurality of bonding wires BW and the internal wiring of the substrate 60. It is connected.

  As shown in FIG. 18, the lower surface of the semiconductor chip of the semiconductor integrated circuit 10 is fixed to the lower magnet member 30 by an insulating adhesive, while the upper surface of the semiconductor chip of the semiconductor integrated circuit 10 is fixed to the upper magnet by the insulating adhesive. It is fixed to the member 20.

  As shown in FIG. 18, since the semiconductor chip of the semiconductor integrated circuit 10 incorporating the nonvolatile memory 3 is disposed between the upper magnet member 20 and the lower magnet member 30, the upper magnet member 20 and the lower magnet member 30, the lower magnetic field of the upper magnet member 20 and the lower magnetic field of the lower magnet member 30 are canceled out.

  However, one of the upper magnet member 20 and the lower magnet member 30 is destroyed by an unauthorized access attack to the semiconductor chip of the semiconductor integrated circuit 10 sealed in the QFP package shown in FIG. If removed, the equilibrium state of the magnetic field is lost. As a result, the magnetization direction of the upper fixed layer of the magnetic tunnel junction MTJ of the plurality of magnetic read-only memory (MROM) cells MROM Cell of the nonvolatile memory 3 is reversed by the influence of the residual magnetic flux from the remaining magnet member.

  As described with reference to FIGS. 10 and 11, the reversal of the magnetization direction of the upper fixed layer of the magnetic tunnel junction MTJ of the MROM Cell of the plurality of magnetic read-only memories (MROM) of the nonvolatile memory 3 is illegal. It can be detected by the write detection circuit 2.

  FIG. 19 shows another structure of the BGA package according to the second embodiment of the present invention for magnetically shielding the semiconductor chip of the semiconductor integrated circuit 10 according to the first embodiment of the present invention described with reference to FIGS. FIG.

  The package PKG shown in FIG. 19 is different from the package PKG shown in FIG. 18 in the following points.

  That is, in the package PKG shown in FIG. 19, the soft magnetic layer 40 is formed on the upper magnet member 20 in order to reduce the strength of the upper magnetic field from the upper magnet member 20, and the lower magnetic field from the lower magnet member 30. In order to reduce the strength, a soft magnetic layer 50 is formed below the lower magnet member 30. Accordingly, when the semiconductor integrated circuit 10 having the package PKG shown in FIG. 19 is mounted on various electronic devices, it is possible to reduce the influence on the various electronic devices from the upper surface magnetic field and the lower surface magnetic field. Other than that, the same functions as those of the package PKG shown in FIG. 18 can be realized by the package PKG shown in FIG.

  Although the invention made by the present inventor has been specifically described based on various embodiments, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention. Yes.

  For example, in the nonvolatile memory 3 described with reference to FIGS. 2, 10, and 11, the cell MROM Cell of the magnetic read only memory (MROM) is arranged at a specific physical address inside the nonvolatile memory 3.

  Therefore, in the normal write operation and the normal read operation by the processor 1 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG. 1, the magnetic read only memory arranged at a specific physical address in the nonvolatile memory 3 (MROM) cell MROM Cell is never accessed. Accordingly, in the normal write operation and the normal read operation, the processor 1 accesses only the magnetic random access memory (MRAM) cell MRAM Cell arranged at another physical address (user area) inside the nonvolatile memory 3. It is. The logical address of the access by the processor 1 and the MRAM of the nonvolatile memory 3 so as to skip a magnetic read only memory (MROM) cell arranged at a specific physical address at the time of access of the normal write operation or normal read operation. An address conversion table for normal access indicating the correspondence with the physical address of cell access is constructed.

  The address conversion table for normal access can be stored in the nonvolatile memory 3 of the semiconductor integrated circuit 10 according to the first embodiment of the present invention shown in FIG.

  Further, only when the execution information corresponding to the secret key stored in the nonvolatile memory 3 is supplied to the processor 1, the processor 1 is allowed to execute the normal write operation and the normal read operation of the nonvolatile memory 3. As a result, the security of the secret information stored in the nonvolatile memory 3 can be improved.

  Furthermore, the semiconductor integrated circuit 10 incorporating the non-volatile memory 3 according to the present invention is not only mounted on an IC card, a portable terminal, etc., but also has high security of secret information stored in the non-volatile memory 3. It can be mounted on various electronic devices that are required.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor integrated circuit 1 ... Processor 2 ... Unauthorized writing detection circuit 3 ... Non-volatile memory 4 ... Peripheral function module 5 ... Volatile memory 6 ... Internal bus 6
300 ... 3MN ... Multiple memory cells WWL0, WWL1, WWL2, WWL3 ... WWLM ... Write word lines RWL0, RWL1, RWL2, RWL3 ... RWLM ... Read word lines BL0, BL1, BL2, BL3 ... BLN ... Bit lines MRAM Cell ... Magnetic Random access memory (MRAM) cell MROM Cell ... Magnetic read-only memory (MROM) cell MTJ ... Magnetic tunnel junction 3000 ... Antiferromagnetic layer 3001 ... Ferromagnetic layer 3002 ... Insulating layer 3003 ... Ferromagnetic layer Fix ... Fixed layer Tunnel ... Tunnel insulating layer Free ... Free layer TR ... N-channel MOS transistor S ... Source G ... Gate D ... Drain Vss ... Ground voltage RWL ... Read word line WWL ... Write word line BL ... Bit line

Claims (24)

A semiconductor integrated circuit comprising a processor and a nonvolatile memory,
The non-volatile memory includes a plurality of magnetic random access memory cells and a plurality of magnetic read-only memory cells,
The plurality of magnetic random access memory cells of the non-volatile memory can be rewritten by normal writing by the processor, and the plurality of magnetic read-only memory cells of the non-volatile memory can be rewritten by the normal writing by the processor. Impossible,
The semiconductor integrated circuit further comprises a sensing circuit connected to the nonvolatile memory,
The sensing circuit is capable of sensing a state transition of the plurality of magnetic read-only memory cells due to unauthorized access to the nonvolatile memory;
In response to the state transition of the plurality of magnetic read-only memory cells due to the unauthorized access of the nonvolatile memory, the sensing circuit notifies the processor of a detection result of the unauthorized access. . In claim 1,
2. A semiconductor integrated circuit according to claim 1, wherein a normal access operation by the processor of the plurality of magnetic random access memory cells of the nonvolatile memory is stopped according to a detection result of the unauthorized access of the sensing circuit. In claim 2,
The sensing circuit generates an interrupt to the processor according to the unauthorized access detection result,
The semiconductor integrated circuit according to claim 1, wherein the normal access operation by the processor of the plurality of magnetic random access memory cells of the nonvolatile memory is stopped by the interrupt. In claim 2,
The sensing circuit sets flag information to the processor according to the detection result of the unauthorized access,
The semiconductor integrated circuit according to claim 1, wherein the normal access operation by the processor of the plurality of magnetic random access memory cells of the nonvolatile memory is stopped by the flag information. In claim 2,
The semiconductor integrated circuit further comprises an input / output port connected to the nonvolatile memory,
The input / output port is capable of reading information stored in the plurality of magnetic random access memory cells of the nonvolatile memory to the outside of the semiconductor integrated circuit,
According to the detection result of the unauthorized access of the sensing circuit, the reading of the storage information of the plurality of magnetic random access memory cells of the nonvolatile memory by the input / output port to the outside of the semiconductor integrated circuit is stopped. A semiconductor integrated circuit. In claim 2,
Each of the plurality of magnetic random access memory cells of the non-volatile memory includes an MRAM free layer that includes a ferromagnetic layer and whose magnetization direction can be controlled from the outside, an MRAM tunnel insulating layer that includes an insulating layer, a ferromagnetic layer Including an MRAM magnetic tunnel junction comprising a laminated film of an antiferromagnetic layer and an MRAM pinned layer in which the magnetization direction of the ferromagnetic layer is strongly pinned by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer. A semiconductor integrated circuit. In claim 6,
Each of the plurality of magnetic read-only memory cells of the nonvolatile memory is composed of a laminated film of a ferromagnetic layer and an antiferromagnetic layer, and the magnetization of the ferromagnetic layer is formed by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer. MROM upper fixed layer whose direction is strongly fixed, MROM tunnel insulating layer made of an insulating layer, and a laminated film of a ferromagnetic layer and an antiferromagnetic layer. A semiconductor integrated circuit comprising an MROM magnetic tunnel junction comprising an MROM lower fixed layer in which the magnetization direction of the magnetic layer is strongly fixed. In claim 2,
Before the semiconductor integrated circuit receives the unauthorized access of the nonvolatile memory, low-level storage information is written to the plurality of magnetic read-only memory cells of the nonvolatile memory,
2. The semiconductor integrated circuit according to claim 1, wherein the sensing circuit includes an OR circuit having a plurality of input terminals connected to a plurality of bit lines connected to the plurality of magnetic read-only memory cells. In claim 2,
Before the semiconductor integrated circuit receives the unauthorized access of the nonvolatile memory, high-level storage information is written to the plurality of magnetic read-only memory cells of the nonvolatile memory,
2. The semiconductor integrated circuit according to claim 1, wherein the sensing circuit includes a NAND circuit having a plurality of input terminals connected to a plurality of bit lines connected to the plurality of magnetic read-only memory cells. In claim 2,
A semiconductor integrated circuit, wherein the semiconductor chip of the semiconductor integrated circuit including the processor and the nonvolatile memory is disposed between an upper magnet member and a lower magnet member of a package structure. In claim 10,
A semiconductor integrated circuit, wherein a lower magnetic field from the upper magnet member and an upper magnetic field from the lower magnet member are canceled between the upper magnet member and the lower magnet member of the package structure. In claim 11,
The state of the plurality of magnetic read-only memory cells of the nonvolatile memory by destroying and removing one of the upper magnet member and the lower magnet member of the package structure by the unauthorized access of the nonvolatile memory A semiconductor integrated circuit characterized in that a transition occurs. A method of operating a semiconductor integrated circuit comprising a processor and a nonvolatile memory,
The non-volatile memory includes a plurality of magnetic random access memory cells and a plurality of magnetic read-only memory cells,
The plurality of magnetic random access memory cells of the non-volatile memory can be rewritten by normal writing by the processor, and the plurality of magnetic read-only memory cells of the non-volatile memory can be rewritten by the normal writing by the processor. Impossible,
The semiconductor integrated circuit further comprises a sensing circuit connected to the nonvolatile memory,
The sensing circuit is capable of sensing a state transition of the plurality of magnetic read-only memory cells due to unauthorized access to the nonvolatile memory;
In response to the state transition of the plurality of magnetic read-only memory cells due to the unauthorized access of the nonvolatile memory, the sensing circuit notifies the processor of a detection result of the unauthorized access. How it works. In claim 13,
A method of operating a semiconductor integrated circuit, wherein normal access operation by the processor of the plurality of magnetic random access memory cells of the nonvolatile memory is stopped according to a detection result of the unauthorized access of the sensing circuit. In claim 14,
The sensing circuit generates an interrupt to the processor according to the unauthorized access detection result,
A method of operating a semiconductor integrated circuit, wherein the normal access operation by the processor of the plurality of magnetic random access memory cells of the nonvolatile memory is stopped by the interrupt. In claim 14,
The sensing circuit sets flag information to the processor according to the detection result of the unauthorized access,
The operation method of a semiconductor integrated circuit, wherein the normal access operation by the processor of the plurality of magnetic random access memory cells of the nonvolatile memory is stopped by the flag information. In claim 14,
The semiconductor integrated circuit further comprises an input / output port connected to the nonvolatile memory,
The input / output port is capable of reading information stored in the plurality of magnetic random access memory cells of the nonvolatile memory to the outside of the semiconductor integrated circuit,
According to the detection result of the unauthorized access of the sensing circuit, the reading of the storage information of the plurality of magnetic random access memory cells of the nonvolatile memory by the input / output port to the outside of the semiconductor integrated circuit is stopped. A method for operating a semiconductor integrated circuit. In claim 14,
Each of the plurality of magnetic random access memory cells of the non-volatile memory includes an MRAM free layer that includes a ferromagnetic layer and whose magnetization direction can be controlled from the outside, an MRAM tunnel insulating layer that includes an insulating layer, a ferromagnetic layer Including an MRAM magnetic tunnel junction comprising a laminated film of an antiferromagnetic layer and an MRAM pinned layer in which the magnetization direction of the ferromagnetic layer is strongly pinned by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer. A method for operating a semiconductor integrated circuit. In claim 18,
Each of the plurality of magnetic read-only memory cells of the nonvolatile memory is composed of a laminated film of a ferromagnetic layer and an antiferromagnetic layer, and the magnetization of the ferromagnetic layer is formed by exchange coupling between the antiferromagnetic layer and the ferromagnetic layer. MROM upper fixed layer whose direction is strongly fixed, MROM tunnel insulating layer made of an insulating layer, and a laminated film of a ferromagnetic layer and an antiferromagnetic layer. A method of operating a semiconductor integrated circuit, comprising an MROM magnetic tunnel junction comprising an MROM lower fixed layer in which the magnetization direction of the magnetic layer is strongly fixed. In claim 14,
Before the semiconductor integrated circuit receives the unauthorized access of the nonvolatile memory, low-level storage information is written to the plurality of magnetic read-only memory cells of the nonvolatile memory,
The method of operating a semiconductor integrated circuit, wherein the sensing circuit includes an OR circuit having a plurality of input terminals connected to a plurality of bit lines connected to the plurality of magnetic read-only memory cells. In claim 14,
Before the semiconductor integrated circuit receives the unauthorized access of the nonvolatile memory, high-level storage information is written to the plurality of magnetic read-only memory cells of the nonvolatile memory,
The method of operating a semiconductor integrated circuit, wherein the sensing circuit includes a NAND circuit having a plurality of input terminals connected to a plurality of bit lines connected to the plurality of magnetic read-only memory cells. In claim 14,
A semiconductor integrated circuit operating method, wherein a semiconductor chip of the semiconductor integrated circuit including the processor and the nonvolatile memory is disposed between an upper magnet member and a lower magnet member of a package structure. In claim 22,
A method of operating a semiconductor integrated circuit, wherein a lower magnetic field from the upper magnet member and an upper magnetic field from the lower magnet member are canceled between the upper magnet member and the lower magnet member of the package structure. In claim 23,
The state of the plurality of magnetic read-only memory cells of the nonvolatile memory by destroying and removing one of the upper magnet member and the lower magnet member of the package structure by the unauthorized access of the nonvolatile memory A method for operating a semiconductor integrated circuit, wherein a transition occurs.

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