JP2004153182A - Magnetic memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stabilize the storage status of a memory cell by making mis-writing preventable at writing. <P>SOLUTION: A magnetic memory is provided with a memory cell provided with: a magnetoresistance effect element 3; a cell bit line 6 which is branched from a bit line BL and makes a writing current flow to the magnetoresistance effect element; a yoke 8, having an easily-magnetized axis direction same as the magnetoresistance effect element, which is provided to the cell bit line; and a writing-selective transistor 19 in which one of source/drain is connected to the cell bit line. Consequently, mis-writing can be prevented at writing, and the storage status of the memory cell is stabilized. <P>COPYRIGHT: (C)2004,JPO

Description

図１２中の矢印Ａ２の条件は以下の不等式になる。
【００４６】
【数２】

図１２中の矢印Ａ３の条件は以下の不等式になる。
【００４７】
【数３】

以上の３つの不等式を連立すると、以下の式が得られる。
【００４８】
【数４】

誤書き込みが起きないためには、Ｈ_ｏｆｆ， ｄＨ_ｏｆｆ， ｒ， ｄＨ_ｃ， が上式を満たすように小さいことが必要である。実際にメモリとして実用になるには、標準偏差をσとすると±６σの範囲内で誤書き込みが無い必要がある。その場合は、例えば、
Ｈ_ｃ＝３６［Ｏｅ］、かつａ_Ｕ／ａ_Ｌ≦１．７
を仮定すると
６σ（Ｈ_ｃ）≦３．５［Ｏｅ］、 Ｈ_ｏｆｆ≦３．５［Ｏｅ］、 ６σ（Ｈ_ｏｆｆ）≦３．５［Ｏｅ］
の条件を満たす必要がある。
【００４９】
ＭＲＡＭの製造上、多数のメモリセルに渡って上記条件ほど高精度にスイッチング磁場のばらつきを抑制することは従来困難であった。しかし、本実施形態のように、各メモリセルに設けられたトランジスタを書き込み選択用に用い、１メモリセル毎に書込電流を流す方式の場合は、原理的にいくらばらつきがあろうとも、磁化容易軸方向に十分大きな磁場をかければ書き込める。
【００５０】
その理由を、以下説明する。ビット線から枝分かれしたセルビット線毎に電流を流すため、ビット線方向の他のメモリセルはｈａｌｆ ｓｅｃｔｉｏｎの状態にならない。したがって、図１２の矢印Ａ２の条件は、不要になり、制約が無くなる。その結果、ｘ方向（磁化容易軸方向）に十分大きな磁場をかければ誤書き込みが無くなる。
【００５１】
したがって、本実施形態は、スイッチング磁場のメモリセル毎のばらつきに非常に強い磁気メモリ、すなわち誤書き込みの起きにくい磁気メモリを得ることができる。
【００５２】
以上説明したように、本実施形態においては、共用ビット線ＢＬから枝分かれしたセルビット線６を各メモリセル２に設けるとともにセルビット線６上に設けられたヨーク８の磁化容易軸方向をＴＭＲ素子３の磁化容易軸方向とほぼ同じとなるようにしたので、ヨーク８に残留磁化が発生した場合や、ヨーク８の磁化容易軸方向に磁化の乱れが発生した場合でも、これらの残留磁化や磁化の乱れは、ＴＭＲ素子３に書き込んだ情報と同じ方向に磁場を発生することになり、これにより、ＴＭＲ素子３の記憶状態が安定する。また、各メモリセル２にセルビット線６と書き込み選択トランジスタ１７が設けられているので、選択されたメモリセルに書き込み電流を流すときに、同じカラム上の他のメモリセルには書き込み電流が流れない。この結果およびＴＭＲ素子３の記憶状態が安定であることにより、他のメモリセルの記録ビットを反転させることがなく、誤書き込みを防止することができる。
【００５３】
また、ヨーク８、９に付与する一軸磁気異方性とＴＭＲ素子３に付与する一軸磁気異方性がほぼ同じ方向であるので、ＴＭＲ素子３に一軸磁気異方性を付与する工程と、ヨーク８、９に一軸磁気異方性を付与する工程とを、同じ磁界の方向で、一括して行うことができる。その結果、従来に比べて製造工程が簡略化され、コストが下がる。
【００５４】
なお、第２実施形態においては、セルビット線６は第１配線部６ａと第２配線部６ｂからなっており、第１配線部６ａに流れる電流による電流磁場ばかりでなく、ＴＭＲ素子３の側部に配置された第２配線部６ｂに流れる電流による電流磁場もＴＭＲ素子３の書き込みに用いることができる。このため、従来よりも少ない電流で書き込みを行うことができる。
【００５５】
（第３実施形態）
次に、本発明の第３実施形態による磁気メモリのメモリセルの構成を図５に示し、メモリセルアレイの構成を図６に示す。この実施形態による磁気メモリは第２実施形態の磁気メモリの読み出し選択トランジスタ１７を削除するとともに書き込みワード線ＷＬが読み出しワード線を兼ねた構成となっている。したがって、ＴＭＲ素子３の下部電極は書き込みワード線ＷＬに電気的に接続された構成となっている。また、セルビット線６の第１配線部６ａ上には第２実施形態と同様にヨーク８ａが設けられているが、第２配線部６ｂ上にもヨーク８ｂが設けられている。なお、図５に示すように、ＴＭＲ素子３、セルビット線６のヨーク８ａ，８ｂ、およびワード線ＷＬのヨーク９の磁化容易軸方向はほぼ同じ方向となるように形成される。
【００５６】
この第３実施形態による磁気メモリの選択されたメモリセル２へのデータの書き込みは、第２実施形態の場合と同様にして行う。この第３実施形態による磁気メモリの選択されたメモリセル２からのデータ読み出し動作はクロスポイント型と呼ばれる方法で行われる。ロウがｉ番目でカラムがｊ番目のメモリセル２からデータを読み出す場合は、ロウデコーダ４１によってロウ選択トランジスタ３３_ｉをＯＮ、カラムデコーダ４５によってカラムトランジスタ３７_ｊをＯＮさせる。このとき、ロウ選択トランジスタ３４_ｉおよびカラムトランジスタ３５_ｊはＯＦＦ状態とする。これにより、書き込みワード線ＷＬからＴＭＲ素子３、セルビット線６を介して共用ビット線ＢＬ_ｊに電流が流れる。このとき、共用ビット線ＢＬ_ｊの電位はＴＭＲ素子３に記憶されたデータに応じた値となる。この共用ビット線ＢＬ_ｊの電位をセンスアンプ６１，６２において基準電位ＶＲＥＦと比較することにより、ＴＭＲ素子３に記憶されたデータが読み出される。
【００５７】
この第３実施形態のように読み出し選択トランジスタを用いないでクロスポイント型で読み出す場合には、読み出しに選択性を持たせることが必要である。すなわち、選択したメモリセル以外の他のメモリセルからの回り込み電流をセンスしないようにすることが必要になる。その第１の方式は、図６に示したように、読出しワード線ＷＬの上下にロウ選択トランジスタ３３_ｉ、３４_ｉと、ロウデコーダ４１、４４を設ける方式である。読み出すべきメモリセルへの読み出しワード線ＷＬ_ｉをロウ選択信号ＲＳＬ（ｉ）で選択して読出し用電流を流す場合、他のワード線ＷＬ_ｍ（ｍ≠ｉ）はＲＳＬ（ｍ）で選択されて下のロウデコーダ４４に接続される。その結果、選択したメモリセル以外の他のメモリセルを通った電流は下のロウデコーダ４４に吸い込まれてセンスアンプ６１、６２には流れない。
【００５８】
第２の方式を、図９を参照して説明する。この方式ではビット線ＢＬ_ｊ（ｊ＝１，・・・）毎にセンスアンプ６１_ｊを設け、３組のセンスアンプの６１_ｊ−１、６１_ｊ、６１_ｊ＋１の出力をセレクタ６５によって選択し、この選択した出力がセンスアンプ６２を介して外部に出力される。その結果、選択したセル以外の他のセルを通った電流は他のセンスアンプに入り、選択したセンスアンプには入らない。
【００５９】
これらの方式により、読出し選択トランジスタを使わずとも、選択性を持たせた読出しができる。各メモリセル２に読出し用に設けられたトランジスタやダイオードがある場合は、これらの特性のばらつき、例えばトランジスタのＯＮ抵抗のばらつきが、読出し信号のばらつきになり、問題となっていた。ここで説明した読出し選択トランジスタを使わない方法の場合は、トランジスタやダイオードのばらつきに左右されない利点がある。
【００６０】
以上説明したように、第３実施形態においては、セルビット線６はＬ字型に曲がってＴＭＲ素子３の周囲を取り巻いており、セルビット線６の周囲に被覆したヨーク８ａ、８ｂの効果と相俟って、ＴＭＲ素子３において大きな磁場を発生できる。このセル構造では特に、書き込みワード線ＷＬがＴＭＲ素子３に最も近くなるため、ＴＭＲ素子３において最も強い磁場を発生できる。書き込みワード線ＷＬには断面がコの字型のヨーク９を設けることで磁場を強くする。したがって、書き込みに要する電流を小さくするができる。また、図５に示したように、セルビット線６のヨーク８ａ，８ｂと、ワード線ＷＬのヨーク９と、ＴＭＲ素子３の磁化容易軸は同じ方向に形成されるので、ＴＭＲ素子３の記憶状態は安定となる。またＴＭＲ素子３の記憶状態が安定であること、およびメモリセル毎に、セルビット線６と書き込み選択トランジスタ１９が設けられていることにより、選択されたメモリセル以外のメモリセルの記録ビットが反転するのを防止することができる。この結果およびＴＭＲ素子３の記憶状態が安定であることにより、他のメモリセルの記録ビットを反転させることがなく、誤書き込みを防止することができる。
【００６１】
また、ヨーク８ａ、８ｂおよびＴＭＲ素子３の磁化容易軸方向がほぼ一致しているので、ヨーク８ａ、８ｂおよびＴＭＲ素子３に一軸磁気異方性を付与する工程を一括して行うことが可能となり、製造工程が簡略化され、製造コストを下げることができる。
【００６２】
（第４実施形態）
次に、本発明の第４実施形態による磁気メモリのメモリセルの構成を図７に示す。この第４実施形態による磁気メモリは、図５に示す第３実施形態の磁気メモリの書き込みおよび読み出し兼用のワード線ＷＬを読み出し専用のワード線ＲＷＬに置き換えるとともにセルビット線６が第１配線部６ａおよび第２配線部６ｂだけでなく、読み出しワード線ＲＷＬの下側に図示しない絶縁膜を介して配置された第３配線部６ｃを備えるように構成されている。そして、第１乃至第３配線部６ａ、６ｂ、６ｃには、それぞれヨーク８ａ、８ｂ、８ｃが設けられている。これらのヨーク８ａ、８ｂ、８ｃは、磁化容易軸方向がＴＭＲ素子３の磁化容易軸方向とほぼ一致するように形成される。
【００６３】
この第４実施形態による磁気メモリの読み出し動作は、第３実施形態の磁気メモリの場合と同様にして行う。しかし、書き込み動作は、第１実施形態の場合と同様に、セルビット線６からの電流磁場によって行う。したがって、第１実施形態の場合と同様に、書き込み電流を低減するためには、セルビット線６の第１および第３配線部６ａ、６ｃは、ＴＭＲ素子３の磁化容易軸方向と所定の角度（例えば、４５度）をなすように形成することが望ましい。
【００６４】
この第４実施形態によれば、セルビット線６には、磁化容易軸方向がＴＭＲ素子３の磁化容易軸方向にほぼ一致するヨーク８ａ、８ｂ、８ｃが設けられているとともに各メモリセルに書き込み選択トランジスタが設けられているため、ＴＭＲ素子３の記憶状態は安定となり、さらに選択されたメモリセル以外のメモリセルの記録ビットが反転するのを防止することができる。
【００６５】
また、セルビット線６は、第１乃至第３配線部６ａ、６ｂ、６ｃがＴＭＲ素子３を取り囲むように形成されているとともに、第１乃至第３配線部６ａ、６ｂ、６ｃには、ヨーク８ａ、８ｂ、８ｃがそれぞれ設けられているので、小さな書き込み電流で大きな磁場を発生することが可能となる。
【００６６】
また、ヨーク８ａ、８ｂ、８ｃおよびＴＭＲ素子３の磁化容易軸方向がほぼ一致しているので、ヨーク８ａ、８ｂ、８ｃおよびＴＭＲ素子３に一軸磁気異方性を付与する工程を一括して行うことが可能となり、製造工程が簡略化され、製造コストを下げることができる。
【００６７】
なお、第４実施形態においては、ワード線ＲＷＬは読み出し専用であるため、第３実施形態の書き込みと読み出しを兼ねたワード線ＷＬに比べて薄くすることができ、また、ワード線ＲＷＬを覆うヨークが不要となる。
【００６８】
なお、この第４の実施形態においては、ＴＭＲ素子３は第１配線部６ａに電気的に接続されるように設けたが、第１配線部６ａに接続されず、第３配線部６ｃに電気的に接続されるように設けても良い。
【００６９】
（第５実施形態）
第１および第２実施形態による磁気メモリでは、一つのＴＭＲ素子３に二つのトランジスタ１７、１９が必要であり、その分、各メモリセル２の必要面積が大きくなり、高密度に配置したメモリを作ることが困難である欠点がある。しかし、読出しの選択性をきちんと取れる利点がある。
【００７０】
これに対して、第３および第４実施形態による磁気メモリでは、読出し選択トランジスタ１７を用いないため、メモリセル２の必要面積はそれほど大きくならない利点がある。しかし、読み出しをクロスポイント型と呼ばれる方法で行うため、回り込み電流があって読出しの選択性をあまり取れない欠点がある。
【００７１】
これら両者の利点を併せ持つ磁気メモリを、本発明の第５実施形態として説明する。この第５実施形態による磁気メモリのメモリセルアレイを図８に示す。図８に示すように、本実施形態の磁気メモリにおいては、一つのＴＭＲ素子３に一つの書き込み選択トランジスタ１９が設けられているが、読み出し選択トランジスタは２個から１６個のＴＭＲ素子３に一つだけ設けた構成となっている。この結果、読み出しの選択性をある程度確保しつつ、高密度に配置したメモリを作ることができる。図８では、４個のＴＭＲ素子３に一つの読み出し選択トランジスタ１７を配置している。読み出し時に４個のＴＭＲ素子３が同時に選択されるが、それぞれを独立の４個のセンスアンプ６０_１〜６０_４で読み出すため、回り込み電流の影響を受けずに独立して読み出せる。
【００７２】
（第６実施形態）
次に、本発明の第６実施形態による磁気メモリの製造方法を説明する。この第６実施形態による製造方法は、図７に示す第４実施形態による磁気メモリを製造するものであり、以下、図７を参照して説明する。
【００７３】
まず、ｐ型シリコン基板を用意する。次に、書き込み選択トランジスタ１９としてＮチャンネルＭＯＳＦＥＴを通常のＣＭＯＳプロセスで形成する。このとき、ゲート電極はそのまま書き込み選択ワード線ＷＷＬとして働くよう形成する。ドレインとソース上に電極７を形成し、コモン線２０を配線する。
【００７４】
次に、絶縁層（図示せず）を形成する。その後、第３配線部６ｃを形成する。第３配線部６ｃに用いる材料は、Ａｌ、Ａｌ−Ｃｕ、Ｃｕ、Ａｇ等が考えられるが、ここではダマシン法で形成したＣｕが用いられている。第３配線部６ｃには強磁性体であるＮｉＦｅからなるヨーク８ｃが被覆された配線となっている。なお、ヨーク８ｃにはバリアメタルとしてＮｉＦｅの外側にＴｉＮ、ＮｉＦｅとＣｕの間にはＣｏＦｅが挿入されている。
【００７５】
次に、図示しない絶縁膜を形成し、その上に読み出しワード線ＲＷＬを形成し、更に図示しない絶縁膜を被覆し、この絶縁膜を、読み出しワード線ＲＷＬが露出するように平坦化する。次に、ＴＭＲ積層膜３を堆積する。このＴＭＲ積層膜３は、ワード線ＷＬ上に、膜厚２０ｎｍのＴａからなる下部配線接続層、膜厚５ｎｍのＲｕからなるバッファ層、膜厚６ｎｍのＩｒＭｎからなる反強磁性層、膜厚２ｎｍのＣｏ_９０Ｆｅ_１０からなる磁化固着層、膜厚１ｎｍのＡｌ_２Ｏ_３からなるトンネルバリア層、膜厚３ｎｍのＮｉ_７９Ｆｅ_２１からなる磁化自由層、膜厚２ｎｍのＣｕからなる表面保護層、膜厚２０ｎｍのＲｕからなるエッチングストップ層兼表面保護層、Ｔａからなる上部接続層を順次積層することによって得られる。
【００７６】
次に、ＴｉＮまたはＴａをハードマスクとして用いて、ＴＭＲ積層膜３を所定の形状にエッチング、例えば０．２４×０．４８μｍ^２の長方形にし、ＴＭＲ素子３を形成する。その後、層間絶縁膜（図示せず）を堆積する。ＴＭＲ素子３の横に、垂直方向のセルビット線６ｂを形成するための直方体のビアホールを上記層間絶縁膜に形成する。このビアホールを形成している垂直面４面の内、３面を強磁性体であるＮｉＦｅで被覆する。これが垂直方向のセルビット線６ｂのヨーク８ｂとして働く。ＮｉＦｅからなるヨーク８ｂの外側にバリアメタルとして、ＴｉＮが挿入されている。続いて上記ビアホールをダマシン法を用いてＣｕで埋める。ＮｉＦｅとＣｕ層との間にはＣｏＦｅが挿入されている。
【００７７】
次に、ＴＭＲ素子３の上部接続層とコンタクトが取れるよう上記層間絶縁膜をエッチングする。共用ビット線ＢＬおよびセルビット線６ａを形成するためにＣｕからなる金属膜を、ＴＭＲ素子３の上部接続層と接続するように、また垂直方向のセルビット線６ｂと接続するように堆積する。続いて、共用ビット線ＢＬおよびセルビット線を形成するようにＣｕからなる金属膜をエッチングする。平面配置で見ると、各ＴＭＲ素子３の間に共用ビット線ＢＬを配置し、そこから分岐したセルビット線６が各ＴＭＲ素子３の直上を通るよう配置する。
【００７８】
次に、セルビット線６ａの最上層と側面を強磁性体であるＮｉＦｅ膜で被覆し、ヨーク８ａが形成された配線とする。なお、ＮｉＦｅからなるヨーク８ａとセルビット線６ａとの間にはバリアメタルとしてＣｏＦｅ膜が挿入されている。また、バリアメタルとしては、ＣｏＦｅの代わりにＴａ、ＴｉＮ、ＴａＮ、Ｗ、ＷＮなども使い得る。なお、ヨーク８ａの上にＴｉＮからなるバリアメタルを形成しても良い。
【００７９】
ヨーク８ａを形成した後、図示しない保護層を堆積する。続いて、磁場中でアニールし、ＴＭＲ素子３と、ビット線ヨーク８ａ、８ｂ、８ｃに一括して同じ方向に一軸磁気異方性を付与する。磁場の方向は、図７で示した方向であり、アニール条件は、例えば、２８５℃で１時間、６．５ｋＯｅの磁場中で行う。この磁場中でのアニール直後は、磁化自由層の磁化方向とヨークの残留磁化から磁化自由層にかかる磁界とは反平行になっている。すなわち、磁化自由層の磁化は不安定な状態に置かれている。そこで、メモリとして出荷する前に、書き込み配線に電流を流して“０”の状態に初期化することが望ましい。この工程によって、磁化自由層の磁化とヨークの残留磁化から磁化自由層にかかる磁場とが平行になる。
【００８０】
ＴＭＲ素子３は重要不可欠な要素としてトンネルバリア層がある。これは１〜２ｎｍと薄い絶縁層であり、静電放電破壊に弱い。従来の磁気メモリの製造プロセスにおいては、典型的にはＴＭＲ素子３の上部接続層を露出させるために層間絶縁膜をドライエッチング、例えばリアクティブイオンエッチング（ＲＩＥ）する際に、図１４の矢印に示すように、表面に溜まった電荷がＴＭＲ素子３を通って放電し、トンネルバリア層を静電放電破壊する問題があった。これは、ＴＭＲ素子３から読出し選択トランジスタ１７、或いはワード線を通って基板への電流パスがあるためである。しかし、第１乃至第６実施形態による磁気メモリのメモリセル構造では、図１３に示すように、ＴＭＲ素子３毎に、ＴＭＲ素子３の脇にセルビット線６ｂが基板に向けて通っており、このセルビット線６ｂの方がＴＭＲ素子３に比べて抵抗が低い。このため、表面に溜まった電荷はＴＭＲ素子３を通らずにセルビット線６ｂを通って放電される。その結果、作製プロセス中のトンネルバリア層の破壊が起きにくい。
【００８１】
なお、上記実施形態で説明した以外の構造のＴＭＲ素子を用いても良い。例えば、この構造のＴＭＲ素子は、ワード線ＷＬ上に、膜厚５ｎｍのＴａからなる下部配線接続層、膜厚５ｎｍのＮｉＦｅＣｒからなるシード層、膜厚１２ｎｍのＰｔＭｎからなる反強磁性層、膜厚２ｎｍのＣｏ_９０Ｆｅ_１０からなる磁化固着層、膜厚０．８ｎｍのＲｕからなる中間層、膜厚２ｎｍのＣｏ_９０Ｆｅ_１０からなる磁化固着層、膜厚１ｎｍのＡｌ_２Ｏ_３からなるトンネルバリア層、膜厚３ｎｍのＮｉ_８１Ｆｅ_１９からなる磁化自由層、膜厚１０ｎｍのＴａからなる保護層、Ａｌからなる上部配線接続層を順次積層することによって得られる。この構造は、磁化固着層として交換結合膜、すなわちシンセティック・反強磁性層を用いた場合である。
【００８２】
【発明の効果】
以上述べたように、本発明によれば、書き込みの際に誤書き込みを防止することができ、メモリセルの記憶状態を安定化することができる。
【図面の簡単な説明】
【図１】本発明の第１実施形態による磁気メモリのメモリセルの構成を示す断面図。
【図２】第１実施形態による磁気メモリのメモリセルアレイを示す配線図。
【図３】本発明の第２実施形態による磁気メモリのメモリセルの構成を示す断面図。
【図４】第２実施形態による磁気メモリのメモリセルアレイを示す配線図。
【図５】本発明の第３実施形態による磁気メモリのメモリセルの構成を示す断面図。
【図６】第３実施形態による磁気メモリのメモリセルアレイを示す配線図。
【図７】本発明の第４実施形態による磁気メモリのメモリセルの構成を示す断面図。
【図８】本発明の第５実施形態による磁気メモリのメモリセルアレイを示す配線図。
【図９】第３実施形態において、選択したメモリセル以外の他のメモリセルからの回り込み電流をセンスしないようにする他の方式を説明する図。
【図１０】書き込み電流の流し方を説明する図。
【図１１】書き込み電流の流し方を説明する図。
【図１２】誤書き込みが起きないことを説明する図。
【図１３】製造工程中にＴＭＲ素子に静電絶縁破壊が生じるのを防止することができることを説明する図。
【図１４】製造工程中にＴＭＲ素子に静電絶縁破壊が生じるのを説明する図。
【図１５】従来の磁気メモリの書き込み配線を示す図。
【図１６】従来の磁気メモリの問題点を説明する図。
【符号の説明】
２ メモリセル
３ ＴＭＲ素子
６ セルビット線
６ａ 第１配線部
６ｂ 第２配線部
７ 接続プラグ
８ ヨーク
８ａ ヨーク
８ｂ ヨーク
９ ヨーク
１４ 引き出し電極
１５ 接続プラグ
１７ 読み出し選択トランジスタ
１８ 接続プラグ
１９ 書き込み選択トランジスタ
２０ コモン線
ＢＬ 共用ビット線
ＷＬ 書き込みワード線
ＲＷＬ 読み出し選択ワード線
ＷＷＬ 書き込み選択ワード線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a magnetic random access memory (MRAM).
[0002]
[Prior art]
2. Description of the Related Art A magnetic random access memory (hereinafter, also referred to as an MRAM) is a memory device using a magnetoresistive element having a magnetoresistive effect in a memory cell for storing information, and is characterized by high-speed operation, large capacity, and non-volatility. As a next generation memory device. The magnetoresistance effect is a phenomenon in which when a magnetic field is applied to a ferromagnetic material, the electric resistance changes according to the direction of magnetization of the ferromagnetic material. The memory device can be operated as a memory device by using the direction of magnetization of the ferromagnetic material constituting the magnetoresistive element for recording information and reading the information depending on the magnitude of electric resistance corresponding to the direction of magnetization.
[0003]
In recent years, in a ferromagnetic tunnel junction including a sandwich structure in which an insulating layer called a tunnel barrier layer is inserted between two ferromagnetic layers, a magnetoresistance change of 20% or more due to a tunnel magnetoresistance effect (hereinafter, also referred to as a TMR effect). MRAM using a ferromagnetic tunnel junction magnetoresistive element (hereinafter, also referred to as a TMR element) utilizing a tunnel magnetic effect has attracted attention and attention since the ratio (MR ratio) has been obtained. I have.
[0004]
When a TMR element is used in a memory cell of an MRAM, one of two ferromagnetic layers sandwiching a tunnel barrier layer is fixed to a magnetization pinned layer (also referred to as a reference layer) so that the direction of magnetization does not change. The other ferromagnetic layer is a magnetization free layer (or a storage layer) whose magnetization direction is reversed according to an external magnetic field. Information can be stored by associating a state where the magnetization directions of the reference layer and the storage layer are parallel and an anti-parallel state with binary information “0” and “1”. Writing of recording information is performed by reversing the direction of magnetization of the storage layer by an induced magnetic field generated by passing a current through a write wiring provided near the TMR element.
[0005]
In a conventional MRAM, the large current required for writing has prevented its spread, and reducing the writing current has been an important issue. Reading of recorded information is performed by detecting a resistance change due to the TMR effect. Therefore, it is preferable that the storage layer has a large resistance change rate (MR ratio) due to the TMR effect and a small magnetic field required for magnetization reversal, that is, a switching magnetic field.
[0006]
On the other hand, it is necessary to fix the direction of magnetization so that the magnetization of the reference layer is not easily reversed. For this purpose, an antiferromagnetic layer is provided so as to be in contact with the ferromagnetic layer, and the magnetization reversal is performed by exchange coupling force. A method of reducing the occurrence is used, and such a structure is called a spin valve type structure. In this structure, the direction of magnetization of the reference layer is determined by performing a heat treatment while applying a magnetic field (annealing annealing).
[0007]
As described above, as shown in FIG. 15A, the magnetization reversal of the storage layer 3c of the TMR element 3 uses the induced magnetic field due to the current flowing through the write wiring 80, so that the switching magnetic field of the storage layer 3c is large. There is a problem that a current flowing through the write wiring increases and power consumption increases. In order to solve this, as shown in FIG. 15B, a wiring with a yoke is proposed in which the writing wiring 80 is covered with a soft magnetic material 82 and the induced magnetic field generated from the writing wiring 80 is strengthened near the TMR element 3. Have been. In FIGS. 15A and 15B, the TMR element 3 includes a reference layer 3a, a tunnel insulating layer 3b, and a storage layer 3c.
[0008]
An MRAM in which a thin film (yoke) made of a high magnetic permeability material is provided around a write wiring has been proposed (for example, see Patent Documents 1 and 2).
[0009]
[Patent Document 1]
U.S. Pat. No. 5,659,499
[Patent Document 2]
JP-A-2002-110938
[0010]
[Problems to be solved by the invention]
The problem in the case where a yoke is used as a write wiring is that a current for applying a magnetic field in the direction of the easy axis of the reference layer and the storage layer constituting the TMR element flows through the bit line used for writing, and the TMR element flows through the word line. Will be described by way of an example in which a current is applied to apply a magnetic field in the direction of the hard axis of the reference layer and the storage layer.
[0011]
In general, in the MRAM, the bit line is common to one column, and therefore, the yoke 82 formed around the write bit line BL is provided in the direction shown by the arrow 90 in FIG. 16, that is, in the direction in which the write current flows. Annealing in a magnetic field has been performed to impart uniaxial magnetic anisotropy. If the yoke 82 has a uniaxial magnetic anisotropy component in the direction of arrow 92 in FIG. 16, that is, the direction orthogonal to the direction in which the write current flows, and the residual magnetization remains in this direction, a certain memory cell When a write current is applied to the bit line BL to store the information “1”, a magnetic field is applied in the direction of “1” to other memory cells on the same bit line BL that store the information “0”, The memory state becomes unstable. Therefore, annealing in a magnetic field is required to impart uniaxial magnetic anisotropy in the direction indicated by arrow 90 in FIG.
[0012]
However, the direction indicated by the arrow 90 is orthogonal to the direction in which the uniaxial magnetic anisotropy is imparted to the TMR element 3 (the direction of the easy axis of magnetization), and it is very difficult to make them compatible. When the yoke 82 is manufactured such that the uniaxial magnetic anisotropy of the TMR element 3 is orthogonal to the uniaxial magnetic anisotropy of the TMR element 3, the yoke 82 of the bit line BL has disturbance of the axis of easy magnetization and the direction of the arrow 92 in FIG. In this case, there is a problem that residual magnetization occurs, the storage state becomes unstable, and recording bits of other memory cells are inverted. The yoke of the write word line is given uniaxial magnetic anisotropy in the same direction as the TMR element.
[0013]
In a conventional MRAM, the magnetization of the storage layer is reversed by a composite magnetic field of a magnetic field generated by a bit line current and a magnetic field generated by a word line current. As a result, when data is recorded in a certain memory cell, the other memory cells on the same word line as the other memory cells on the same bit line as the above memory cell are in a half selection state. In order to prevent an erroneous write from occurring in a memory cell in a half selection state, it is necessary to greatly suppress the variation in the switching magnetic field for each memory cell.
[0014]
The present invention has been made in view of the above circumstances, and has as its object to provide a magnetic memory capable of preventing erroneous writing at the time of writing and stabilizing the storage state of a memory cell. And
[0015]
[Means for Solving the Problems]
A magnetic memory according to one embodiment of the present invention includes a magnetoresistive element, a cell bit line branched from a bit line and flowing a write current to the magnetoresistive element, and provided on the cell bit line and having the same magnetization as the magnetoresistive element. The memory cell includes a yoke having an easy axis direction and a write selection transistor having one of a source and a drain connected to the cell bit line.
[0016]
Note that having the same easy axis direction as the magnetoresistive element means that at least a part of the yoke has the same easy axis direction as the magnetoresistive element.
[0017]
The cell bit line is provided along a first wiring portion electrically connected to one end of the magnetoresistive element, and a side portion of the magnetoresistive element via an insulating film, and is provided with a write select transistor. Preferably, a second wiring portion connected to one of the source and the drain is provided, and the yoke is provided in the first and second wiring portions.
[0018]
A word line through which a write current flows may be electrically connected to the other end of the magnetoresistive element.
[0019]
Note that a read word line is electrically connected to one end of the magnetoresistive element, and the cell bit line is connected to a first wiring portion branched from the bit line and the magnetoresistive element via an insulating film. A second wiring portion provided along a side portion of the second wiring portion, one end of which is connected to the first wiring portion, one end of which is connected to the other end of the second wiring portion, and the other end of which is a source / drain of the write selection transistor. A third wiring portion having a portion provided substantially in parallel with the first wiring portion with the magnetoresistive effect element interposed therebetween, and the other end of the magnetoresistive effect element is connected to the first wiring portion. And the first and second wiring portions are provided with the yoke, and the third wiring portion has the same easy axis direction of magnetization as the magnetoresistive element. A second yoke is provided Good.
[0020]
The memory cell may include a read select transistor to which one of a source and a drain is connected to the other end of the magnetoresistive element via a lead electrode.
[0021]
Note that a word line through which a write current flows may be formed on the opposite side of the extraction electrode from the magnetoresistive element via an insulating film.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to the drawings.
[0023]
(1st Embodiment)
FIG. 1 shows a configuration of a memory cell of the magnetic memory according to the first embodiment of the present invention, and FIG. 2 shows a configuration of a memory cell array. The memory cell 2 of the magnetic memory according to this embodiment includes a TMR element 3, a cell bit line 6, a yoke 8, a read select transistor 17, and a write select transistor 19.
[0024]
The TMR element 3 includes a lower electrode layer, a base layer, an antiferromagnetic layer, a ferromagnetic layer (reference layer), a tunnel insulating layer, a ferromagnetic layer (memory layer), and an upper electrode. The cell bit line 6 is branched from the shared bit line BL and is electrically connected to the upper electrode of the TMR element 3. A second wiring portion 6b connected to one of the source and the drain of the transistor 19. The first wiring portion 6a has a portion substantially parallel to the shared bit line BL, and is provided so that a current flows in a direction at a predetermined angle with respect to the easy axis direction of the TMR element 3. The second wiring portion 6b is provided along the side of the TMR element 3 via an insulating film (not shown).
[0025]
The yoke 8 is formed on the first wiring portion 6a on the side opposite to the side on which the TMR element 3 is provided. As shown in FIG. 1, the yoke 8 is formed such that the direction of the easy axis has at least partly the same direction as the direction of the easy axis of the TMR element 3.
[0026]
The lower electrode of the TMR element 3 is connected to one of the source and the drain of the read selection transistor 17 via the extraction electrode 14 and the connection plug 15. Note that the lower electrode of the TMR element 3 may also serve as the extraction electrode 14.
[0027]
The other of the read select transistor 17 has the other of the source and the drain connected to the ground power supply via the connection plug 18, and the gate also serves as the read select word line RWL. In the write selection transistor 19, the other of the source and the drain is connected to a common line 20 used when a write current flows, and the gate also serves as a write selection word line WWL.
[0028]
Next, the write operation and the read operation of the magnetic memory according to the present embodiment will be explained with reference to FIG. When the row is the i-th row (i = 1,...), The selected word line WWL is written._iAnd read select word line RWL_i, The column is j-th (j = 1,...) And the shared bit line BL_jIs selected when the memory cell 2 connected to is selected. A case where bit data is written to the selected memory cell 2 will be described. An address for selecting the memory cell 2 having the i-th row and the j-th column is input to the row decoder 41 and the column decoder 45. Then, the row decoder 41 causes the row selection transistor 31_iIs turned on and the write selection word line WWL_iIs selected, and the column selection transistor 35 is_jIs turned on and the shared bit line BL_jIs selected. At this time, the column selection transistor 37_jIs not turned on and is in the off state. Also, the row selection transistor 32_iIs also in the OFF state. Column selection transistor 35_jIs turned on, the shared bit line BL_j, A write current flows. Then, the row selection transistor 31_iIs turned on, the potential Vb is applied to the gate of the write selection transistor 19, and the write selection transistor 19 is turned on. At this time, the column selection transistor 35_jIs also ON, the write current is applied to the shared bit line BL._j, Flows to the cell bit line 6 of the selected memory cell 2. At this time, the shared bit line BL_j, But no write current flows through the cell bit line 6 of another memory cell that is not selected. The current magnetic field induced by the write current flowing through the cell bit line 6 of the selected memory cell 2 is strengthened by the yoke 8, and reverses the magnetization of the storage layer of the TMR element 3 constituting the selected memory cell 2.
[0029]
A method for supplying a write current will be described. In an ordinary MRAM, as shown in FIG. 10, a transistor 72 called a driver is provided at one end of a write wiring, for example, a write bit line BL, and a transistor 74 called a sinker is provided at the other end, and a current flows. A current flows in the write bit line BL in two directions when "0" is recorded and "1" is recorded. Therefore, it is necessary to provide two sets of the driver 72 and the sinker 74. In the present embodiment, a write current flows from the shared bit line BL to the cell bit line 6. FIG. 11 shows a schematic configuration of a write current drive circuit for supplying the write current. In FIG. 11, two sets of drivers 72a and 72b and sinkers 74a and 74b are provided. A current flows in two directions through the write selection transistor 19 of each memory cell. The current direction changes depending on whether the potential of the common line 20 is set to the “L” level (for example, 0 V) or the “H” level (for example, 1.5 V). For example, when writing data “1” to the j-th (= 1,...) -Th memory cell 2 in the column, the column selection signal CSL1_jOf the column selection signal CSL0_jIs set to the “L” level. Then, the driver 72a and the sinker 74b are turned on, and the driver 72b and the sinker 74a are turned off. Therefore, the write current is supplied from the current source Vwb1 to the driver 72a, the shared bit line BL, the cell bit line 6, the write selection transistor 19, and the common line 20. , And sinker 74b. When writing data “0” to the j-th (= 1,...) -Th memory cell 2, the column selection signal CSL0_jOf the column selection signal CSL1_jIs set to the “L” level. Then, the driver 72b and the sinker 74a are turned on, and the driver 72a and the sinker 74b are turned off. Therefore, the write current is supplied from the current source Vwb0 to the driver 72b, the common line 20, the write selection transistor 19, the cell bit line 6, and the shared bit line BL. , And sinker 74a. Therefore, when data “1” and data “0” are written, the direction of the current flowing through the cell bit line 6 is opposite.
[0030]
If the write current is not so large and the voltage difference between both ends of the shared bit line BL is not so large, the write selection transistor 19 of each memory cell 2 needs only one N-channel MOSFET. When the current is large, there is a method of providing a P-channel MOSFET and an N-channel MOSFET in each memory cell. However, in order to realize a high-density memory, one write selection transistor 19 is desirably provided in each cell.
[0031]
Next, returning to FIG. 2, a case where bit data is read from the selected memory cell will be described. An address for selecting the memory cell 2 having the i-th row and the j-th column is input to the row decoder 41 and the column decoder 45. Then, the row decoder 41 causes the row selection transistor 32_iIs turned on and the read selected word line RWL_iIs selected, and the column selection transistor 35 is_j, 37_jIs turned on and the shared bit line BL_jIs selected. At this time, the row selection transistor 31_iIs in the OFF state. Column selection transistor 35_jIs turned on, a current flows through the shared bit line BLj. At this time, the row selection transistor 32_iIs in the ON state, the read selection transistor 17 of the selected memory cell 2 is also in the ON state, and the above-mentioned current is supplied to the shared bit line BL._jFrom the cell bit line 6, the TMR element 3, and the read selection transistor 17. Thereby, the shared bit line BL_jHas a value corresponding to the resistance of the TMR element 3. This potential is applied to the column selection transistor 37._j, And is compared with the reference potential VREF, so that the data stored in the TMR element 3 is read.
[0032]
As described above, in the present embodiment, the cell bit line 6 branched from the shared bit line BL is provided in each memory cell 2 and the direction of the easy axis of the yoke 8 provided on the cell bit line 6 is set to the direction of the TMR element 3. Since the direction of the magnetization is substantially the same as the direction of the easy axis of magnetization, even when the residual magnetization occurs in the yoke 8 or the disturbance of the magnetization occurs in the direction of the easy axis of the yoke 8, the residual magnetization and the disturbance of the magnetization are generated. Generates a magnetic field in the same direction as the information written in the TMR element 3, whereby the storage state of the TMR element 3 is stabilized. Further, since the memory cell 2 is provided with the cell bit line 6 and the write selection transistor 17, when a write current flows through the selected memory cell, the write current does not flow through other memory cells on the same column. . As a result and the stable storage state of the TMR element 3, it is possible to prevent erroneous writing without inverting the recording bit of another memory cell.
[0033]
Since the uniaxial magnetic anisotropy given to the yoke 8 and the uniaxial magnetic anisotropy given to the TMR element 3 are in the same direction, the step of giving the TMR element 3 uniaxial magnetic anisotropy, The step of providing magnetic anisotropy can be performed collectively in the same magnetic field direction. As a result, the manufacturing process is simplified as compared with the related art, and the cost is reduced.
[0034]
In the first embodiment, the cell bit line 6 includes a first wiring portion 6a and a second wiring portion 6b. Not only a current magnetic field caused by a current flowing through the first wiring portion 6a but also a side portion of the TMR element 3 is formed. A current magnetic field caused by a current flowing through the second wiring portion 6b disposed in the TMR element 3 can also be used for writing in the TMR element 3. For this reason, writing can be performed with a smaller current than before.
[0035]
In the first embodiment, since writing is performed by a current magnetic field generated from the cell bit line 6, the direction of the axis of easy magnetization of the TMR element 3 and the direction of the current flowing through the cell bit line 6 are not orthogonal but at a certain inclination. An angle is preferable because the write current can be reduced. This inclination angle is typically selected to be 45 degrees. For example, in the first embodiment, without changing the direction of the cell bit line 6, the direction of the axis of easy magnetization of the TMR element 3 forms a certain angle (for example, 45 degrees) with the direction of the current flowing through the cell bit line 6. , Or by changing the direction of the cell bit line 6 near the TMR element 3 without changing the position of the TMR element 3.
[0036]
(2nd Embodiment)
Next, FIG. 3 shows a configuration of a memory cell of a magnetic memory according to a second embodiment of the present invention, and FIG. 4 shows a configuration of a memory cell array. The memory cell 2 of the magnetic memory according to this embodiment includes a TMR element 2, a cell bit line 6, yokes 8, 9, a read select transistor 17, and a write select transistor 19.
[0037]
The TMR element 3 includes a lower electrode layer, a base layer, an antiferromagnetic layer, a ferromagnetic layer (reference layer), a tunnel insulating layer, a ferromagnetic layer (memory layer), and an upper electrode. The cell bit line 6 is branched from the shared bit line BL and is electrically connected to the upper electrode of the TMR element 3. A second wiring portion 6b connected to one of the source and the drain of the transistor 19. The first wiring portion 6a has a portion substantially parallel to the shared bit line BL, and is provided so that a current flows in a direction orthogonal to the easy axis direction of the TMR element 3. The second wiring portion 6b is provided along the side of the TMR element 3 via an insulating film (not shown).
[0038]
The yoke 8 is formed on the first wiring portion 6a on the side opposite to the side on which the TMR element 3 is provided. The direction of the easy axis of the yoke 8 is formed to be the same as the direction of the easy axis of the TMR element 3 as shown in FIG. The yoke 9 has a write word line WL provided on the lower side of the lead electrode 14 connected to the lower electrode of the TMR element 3 via a not-shown insulating film, except for a surface of the write word line WL facing the lead electrode 14. It is formed so as to cover WL. 3, the yoke 9 is formed so that the direction of the easy axis of magnetization is the same as the direction of the easy axis of magnetization of the TMR element 3, as shown in FIG. The cell bit line 6 is formed so as to be substantially orthogonal to the write word line WL.
[0039]
The lower electrode of the TMR element 3 is connected to one of the source and the drain of the read selection transistor 17 via the extraction electrode 14 and the connection plug 15. Note that the lower electrode of the TMR element 3 may also serve as the extraction electrode 14.
[0040]
The other of the read select transistor 17 has the other of the source and the drain connected to the ground power supply via the connection plug 18, and the gate also serves as the read select word line RWL. In the write selection transistor 19, the other of the source and the drain is connected to a common line 20 used when a write current flows, and the gate also serves as a write selection word line WWL.
[0041]
Next, the write operation and the read operation of the magnetic memory according to the present embodiment will be explained with reference to FIG. When the row is the i-th row (i = 1,...), The selected word line WWL is written._iAnd read select word line RWL_i, The column is j-th (j = 1,...) And the shared bit line BL_jIs selected when the memory cell 2 connected to is selected. A case where bit data is written to the selected memory cell 2 will be described. An address for selecting the memory cell 2 having the i-th row and the j-th column is input to the row decoder 41 and the column decoder 45. Then, the row decoder 41 causes the row selection transistor 31_iAnd row selection transistor 33_iIs turned on and the write selection word line WWL_iAnd write word line WL_iIs selected, and the column selection transistor 35 is_jIs turned on and the shared bit line BL_jIs selected. At this time, the column selection transistor 37_jIs not turned on and is in the off state. Also, the row selection transistor 32_iIs also in the OFF state. Column selection transistor 35_jIs turned on, the shared bit line BL_j, A write current flows. Then, the row selection transistor 31_iIs turned on, the potential Vb is applied to the gate of the write selection transistor 19, and the write selection transistor 19 is turned on. At this time, the column selection transistor 35_jIs also ON, the write current is applied to the shared bit line BL._j, Flows to the cell bit line 6 of the selected memory cell 2. At this time, the shared bit line BL_j, But no write current flows through the cell bit line 6 of another memory cell that is not selected. On the other hand, the row selection transistor 33_iIs also ON, the selected write word line WL_i, A write current flows. The current magnetic field induced by the write current flowing through the cell bit line 6 of the selected memory cell 2 is strengthened by the yoke 8, and the write word line WL_iThe magnetic field induced by the write current flowing through the yoke 9 is strengthened by the yoke 9. The magnetization of the storage layer of the TMR element 3 constituting the selected memory cell 2 is reversed by the enhanced current magnetic field. The writing current is applied in the same manner as in the first embodiment.
[0042]
Also, the case of reading bit data from the selected memory cell is performed in the same manner as in the first embodiment.
[0043]
In the conventional MRAM, the magnetization of the storage layer of the TMR element 3 is generally reversed by a combined magnetic field of a current magnetic field generated by a bit line and a current magnetic field generated by a write word line WL. As a result, when data is recorded in a certain memory cell, a memory cell on the same bit line and a cell on the same word line are in a half selection state. In order to prevent an erroneous write from occurring in the memory cell 2 in the half selection state, it is necessary to greatly suppress the variation in the switching magnetic field for each memory cell.
[0044]
The suppression of the variation of the switching magnetic field will be described with reference to FIG. The assumption in FIG. 12 is that the asteroid curve
H_x ^2/3+ (H_y/ A)^2/3= H_c ^2/3
The parameter a indicates that the asteroid is elongated due to a large demagnetizing field in the hard axis direction. The upper limit level of the expansion is a_U, The lower level is a_L, Its ratio r (= a_U/ A_L). The coercive force H is の of the hysteresis width of the magnetic field_c(> 0), the variation is dH_cAnd Average offset magnetic field H_off  (> 0), variation is dH_offAnd In order to prevent erroneous writing, the following three inequalities must be satisfied. The condition of arrow A1 in FIG. 12 is the following inequality.
[0045]
(Equation 1)

The condition of the arrow A2 in FIG. 12 is the following inequality.
[0046]
(Equation 2)

The condition of the arrow A3 in FIG. 12 becomes the following inequality.
[0047]
(Equation 3)

When the above three inequalities are simultaneously established, the following equation is obtained.
[0048]
(Equation 4)

To prevent erroneous writing, H_off, DH_off, R, dH_c, Must be small enough to satisfy the above equation. For practical use as a memory, it is necessary that there is no erroneous writing within a range of ± 6σ, where σ is a standard deviation. In that case, for example,
H_c= 36 [Oe] and a_U/ A_L≦ 1.7
Assuming
6σ (H_c) ≦ 3.5 [Oe], H_off≦ 3.5 [Oe], 6σ (H_off) ≦ 3.5 [Oe]
Condition must be satisfied.
[0049]
In the manufacture of MRAM, it has been conventionally difficult to suppress the variation of the switching magnetic field with high accuracy under the above conditions over a large number of memory cells. However, in the case of a method in which a transistor provided in each memory cell is used for write selection and a write current flows for each memory cell as in the present embodiment, no matter how much variation may occur in principle, Writing is possible if a sufficiently large magnetic field is applied in the easy axis direction.
[0050]
The reason will be described below. Since a current flows through each cell bit line branched from the bit line, other memory cells in the bit line direction do not enter the half section state. Therefore, the condition of the arrow A2 in FIG. 12 becomes unnecessary, and the restriction is eliminated. As a result, erroneous writing is eliminated if a sufficiently large magnetic field is applied in the x direction (the direction of the easy axis).
[0051]
Therefore, according to the present embodiment, it is possible to obtain a magnetic memory that is extremely resistant to the variation of the switching magnetic field among the memory cells, that is, a magnetic memory in which erroneous writing hardly occurs.
[0052]
As described above, in the present embodiment, the cell bit line 6 branched from the shared bit line BL is provided in each memory cell 2 and the direction of the easy axis of the yoke 8 provided on the cell bit line 6 is set to the direction of the TMR element 3. Since the direction of the magnetization is substantially the same as the direction of the easy axis of magnetization, even when the residual magnetization occurs in the yoke 8 or the disturbance of the magnetization occurs in the direction of the easy axis of the yoke 8, the residual magnetization and the disturbance of the magnetization are generated. Generates a magnetic field in the same direction as the information written in the TMR element 3, whereby the storage state of the TMR element 3 is stabilized. Further, since the memory cell 2 is provided with the cell bit line 6 and the write selection transistor 17, when a write current flows through the selected memory cell, the write current does not flow through other memory cells on the same column. . As a result and the stable storage state of the TMR element 3, it is possible to prevent erroneous writing without inverting the recording bit of another memory cell.
[0053]
Further, since the uniaxial magnetic anisotropy given to the yokes 8 and 9 and the uniaxial magnetic anisotropy given to the TMR element 3 are almost in the same direction, a step of giving the TMR element 3 uniaxial magnetic anisotropy, The steps of imparting uniaxial magnetic anisotropy to 8 and 9 can be performed collectively in the same magnetic field direction. As a result, the manufacturing process is simplified as compared with the related art, and the cost is reduced.
[0054]
In the second embodiment, the cell bit line 6 includes a first wiring portion 6a and a second wiring portion 6b. Not only a current magnetic field caused by a current flowing through the first wiring portion 6a but also a side portion of the TMR element 3 is formed. A current magnetic field caused by a current flowing through the second wiring portion 6b disposed in the TMR element 3 can also be used for writing in the TMR element 3. For this reason, writing can be performed with a smaller current than before.
[0055]
(Third embodiment)
Next, FIG. 5 shows a configuration of a memory cell of a magnetic memory according to a third embodiment of the present invention, and FIG. 6 shows a configuration of a memory cell array. The magnetic memory according to this embodiment has a configuration in which the read selection transistor 17 of the magnetic memory according to the second embodiment is eliminated and the write word line WL also serves as a read word line. Therefore, the lower electrode of the TMR element 3 is electrically connected to the write word line WL. The yoke 8a is provided on the first wiring portion 6a of the cell bit line 6 as in the second embodiment, but the yoke 8b is also provided on the second wiring portion 6b. As shown in FIG. 5, the TMR element 3, the yokes 8a and 8b of the cell bit line 6, and the yoke 9 of the word line WL are formed so that the directions of easy axes of magnetization are substantially the same.
[0056]
Data writing to the selected memory cell 2 of the magnetic memory according to the third embodiment is performed in the same manner as in the second embodiment. The operation of reading data from the selected memory cell 2 of the magnetic memory according to the third embodiment is performed by a method called a cross-point type. When data is read from the memory cell 2 having the i-th row and the j-th column, the row selection transistor 33 is read by the row decoder 41._iIs turned ON, and the column transistor 37 is_jIs turned on. At this time, the row selection transistor 34_iAnd column transistor 35_jIs in the OFF state. Thereby, the shared bit line BL is transferred from the write word line WL through the TMR element 3 and the cell bit line 6._jCurrent flows through At this time, the shared bit line BL_jHas a value corresponding to the data stored in the TMR element 3. This shared bit line BL_jIs compared with reference potential VREF in sense amplifiers 61 and 62, so that data stored in TMR element 3 is read.
[0057]
In the case where reading is performed in a cross-point type without using a read selection transistor as in the third embodiment, it is necessary to provide readability with selectivity. That is, it is necessary not to sense a sneak current from another memory cell other than the selected memory cell. In the first method, as shown in FIG. 6, row select transistors 33 are provided above and below a read word line WL._i, 34_iAnd row decoders 41 and 44 are provided. Read word line WL to the memory cell to be read_iIs selected by the row selection signal RSL (i) and the read current flows, the other word lines WL_m(M ≠ i) is selected by RSL (m) and connected to the lower row decoder 44. As a result, the current that has passed through other memory cells than the selected memory cell is sucked into the lower row decoder 44 and does not flow through the sense amplifiers 61 and 62.
[0058]
The second method will be described with reference to FIG. In this method, the bit line BL_j(J = 1,...) For each sense amplifier 61_jAnd 61 pairs of three sense amplifiers_j-1, 61_j, 61_{j + 1}Is selected by the selector 65, and the selected output is output to the outside via the sense amplifier 62. As a result, current passing through cells other than the selected cell enters another sense amplifier and does not enter the selected sense amplifier.
[0059]
According to these methods, selective read can be performed without using a read select transistor. When each memory cell 2 has a transistor or a diode provided for reading, variations in these characteristics, for example, variations in the ON resistance of the transistor become variations in the read signal, which is a problem. The method using no read selection transistor described here has an advantage that it is not affected by variations in transistors and diodes.
[0060]
As described above, in the third embodiment, the cell bit line 6 is bent in an L-shape and surrounds the periphery of the TMR element 3, and is combined with the effects of the yokes 8a and 8b covering the periphery of the cell bit line 6. Therefore, a large magnetic field can be generated in the TMR element 3. In particular, in this cell structure, the write word line WL is closest to the TMR element 3, so that the TMR element 3 can generate the strongest magnetic field. A magnetic field is strengthened by providing a yoke 9 having a U-shaped cross section in the write word line WL. Therefore, the current required for writing can be reduced. Further, as shown in FIG. 5, the yokes 8a and 8b of the cell bit line 6, the yokes 9 of the word lines WL, and the easy magnetization axis of the TMR element 3 are formed in the same direction. Becomes stable. Further, since the storage state of the TMR element 3 is stable and the cell bit line 6 and the write selection transistor 19 are provided for each memory cell, the recording bits of the memory cells other than the selected memory cell are inverted. Can be prevented. As a result and the stable storage state of the TMR element 3, it is possible to prevent erroneous writing without inverting the recording bit of another memory cell.
[0061]
Further, since the directions of easy axes of magnetization of the yokes 8a and 8b and the TMR element 3 are substantially coincident with each other, it is possible to collectively perform the process of imparting uniaxial magnetic anisotropy to the yokes 8a and 8b and the TMR element 3. The manufacturing process is simplified, and the manufacturing cost can be reduced.
[0062]
(Fourth embodiment)
Next, FIG. 7 shows a configuration of a memory cell of a magnetic memory according to a fourth embodiment of the present invention. In the magnetic memory according to the fourth embodiment, the write / read word line WL of the magnetic memory of the third embodiment shown in FIG. 5 is replaced with a read-only word line RWL, and the cell bit line 6 is connected to the first wiring portion 6a. In addition to the second wiring portion 6b, a third wiring portion 6c is provided below the read word line RWL via an insulating film (not shown). The first to third wiring portions 6a, 6b, 6c are provided with yokes 8a, 8b, 8c, respectively. These yokes 8a, 8b, 8c are formed such that the direction of the easy axis of magnetization substantially coincides with the direction of the easy axis of the TMR element 3.
[0063]
The read operation of the magnetic memory according to the fourth embodiment is performed in the same manner as the magnetic memory according to the third embodiment. However, the write operation is performed by the current magnetic field from the cell bit line 6, as in the case of the first embodiment. Therefore, as in the case of the first embodiment, in order to reduce the write current, the first and third wiring portions 6a and 6c of the cell bit line 6 are set at a predetermined angle (with respect to the easy axis direction of the TMR element 3). For example, it is desirable to form them at 45 degrees.
[0064]
According to the fourth embodiment, the cell bit line 6 is provided with the yokes 8a, 8b and 8c whose easy axis directions substantially coincide with the easy axis direction of the TMR element 3, and also selects and writes data into each memory cell. Since the transistor is provided, the storage state of the TMR element 3 becomes stable, and the recording bits of memory cells other than the selected memory cell can be prevented from being inverted.
[0065]
The cell bit line 6 is formed so that the first to third wiring portions 6a, 6b, 6c surround the TMR element 3, and the first to third wiring portions 6a, 6b, 6c have a yoke 8a. , 8b and 8c are provided, so that a large magnetic field can be generated with a small write current.
[0066]
In addition, since the directions of the axes of easy magnetization of the yokes 8a, 8b, 8c and the TMR element 3 are substantially the same, the step of imparting uniaxial magnetic anisotropy to the yokes 8a, 8b, 8c and the TMR element 3 is performed collectively. It is possible to simplify the manufacturing process and reduce the manufacturing cost.
[0067]
In the fourth embodiment, the word line RWL is read-only, so that the word line RWL can be made thinner than the word line WL for both writing and reading in the third embodiment, and a yoke that covers the word line RWL. Becomes unnecessary.
[0068]
In the fourth embodiment, the TMR element 3 is provided so as to be electrically connected to the first wiring portion 6a. However, the TMR element 3 is not connected to the first wiring portion 6a, and is electrically connected to the third wiring portion 6c. It may be provided so as to be connected to each other.
[0069]
(Fifth embodiment)
In the magnetic memory according to the first and second embodiments, two transistors 17 and 19 are required for one TMR element 3, and accordingly, the required area of each memory cell 2 is increased, and a memory arranged at high density is required. There are drawbacks that are difficult to make. However, there is an advantage that read selectivity can be properly taken.
[0070]
On the other hand, the magnetic memories according to the third and fourth embodiments have an advantage that the required area of the memory cell 2 is not so large because the read selection transistor 17 is not used. However, since reading is performed by a method called a cross-point type, there is a drawback that there is a sneak current and reading selectivity cannot be sufficiently obtained.
[0071]
A magnetic memory having both of these advantages will be described as a fifth embodiment of the present invention. FIG. 8 shows a memory cell array of the magnetic memory according to the fifth embodiment. As shown in FIG. 8, in the magnetic memory of the present embodiment, one write select transistor 19 is provided for one TMR element 3, but one read select transistor is provided for two to 16 TMR elements 3. Only one is provided. As a result, it is possible to produce a memory arranged at high density while ensuring the read selectivity to some extent. In FIG. 8, one read selection transistor 17 is arranged for four TMR elements 3. At the time of reading, four TMR elements 3 are simultaneously selected.₁~ 60₄, And can be read independently without being affected by the sneak current.
[0072]
(Sixth embodiment)
Next, a method for manufacturing the magnetic memory according to the sixth embodiment of the present invention will be described. The manufacturing method according to the sixth embodiment is for manufacturing the magnetic memory according to the fourth embodiment shown in FIG. 7, and will be described below with reference to FIG.
[0073]
First, a p-type silicon substrate is prepared. Next, an N-channel MOSFET is formed as the write selection transistor 19 by a normal CMOS process. At this time, the gate electrode is formed so as to function as the write selection word line WWL. The electrode 7 is formed on the drain and the source, and the common line 20 is wired.
[0074]
Next, an insulating layer (not shown) is formed. After that, the third wiring portion 6c is formed. The material used for the third wiring portion 6c may be Al, Al-Cu, Cu, Ag, or the like. Here, Cu formed by a damascene method is used. The third wiring portion 6c is a wiring covered with a yoke 8c made of NiFe which is a ferromagnetic material. In the yoke 8c, TiN is inserted outside NiFe as a barrier metal, and CoFe is inserted between NiFe and Cu.
[0075]
Next, an insulating film (not shown) is formed, a read word line RWL is formed thereon, and an insulating film (not shown) is further covered. The insulating film is flattened so that the read word line RWL is exposed. Next, the TMR laminated film 3 is deposited. The TMR laminated film 3 has a lower wiring connection layer made of Ta with a thickness of 20 nm, a buffer layer made of Ru with a thickness of 5 nm, an antiferromagnetic layer made of IrMn with a thickness of 6 nm, and a thickness of 2 nm on the word line WL. Co₉₀Fe₁₀Pinned layer made of Al, 1 nm thick Al₂O₃Barrier layer made of Ni, 3 nm thick Ni₇₉Fe₂₁, A surface protection layer made of Cu with a thickness of 2 nm, an etching stop layer / surface protection layer made of Ru with a thickness of 20 nm, and an upper connection layer made of Ta.
[0076]
Next, the TMR laminated film 3 is etched into a predetermined shape using TiN or Ta as a hard mask, for example, 0.24 × 0.48 μm²And the TMR element 3 is formed. After that, an interlayer insulating film (not shown) is deposited. Next to the TMR element 3, a rectangular parallelepiped via hole for forming a vertical cell bit line 6b is formed in the interlayer insulating film. Three of the four vertical surfaces forming the via holes are covered with a ferromagnetic material, NiFe. This serves as a yoke 8b for the cell bit line 6b in the vertical direction. TiN is inserted outside the yoke 8b made of NiFe as a barrier metal. Subsequently, the via hole is filled with Cu using a damascene method. CoFe is inserted between the NiFe and the Cu layer.
[0077]
Next, the above-mentioned interlayer insulating film is etched so as to make contact with the upper connection layer of the TMR element 3. A metal film made of Cu for forming the common bit line BL and the cell bit line 6a is deposited so as to be connected to the upper connection layer of the TMR element 3 and to be connected to the vertical cell bit line 6b. Subsequently, the metal film made of Cu is etched so as to form the shared bit line BL and the cell bit line. In a plan view, the shared bit line BL is arranged between the TMR elements 3, and the cell bit line 6 branched therefrom is arranged so as to pass right above each TMR element 3.
[0078]
Next, the uppermost layer and side surfaces of the cell bit line 6a are covered with a NiFe film, which is a ferromagnetic material, to form a wiring on which a yoke 8a is formed. Note that a CoFe film is inserted as a barrier metal between the yoke 8a made of NiFe and the cell bit line 6a. Further, as the barrier metal, Ta, TiN, TaN, W, WN, or the like can be used instead of CoFe. Note that a barrier metal made of TiN may be formed on the yoke 8a.
[0079]
After forming the yoke 8a, a protective layer (not shown) is deposited. Subsequently, annealing is performed in a magnetic field to give the TMR element 3 and the bit line yokes 8a, 8b, 8c collectively uniaxial magnetic anisotropy in the same direction. The direction of the magnetic field is the direction shown in FIG. 7, and the annealing condition is, for example, at 285 ° C. for 1 hour in a magnetic field of 6.5 kOe. Immediately after annealing in this magnetic field, the magnetization direction of the magnetization free layer and the magnetic field applied to the magnetization free layer from the residual magnetization of the yoke are antiparallel. That is, the magnetization of the magnetization free layer is in an unstable state. Therefore, before shipment as a memory, it is desirable to initialize the state to “0” by flowing a current to the write wiring. By this step, the magnetization of the magnetization free layer and the magnetic field applied to the magnetization free layer from the residual magnetization of the yoke become parallel.
[0080]
The TMR element 3 has a tunnel barrier layer as an indispensable element. This is an insulating layer as thin as 1 to 2 nm and is vulnerable to electrostatic discharge breakdown. In a conventional manufacturing process of a magnetic memory, typically, when dry etching, for example, reactive ion etching (RIE) an interlayer insulating film to expose an upper connection layer of the TMR element 3, an arrow shown in FIG. As shown, the electric charge accumulated on the surface is discharged through the TMR element 3, and there is a problem that the tunnel barrier layer is destroyed by electrostatic discharge. This is because there is a current path from the TMR element 3 to the substrate through the read selection transistor 17 or the word line. However, in the memory cell structure of the magnetic memory according to the first to sixth embodiments, as shown in FIG. 13, for each TMR element 3, a cell bit line 6b passes beside the TMR element 3 toward the substrate. The resistance of the cell bit line 6b is lower than that of the TMR element 3. Therefore, the charges accumulated on the surface are discharged through the cell bit line 6b without passing through the TMR element 3. As a result, destruction of the tunnel barrier layer during the manufacturing process hardly occurs.
[0081]
Note that a TMR element having a structure other than that described in the above embodiment may be used. For example, the TMR element having this structure includes a lower wiring connection layer made of Ta with a thickness of 5 nm, a seed layer made of NiFeCr with a thickness of 5 nm, an antiferromagnetic layer made of PtMn with a thickness of 12 nm, and a film on the word line WL. 2 nm thick Co₉₀Fe₁₀Pinned layer made of Ru, an intermediate layer made of Ru with a thickness of 0.8 nm, and Co with a thickness of 2 nm₉₀Fe₁₀Pinned layer made of Al, 1 nm thick Al₂O₃Barrier layer made of Ni, 3 nm thick Ni₈₁Fe₁₉, A protection layer made of Ta having a thickness of 10 nm, and an upper wiring connection layer made of Al. This structure is a case where an exchange coupling film, that is, a synthetic antiferromagnetic layer is used as the magnetization fixed layer.
[0082]
【The invention's effect】
As described above, according to the present invention, erroneous writing can be prevented at the time of writing, and the storage state of the memory cell can be stabilized.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a configuration of a memory cell of a magnetic memory according to a first embodiment of the present invention.
FIG. 2 is a wiring diagram showing a memory cell array of the magnetic memory according to the first embodiment.
FIG. 3 is a sectional view showing a configuration of a memory cell of a magnetic memory according to a second embodiment;
FIG. 4 is a wiring diagram showing a memory cell array of the magnetic memory according to the second embodiment.
FIG. 5 is a sectional view showing the configuration of a memory cell of a magnetic memory according to a third embodiment;
FIG. 6 is a wiring diagram showing a memory cell array of a magnetic memory according to a third embodiment.
FIG. 7 is a sectional view showing a configuration of a memory cell of a magnetic memory according to a fourth embodiment;
FIG. 8 is a wiring diagram showing a memory cell array of a magnetic memory according to a fifth embodiment of the present invention.
FIG. 9 is a diagram illustrating another method for preventing a sneak current from a memory cell other than a selected memory cell from being sensed in the third embodiment.
FIG. 10 is a diagram illustrating how a write current flows.
FIG. 11 is a diagram illustrating how a write current flows.
FIG. 12 illustrates that erroneous writing does not occur.
FIG. 13 is a diagram illustrating that it is possible to prevent electrostatic breakdown from occurring in a TMR element during a manufacturing process.
FIG. 14 is a view for explaining that electrostatic breakdown occurs in a TMR element during a manufacturing process.
FIG. 15 is a diagram showing write wiring of a conventional magnetic memory.
FIG. 16 is a diagram illustrating a problem of a conventional magnetic memory.
[Explanation of symbols]
2 memory cells
3 TMR element
6 cell bit line
6a first wiring section
6b Second wiring section
7 Connection plug
8 York
8a York
8b York
9 York
14 Leader electrode
15 Connection plug
17 Read select transistor
18 Connection plug
19 Write selection transistor
20 common wire
BL shared bit line
WL write word line
RWL read select word line
WWL write select word line

Claims (6)

A magnetoresistive element, a cell bit line branched from a bit line and flowing a write current to the magnetoresistive element, a yoke provided on the cell bit line and having the same easy axis direction as the magnetoresistive element, and a cell bit line. A magnetic memory, comprising: memory cells each having a write selection transistor connected to one of a source and a drain to a line. The cell bit line is provided along a first wiring portion electrically connected to one end of the magnetoresistive element and a side portion of the magnetoresistive effect element via an insulating film. 2. The magnetic memory according to claim 1, further comprising a second wiring portion connected to one of the drains, wherein the yoke is provided in the first and second wiring portions. 3. The magnetic memory according to claim 2, wherein a word line through which a write current flows is electrically connected to the other end of the magnetoresistive element. A word line for reading is electrically connected to one end of the magnetoresistive element, and the cell bit line is connected to a first wiring portion branched from the bit line and a side of the magnetoresistive element via an insulating film. A second wiring portion provided along the portion and having one end connected to the first wiring portion; one end connected to the other end of the second wiring portion; and the other end being one of a source and a drain of the write selection transistor. A third wiring portion having a portion provided substantially in parallel with the first wiring portion with the magnetoresistive effect element interposed therebetween, and the other end of the magnetoresistive effect device is connected to the first wiring portion or A second wiring portion electrically connected to one of the third wiring portions, the first and second wiring portions provided with the yoke, and the third wiring portion having a second direction having the same easy axis of magnetization as the magnetoresistive element; That a yoke is provided The magnetic memory of claim 1 wherein symptoms. 3. The magnetic memory according to claim 2, wherein the memory cell includes a read select transistor having one of a source and a drain connected to the other end of the magnetoresistive element via a lead electrode. 6. The magnetic memory according to claim 5, wherein a word line through which a write current flows is formed on an opposite side of the extraction electrode from the magnetoresistive element via an insulating film.

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