JP2013085008A - Arithmetic circuit having resistance adjustment function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic circuit having a resistance adjustment function with a MOS switch capable of reducing an influence of a parasitic capacitance on a MOS switch with an extremely simple method with a smallest area.SOLUTION: Resistances 31-33 and 61, several times as large as the resistances 11-13 to be adjusted, are provided to the gate and the back gate of MOS switches 21-23. 0 is generated at a frequency almost the same pole where a parasitic capacitance is generated, thereby the influence of the parasitic capacitance can be prevented. The resistance does not require characteristics such as absolute variation, temperature characteristic, relative variation and noises. A resistance, which has the highest sheet resistance in the used processes, may be formed in a small width resulted in little area increase. Since the resistance can be reduced in size easier than the capacitance, this art is applicable to a future miniaturization process.

Description

  The present invention relates to an arithmetic circuit having a resistance adjustment function using a MOS switch.

  Conventionally, a method of switching the gain of an operational amplifier by adjusting an input resistance or a feedback resistance has been performed in various technical fields that perform signal processing. As shown in Patent Document 1, a means of configuring a feedback resistor of an operational amplifier by arranging a plurality of resistors in series, inclining the resistance value, and providing a switch in parallel with each resistor to adjust the resistance value is One of the typical ones.

  Conventionally, the switch is mechanically opened and closed by discrete components, but with the development of integrated circuits, MOS has been used for the switch. Also, with the recent development of integrated technology, a process capable of incorporating a memory has been developed, and it has become possible to control the memory with a digital circuit and adjust the resistance value. Therefore, it is considered that the resistance adjustment by the MOS switch will be used in more technical fields in the future.

JP 58-29209 A

  However, if the switch is composed of a MOS, a pole is generated due to the parasitic capacitance of the MOS, the phase changes in a higher frequency band than when there is no switch, and there is no phase margin and oscillation tends to occur. Conventionally, as a countermeasure, a phase compensation capacitor is added or newly provided inside the operational amplifier to create a pole at a low frequency so that the influence of the parasitic capacitance is invisible. This is shown in FIG.

  However, this method has a problem that the frequency characteristic of the operational amplifier deteriorates and the operation speed decreases. Another problem is that the circuit area increases due to the phase compensation capacitance. This can become a serious problem as the process becomes finer. This is because it is difficult to miniaturize the capacity.

  Therefore, the present invention solves the above-described conventional problems, and provides an arithmetic circuit that minimizes the increase in area and suppresses the influence of parasitic capacitance of a MOS switch by a very simple method. Objective.

  According to one aspect of the present invention, the arithmetic circuit includes an operational amplifier and at least one first resistor for determining a gain, and includes at least one MOS switch for adjusting the resistance value. The switch has a second resistor at the gate and a third resistor at the back gate. However, the second resistor and the third resistor are not necessarily provided, and either one may be provided. The larger the second and third resistances are, the more effective the effect is.

  Such a configuration makes it difficult to see the parasitic capacitance of the MOS switch, and has an effect of suppressing the influence.

  In addition, if it supplements about "the operational circuit having at least one first resistor for determining the operational amplifier and the gain", if the operational amplifier and the resistor are used, the inverting amplifier, the IV converter, the differential An amplifier may be used. Moreover, the case where the input resistance and the feedback resistance are divided and configured by a plurality of resistors is also included.

  In addition, to supplement “having at least one MOS switch for adjusting the resistance value”, even if there are a plurality of resistors, it is not necessary to attach switches to all of them, and at least one resistor may be used.

  The effects obtained by typical ones of the inventions disclosed in the present invention will be briefly described as follows.

  By providing the gate with a sufficiently large resistance, there is an effect of suppressing the influence of the parasitic capacitance by generating a zero point at substantially the same frequency as the pole generated by the parasitic capacitance between the gate source and the gate drain and between the back gate gate. In addition, by providing a sufficiently large resistance to the back gate, a zero point is generated at almost the same frequency as the pole caused by the parasitic capacitance between the back gate source, back gate drain, and back gate gate, and the effect of parasitic capacitance is reduced. There is an effect to suppress. Due to the above effects, there is no change in the frequency characteristics of the operational amplifier without the MOS switch. Therefore, there is no need to add a phase compensation capacitor, and there is no increase in area due to the capacitor.

  In addition, it is desirable that the resistance of the gate and the back gate be large, but the resistance is not required to have characteristics such as variation in absolute value, temperature characteristics, relative accuracy, and low noise. Therefore, a sheet having a high sheet resistance, which generally has poor characteristics, can be made with a narrow width, so that the increase in area can be reduced. In addition, since the resistance can be easily miniaturized unlike the capacitance, the increase rate of the area hardly changes even in the fine process, which matches the future trend.

FIG. 5 is a diagram illustrating an example of an arithmetic circuit according to the first embodiment. The figure which shows the equivalent circuit of the arithmetic circuit which does not apply this patent The figure which shows the equivalent circuit of the arithmetic circuit which does not apply this patent The figure which shows the equivalent circuit of the arithmetic circuit which does not apply this patent The figure which shows the equivalent circuit of the arithmetic circuit shown in FIG. The figure which shows the modification of the arithmetic circuit shown in FIG. FIG. 9 is a diagram illustrating an example of an arithmetic circuit according to the second embodiment. The figure which shows the equivalent circuit of the arithmetic circuit shown in FIG. FIG. 10 is a diagram illustrating an example of an arithmetic circuit according to the third embodiment. The figure which shows the equivalent circuit of the arithmetic circuit shown in FIG. Diagram showing the problems of the prior art

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a diagram illustrating an example of an arithmetic circuit according to the first embodiment. The arithmetic circuit in the figure is an inverting amplifier using the operational amplifier 1. The reference voltage is connected to the non-inverting input terminal N1 of 1, and the input resistors 14 are connected between the inverting input terminal N2 and the input terminal N3, and the feedback resistors 11, 12, 13 are connected between the N2 and the output terminal N4. Connect in series. Three PMOS switches 21, 22, and 23 are connected in parallel to the resistors 11 to 13, respectively. Gate resistors 31, 32, and 33 are connected to the gates of the respective switches. Terminals on the opposite side of the gates 31 to 33 are connected to a low voltage and a high voltage (for example, the low voltage is GND and the high voltage is VCC), the switch is turned on and off, and the value of the feedback resistor is adjusted. Switching between the low voltage and the high voltage is performed, for example, by controlling an internal memory. The back gate is connected to a suitably high voltage. For example, if the value of the resistor 12 is double that of the resistor 11 and the value of the resistor 13 is double that of the resistor 12, the total feedback resistance is adjusted to 8 patterns at equal intervals from 0 to 7 times that of the resistor 11. Can do.

[Equivalent circuit of conventional configuration]
First, consider an equivalent circuit of an arithmetic circuit having a conventional configuration and no resistance at the gate. The switch gate is directly connected to a low or high voltage to turn the switch on and off. Assume that the switches 21 and 23 are off and the switch 22 is on. At this time, feedback is applied via the resistor 11, the switch 22, and the resistor 13 as indicated by a dotted arrow in FIG.

  FIG. 2a shows an equivalent circuit considering all the components and parasitic capacitance. When viewed from the output terminal N4, first, there is the output impedance 15 of the operational amplifier 1, and then the resistor 11 is visible. The tip is the source terminal N5 of the switch 22, and the capacitor 41 is connected to the back gate terminal N7, and the capacitor 42 is connected to the gate terminal N8. Between the source terminal N5 and the drain terminal N6, the capacitor 43 and the on-resistance 16 of the switch 22 appear in parallel. Further, a capacitor 44 is provided between the drain terminal N6 and the back gate terminal N7, a capacitor 45 is provided between the drain terminal N6 and the gate terminal N8, and a capacitor 46 is provided between the gate terminal N8 and the back gate terminal N7. The tip of the drain terminal N6 is connected to the inverting input terminal N2 through the resistor 13, and an input resistor 14 is provided between the N2 and the input terminal N3.

  In a configuration such as this arithmetic circuit, the on-resistance of the switch is generally set to a value sufficiently smaller than the resistance to be adjusted. This is because if the on-resistance is large, the linearity at the time of resistance switching is lost. In other words, it can be assumed that the on-resistance 16 of the switch 22 is sufficiently smaller than the resistance 11. Under the assumption, since the source terminal N5 and the drain terminal N6 are common, the capacitance 43 between N5 and N6 can be ignored, and the parasitic capacitance considered separately for the source terminal and the drain terminal can be collected. . In addition, since there is no capacitance before the resistor 13, the frequency characteristics are not affected. Considering these, the equivalent circuit can be simplified as shown in FIG.

  As seen from the output terminal N4, the output impedance 15 and the resistor 11 are first visible as in FIG. 2a. The source / drain terminal N9 ahead is a terminal where the source terminal N5 and the drain terminal N6 are common. A capacitor 47 is provided between N9 and the gate terminal N8, and a capacitor 48 is provided between the back gate terminal N7. The capacitance value 47 is the sum of the source-gate capacitance 42 and the drain-gate capacitance 45, and the capacitance value 48 is the sum of the source back-gate capacitance 41 and the drain back-gate capacitance 44. As in FIG. 2a, a capacitor 46 is provided between the gate terminal N8 and the back gate terminal N7.

  Next, the transfer function from the output terminal to the inverting input terminal of the circuit of FIG. The value of the output impedance 15 is Rout, the value of the resistor 11 is R, the value of the capacitor 47 is Cg, the value of the capacitor 48 is Cb, and the value of the capacitor 46 is Cgb.

  In order to clarify the effect of the present invention, the transfer function G11 (s) of the low-pass filter mainly due to the capacitor 47 attached to the gate and the transfer function G12 (s) of the low-pass filter mainly caused by the capacitor 48 attached to the back gate. Think of it divided into two. However, since the capacity 46 influences which path is considered, it cannot be simply divided. Therefore, as shown in FIG. 2c, the back gate terminal N7 is opened when G11 (s) is obtained, and the gate terminal N8 is opened when G12 (s) is obtained. In this way, it can be considered as a simple RC low-pass filter.

  In the former case, since the capacitances 46 and 48 are connected in parallel with the capacitance 47, the value Cg ′ of the combined capacitance 51 is Cg ′ = Cg + (Cb * Cgb) / (Cb + Cgb). Become. Since the resistance is Rout + R, G11 (s) = 1 / (1 + sCg ′ (Rout + R)).

  In the latter case, since the capacitances 46 and 47 are connected in series with the capacitance 48, the value Cb ′ of the combined capacitance 52 is Cb ′ = Cb + (Cg * Cgb) / (Cg + Cgb). , G12 (s) = 1 / (1 + sCb ′ (Rout + R)).

  When Cgb is sufficiently smaller than Cg and Cb, Cg′≈Cg and Cb′≈Cb.

[Equivalent Circuit of Embodiment 1]
FIG. 3 is an equivalent circuit proposed in the present invention in the case where there are resistors 31 to 33 at the gate. A configuration in which a resistor 32 is inserted between the gate terminal N8 and GND of the MOS switch of FIG. 2b is the same as that of FIG. 2b. The value of the resistor 32 is Rg.

  Here again, the transfer functions of Cg ′ and Cb ′ are considered separately. The transfer function G21 (s) of the filter formed by Cg ′ is G21 (s) = (Rg + 1 / sCg ′) / (R + Rout + Rg + 1 / sCg ′) = (1 + sCg′Rg) / (1 + sCg ′ (R + Rout + Rg)) At this time, if R + Rout << Rg, G21 (s) ≈1, and it can be seen that the effect of Cg ′ can be canceled when Rg is sufficiently large. As is clear from the equation of the transfer function, there is a zero that makes the pole at frequency fp = 2 * π * Cg '(R + Rout + Rg) to frequency fz = 2 * π * Cg' * Rg. This is to counteract.

  On the other hand, the transfer function G22 (s) of the filter formed by Cb ′ is G22 (s) = G12 (s) = 1 / (1 + sCb ′ (Rout + R)), similarly to the case without the resistor 32. The influence of the parasitic capacitance of the back gate remains. In order to eliminate the influence of the pole due to Cb ', it is desirable to short-circuit the source terminal and the back gate terminal of the MOS switch as shown in FIG. By doing so, the source-back gate capacitance and the drain back-gate capacitance can be ignored. Furthermore, since the gate-back gate capacitance is attached to the same location as the gate-source capacitance, it can be canceled by the gate resistors 31 to 33, and as a result, the parasitic capacitance attached to all the back gates can be ignored. However, in this method, it is necessary to divide all the MOS back gates, and there is a problem that the area becomes large when integrating. Embodiment 2 solves the problem.

(Embodiment 2)
FIG. 5 is a diagram illustrating an example of an arithmetic circuit according to the second embodiment. The back gate resistor 61 is added to the configuration of the first embodiment, and other configurations are the same as those of the first embodiment. As shown in the figure, it is desirable that the back gates of a plurality of MOSs are all short-circuited and then connected to a fixed potential with a single resistor. By doing so, all the back gates can be created in common, so that the area can be made small. However, it should be noted that the leakage current of all the MOS switches flows through one resistor, so that the potential of the back gate is likely to shift when the leakage current increases, such as at high temperatures. Note that a resistor may be provided for each MOS back gate, like the gate resistor of the first embodiment. However, since it is necessary to create all MOS back gates separately, the area becomes large.

[Equivalent Circuit of Embodiment 2]
As before, FIG. 6 shows an equivalent circuit of FIG. 5 as seen from the output of the operational amplifier when only the switch 22 is turned on. In addition to the configuration of FIG. 3, a resistor 61 is added to the back gate, and other configurations are the same as those of FIG. The value of the resistor 61 is Rb. As in the case of the first embodiment, transfer functions based on Cg ′ and Cb ′ are considered separately. The transfer function G31 (s) of the filter formed by Cg ′ is the same as in the first embodiment.
G31 (s) = G21 (s) = (1 + sCg'Rg) / (1 + sCg '(R + ROUT + Rg)) ≒ 1 (when Rg >> R + ROUT)
It is. On the other hand, the transfer function of the filter formed by Cb ′ is
G32 (s) = (1 + sCb′Rb) / (1 + sCb ′ (R + ROUT + Rb)) ≈1 (when Rb >> R + ROUT).
From the above, if Rg >> R + ROUT and Rb >> R + ROUT, the influence of most of the parasitic capacitance of the MOS switch can be canceled.

(Embodiment 3)
For example, when the potential difference between the back gate source and the back gate drain is small, the junction capacitance sometimes becomes larger than the parasitic capacitance of the gate terminal. As described above, when the junction capacitance of the back gate is dominant, a resistor may be added only to the back gate. That is, the gate resistances 31 to 33 are eliminated from FIG. The configuration is shown in FIG.

[Equivalent Circuit of Embodiment 3]
As before, FIG. 8 shows an equivalent circuit of FIG. 7 as seen from the output of the operational amplifier when only the switch 22 is turned on. This also has a configuration in which the gate resistor 32 is eliminated from FIG. As before, the influence of Cg ′ and Cb ′ will be considered separately.

The transfer function G41 (s) of the filter by Cg ′ is G41 (s) = G11 (s) = 1 / (1 + sCg ′ (Rout + R))
The transfer function G42 (s) of the filter by Cb ′ is
G42 (s) = G32 (s) = (1 + sCb'Rb) / (1 + sCb '(R + Rout + Rb)) ≒ 1 (when Rb >> R + Rout)
If Rb is sufficiently larger than R + Rout, the influence of Cb ′ can be canceled.

(Modification of the embodiment)
In all the embodiments, the inverting amplifier is described as an example. However, if a resistor and an operational amplifier are used, the inverting amplifier is not particular. A non-inverting amplifier, an IV conversion amplifier, a summing amplifier, a differential amplifier, or the like may be used. Further, the resistor to be adjusted is not a feedback resistor but may be another resistor such as an input resistor. The resistors may not be arranged in series, but may be in parallel or a combination of series and parallel. Further, the resistor and the MOS switch may be in series instead of in parallel. Further, it is not necessary to provide a resistor at the gate or back gate of all the MOS switches used. Further, the switch is not a PMOS, but may be an NMOS or an analog switch. Also, the number of switches may be two or less or four or more.

  As described above, the present circuit configuration in which a high resistance is inserted in the MOS gate and the back gate to suppress the influence of the parasitic capacitance is very simple and the increase in area is small. In addition, there is almost no concern in this circuit due to the insertion of resistors. Therefore, the circuit configuration is suitable in various fields using an integrated circuit.

1 operational amplifier 11 feedback resistor 1
12 Feedback resistor 2
13 Feedback resistor 3
14 Input resistance 15 Output impedance of operational amplifier 16 On-resistance of PMOS switch 22 21 PMOS switch 1
22 PMOS switch 2
23 PMOS switch 3
31 Resistance 1 at the gate
32 Resistance 2 at the gate
33 Resistance 3 at the gate
34 Resistance provided at the back gate 41 Junction capacitance between source back gates 42 Parasitic capacitance between source gates 43 Parasitic capacitance between source drains 44 Junction capacitance between drain back gates 45 Parasitic capacitance between drain gates 46 Parasitic capacitance between gate back gates 47 Parallel capacitance 48 Parallel capacitance of 42 and 44 51 Series capacitance of 46 and 48 and 47 Parallel capacitance 52 Series capacitance of 46 and 47 and 48 parallel capacitance N1 Non-inverting input terminal of operational amplifier 1 N2 Inverting input terminal of operational amplifier 1 N3 input Terminal N4 Output terminal N5 Source terminal of PMOS switch 22 N6 Drain terminal of PMOS switch 22 N7 Back gate terminal of PMOS switch 22 N8 Gate terminal of PMOS switch 22 N9 Source drain terminal of PMOS switch 22 when source drain is shorted

Claims (3)

An operational circuit having an operational amplifier and at least one first resistor for determining gain has at least one MOS switch for adjusting the resistance value, and the gate of the MOS switch has a second resistor. An arithmetic circuit comprising: 2. The arithmetic circuit according to claim 1, wherein the back gate includes a third resistor. An operational circuit having an operational amplifier and at least one first resistor for determining a gain has at least one MOS switch for adjusting the resistance value, and a back gate of the MOS switch has a second gate An arithmetic circuit comprising a resistor.

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