JP2013080842A - Semiconductor wafer, semiconductor wafer inspection device and semiconductor wafer inspection method - Google Patents

Semiconductor wafer, semiconductor wafer inspection device and semiconductor wafer inspection method Download PDF

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JP2013080842A
JP2013080842A JP2011220357A JP2011220357A JP2013080842A JP 2013080842 A JP2013080842 A JP 2013080842A JP 2011220357 A JP2011220357 A JP 2011220357A JP 2011220357 A JP2011220357 A JP 2011220357A JP 2013080842 A JP2013080842 A JP 2013080842A
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semiconductor wafer
electrode
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inspection stage
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JP5942376B2 (en
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Yasuhiro Matsuo
泰弘 松尾
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Mitsubishi Electric Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor wafer, a semiconductor wafer inspection device and a semiconductor wafer inspection method, which can prevent an excessive power from being applied to the semiconductor wafer while maintaining a function as a terminal of a back electrode of the semiconductor wafer in semiconductor wafer inspection.SOLUTION: A semiconductor wafer according to an embodiment comprises: a surface electrode formed on a surface side of the semiconductor wafer on which a plurality of chips are arranged across dicing lines; a plurality of back electrodes formed on a rear face side of the semiconductor wafer across the dicing lines; and a connection pattern on the rear face side of the semiconductor wafer for electrically connecting the plurality of back electrodes across the dicing lines. At least one of the plurality of back electrodes is electrically connected with the surface electrode through a via hole of the semiconductor wafer.

Description

本発明は、例えば高周波デバイスチップの製造に用いられる半導体ウエハ、半導体ウエハ検査装置、及び半導体ウエハの検査方法に関する。   The present invention relates to a semiconductor wafer, a semiconductor wafer inspection apparatus, and a semiconductor wafer inspection method used, for example, for manufacturing a high frequency device chip.

特許文献１には、プローブカードを用いて半導体ウエハの特性を検査する技術が開示されている。   Patent Document 1 discloses a technique for inspecting the characteristics of a semiconductor wafer using a probe card.

特開２００６−３４４６６２号公報JP 2006-344661 A

半導体ウエハの検査において、半導体ウエハの裏面電極を検査ステージに吸着させ、裏面電極を端子として用いることがある。その場合、裏面電極と検査ステージの電気的接続を安定させるために、半導体ウエハを検査ステージに強く吸着させなければならない。しかし、半導体ウエハと検査ステージの間に異物などが混入すると、強い吸着力により半導体ウエハに過度の力がかかり半導体ウエハがダメージを受けたり、測定精度が低下したりすることがあった。   In the inspection of a semiconductor wafer, the back electrode of the semiconductor wafer is sometimes attracted to an inspection stage and the back electrode is used as a terminal. In that case, in order to stabilize the electrical connection between the back electrode and the inspection stage, the semiconductor wafer must be strongly adsorbed to the inspection stage. However, if foreign matter or the like is mixed between the semiconductor wafer and the inspection stage, an excessive force is applied to the semiconductor wafer due to a strong adsorption force, and the semiconductor wafer may be damaged or the measurement accuracy may be lowered.

本発明は、上述のような課題を解決するためになされたもので、半導体ウエハの裏面電極の端子としての機能を維持しつつ、半導体ウエハに過度の力がかかることを防止できる半導体ウエハ、半導体ウエハ検査装置、及び半導体ウエハの検査方法を提供することを目的とする。   The present invention has been made in order to solve the above-described problems, and maintains a function as a terminal of a back electrode of a semiconductor wafer while preventing an excessive force from being applied to the semiconductor wafer. It is an object to provide a wafer inspection apparatus and a semiconductor wafer inspection method.

本願の発明に係る半導体ウエハは、ダイシングラインを隔てて複数のチップが並ぶ半導体ウエハの表面側に形成された表面電極と、該半導体ウエハの裏面側に、該ダイシングラインを隔てて形成された複数の裏面電極と、該半導体ウエハの裏面側に、該ダイシングラインを跨いで該複数の裏面電極を電気的に接続する接続パターンと、を備える。そして、該複数の裏面電極のうちの少なくともひとつは、該半導体ウエハのバイアホールを介して該表面電極と電気的に接続されたことを特徴とする。   The semiconductor wafer according to the invention of the present application includes a front surface electrode formed on a front surface side of a semiconductor wafer in which a plurality of chips are arranged across a dicing line, and a plurality of semiconductor wafers formed on the back surface side of the semiconductor wafer with the dicing line therebetween. And a connection pattern for electrically connecting the plurality of back electrodes across the dicing line on the back side of the semiconductor wafer. At least one of the plurality of back electrodes is electrically connected to the surface electrode through a via hole of the semiconductor wafer.

本発明に係る半導体ウエハ検査装置は、半導体ウエハを載置する検査ステージと、該半導体ウエハの外周側の表面電極とコンタクトするように、該検査ステージに取り付けられたプローブ針と、該半導体ウエハの特性を測定するプローブカードを支持するプローブカードホルダーと、を備えたことを特徴とする。   A semiconductor wafer inspection apparatus according to the present invention includes an inspection stage on which a semiconductor wafer is placed, a probe needle attached to the inspection stage so as to be in contact with a surface electrode on the outer peripheral side of the semiconductor wafer, And a probe card holder for supporting a probe card for measuring characteristics.

本発明に係る他の半導体ウエハ検査装置は、半導体ウエハを載置する載置面を有する検査ステージと、該半導体ウエハを吸着する吸気口を該載置面の中央部に有する第１吸着手段と、該半導体ウエハを吸着する吸気口を該載置面の該中央部の外側に有し、該第１吸着手段よりも高い吸着圧で該半導体ウエハを吸着する第２吸着手段と、を備えたことを特徴とする。   Another semiconductor wafer inspection apparatus according to the present invention includes an inspection stage having a mounting surface on which a semiconductor wafer is mounted, and a first suction unit having an intake port for sucking the semiconductor wafer at the center of the mounting surface. And a second suction unit that has an air inlet for sucking the semiconductor wafer outside the central portion of the mounting surface, and sucks the semiconductor wafer with a higher suction pressure than the first suction unit. It is characterized by that.

本発明に係る半導体ウエハの検査方法は、表面電極と、バイアホールを介して該表面電極と電気的に接続された裏面電極を有する半導体ウエハを、検査ステージの載置面に載置する工程と、該検査ステージに取り付けられた第１プローブ針を該表面電極に接続する工程と、該第１プローブ針と該表面電極を接続した状態で、第２プローブ針を有するプローブカードを用いて該半導体ウエハの特性を測定する工程と、を有する。そして、該裏面電極は該半導体ウエハの裏面全体に形成されたことを特徴とする。   A method for inspecting a semiconductor wafer according to the present invention includes a step of placing a semiconductor wafer having a surface electrode and a back electrode electrically connected to the surface electrode through a via hole on a placement surface of an inspection stage. A step of connecting a first probe needle attached to the inspection stage to the surface electrode; and a semiconductor device using a probe card having a second probe needle in a state where the first probe needle and the surface electrode are connected. Measuring the characteristics of the wafer. The back electrode is formed on the entire back surface of the semiconductor wafer.

本発明によれば、半導体ウエハの裏面電極の端子としての機能を維持しつつ、半導体ウエハに過度の力がかかることを防止できる。   ADVANTAGE OF THE INVENTION According to this invention, it can prevent that an excessive force is applied to a semiconductor wafer, maintaining the function as a terminal of the back surface electrode of a semiconductor wafer.

本発明の実施の形態１に係る半導体ウエハの表面を示す図である。It is a figure which shows the surface of the semiconductor wafer which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体ウエハの裏面を示す図である。It is a figure which shows the back surface of the semiconductor wafer which concerns on Embodiment 1 of this invention. 図２のＩＩＩ−ＩＩＩ線における断面図である。It is sectional drawing in the III-III line of FIG. 本発明の実施の形態１に係る半導体ウエハ検査装置を示す図である。It is a figure which shows the semiconductor wafer inspection apparatus which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体ウエハの検査方法を示す図である。It is a figure which shows the inspection method of the semiconductor wafer which concerns on Embodiment 1 of this invention. 第１プローブ針を表面電極に接続することを示す図である。It is a figure which shows connecting a 1st probe needle | hook to a surface electrode. 本発明の実施の形態２に係る半導体ウエハ検査装置を示す図である。It is a figure which shows the semiconductor wafer inspection apparatus which concerns on Embodiment 2 of this invention.

実施の形態１．
図１は、本発明の実施の形態１に係る半導体ウエハの表面を示す図である。半導体ウエハ１０には複数のチップ１２が形成されている。複数のチップ１２は、ダイシングライン１４を隔てて並べられている。半導体ウエハ１０の表面側には表面電極１６ａ、１６ｂ、１６ｃが形成されている。表面電極１６ａ、１６ｂ、１６ｃは、半導体ウエハ１０の外周に沿って複数形成されるものである。表面電極１６ａ、１６ｂ、１６ｃは、半導体ウエハ１０の測定時にグランド端子となるべき部分である。 Embodiment 1 FIG.
FIG. 1 is a view showing the surface of a semiconductor wafer according to Embodiment 1 of the present invention. A plurality of chips 12 are formed on the semiconductor wafer 10. The plurality of chips 12 are arranged with a dicing line 14 therebetween. On the surface side of the semiconductor wafer 10, surface electrodes 16a, 16b, and 16c are formed. A plurality of surface electrodes 16 a, 16 b, and 16 c are formed along the outer periphery of the semiconductor wafer 10. The surface electrodes 16 a, 16 b, and 16 c are portions that should be ground terminals when the semiconductor wafer 10 is measured.

図２は、本発明の実施の形態１に係る半導体ウエハの裏面を示す図である。半導体ウエハ１０の裏面側には複数の裏面電極２０が形成されている。複数の裏面電極２０は、例えばめっきやスパッタによるＡｕで形成されている。複数の裏面電極２０の１つの裏面電極と、隣接する裏面電極との間にはダイシングライン２２が形成されている。ダイシングライン２２はＡｕが形成されずＧａＡｓ基板が露出した部分であって、複数の裏面電極２０を個々の裏面電極に区切るものである。   FIG. 2 is a view showing the back surface of the semiconductor wafer according to the first embodiment of the present invention. A plurality of back surface electrodes 20 are formed on the back surface side of the semiconductor wafer 10. The plurality of back electrodes 20 are formed of Au by plating or sputtering, for example. A dicing line 22 is formed between one back electrode of the plurality of back electrodes 20 and the adjacent back electrode. The dicing line 22 is a portion where Au is not formed and the GaAs substrate is exposed, and divides the plurality of back electrodes 20 into individual back electrodes.

複数の裏面電極２０を一体的に接続するように接続パターン２４が形成されている。具体的に説明する。複数の裏面電極２０のうちの1つの裏面電極２０ｘは、接続パターン２４ａ、２４ｂ、２４ｃ、２４ｄを介して隣接する裏面電極と電気的に接続されている。つまり、接続パターン２４ａ、２４ｂ、２４ｃ、２４ｄは、ダイシングライン２２を跨いで形成され、裏面電極２０ｘと他の裏面電極とを電気的に接続する。同様に全ての裏面電極が接続パターン２４で電気的に接続されている。このように、半導体ウエハ１０の裏面側には、ダイシングライン２２を跨いで複数の裏面電極２０を電気的に接続する接続パターン２４が形成されている。   A connection pattern 24 is formed so as to integrally connect the plurality of back surface electrodes 20. This will be specifically described. One back electrode 20x of the plurality of back electrodes 20 is electrically connected to the adjacent back electrode via connection patterns 24a, 24b, 24c, and 24d. That is, the connection patterns 24a, 24b, 24c, and 24d are formed across the dicing line 22 and electrically connect the back surface electrode 20x and the other back surface electrode. Similarly, all back electrodes are electrically connected by the connection pattern 24. As described above, the connection pattern 24 that electrically connects the plurality of back surface electrodes 20 across the dicing line 22 is formed on the back surface side of the semiconductor wafer 10.

裏面電極２０ａ、２０ｂ、２０ｃには、それぞれバイアホール２６ａ、２６ｂ、２６ｃが形成されている。バイアホール２６ａは、裏面電極２０ａと表面電極１６ａを接続するために形成されている。バイアホール２６ｂは、裏面電極２０ｂと表面電極１６ｂを接続するために形成されている。バイアホール２６ｃは、裏面電極２０ｃと表面電極１６ｃを接続するために形成されている。   Via holes 26a, 26b, and 26c are formed in the back electrodes 20a, 20b, and 20c, respectively. The via hole 26a is formed to connect the back electrode 20a and the front electrode 16a. The via hole 26b is formed to connect the back electrode 20b and the front electrode 16b. The via hole 26c is formed to connect the back electrode 20c and the front electrode 16c.

図３は、図２のＩＩＩ−ＩＩＩ線における断面図である。バイアホール２６ａはＧａＡｓ基板３０を貫くように形成されている。裏面電極２０ａは、バイアホール２６ａの内壁に及ぶように形成されている。裏面電極２０ａはバイアホール２６ａを通って表面電極１６ａと電気的に接続されている。裏面電極２０ａは接続パターン２４により複数の裏面電極２０の全てと接続されているので、表面電極１６ａは複数の裏面電極２０と接続されている。半導体ウエハ１０の表面は適宜に形成された保護膜３２で保護されている。   FIG. 3 is a cross-sectional view taken along line III-III in FIG. The via hole 26 a is formed so as to penetrate the GaAs substrate 30. The back electrode 20a is formed so as to cover the inner wall of the via hole 26a. The back electrode 20a is electrically connected to the front electrode 16a through the via hole 26a. Since the back electrode 20 a is connected to all of the plurality of back electrodes 20 by the connection pattern 24, the front electrode 16 a is connected to the plurality of back electrodes 20. The surface of the semiconductor wafer 10 is protected by a protective film 32 that is appropriately formed.

図４は、本発明の実施の形態１に係る半導体ウエハ検査装置を示す図である。半導体ウエハ検査装置４０は、外箱４２の中にＸ−Ｙステージ４４を備えている。Ｘ−Ｙステージ４４の上には、Ｘ−θ軸を持つ検査ステージ４６が取り付けられている。検査ステージ４６は、半導体ウエハ１０を載置する載置面４６ａを備えている。検査ステージ４６には、載置面４６ａに半導体ウエハ１０を吸着するための吸着手段４８が取り付けられている。吸着手段４８は吸気システムを有する。   FIG. 4 is a diagram showing the semiconductor wafer inspection apparatus according to the first embodiment of the present invention. The semiconductor wafer inspection apparatus 40 includes an XY stage 44 in an outer box 42. An inspection stage 46 having an X-θ axis is mounted on the XY stage 44. The inspection stage 46 includes a placement surface 46a on which the semiconductor wafer 10 is placed. The inspection stage 46 is provided with a suction means 48 for sucking the semiconductor wafer 10 onto the mounting surface 46a. The adsorption means 48 has an intake system.

検査ステージ４６には治具５０が取り付けられている。治具５０には半導体ウエハ１０の外周側に形成された表面電極１６ａ、１６ｂ、１６ｃとコンタクトする第１プローブ針５２が取り付けられている。外箱４２には、半導体ウエハ１０の特性を測定するプローブカードを支持するプローブカードホルダー５４が形成されている。プローブカードホルダー５４には、第２プローブ針５６ａを有するプローブカード５６が取り付けられている。   A jig 50 is attached to the inspection stage 46. A first probe needle 52 that is in contact with the surface electrodes 16 a, 16 b, 16 c formed on the outer peripheral side of the semiconductor wafer 10 is attached to the jig 50. A probe card holder 54 that supports a probe card for measuring the characteristics of the semiconductor wafer 10 is formed in the outer box 42. A probe card 56 having a second probe needle 56 a is attached to the probe card holder 54.

続いて、半導体ウエハの検査方法を説明する。図５は、本発明の実施の形態１に係る半導体ウエハの検査方法を示す図である。まず、外箱４２のカバードア又はウエハローダ部を経由して、半導体ウエハ１０を載置面４６ａに載置する。次いで、第１プローブ針５２を表面電極１６ａ、１６ｂ、１６ｃに接続する。図６は、第１プローブ針を表面電極に接続することを示す図である。図６に示すように、第１プローブ針５２は半導体ウエハ１０の外側から表面電極１６ａ、１６ｂ、１６ｃに伸びている。   Next, a semiconductor wafer inspection method will be described. FIG. 5 is a diagram showing a semiconductor wafer inspection method according to the first embodiment of the present invention. First, the semiconductor wafer 10 is mounted on the mounting surface 46a via the cover door of the outer box 42 or the wafer loader unit. Next, the first probe needle 52 is connected to the surface electrodes 16a, 16b, and 16c. FIG. 6 is a diagram showing that the first probe needle is connected to the surface electrode. As shown in FIG. 6, the first probe needle 52 extends from the outside of the semiconductor wafer 10 to the surface electrodes 16a, 16b, and 16c.

次いで、第１プローブ針５２と表面電極１６ａ、１６ｂ、１６ｃを接続した状態で、プローブカード５６を用いて半導体ウエハ１０の特性を測定する。この測定は、例えば、高周波測定でもよい。   Next, characteristics of the semiconductor wafer 10 are measured using the probe card 56 in a state where the first probe needle 52 and the surface electrodes 16a, 16b, and 16c are connected. This measurement may be, for example, a high frequency measurement.

本発明の実施の形態１に係る半導体ウエハ１０の検査では、第１プローブ針５２を表面電極１６ａ、１６ｂ、１６ｃに接続することで、複数の裏面電極２０をグランド端子として用いることができる。複数の裏面電極２０をグランド端子として用いると、第１プローブ針５２を電気的に安定させることができるので、半導体ウエハ１０を載置面４６ａに強く吸着させる必要はない。そのため吸着手段４８による吸着圧は、半導体ウエハ１０が位置ずれしない程度まで減圧してよい。よって、裏面電極２０の端子としての機能を維持しつつ、半導体ウエハ１０に過度の力がかかることを防止できる。   In the inspection of the semiconductor wafer 10 according to the first embodiment of the present invention, the plurality of back surface electrodes 20 can be used as ground terminals by connecting the first probe needles 52 to the front surface electrodes 16a, 16b, and 16c. When the plurality of back surface electrodes 20 are used as ground terminals, the first probe needle 52 can be electrically stabilized, so that it is not necessary to strongly adsorb the semiconductor wafer 10 to the mounting surface 46a. Therefore, the suction pressure by the suction means 48 may be reduced to such an extent that the semiconductor wafer 10 is not displaced. Therefore, it is possible to prevent an excessive force from being applied to the semiconductor wafer 10 while maintaining the function as the terminal of the back electrode 20.

さらに、本発明の実施の形態１によれば、複数の裏面電極２０と検査ステージ４６の電気的接続は不要であるので、検査ステージ４６は導電性材料以外の材料で形成することができる。例えば、検査ステージ４６の上に弾性部分を形成してもよい。弾性部分を形成すると、検査ステージと半導体ウエハの間に異物があっても弾性部分が異物を吸収するように変形するので半導体ウエハへのダメージを緩和できる。   Furthermore, according to the first embodiment of the present invention, since the electrical connection between the plurality of back electrodes 20 and the inspection stage 46 is not necessary, the inspection stage 46 can be formed of a material other than the conductive material. For example, an elastic part may be formed on the inspection stage 46. When the elastic portion is formed, even if there is a foreign matter between the inspection stage and the semiconductor wafer, the elastic portion is deformed so as to absorb the foreign matter, so that damage to the semiconductor wafer can be reduced.

表面電極１６ａ、１６ｂ、１６ｃは、半導体ウエハ１０の外周に沿って複数形成したので、これらを第１プローブ針５２と接続すると、半導体ウエハ１０を検査ステージ４６に固定することができる。第１プローブ針５２による半導体ウエハ１０の固定が十分であれば、吸着手段４８は省略しても良い。   Since a plurality of surface electrodes 16 a, 16 b and 16 c are formed along the outer periphery of the semiconductor wafer 10, the semiconductor wafer 10 can be fixed to the inspection stage 46 by connecting them to the first probe needle 52. If the fixing of the semiconductor wafer 10 by the first probe needle 52 is sufficient, the suction means 48 may be omitted.

ところで、本発明の表面電極１６ｂ、１６ｃは予備的に形成されているものである。そのため、表面電極は１つだけ形成してもよい。同様に、複数の裏面電極２０のうちの少なくともひとつが、半導体ウエハ１０のバイアホールを介して表面電極と電気的に接続されればよい。   By the way, the surface electrodes 16b and 16c of the present invention are preliminarily formed. Therefore, only one surface electrode may be formed. Similarly, at least one of the plurality of back surface electrodes 20 may be electrically connected to the front surface electrode via the via hole of the semiconductor wafer 10.

実施の形態２．
本発明の実施の形態２に係る発明は、実施の形態１に係る発明と共通点が多いので、実施の形態１に係る発明との相違点を中心に説明する。図７は、本発明の実施の形態２に係る半導体ウエハ検査装置を示す図である。検査ステージ６０は導電性の材料で形成されている。検査ステージ６０のうち、半導体ウエハ１０を載置する面は載置面６０ａである。検査ステージ６０には、半導体ウエハ１０を載置面６０ａに吸着するための第１吸着手段６２と第２吸着手段６４が形成されている。第１吸着手段６２は、載置面６０ａの中央部に半導体ウエハ１０を吸着する吸気口を有している。第２吸着手段６４は、載置面６０ａの中央部の外側に半導体ウエハ１０を吸着する吸気口を有している。第２吸着手段６４は、第１吸着手段６２よりも高い吸着圧で半導体ウエハ１０を吸着するものである。 Embodiment 2. FIG.
Since the invention according to the second embodiment of the present invention has much in common with the invention according to the first embodiment, differences from the invention according to the first embodiment will be mainly described. FIG. 7 shows a semiconductor wafer inspection apparatus according to Embodiment 2 of the present invention. The inspection stage 60 is made of a conductive material. Of the inspection stage 60, the surface on which the semiconductor wafer 10 is placed is a placement surface 60a. The inspection stage 60 is formed with first suction means 62 and second suction means 64 for sucking the semiconductor wafer 10 to the mounting surface 60a. The first suction means 62 has an air inlet for sucking the semiconductor wafer 10 at the center of the mounting surface 60a. The second suction means 64 has an air inlet that sucks the semiconductor wafer 10 outside the central portion of the mounting surface 60a. The second adsorption unit 64 adsorbs the semiconductor wafer 10 with a higher adsorption pressure than the first adsorption unit 62.

上述の半導体ウエハ検査装置を用いて、実施の形態１と同様の検査方法により半導体ウエハ１０の特性を測定する。ただし、実施の形態１と異なり、本発明の実施の形態２に係る半導体ウエハ検査装置には第１プローブ針はない。   Using the semiconductor wafer inspection apparatus described above, the characteristics of the semiconductor wafer 10 are measured by the same inspection method as in the first embodiment. However, unlike the first embodiment, the semiconductor wafer inspection apparatus according to the second embodiment of the present invention has no first probe needle.

半導体ウエハ１０の外側は、第２吸着手段６４により載置面６０ａに強く吸着する。こうすると、表面電極１６ａ、１６ｂ、１６ｃの直下の裏面電極が載置面６０ａに強く吸着し、表面電極１６ａ、１６ｂ、１６ｃから検査ステージ６０に至る最短経路の接続を強化できる。よって、裏面電極と検査ステージ６０の電気的接続を安定させ測定精度を高めることができる。   The outside of the semiconductor wafer 10 is strongly adsorbed to the mounting surface 60 a by the second adsorbing means 64. In this way, the back electrode immediately below the front electrodes 16a, 16b, 16c is strongly adsorbed to the mounting surface 60a, and the connection of the shortest path from the front electrodes 16a, 16b, 16c to the inspection stage 60 can be strengthened. Therefore, the electrical connection between the back electrode and the inspection stage 60 can be stabilized and the measurement accuracy can be increased.

他方、半導体ウエハ１０の中央部は、第１吸着手段６２により比較的弱く載置面６０ａに吸着する。こうすると、半導体ウエハ１０と検査ステージ６０の間の異物による半導体ウエハ１０のダメージを緩和できる。以上より、半導体ウエハ１０の裏面電極の端子としての機能を維持しつつ、半導体ウエハ１０に過度の力がかかることを防止できる。   On the other hand, the central portion of the semiconductor wafer 10 is relatively weakly attracted to the mounting surface 60 a by the first suction means 62. In this way, damage to the semiconductor wafer 10 due to foreign matter between the semiconductor wafer 10 and the inspection stage 60 can be reduced. As described above, it is possible to prevent an excessive force from being applied to the semiconductor wafer 10 while maintaining the function as the terminal of the back electrode of the semiconductor wafer 10.

なお、本発明の実施の形態２に係る半導体ウエハ、半導体ウエハ検査装置、及び半導体ウエハの検査方法は、少なくとも実施の形態１と同程度の変形が可能である。また、本発明の実施の形態１、２では基板はＧａＡｓで形成されることとしたが、例えばＳｉ、ＳｉＣ、ＩｎＰ、Ａｌ２Ｏ３（サファイア）、又はＧａＮで基板を形成してもよい。 The semiconductor wafer, the semiconductor wafer inspection apparatus, and the semiconductor wafer inspection method according to the second embodiment of the present invention can be modified at least as much as the first embodiment. In the first and second embodiments of the present invention, the substrate is formed of GaAs. However, the substrate may be formed of, for example, Si, SiC, InP, Al 2 O 3 (sapphire), or GaN.

１０ 半導体ウエハ、 １２ 複数のチップ、 １４ ダイシングライン、 １６ａ,１６ｂ,１６ｃ 表面電極、 ２０ 複数の裏面電極、 ２２ ダイシングライン、 ２４ 接続パターン、 ２６ａ，２６ｂ,２６ｃ バイアホール、 ３０ ＧａＡｓ基板、 ３２ 保護膜、 ４０ 半導体ウエハ検査装置、 ４２ 外箱、 ４４ Ｘ−Ｙステージ、 ４６ 検査ステージ、 ４６ａ 載置面、 ４８ 吸着手段、 ５０ 治具、 ５２ 第１プローブ針、 ５４ プローブカードホルダー、 ５６ プローブカード、 ５６ａ 第２プローブ針、 ６０ 検査ステージ、 ６０ａ 載置面、 ６２ 第１吸着手段、 ６４ 第２吸着手段   10 semiconductor wafers, 12 multiple chips, 14 dicing lines, 16a, 16b, 16c surface electrodes, 20 multiple back electrodes, 22 dicing lines, 24 connection patterns, 26a, 26b, 26c via holes, 30 GaAs substrates, 32 protective films 40 Semiconductor wafer inspection device, 42 Outer box, 44 XY stage, 46 Inspection stage, 46a Mounting surface, 48 Adsorption means, 50 Jig, 52 First probe needle, 54 Probe card holder, 56 Probe card, 56a Second probe needle, 60 inspection stage, 60a mounting surface, 62 first suction means, 64 second suction means

Claims (6)

ダイシングラインを隔てて複数のチップが並ぶ半導体ウエハの表面側に形成された表面電極と、
前記半導体ウエハの裏面側に、前記ダイシングラインを隔てて形成された複数の裏面電極と、
前記半導体ウエハの裏面側に、前記ダイシングラインを跨いで前記複数の裏面電極を電気的に接続する接続パターンと、を備え、
前記複数の裏面電極のうちの少なくともひとつは、前記半導体ウエハのバイアホールを介して前記表面電極と電気的に接続されたことを特徴とする半導体ウエハ。 A surface electrode formed on the surface side of a semiconductor wafer in which a plurality of chips are arranged across a dicing line;
A plurality of backside electrodes formed on the backside of the semiconductor wafer across the dicing line;
A connection pattern for electrically connecting the plurality of back surface electrodes across the dicing line on the back surface side of the semiconductor wafer,
At least one of the plurality of back electrodes is electrically connected to the surface electrode through a via hole of the semiconductor wafer. 前記表面電極は前記半導体ウエハの外周に沿って複数形成されたことを特徴とする請求項１に記載の半導体ウエハ。   The semiconductor wafer according to claim 1, wherein a plurality of the surface electrodes are formed along an outer periphery of the semiconductor wafer. 半導体ウエハを載置する検査ステージと、
前記半導体ウエハの外周側の表面電極とコンタクトするように、前記検査ステージに取り付けられたプローブ針と、
前記半導体ウエハの特性を測定するプローブカードを支持するプローブカードホルダーと、
を備えたことを特徴とする半導体ウエハ検査装置。 An inspection stage for mounting a semiconductor wafer;
A probe needle attached to the inspection stage so as to contact the surface electrode on the outer peripheral side of the semiconductor wafer;
A probe card holder for supporting a probe card for measuring the characteristics of the semiconductor wafer;
A semiconductor wafer inspection apparatus comprising: 半導体ウエハを載置する載置面を有する検査ステージと、
前記半導体ウエハを吸着する吸気口を前記載置面の中央部に有する第１吸着手段と、
前記半導体ウエハを吸着する吸気口を前記載置面の前記中央部の外側に有し、前記第１吸着手段よりも高い吸着圧で前記半導体ウエハを吸着する第２吸着手段と、
を備えたことを特徴とする半導体ウエハ検査装置。 An inspection stage having a mounting surface for mounting a semiconductor wafer;
First suction means having a suction port for sucking the semiconductor wafer at the center of the mounting surface;
A second adsorbing means for adsorbing the semiconductor wafer at an adsorption pressure higher than that of the first adsorbing means, having an air inlet for adsorbing the semiconductor wafer outside the central portion of the mounting surface;
A semiconductor wafer inspection apparatus comprising: 前記検査ステージの上に形成された弾性部分を備えたことを特徴とする請求項３に記載の半導体ウエハ検査装置。   The semiconductor wafer inspection apparatus according to claim 3, further comprising an elastic portion formed on the inspection stage. 表面電極と、バイアホールを介して前記表面電極と電気的に接続された裏面電極を有する半導体ウエハを、検査ステージの載置面に載置する工程と、
前記検査ステージに取り付けられた第１プローブ針を前記表面電極に接続する工程と、
前記第１プローブ針と前記表面電極を接続した状態で、第２プローブ針を有するプローブカードを用いて前記半導体ウエハの特性を測定する工程と、を有し、
前記裏面電極は前記半導体ウエハの裏面全体に形成されたことを特徴とする半導体ウエハの検査方法。 Placing a semiconductor wafer having a front electrode and a back electrode electrically connected to the front electrode through a via hole on a mounting surface of the inspection stage;
Connecting a first probe needle attached to the inspection stage to the surface electrode;
Measuring the characteristics of the semiconductor wafer using a probe card having a second probe needle in a state in which the first probe needle and the surface electrode are connected, and
The method for inspecting a semiconductor wafer, wherein the back electrode is formed on the entire back surface of the semiconductor wafer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016062990A (en) * 2014-09-16 2016-04-25 株式会社デンソー Wafer prober device
CN109457230A (en) * 2018-11-07 2019-03-12 杭州鸿星电子有限公司 A kind of quartz wafer film coating jig integrated frame

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541513A (en) * 1991-08-02 1993-02-19 Sumitomo Electric Ind Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541513A (en) * 1991-08-02 1993-02-19 Sumitomo Electric Ind Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016062990A (en) * 2014-09-16 2016-04-25 株式会社デンソー Wafer prober device
CN109457230A (en) * 2018-11-07 2019-03-12 杭州鸿星电子有限公司 A kind of quartz wafer film coating jig integrated frame

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